A DMA controller testing system and method

Abstract

The application relates to the storage field and particularly relates to a DMA controller testing system and method. The system comprises a host, a hardware switching device and an FPGA board, the FPGA board simulates a hard disk structure, the host is connected with a serial port module on the FPGA through the hardware switching device, and a DMA is connected with a PCIe interface of the host; a test program is arranged on the host, a detailed operation model is defined for the DMA controller in the test program, all working modes are covered, meanwhile, the test system integrates operation models of interactive operation of other hardware components and the DMA controller, and test scenes of interactive operation or parallel operation are covered. The application generates various test commands according to different test requirements, can comprehensively test the function of the DMA controller, and secondly, an address record database of each test is removed from a test command generation algorithm, so that the coverage of test addresses is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, in particular to a DMA controller testing system and method. BACKGROUND

[0002] DMA (Direct Memory Access) is a data transfer technology that exchanges data directly with system memory without CPU, which can realize data transmission from memory to memory, device to memory and memory to device, greatly reducing the CPU workload. DMA controller testing mainly tests DMA reading and writing, operation, comparison, encryption and other tests, focusing on the correctness of data transmission, whether the data path is normal, and the data transmission performance. The working process of DMA is realized by DMA controller. DMA control data transfer involves two operations of reading and writing, which requires the DMA controller to be able to address the memory and modify the address pointer to realize the reading and writing operation of the memory; be able to determine the number of bytes of this DMA transfer. The DMA controller initiates the transmission transaction according to the data source address, destination address and transmission length. DMA controller testing includes copy function, encryption function, performance, error injection and other test items of specified addressing mode.

[0003] In the chip design stage of the SSD hard disk research and development process, a FPGA board is usually used to simulate the real SSD hard disk. The FPGA board will carry the CPU, nand flash and other modules necessary for the work of the SSD hard disk, and the DMA controller module. This testing method has two problems in terms of test coverage. First, it is difficult to cover all working modes and scenarios. DMA controller usually has multiple working modes and complex usage scenarios, such as different data transmission sizes, different transmission sources and targets, different interrupt processing methods, etc. The existing testing method is difficult to fully cover these different modes and scenarios, and some potential problems may be missed. Second, it is difficult to find problems in complex system integration. In actual systems, DMA controller usually works with other hardware components and software systems. The existing testing method is often difficult to fully test DMA controller in a complex system integration environment, and may not be able to find problems when interacting with other components. SUMMARY

[0004] In view of the defects of the prior art, the present application provides a DMA controller testing system and method, which can generate various test commands according to different test requirements, and can fully test the functions of the DMA controller.

[0005] In order to solve the technical problem, the technical scheme adopted by the present application is: a DMA controller test system, comprising a host, a hardware switching device and an FPGA board, the FPGA board is provided with a CPU, a NAND flash, a DMA, a cache and a serial port module, the CPU, the NAND flash, the DMA and the cache constitute a hard disk simulation system, a USB interface of the host is connected with the hardware switching device through a data line, a serial port module of the hardware switching device is connected with the serial port module on the FPGA through a serial port line, and the DMA is connected with a PCIe interface of the host; a test program is arranged on the host, the test program comprises a custom command window, a command generation module, a command transmission module, a data display and analysis module, the operation type to be tested is set through the custom command window, including a source address range, a destination address range, an address random mode, a test granularity, a test command and a transmission length, the command generation module generates a test command according to the operation type information input by the custom command window, the command transmission module sends the test command to the FPGA board through the hardware switching device, and the data display and analysis module receives the information returned by the FPGA, analyzes the test result and displays the test result.

[0006] Further, the hardware switching device comprises a programmable controller and a serial port module, one end of the serial port module is connected with the programmable controller, and the other end is connected with the serial port module on the FPGA board through a serial port line.

[0007] The present application further discloses a DMA controller test method, and the method is realized based on the test system and comprises the following steps.

[0008] S01, setting a hardware switching device, the hardware switching device comprises a programmable controller and a serial port module, the programmable controller is connected with the host, the serial port module is connected with the FPGA board, and the hardware switching device realizes the bidirectional communication between the host and the FPGA board;

[0009] S02, prepare a host with a PCIe interface and a to-be-tested FPGA board, the to-be-tested FPGA board is loaded with a CPU, a NAND flash, a DMA, a cache, and a serial port module, the CPU, the NAND flash, the DMA, and the cache constitute a hard disk simulation system, a test program is arranged on the host, the test program includes a custom command window, a command generation module, a command transmission module, a data display and analysis module, the operation type to be tested is set through the custom command window, including the source address range, the destination address range, the address random mode, the test granularity, the test command, and the transmission length, the command generation module generates the test command according to the operation type information input by the custom command window, the command transmission module sends the test command to the FPGA board through a hardware switching device, the data display and analysis module receives the information returned by the FPGA, analyzes the test result, and displays the test result; the to-be-tested FPGA board is connected to the PCIe interface of the host, the serial port line led out of the FPGA board is connected to the serial port module of the hardware switching device, and the data line led out of the programmable controller module of the hard disk switching device is connected to the host;

[0010] S03, the host is started, and the control software is run on the host, first, the operation model to be tested is set, including the source address range, the destination address range, the address random mode, the test granularity, the test command, and the transmission length, and then the required test command is automatically generated;

[0011] S04, start testing, and the test process is as follows:

[0012] S41, send a smoke test command, check the command return state in the data display and analysis module of the control software, and confirm whether the working state of the FPGA board is normal, if the working state is normal, proceed to the next step;

[0013] S42, connect the host and the DMA controller of the to-be-tested FPGA through the DMA test drive module;

[0014] S43, send the test command to the DMA controller of the FPGA board through the command transmission module;

[0015] S44, collect the command execution result of the DMA controller through the data display and analysis module;

[0016] S45, process the command execution result through the data display and analysis module, and analyze whether the processing result of the command meets the expectation.

[0017] Further, the test command generation process is as follows:

[0018] S31, setting command parameters on the custom command window of the control software, the command parameters including the transmission module to be tested, the source address range, the destination address range, the address randomization mode, the alignment mode, the test granularity, the test command, the test data length and the test times;

[0019] S32, performing address calculation according to the parameter rules in the pre-defined operation model in the control software, the control software generating an address table according to the selected address range, address randomization mode, granularity and alignment mode, so as to ensure that the addresses are aligned according to the selected alignment mode;

[0020] S33, the control software reading the historical test address table in the database, modifying the address table according to the principle of covering more test ranges with the same test command as much as possible, and removing the addresses that have been tested in the history;

[0021] S34, the control software randomly selecting a specified number of address range combinations based on the selected test command, address range table, test data length and test times, and checking whether the address ranges overlap in combination with the data length of each command test;

[0022] S35, if the address ranges overlap, further modifying the address ranges of the test command according to the pre-set rules;

[0023] S36, combining the test command with the address table to generate a test command list.

[0024] Further, the test command and the address table used thereby are recorded in a database, and are used in combination with a suitable address selection algorithm to cover more test ranges in multiple tests.

[0025] Further, if a single core or multi-core operation is specified in the command window in step S35, the corresponding parameters in the command are modified.

[0026] Further, the general format of the test command is: tdma -m mode -s source -d dest -p pattern -l pattern_len -z size -n num -u unit -c core_num, wherein tdma represents testing the DMA controller; -m mode represents the transmission mode, which is set on the custom command window of the control software; -s source represents the source address, which is set on the custom command window of the control software; -d dest represents the destination address, which is set on the custom command window of the control software; -p pattern represents the test data content, which is set on the custom command window of the control software or randomly generated by the control software; -l pattern_len represents the length of the test data pattern, which is set on the custom command window of the control software; -z size represents the test data length, which is set on the custom command window of the control software; -n num represents the number of times of testing, which is set on the custom command window of the control software; -u unit represents the data length unit, which is set on the custom command window of the control software; and -c core_num represents issuing the command by a certain core, supporting single-core or multi-core simultaneous issuing, which is set on the custom command window of the control software.

[0027] Further, the transmission mode includes copy, set, crc and speed.

[0028] The present application has the following advantages: firstly, the test command generation module can generate various test commands according to different test requirements, and can comprehensively test the function of the DMA controller; secondly, the address record database of each test removes the tested address in the test command generation algorithm, and improves the coverage of the test address. The test system of the present application has simple structure, low cost and easy implementation. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 It is a principle block diagram of the test system described in embodiment 1;

[0030] Figure 2 It is a flow chart of the test method described in embodiment 2;

[0031] Figure 3 It is a flow chart of the test command generation. DETAILED DESCRIPTION

[0032] The present application will be further described below in combination with the drawings and specific embodiments.

[0033] Embodiment 1

[0034] The embodiment discloses a DAM test system, as shown in Figure 1 The test system comprises a host, a hardware switching device and an FPGA board, the FPGA board is provided with a CPU, a NAND flash, a DMA, a cache and a serial port module, the CPU, the NAND flash, the DMA and the cache constitute a hard disk simulation system, a USB interface of the host is connected with the hardware switching device through a data line, a serial port module of the hardware switching device is connected with the serial port module on the FPGA through a serial port line, and the DMA is connected with a PCIe interface of the host; a test program is arranged on the host, the test program comprises a custom command window, a command generation module, a command transmission module, a data display and analysis module, an operation type to be tested is set through the custom command window, including a source address range, a destination address range, an address random mode, a test granularity, a test command and a transmission length, the command generation module generates a test command according to the operation type information input by the custom command window, the command transmission module sends the test command to the FPGA board through the hardware switching device, and the data display and analysis module receives information returned by the FPGA, analyzes a test result and displays the test result.

[0035] In the embodiment, the hardware switching device comprises a programmable controller and a serial port module, one end of the serial port module is connected with the programmable controller, and the other end is connected with the serial port module on the FPGA board through a serial port line.

[0036] The test system defines a detailed operation model for the DMA controller in the control software to cover all working modes, the model can accurately reflect the expected behavior of the DMA controller under various input conditions, including different data transmission sizes, transmission sources and targets and the like. Meanwhile, the test system integrates an operation model for the interactive operation of other hardware components and the DMA controller to cover the test scene of the interactive operation or the parallel operation.

[0037] The control software is installed on the host, and the software comprises a custom command window, a command generation module, a command transmission module and a data display and analysis module.

[0038] The host is in communication with the hardware switching device through a data line, the device comprises a programmable controller and a serial port module, and the serial port module is connected to the FPGA board through switching, so that the test of the DMA controller on the FPGA board by the host is realized.

[0039] Embodiment 2

[0040] The embodiment discloses a DMA controller test method, as shown in Figure 2 The method comprises the following steps:

[0041] The method is realized based on the test system in the embodiment 1, and comprises the following steps:

[0042] S01, set up a hardware adapter, the hardware adapter includes a programmable controller and a serial port module, the programmable controller is connected to a host computer, and the serial port module is connected to an FPGA board, the hardware adapter serves as a bridge to realize bidirectional communication between the host computer and the FPGA board.

[0043] S02, prepare a host computer with a PCIe interface and a to-be-tested FPGA board, the to-be-tested FPGA board is equipped with a CPU, a NAND flash, a DMA, a cache and a serial port module, the CPU, the NAND flash, the DMA and the cache constitute a hard disk simulation system, the host computer is provided with a test program, the test program includes a custom command window, a command generation module, a command transmission module, a data display and analysis module, the operation type to be tested is set through the custom command window, including a source address range, a destination address range, an address random mode, a test granularity, a test command and a transmission length, the command generation module generates a test command according to the operation type information input by the custom command window, the command transmission module sends the test command to the FPGA board through the hardware adapter, the data display and analysis module receives the information returned by the FPGA, analyzes the test results and displays them; connect the to-be-tested FPGA board to the PCIe interface of the host computer, connect the serial port line led out by the FPGA board to the serial port module of the hardware adapter, and connect the data line led out by the programmable controller module of the hard disk adapter to the host computer.

[0044] In this embodiment, the source address range can be in the buffer or the dram, and correspondingly, the destination address range can also be in the dram or the buffer, so that data can be transmitted from the buffer to the dram, and data can also be transmitted from the dram to the buffer, the buffer and the dram are different hardware components, and the interaction between the DMA and other hardware components can be embodied.

[0045] S03, start the host computer, run the control software on the host computer, first set the operation model to be tested, including a source address range, a destination address range, an address random mode, a test granularity, a test command, a transmission length, and then automatically generate the required test command.

[0046] S04, start testing, the testing process is as follows:

[0047] S41, send a smoke test command, check the command return state in the data display and analysis module of the control software, and confirm whether the working state of the FPGA board is normal, if normal, proceed to the next step;

[0048] S42, connect the host computer and the DMA controller of the to-be-tested FPGA through the DMA test driver module;

[0049] S43, sending the test command to the DMA controller of the FPGA board through the command transmission module;

[0050] S44, collecting the command execution result of the DMA controller through the data display and analysis module;

[0051] S45, processing the command execution result through the data display and analysis module, and analyzing whether the processing result of the command meets the expectation.

[0052] As shown in the figure, the test command generation process is as follows: Figure 2

[0053] S31, setting the command parameters on the custom command window of the control software, and the command parameters include the transmission module to be tested, the source address range, the destination address range, the address randomization mode, the alignment mode, the test granularity, the test command, the test data length, and the test times;

[0054] S32, performing address calculation according to the parameter rules in the pre-defined operation model in the control software, and the control software generates an address table according to the selected address range, address randomization mode, granularity, and alignment mode, to ensure that the addresses are aligned according to the selected alignment mode, such as 4k alignment, 4 bytes alignment, etc.;

[0055] S33, the control software reads the historical test address table in the database, modifies the address table according to the principle of covering more test ranges with the same test command as much as possible, and removes the addresses that have been tested in the history;

[0056] S34, the control software randomly selects a specified number of address range combinations based on the selected test command, address range table, test data length, and test times, and checks whether the address ranges overlap in combination with the data length of each command test;

[0057] S35, if the address ranges overlap, further modify the address range of the test command according to the pre-set rules;

[0058] S36, if the single core or multi-core operation is specified in the command window, modify the corresponding parameters in the command;

[0059] S37, combining the test command with the address table to generate a test command list.

[0060] In this embodiment, the test command and the address table used are recorded in a database, and appropriate address selection algorithms are used to cover more test ranges in multiple tests.

[0061] ​The address selection algorithm is used to select test addresses from the address table of the database record. It includes random selection algorithm, linear traversal algorithm (with interval), stratified sampling algorithm, etc. The random selection algorithm is to randomly select memory addresses from the address table for testing. The linear traversal algorithm (with interval) is to select addresses according to a certain order and interval. The stratified sampling algorithm is to divide the memory addresses into different levels or regions (for example, stratified according to the high byte), and then randomly select a certain number of levels from the large level, and then randomly select some addresses in each selected level for testing. The address selection algorithm of the embodiment preferentially adopts the third one, i.e. the stratified sampling algorithm.

[0062] In the embodiment, the general format of the test command is: tdma -m mode -s source -d dest -p pattern -l pattern_len -z size -n num -u unit -c core_num, and the parameter meanings are explained as follows:

[0063] tdma, indicating testing the DMA controller;

[0064] -m mode, indicating the transmission mode, such as copy, set, crc, speed, etc., which is set on the command window of the control software;

[0065] -s source, indicating the source address, which is set on the command window of the control software;

[0066] -d dest, indicating the destination address, which is set on the command window of the control software;

[0067] -p pattern, indicating the test data content, which can be set on the command window of the control software or randomly generated by the control software;

[0068] -l pattern_len, indicating the length of the test data pattern, which can be set on the command window of the control software;

[0069] -z size, indicating the test data length, which can be set on the command window of the control software;

[0070] -n num, indicating the number of tests, i.e. the command is tested several times in one test, which can be set on the command window of the control software;

[0071] -u unit, indicating the data length unit, including byte, 4k byte, etc., which can be set on the command window of the control software;

[0072] -c core_num, indicating that the command is issued by a certain A55 or M33 core, and can be issued by single core or multiple cores simultaneously, which can be set on the command window of the control software.

[0073] A typical test command is as follows:

[0074] tdma -m copy -s 0x05010000 -d 0x05040000 -z 4 -u 0 -n 8, which indicates that a copy test is performed, the source address is 0x05010000, the destination address is 0x05040000, the test data length is 4 bytes, and the test is repeated 8 times.

[0075] The above description is only the basic principle and preferred embodiment of the present application, and the improvements and replacements made by those skilled in the art according to the present application are within the protection scope of the present application.

Claims

1. A DMA controller testing method, characterized in that: The method is implemented based on a DMA controller test system. The DMA controller test system includes a host, a hardware adapter and an FPGA board. The FPGA board is equipped with a CPU, a NAND flash, a DMA, a cache and a serial port module. The CPU, NAND flash, DMA and cache constitute a hard disk simulation system. The USB interface of the host is connected to the hardware adapter via a data cable. The serial port module of the hardware adapter leads a serial port line to be connected to the serial port module on the FPGA. The DMA is connected to the PCIe interface of the host. The host is provided with a test program, which includes a custom command window, a command generation module, a command transmission module and a data display and analysis module. The operation type to be tested, including the source address range, the destination address range, the address randomization method, the test granularity, the test command and the transmission length, is set through the custom command window. The command generation module generates a test command according to the operation type information input in the custom command window. The command transmission module sends the test command to the FPGA board via the hardware adapter. The database display and analysis module receives the information returned by the FPGA, analyzes the test results and displays them. The test method includes the following steps: S01. Setting a hardware adapter, which includes a programmable controller and a serial port module, wherein the programmable controller is connected to a host computer, and the serial port module is connected to an FPGA board. The hardware adapter realizes two-way communication between the host computer and the FPGA board; S02. Prepare a host with a PCIe interface and an FPGA board to be tested. The FPGA board to be tested is equipped with a CPU, NAND flash, DMA, cache, and a serial port module. The CPU, NAND flash, DMA, and cache constitute a hard disk simulation system. The host is provided with a test program, which includes a custom command window, a command generation module, a command transmission module, and a data display and analysis module. The operation type to be tested is set through the custom command window, including the source address range, destination address range, address randomization method, test granularity, test command, and transmission length. The command generation module generates a test command according to the operation type information entered in the custom command window. The command transmission module sends the test command to the FPGA board through a hardware adapter. The data display and analysis module receives the information returned by the FPGA, analyzes the test results, and displays them. Connect the FPGA board to the PCIe interface of the host, connect the serial port line led out of the FPGA board to the serial port module of the hardware adapter, and connect the data line led out of the programmable controller module of the hard disk adapter to the host. S03. The host is powered on and the control software is run on the host. First, the operation model to be tested is set, including the source address range, destination address range, address randomization method, test granularity, test command, and transmission length. Then, the required test command is automatically generated. S04. Start the test. The test process is as follows: S41. Send a smoke test command and check the command return status in the data display and analysis module of the control software to confirm whether the FPGA board is working normally. If it is normal, proceed to the next step. S42, connecting the host to the DMA controller of the FPGA to be tested through the DMA test driver module; S43, sending a test command to the DMA controller of the FPGA board through the command transmission module; S44, collecting command execution results of the DMA controller through the data display and analysis module; S45. Process the command execution result through the data display and analysis module to analyze whether the command processing result meets expectations.

2. The DMA controller testing method according to claim 1, wherein: The test command generation process is: S31. Set command parameters in the custom command window of the control software, where the command parameters include the transmission module to be tested, source address range, destination address range, address randomization mode, alignment mode, test granularity, test command, test data length, and number of tests; S32. Perform address calculation according to the parameter rules in the predefined operation model in the control software. The control software generates an address table according to the selected address range, address randomization method, granularity, and alignment method to ensure that the addresses are aligned according to the selected alignment method. S33, the control software reads the historical test address table in the database, and modifies the address table according to the principle of covering as many test ranges as possible with the same test command, removing the addresses that have been tested in the past; S34. The control software randomly selects a specified number of address range combinations based on the selected test command, the address range table, the test data length, and the number of tests, and checks whether the address ranges overlap in combination with the data length of each command test; S35. If the address ranges overlap, further modify the address range of the test command according to a pre-set rule; S36. Combine the test command with the address table to generate a test command list.

3. The DMA controller testing method according to claim 2, wherein: The test commands and the address table they use are recorded in a database and used in conjunction with the address selection algorithm to cover more test ranges in multiple tests.

4. The DMA controller testing method according to claim 2, wherein: After executing step S35, if a single-core or multi-core operation is specified in the command window, the corresponding parameters in the command are modified.

5. The DMA controller testing method according to claim 1 or 2, wherein: The general format of the test command is: tdma -m mode -s source -d dest -p pattern -l pattern_len -z size -n num -uunit -c core_num, where tdma indicates testing the DMA controller; -m mode indicates the transfer mode, which is set in the custom command window of the control software; -s source indicates the source address, which is set in the custom command window of the control software; -d dest indicates the destination address, which is set in the custom command window of the control software; -p pattern indicates the test data content, which is set in the custom command window of the control software or the control software randomly generates the test data; -l pattern_len indicates the length of the test data pattern, which is set in the custom command window of the control software; -z size indicates the test data length, which is set in the custom command window of the control software; -n num indicates the number of tests per test, which is set in the custom command window of the control software; -u unit indicates the data length unit, which is set in the custom command window of the control software; -c core_num indicates the core that issues the command. It supports issuing commands to a single core or multiple cores simultaneously and is set in the custom command window of the control software.

6. The DMA controller testing method according to claim 5, wherein: The transmission modes include copy, set, crc, and speed.

7. The DMA controller testing method according to claim 1, wherein: The hardware transfer device includes a programmable controller and a serial port module. The programmable controller is connected to the USB interface of the host. One end of the serial port module is connected to the programmable controller, and the other end is connected to the serial port module on the FPGA board through a serial port line.

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