PCIe device optimized memory allocation method, storage medium, device and system

Abstract

The application discloses a PCIe device optimized memory allocation method, a storage medium, a device and a system, and relates to the technical field of PCIe. The method comprises the following steps: using a memory size configuration interface to set the required memory size of a PCIe device in a PCIe enumeration process; using an allocation strategy configuration interface to set the memory allocation strategy of the PCIe device; when allocating memory, sorting the memory resource requests of each PCIe device according to the memory allocation strategy and writing the memory resource requests into a memory request linked list; reading PCIe controller resources, allocating memory space according to the required memory size of the PCIe device and in combination with a base address alignment principle in the order in the memory request linked list. The application can not only modify the memory requirement size of a PCIe device according to the actually used memory space of the PCIe device, but also flexibly configure the memory allocation strategy according to the device requirement, has strong flexibility, can adapt to the requirements of various chips, can carry more devices in limited resources and meets the actual application requirement.

Description

Technical Field

[0001] This invention relates to the field of PCIe technology, specifically to a method, storage medium, device, and system for optimizing memory allocation in PCIe devices. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial interface used to connect external devices in a computer system. It employs a new serial communication protocol, offering higher bandwidth and lower latency compared to the traditional PCI bus architecture. The PCIe bus architecture uses a point-to-point connection, meaning each device connects directly to the host, avoiding bus contention issues.

[0003] Currently, existing Linux kernels, in order to reduce memory fragmentation, uniformly follow the principle of allocating memory space based on the PCIe device's memory request, from largest to smallest. Figure 1 For example, the current Linux system allocates memory for PCIe devices as follows:

[0004] 1. During the Linux system initialization phase, the memory size of all PCI devices (i.e., EPs, End Points) on the current PCI bus is obtained by enumerating the PCI bus tree; that is, the size of the memory resource requests. For example, Figure 1 EP0 is 128M, 128M = 2 27 That is, the data width of EP0 is 27 bits, EP1 is 64M, and EP2 is 256M;

[0005] 2. During the initialization phase of the CPU PCIe controller (i.e., RC, Root Complex), the memory resources of the current RC are obtained by parsing the device tree file (dts); for example, Figure 1 The RC can allocate 512M of memory, which will be subsequently allocated to each EP within the PCI bus;

[0006] 3. For example Figure 1 As shown, when allocating memory, the Linux system first writes the memory resource requests of each EP (Entity Request) into a memory request linked list in descending order; for example... Figure 1 As shown in the figure, the memory request list in process 3 represents the PCIe memory space required by each peripheral. They are arranged in descending order and placed into the memory request list. The list only contains the request size of each EP. At this time, no memory address is actually allocated for the EP.

[0007] 4. For example Figure 1As shown, when actually allocating memory for PCIe devices, the Linux system allocates memory to each EP according to the memory request list and the principle of address alignment (i.e., bit alignment); for example... Figure 1 As shown, in process 4, each element in the memory request list will be taken out and allocated in combination with the CPU's RC memory address. For example, if the RC address range is 0x1000,0000~0x3000,0000, then according to the requirement of 256M space for EP2, the address allocation is 0x1000,0000~0x1fff,ffff.

[0008] However, in practical applications, the current PCIe device memory allocation method still has the following problems:

[0009] 1. When users have memory allocation needs for multiple PCIe devices, especially when there are priority allocation needs within the limited scope of the PCIe controller, the existing Linux kernel cannot configure and adjust PCIe memory allocation according to user needs.

[0010] 2. If the actual memory space used by a PCIe device is less than the initial hardware settings, its memory requirements cannot be modified. This may result in the CPU-side RC (i.e., PCIe controller) being unable to allocate memory to the PCIe device due to limited space, or the allocated memory address not meeting the hardware requirements of the PCIe device. Summary of the Invention

[0011] The purpose of this invention is to provide a method, storage medium, device, and system for optimizing memory allocation in PCIe devices. This method not only allows modification of the memory requirements of PCIe devices based on their actual memory usage, but also enables flexible configuration of memory allocation strategies according to device requirements. It offers high flexibility, adapts to various chip needs, and can support more devices within limited resources, thus meeting practical application requirements.

[0012] To achieve the above objectives, in a first aspect, embodiments of the present invention provide a method for optimizing memory allocation in a PCIe device, the method comprising:

[0013] During the PCIe enumeration process, the required memory size of the PCIe device is set using a preset memory size configuration interface; the memory allocation strategy of the PCIe device is set using a preset allocation strategy configuration interface; when allocating memory, the memory resource requests of each PCIe device are sorted according to the memory allocation strategy and written into the memory request list; the PCIe controller resources are read, and memory space is allocated to each PCIe device according to the order in the memory request list, based on the set required memory size of the PCIe device and the base address alignment principle.

[0014] In conjunction with the first aspect, in one implementation, a preset memory size configuration interface is used to set the required memory size of the PCIe device during the PCIe enumeration process, including:

[0015] The memory size configuration interface is used to obtain the memory size required by the PCIe device as set by the user; the original memory size of the PCIe device is obtained from the hardware; when the original memory size in the hardware is different from the memory size required by the PCIe device set by the user, the memory size required by the PCIe device set by the user is saved as the memory size that the PCIe device needs to request.

[0016] In conjunction with the first aspect, in one implementation, the memory allocation strategy includes: priority sorting, sorting from largest to smallest, and sorting from smallest to largest.

[0017] In conjunction with the first aspect, in one implementation, when the memory allocation strategy of the PCIe devices is set to priority sorting, the priority of each PCIe device will be configured according to user needs; wherein, the priority of the PCIe devices is indicated by adding specific variables to the Linux standard structure struct pci_dev of the PCIe devices.

[0018] In conjunction with the first aspect, in one implementation, the memory resource requests of each PCIe device are sorted according to the memory allocation strategy and written into a memory request linked list, including:

[0019] If the memory allocation strategy is to sort by size from largest to smallest, then the memory resource requests are placed in the memory request linked list in descending order.

[0020] If the memory allocation strategy is to sort from smallest to largest, then the memory resource requests are added to the memory request linked list in ascending order. The insertion method is as follows: loop through and judge the newly added memory resource request. If it is smaller than the current head element of the linked list, insert it at the front of the linked list. Otherwise, compare it with each linked list element in turn. If it is smaller than the current comparison element, insert it before the current comparison element.

[0021] If the memory allocation strategy is priority sorting, then an arbitrary sorting method will be used to sort the memory according to priority.

[0022] In conjunction with the first aspect, in one implementation, when the actual memory size used by a PCIe device is less than its initial hardware configuration size and priority allocation is required, the method includes:

[0023] Using a preset memory size configuration interface, the memory size required by a certain PCIe device is set to its actual memory size during the PCIe enumeration process; using a preset allocation strategy configuration interface, the memory allocation strategy is set to priority sorting, and the priority of the certain PCIe device is set to the highest; when allocating memory, the memory resource requests of each PCIe device are sorted according to priority and written into the memory request list; the PCIe controller resources are read, and memory space is allocated to each PCIe device according to the order in the memory request list, based on the set memory size required by the PCIe device and the base address alignment principle.

[0024] In conjunction with the first aspect, in one implementation, when the actual memory size used by a PCIe device is less than its initial hardware configuration size, and the freed-up memory is available for use by a new PCIe device, the method includes:

[0025] Using a preset memory size configuration interface, the memory size required by a certain PCIe device is set to its actual memory size during the PCIe enumeration process; simultaneously, the required memory size is set for the new PCIe device; using a preset allocation strategy configuration interface, the memory allocation strategy for the PCIe device is set; when allocating memory, the memory resource request of the new PCIe device is added, and the memory resource requests of all current PCIe devices are written into the memory request list according to the set allocation strategy; the PCIe controller resources are read, and memory space is allocated to each PCIe device according to the order in the memory request list, based on the set memory size required by the PCIe device and the base address alignment principle.

[0026] Secondly, embodiments of the present invention also provide a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method of the first aspect embodiment.

[0027] Thirdly, embodiments of the present invention also provide an electronic device, the electronic device including a processor, a memory, and a PCIe device optimized memory allocation program stored in the memory and executable by the processor, wherein when the PCIe device optimized memory allocation program is executed by the processor, it implements the steps of the method in the first aspect embodiment.

[0028] Fourthly, embodiments of the present invention also provide a PCIe device optimized memory allocation system based on the method in the first aspect embodiment, comprising: a memory size configuration module, an allocation strategy configuration module, a linked list modification module, and a memory allocation module;

[0029] The memory size configuration module is used to: set the memory size required by the PCIe device during the PCIe enumeration process using a preset memory size configuration interface;

[0030] The allocation strategy configuration module is used to: set the memory allocation strategy of the PCIe device using a preset allocation strategy configuration interface;

[0031] The linked list modification module is used to: when allocating memory, sort the memory resource requests of each PCIe device according to the memory allocation strategy and write them into the memory request linked list;

[0032] The memory allocation module is used to: read PCIe controller resources, allocate memory space to each PCIe device according to the order of the memory request list, based on the set memory size required by the PCIe device, and in combination with the base address alignment principle.

[0033] The beneficial effects of the technical solutions provided in this application include:

[0034] This embodiment includes a memory size configuration interface, which can be used to reset the memory size required by the PCIe device. When the actual memory size used by the PCIe device does not match the initial hardware settings, this memory size configuration interface can be used to flexibly set the required memory size, solving the problem that existing technologies cannot modify the required memory size. Furthermore, this method of modifying kernel code instead of modifying ASIC hardware can significantly reduce the cost of hardware upgrades, resulting in practical economic benefits.

[0035] Meanwhile, this embodiment also features a specially designed allocation strategy configuration interface, which can be used to configure the memory allocation strategy for PCIe devices. This can meet various memory allocation needs, is highly flexible, adapt to the requirements of various chips, and support more devices within limited resources, thus meeting practical application needs. Attached Figure Description

[0036] Figure 1 A schematic diagram illustrating how a Linux system allocates memory for a PCIe device in the prior art;

[0037] Figure 2 A flowchart illustrating an embodiment of the PCIe device memory allocation optimization method of this application;

[0038] Figure 3 This is a schematic diagram illustrating a scenario where the PCIe device memory allocation method of this application is applied;

[0039] Figure 4 A schematic diagram illustrating a scenario where the PCIe device memory allocation method of this application is applied in another example;

[0040] Figure 5 This is a schematic diagram of the hardware structure of an embodiment of the electronic device of this application;

[0041] Figure 6 A schematic diagram of the functional modules of an embodiment of the PCIe device optimized memory allocation system of this application. Detailed Implementation

[0042] To make the technical problems, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] However, it should be noted that the examples described below are merely specific examples and are not intended to limit the embodiments of the present invention to the specific steps, values, conditions, data, order, etc. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0044] Example 1

[0045] This application provides a method for optimizing memory allocation in PCIe devices. (Refer to...) Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the PCIe device memory allocation optimization method of this application. Figure 2 As shown, a method for optimizing memory allocation in a PCIe device includes:

[0046] Step A: Use the preset memory size configuration interface to set the required memory size for the PCIe device during the PCIe enumeration process.

[0047] It is understandable that existing PCIe device memory allocation methods cannot modify the memory requirements of PCIe devices; they are all configured according to the initial hardware settings. However, this embodiment specifically designs a software interface based on the Linux kernel—a memory size configuration interface—to allow for the reconfiguration of the required memory size for PCIe devices. When the actual memory size used by a PCIe device does not match the initial hardware settings, this memory size configuration interface can be used to flexibly set the required memory size, solving the problem of existing technologies being unable to modify the required memory size. Furthermore, this method of modifying kernel code instead of modifying ASIC hardware can significantly reduce the cost of hardware upgrades, resulting in practical economic benefits.

[0048] For example, as an optional implementation, step A utilizes a preset memory size configuration interface to set the required memory size of the PCIe device during the PCIe enumeration process, specifically including the following operations:

[0049] A1. Obtain the memory size required by the PCIe device (i.e., EP) as set by the user through the memory size configuration interface. In practical applications, the memory size required by the PCIe device set by the user can be passed as an input parameter to the function of the memory size configuration interface to obtain the required memory size set by the user.

[0050] A2. Use the Pci_size function in the Linux system to obtain the raw memory size of the PCIe device from the hardware.

[0051] A3. When the initial memory size in the hardware differs from the user-configured memory size required by the PCIe device, the user-configured memory size is saved as the memory size the PCIe device needs to allocate for subsequent memory allocation by the PCIe controller (RC). In practical applications, a variable can be pre-defined to store the memory size required by the PCIe device. For example, a `size` variable can be added to the Linux standard structure `Struct pci_dev` of the PCIe device to store the memory size required by the PCIe device. When the initial memory size in the hardware differs from the user-configured memory size required by the PCIe device, the user-configured memory size is assigned to the `size` variable in the `dev` structure to save the setting.

[0052] For example, the pseudocode for the preset memory size configuration interface can be as follows:

[0053]

[0054] Step B: Configure the memory allocation strategy for the PCIe device using the preset allocation strategy configuration interface.

[0055] It is also understandable that the existing Linux kernel cannot configure and adjust PCIe memory allocation according to user needs. In this embodiment, a Linux kernel-based allocation policy configuration interface is specially designed to configure the memory allocation policy of PCIe devices. This can meet various memory allocation needs, is highly flexible, adapt to the requirements of various chips, and support more devices within limited resources, thus meeting practical application needs.

[0056] Specifically, the memory allocation strategies described in this embodiment include priority sorting, descending sorting, and ascending sorting. Priority sorting means that the memory allocation principle for PCIe devices is based on the priority order configured for each PCIe device; descending / descending sorting means that the memory allocation principle for PCIe devices is based on the memory size requested by each PCIe device, sorted from largest to smallest / smallest to largest.

[0057] Furthermore, it's understandable that in practical applications, when the memory allocation strategy for PCIe devices is set to priority sorting, the priority of each PCIe device needs to be configured according to user requirements. In practice, a variable can be pre-defined to indicate the priority of each PCIe device. For example, a `prio` variable can be added to the Linux standard structure `Structpci_dev` of the PCIe device to indicate its priority. When the user-defined priority of a PCIe device is obtained through the interface, it is assigned to the `prio` variable in the `dev` structure to save the setting for subsequent use by the PCIe controller (RC) when allocating memory.

[0058] For example, the pseudocode for the software interface that configures the priority of each PCIe device can be as follows:

[0059]

[0060] The pseudocode for the preset allocation strategy configuration interface can be as follows:

[0061]

[0062]

[0063] Step C: When allocating memory, sort the memory resource requests of each PCIe device according to the memory allocation strategy and write them into the memory request list.

[0064] It is understood that in this embodiment, the Linux system software will be modified so that when allocating memory, instead of writing the memory resource requests of each PCIe device into the memory request list in descending order in the traditional way, the memory resource requests of each PCIe device will be written into the memory request list according to the set memory allocation strategy.

[0065] For example, as an optional implementation, step C involves sorting the memory resource requests of each PCIe device according to the memory allocation strategy and writing them into a memory request linked list. Specifically, this includes the following operations:

[0066] C1. If the memory allocation strategy is to sort by size from largest to smallest, then the original allocation principle of the Linux kernel is maintained. That is, memory resource requests are placed into the memory request list in descending order. The specific placement method is existing technology and will not be elaborated here. It is understandable that since the existing allocation method writes the memory resource requests of each PCIe device into the memory request list in descending order, when the memory allocation strategy is also set to sort by size from largest to smallest, the Linux system software does not need to be modified, and the original allocation principle of the Linux kernel can be maintained.

[0067] C2. If the memory allocation strategy is to sort by size from smallest to largest, then the memory resource requests are added to the memory request linked list in ascending order. The insertion method is as follows: Iterate through the newly added memory resource request; if it is smaller than the current head element of the linked list, insert it at the front of the list; otherwise, compare it with each element in the linked list sequentially; if it is smaller than the current comparison element, insert it before the current comparison element. It can be understood that after sorting the memory request linked list in ascending order in this way, the Linux system will subsequently retrieve elements from the head of the linked list and allocate addresses based on the available memory resources, thus implementing the ascending order sorting strategy.

[0068] C3. If the memory allocation strategy is priority sorting, then an arbitrary sorting method shall be used to sort according to priority.

[0069] For example, the pseudocode for sorting memory resource requests from various PCIe devices according to memory allocation strategies and writing them into a memory request linked list can be as follows:

[0070]

[0071] In the pseudocode above, `struct list_head` is the Linux kernel's memory request linked list structure, which is a doubly linked list. When the memory allocation strategy is to sort by size from largest to smallest, the original Linux kernel allocation principle is maintained; when the memory allocation strategy is to sort by size from smallest to largest, the memory resource requests need to be modified to be placed into the memory request linked list according to the sorting order from smallest to largest to satisfy the sorting strategy.

[0072] Step D: Read the PCIe controller (RC) resources and allocate memory space for each PCIe device according to the order in the memory request list, based on the set memory size required by the PCIe devices and the base address alignment principle. It can be understood that in this step, memory is allocated for each EP in the memory request list according to the RC's resource range and the address alignment principle. In specific implementation, this part of the code can refer to the Linux kernel source code to align the address of each EP, i.e., 2... nBit alignment is used to assign a PCIe physical address to each EP.

[0073] To better illustrate the details of memory allocation scenarios for various PCIe devices in this embodiment and to better understand the technical effects of this embodiment, several typical memory allocation scenarios will be illustrated below with specific examples, in conjunction with the accompanying drawings.

[0074] Scene 1:

[0075] When certain EPs (PCIe devices) have special address requirements, or when users want to ensure that a certain EP is allocated memory first, they can follow the method in this embodiment to set the priority of each EP and allocate memory to certain EPs first according to the priority sorting memory allocation strategy, thereby meeting various memory allocation needs.

[0076] For example, suppose the initial hardware setup memory space requirement for EP1 (i.e., the original memory size of the PCIe devices in the hardware) is 2. n The address width is n bits, but in actual use, only n-2 bits are used, meaning the actual space requirement is 2. n-2 For traditional Linux kernels, their memory size cannot be changed. Therefore, in such cases, the memory size configuration interface of this embodiment can be used to reset the required memory size of the PCIe device during the PCIe enumeration process. However, since the actual hardware cannot be changed, the BAR base address for memory allocation is 2. n Alignment, meaning that the base addresses n-1…0 of the BAR need to be set to 0. Figure 3 For example, assuming EP1's hardware requirement is 256M (28-bit width), but its actual usage is 64M (26-bit width), and the address needs to be 28-bit aligned, the priority is set as EP1 > EP0 > EP2. The Linux kernel allocates memory to each EP according to the priority and base address alignment principle, as shown in the following figure. Figure 3 As shown, it can meet user needs.

[0077] Scene 2:

[0078] When RC (PCIe controller) resources are limited, but there are many EP (PCIe devices), and the total memory resources of the EPs exceed the memory resources of the RC, the memory size of some EPs can be adjusted using the method in this embodiment, while meeting the hardware data bit width requirements, to expand the available memory resources and support more EPs. For example, assuming that the initial hardware design data bit width of a certain EP is n, and the actual data bit width used is n-1, its BAR space size can be adjusted to 2 during the PCIe enumeration process through the memory size configuration interface. n-1 The extra 2 n-1 The space of that size can then be allocated to other EPs.

[0079] For example, with Figure 4 For example, when there are 4 EPs, the existing Linux kernel RC resources cannot allocate resources to these 4 EPs (the total memory resources of the 4 EPs are 128+64+256+128=576M, which is greater than the RC memory resources of 512M). Suppose that the initial hardware configuration of EP2 is 256M of memory space, but only 128M is actually used. Its memory size can be modified to 128M through the memory size configuration interface, and the freed-up 128M can be allocated to the newly added EP3, such as... Figure 4 As shown. Therefore, the method of this embodiment can support more EPs when RC resources are limited, and the EPs can also have more CPU selectivity through the method of this embodiment.

[0080] As described above, compared to existing PCIe device memory allocation methods, this embodiment features a memory size configuration interface, which allows for the reconfiguration of the required memory size for the PCIe device. When the actual memory size used by the PCIe device differs from the initial hardware setting, this configuration interface allows for flexible setting of the required memory size, solving the problem of existing technologies being unable to modify the required memory size. Furthermore, this method of modifying kernel code instead of ASIC hardware significantly reduces hardware upgrade costs, resulting in practical economic benefits. Simultaneously, this embodiment also includes a dedicated allocation strategy configuration interface, enabling the configuration of the PCIe device's memory allocation strategy. This allows for various memory allocation requirements, offering high flexibility and adaptability to multiple chip requirements, enabling more devices to be supported within limited resources and meeting practical application needs.

[0081] Example 2

[0082] Based on the same inventive concept, embodiments of the present invention also provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a PCIe device optimized memory allocation method as provided in any embodiment of the present invention. The PCIe device optimized memory allocation method can be found in various embodiments of the PCIe device optimized memory allocation method of this application, and will not be repeated here.

[0083] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0084] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0085] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0086] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0087] Example 3

[0088] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, which may be a personal computer (PC), a laptop computer, a server, or other device with data processing capabilities.

[0089] Reference Figure 5 , Figure 5 This is a schematic diagram of the hardware structure of the electronic device of this application. In the embodiments of this application, the electronic device may include a processor, a memory, a communication interface, and a communication bus.

[0090] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0091] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces used to interconnect devices within an electronic device, as well as interfaces used to interconnect the electronic device with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0092] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0093] The processor can be a general-purpose processor, which can call a PCIe device optimized memory allocation program stored in memory and execute the PCIe device optimized memory allocation method provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit. The method executed when the PCIe device optimized memory allocation program is called can be referred to in the various embodiments of the PCIe device optimized memory allocation method of this application, and will not be repeated here.

[0094] Example 4

[0095] join Figure 6 As shown, based on the same inventive concept, this embodiment of the invention also provides a PCIe device optimized memory allocation system, which includes a memory size configuration module, an allocation strategy configuration module, a linked list modification module, and a memory allocation module.

[0096] The system includes the following modules: a memory size configuration module, used to set the required memory size for each PCIe device during PCIe enumeration using a preset memory size configuration interface; an allocation strategy configuration module, used to set the memory allocation strategy for each PCIe device using a preset allocation strategy configuration interface; a linked list modification module, used to sort the memory resource requests of each PCIe device according to the memory allocation strategy and write them into a memory request linked list when allocating memory; and a memory allocation module, used to read PCIe controller resources and allocate memory space for each PCIe device according to the order in the memory request linked list, based on the set required memory size for each PCIe device and the base address alignment principle.

[0097] As described above, the system of this embodiment allows for the reconfiguration of the memory size required by PCIe devices. When the actual memory size used by a PCIe device differs from the initial hardware configuration, the system's memory size configuration module can flexibly set the required memory size, solving the problem of existing technologies being unable to modify the required memory size. Furthermore, this method of modifying kernel code instead of ASIC hardware can significantly reduce hardware upgrade costs, resulting in practical economic benefits. Simultaneously, the system of this embodiment can also configure the memory allocation strategy for PCIe devices, meeting various memory allocation needs. It is highly flexible, adaptable to various chip requirements, and can support more PCIe devices within limited resources, satisfying practical application needs.

[0098] It should be noted that the various variations and specific examples in the foregoing method embodiments are also applicable to the system in this embodiment. Through the detailed description of the foregoing method, those skilled in the art can clearly understand the implementation method of the system in this embodiment. Therefore, for the sake of brevity, they will not be described in detail here.

[0099] Note: The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0100] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0101] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0102] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0103] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0104] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0105] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for optimizing memory allocation in a PCIe device, characterized in that, The method includes: Using a preset memory size configuration interface, the required memory size of the PCIe device is set during the PCIe enumeration process: the required memory size of the PCIe device set by the user is obtained through the memory size configuration interface; the original memory size of the PCIe device is obtained from the hardware; when the original memory size in the hardware is different from the required memory size of the PCIe device set by the user, the required memory size of the PCIe device set by the user is saved as the memory size that the PCIe device needs to request. The memory allocation strategy of the PCIe device is set using a preset allocation strategy configuration interface; the memory allocation strategy includes priority sorting, sorting from largest to smallest, and sorting from smallest to largest. When allocating memory, the memory resource requests of each PCIe device are sorted according to the memory allocation strategy and written into a memory request list: If the memory allocation strategy is sorting from largest to smallest, the memory resource requests are placed into the memory request list in descending order; if the memory allocation strategy is sorting from smallest to largest, the memory resource requests are placed into the memory request list in ascending order, and the placement method is as follows: The newly added memory resource request is checked in a loop; if it is smaller than the current head element of the list, it is inserted at the front of the list; otherwise, it is compared with each element in the list in turn, and if it is smaller than the current comparison element, it is inserted before the current comparison element; if the memory allocation strategy is priority sorting, an arbitrary sorting method is used, and the requests are sorted according to priority. Read the PCIe controller resources, and allocate memory space for each PCIe device according to the order of the memory request list, based on the set memory size required by the PCIe device and the base address alignment principle.

2. The PCIe device optimized memory allocation method as described in claim 1, characterized in that: When the memory allocation policy for PCIe devices is set to priority sorting, the priority of each PCIe device will be configured according to user needs. Specifically, the priority of the PCIe device is indicated by adding specific variables to the Linux standard structure struct pci_dev of the PCIe device.

3. The PCIe device optimized memory allocation method as described in claim 1, characterized in that, When a PCIe device actually uses less memory than its initial hardware configuration and needs to be allocated priority, the method includes: Using a preset memory size configuration interface, the memory size required by a certain PCIe device is set to the actual memory size it uses during the PCIe enumeration process; Using the preset allocation strategy configuration interface, the memory allocation strategy is set to priority sorting, and the priority of a certain PCIe device is set to the highest. When allocating memory, the memory resource requests of each PCIe device are sorted by priority and written into the memory request list; Read the PCIe controller resources, and allocate memory space for each PCIe device according to the order of the memory request list, based on the set memory size required by the PCIe device and the base address alignment principle.

4. The PCIe device optimized memory allocation method as described in claim 1, characterized in that, When a PCIe device actually uses less memory than its initial hardware configuration, and the freed-up memory is available for use by a new PCIe device, the method includes: Using a preset memory size configuration interface, the memory size required by a certain PCIe device is set to the actual memory size it uses during the PCIe enumeration process; at the same time, the required memory size is set for the new PCIe device. Configure the memory allocation strategy for PCIe devices using the preset allocation strategy configuration interface; When allocating memory, add the memory resource request of the new PCIe device, and write the memory resource requests of all current PCIe devices into the memory request chain list according to the set allocation strategy. Read the PCIe controller resources, and allocate memory space for each PCIe device according to the order of the memory request list, based on the set memory size required by the PCIe device and the base address alignment principle.

5. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 4.

6. An electronic device, characterized in that, The electronic device includes a processor, a memory, and a PCIe device optimized memory allocation program stored in the memory and executable by the processor, wherein when the PCIe device optimized memory allocation program is executed by the processor, it implements the steps of the PCIe device optimized memory allocation method as described in any one of claims 1 to 4.

7. A PCIe device optimized memory allocation system based on the method of any one of claims 1 to 4, characterized in that: The PCIe device optimized memory allocation system includes a memory size configuration module, an allocation strategy configuration module, a linked list modification module, and a memory allocation module. The memory size configuration module is used to: set the memory size required by the PCIe device during the PCIe enumeration process using a preset memory size configuration interface; The allocation strategy configuration module is used to: set the memory allocation strategy of the PCIe device using a preset allocation strategy configuration interface; The linked list modification module is used to: when allocating memory, sort the memory resource requests of each PCIe device according to the memory allocation strategy and write them into the memory request linked list; The memory allocation module is used to: read PCIe controller resources, allocate memory space to each PCIe device according to the order of the memory request list, based on the set memory size required by the PCIe device, and in combination with the base address alignment principle.

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