Data prefetching method, electronic equipment, device, medium and product

Abstract

The invention provides a data prefetching method, electronic equipment, a device, a medium and a product, and the method comprises the steps: receiving a demand address for a cache through employing a plurality of entries of a prefetcher, and carrying out the training based on the demand address, so as to recognize a streaming data rule, and generating a streaming data prefetching request; using a multi-path hit detector of the prefetcher to determine whether N entries which will generate repeated prefetch addresses exist in the plurality of entries based on the hit information of the plurality of entries; determining M selected entries from the N entries based on the information of the N entries by utilizing a multi-path hit detector; according to the method, a multipath hit detector is utilized to generate a revocation instruction for unselected entries except M entries in N entries, so that the unselected entries are forbidden to generate streaming data prefetching requests, a part of entries which will generate repeated prefetching addresses can be detected and forbidden, generation of repeated streaming data prefetching requests is avoided, and the efficiency of the streaming data prefetching is improved. Therefore, the waste of power consumption and entry bandwidth caused by repeated prefetching is avoided.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data pre-fetching method, electronic equipment, device, medium, and product. Background Art

[0002] A modern multi-issue high-performance CPU (Central Processing Unit) includes at least one processor core (CPU Core, or CPU core, processor core), and each CPU core can include multiple execution units to execute instructions. In the existing CPU architecture, program instructions and data are generally stored in DRAM memory (Dynamic Random Access Memory). The CPU core operating frequency is much higher than the DRAM memory operating frequency. Therefore, it takes hundreds of CPU core clock cycles to obtain data and instructions from the memory, which will inevitably cause the CPU core to idle due to waiting for related instructions and data, resulting in performance degradation. In response to this, modern high-performance CPUs set up a multi-level cache architecture to save recently accessed data, and use prefetchers to discover the rules of CPU data access, so as to prefetch the data and instructions to be accessed into the cache in advance. How to use prefetchers to perform efficient and accurate data prefetching is particularly important for providing high-performance processors. Summary of the invention

[0003] The embodiments of the present disclosure provide a data prefetching method, electronic device, apparatus, medium and product, which can detect and disable a portion of entries that will generate repeated prefetch addresses, thereby avoiding repeated prefetching requests that waste power consumption and bandwidth, and improving prefetching performance and the overall operating performance of the device.

[0004] According to one aspect of the present disclosure, a data prefetching method is provided. The method according to the present disclosure is applicable to an electronic device, the electronic device includes a prefetcher and a cache, wherein the prefetcher includes multiple entries and a multi-way hit detector, the method includes: using multiple entries to receive a demand address for the cache, and training based on the demand address to identify the regularity of streaming data and generate a streaming data prefetching request, wherein each entry in the multiple entries is independently trained and generates a streaming data prefetching request; and using the multi-way hit detector to determine whether there are N entries in the multiple entries that will generate repeated prefetching addresses based on the hit information of the multiple entries, wherein N is an integer greater than 1; in the case of determining that there are N entries, using the multi-way hit detector to determine M selected entries from the N entries based on the information of the N entries, wherein M is an integer greater than or equal to 1 and less than N; and using the multi-way hit detector to generate a disqualification instruction for unselected entries other than the M entries in the N entries, so as to prohibit the unselected entries from generating streaming data prefetching requests.

[0005] According to some embodiments of the present disclosure, the multi-way hit detector is implemented as a pipeline, independent of the multiple entries, and performs multi-way hit detection in parallel with the training and pre-fetching process of the multiple entries.

[0006] According to some embodiments of the present disclosure, the demand address is a virtual address corresponding to a load instruction or a store instruction.

[0007] According to some embodiments of the present disclosure, determining whether there are N entries among the multiple entries that will generate duplicate prefetch addresses based on hit information of multiple entries using a multi-way hit detector includes: determining that there are N entries that will generate duplicate prefetch addresses when the required address simultaneously hits N entries in the same direction of streaming data and are in prefetch mode or in training mode; or determining that there are N entries that will generate duplicate prefetch addresses when the required address simultaneously hits N entries in the same direction of streaming data and are in prefetch mode or in prefetch mode.

[0008] According to some embodiments of the present disclosure, M is equal to 1, and using a multi-way hit detector to determine M selected entries from N entries based on information of the N entries includes: determining an entry with the highest confidence parameter from the N entries as the selected entry based on information of the N entries.

[0009] According to some embodiments of the present disclosure, M is equal to 1, and using a multi-way hit detector to determine M selected entries from N entries based on information of the N entries includes: determining the entry that is allocated earliest in time from the N entries as the selected entry based on information of the N entries.

[0010] According to some embodiments of the present disclosure, M is equal to 1, and using a multi-way hit detector to determine M selected entries from N entries based on information of the N entries includes: determining the entry with the smallest or largest entry number from the N entries as the selected entry based on the information of the N entries.

[0011] According to some embodiments of the present disclosure, the prefetcher further includes a prefetch request generator. According to the data prefetch method of the embodiment of the present disclosure, the prefetch request generator further includes: generating a streaming data prefetch request based on the M selected entries, the streaming data prefetch request being used to perform a streaming data prefetch process based on the cache.

[0012] According to some embodiments of the present disclosure, a streaming data pre-fetch request is used to perform a streaming data pre-fetch process based on a first-level cache, a second-level cache, and a last-level cache of a cache.

[0013] According to another aspect of the present disclosure, an electronic device is provided. The electronic device includes a prefetcher and a cache, the prefetcher is configured to include multiple entries and a multi-way hit detector, the multiple entries are configured to: receive a demand address for the cache, and train based on the demand address to identify streaming data rules and generate streaming data prefetch requests, wherein each entry in the multiple entries is independently trained and generates streaming data prefetch requests; and the multi-way hit detector is configured to: determine whether there are N entries in the multiple entries that will generate repeated prefetch addresses based on hit information of the multiple entries, wherein N is an integer greater than 1; in the case of determining that there are N entries, determine M selected entries from the N entries based on information of the N entries, wherein M is an integer greater than or equal to 1 and less than N; and generate a disqualification instruction for unselected entries other than the M entries in the N entries, so as to prohibit the unselected entries from generating streaming data prefetch requests.

[0014] According to some embodiments of the present disclosure, the multi-way hit detector is implemented as a pipeline, independent of the multiple entries, and performs multi-way hit detection in parallel with the training and pre-fetching process of the multiple entries.

[0015] According to some embodiments of the present disclosure, the demand address is a virtual address corresponding to a load instruction or a store instruction.

[0016] According to some embodiments of the present disclosure, the multi-way hit detector determines whether there are N entries among the multiple entries that will generate duplicate prefetch addresses based on hit information of the multiple entries, including: when the required address simultaneously hits N entries in the same direction of the streaming data and are in the prefetch mode, or in the training mode, determining that there are N entries that will generate duplicate prefetch addresses; or, when the required address simultaneously hits N entries in the same direction of the streaming data and are in the prefetch mode, or are in the prefetch mode, determining that there are N entries that will generate duplicate prefetch addresses.

[0017] According to some embodiments of the present disclosure, M is equal to 1, and the multi-way hit detector determines M selected entries from N entries based on information of the N entries, including one of the following: determining the entry with the highest confidence parameter from the N entries as the selected entry based on information of the N entries; determining the entry that is allocated earliest in time from the N entries as the selected entry based on information of the N entries; or, determining the entry with the smallest or largest entry number from the N entries as the selected entry based on information of the N entries.

[0018] According to some embodiments of the present disclosure, the prefetcher further includes a prefetch request generator configured to generate a streaming data prefetch request based on the M selected entries, wherein the streaming data prefetch request is used to perform a streaming data prefetch process based on the cache.

[0019] According to some embodiments of the present disclosure, a streaming data pre-fetch request is used to perform a streaming data pre-fetch process based on a first-level cache, a second-level cache, and a last-level cache of a cache.

[0020] According to some embodiments of the present disclosure, the electronic device also includes a read-write unit, wherein the prefetcher is located in the read-write unit of the electronic device, and the read-write unit also includes a read-write queue and an arbitrator, wherein the read-write queue is configured to: generate demand access based on information of the read-write operation; the arbitrator is configured to: generate data access requests based on the demand access of the read-write queue and the streaming data prefetch request generated by the prefetch, the data access request corresponds to the demand address, wherein the prefetcher performs training and prefetching based on the demand address.

[0021] According to another aspect of the present disclosure, an electronic device is provided, which includes a processor and a memory, wherein a computer-readable code is stored in the memory, and when the computer-readable code is executed by the processor, the processor executes the steps of the data pre-fetching method according to an embodiment of the present disclosure.

[0022] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the processor executes the steps of the data prefetching method according to an embodiment of the present disclosure.

[0023] According to another aspect of the present disclosure, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the processor executes the steps of the data pre-fetching method according to the embodiment of the present disclosure.

[0024] According to the data prefetching method, electronic device, apparatus, medium and product provided by the embodiments of the present disclosure, multiple entries of the prefetcher are used to independently train and generate streaming data prefetching requests, thereby reducing the requirements for the pipeline depth of the entries. On the basis of ensuring the rapid training of multiple entries, the hardware implementation area of ​​the multiple entries of the prefetcher can also be controlled. Further, the multi-way hit detector of the prefetcher is used to perform repeated detection on multiple entries in parallel, that is, based on the hit information of multiple entries, it is determined whether there are entries in the multiple entries that will generate repeated prefetch addresses, and a part of the entries that will generate repeated prefetch addresses are prohibited, so as to ensure that the subsequent prefetching process will no longer repeatedly hit multiple entries, and multiple entries will not issue prefetching requests for repeated addresses, thereby avoiding the waste of power consumption and entry bandwidth caused by repeated prefetching, thereby improving the prefetching performance of the prefetcher and improving the overall operating performance of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0026] Figure 1 A schematic block diagram of a read / write unit in a processor and a hardware pre-fetch module thereof is shown;

[0027] Figure 2 A schematic block diagram of a streaming data prefetcher is shown;

[0028] Figure 3 A schematic diagram showing a stream prefetch entry load is shown;

[0029] Figure 4A A schematic flow chart of a training process of a streaming data prefetcher is shown;

[0030] Figure 4B A schematic flow chart of a pre-fetching process performed by a streaming data pre-fetcher is shown;

[0031] Figure 5 A schematic flow chart of a data pre-fetching method according to an embodiment of the present disclosure is shown;

[0032] Figure 6 shows an execution flow chart of a multi-way hit detector according to an embodiment of the present disclosure;

[0033] Fig. 7A An example pre-fetch process diagram in the related art is shown;

[0034] Figure 7B An example prefetch process diagram according to an implementation of the present disclosure is shown;

[0035] Fig. 8A A schematic block diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0036] Figure 8B An exemplary structural diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0037] Fig. 9 A schematic block diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0038] Fig.10 A schematic diagram of the architecture of an exemplary electronic device according to an embodiment of the present disclosure is shown;

[0039] Fig.11 A schematic block diagram of a storage medium according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] In addition, as shown in the present disclosure and claims, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not specifically refer to the singular, but may also include the plural. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0042] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0043] First, terms that may be involved in at least some embodiments of the present disclosure are explained as follows.

[0044] An electronic device usually includes one or more processor cores (CPU Core) and a cache, which can be implemented as a multi-level cache architecture. In the multi-level cache architecture, the first-level (L1) cache memory has the fastest access speed but the smallest capacity and is usually set in the processor core; the last-level (LLC, generally the third level) cache memory has the largest capacity and the slowest access speed and is usually shared by multiple processor cores; the second-level (L2) cache memory has an access speed and capacity between the L1 cache memory and the LLC cache memory and can usually also be set in the processor core.

[0045] Data Prefetch: In the CPU structure, program instructions and data can be stored in the Dynamic Random Access Memory (DRAM). The operating frequency of the processor core is much higher than the operating frequency of the DRAM memory. Therefore, it takes hundreds of processor core clock cycles to obtain data and instructions from the memory, causing the processor core to idle while waiting for related instructions and data, resulting in performance loss. Therefore, modern high-performance electronic devices all contain a multi-level cache architecture to save recently accessed data, and use prefetchers to discover the data access patterns of the CPU in order to prefetch the data and instructions that will be accessed into the cache in advance.

[0046] Prefetcher: The prefetcher can be divided into a first-level data prefetcher (i.e., a data prefetcher that prefetches the target data into the first-level cache memory (L1 Cache)), a second-level data prefetcher (i.e., a data prefetcher that prefetches the target data into the second-level cache memory (L2 Cache)), a last-level data prefetcher (i.e., a data prefetcher that prefetches the target data into the last-level cache memory (LLC Cache)), etc.

[0047] It is understandable that if the prefetcher generates too many inaccurate prefetch requests, it will in turn lead to problems such as longer memory access latency and increased cache pollution, which will have a significant negative impact on CPU performance and ultimately lead to reduced performance. This problem is more obvious for CPUs that support SMT (Simultaneous Multithreading, also known as concurrent multithreading).

[0048] Prefetch Metrics: Prefetch performance metrics are the standards for evaluating the prefetch performance of the prefetcher, which can include accuracy, coverage, and lateness. Accuracy is the ratio of the number of correct prefetches to the total number of prefetches; Coverage refers to the ratio of the number of demand requests (requests generated by memory access instructions in the program) that hit the prefetch data to the total number of demand requests; Lateness refers to the ratio of the number of prefetches that are correct but issued too late to the total number of prefetches. It is often difficult to take both Accuracy and Coverage into account at the same time.

[0049] Load-Store Unit (LSU): A read-write unit, also called a load-store unit, can be configured inside the CPU core. It is the execution unit in the CPU responsible for processing storage and loading instructions, and usually also includes an L1 cache.

[0050] Load-Store Queue (LSQ): It is a queue in the LSU that stores the information required for read and write operations (Load-Store Operation).

[0051] Cache Line (CL): The minimum granularity of data storage in the data cache.

[0052] Miss Status Handling Register (MSHR): used to record each incomplete cache miss event. The recorded information usually includes address, thread ID, etc. The occupancy rate of MSHR can represent the memory usage rate. If the occupancy rate of MSHR is high, it can reflect that the prefetcher has more cache miss events, that is, the prefetch accuracy is reduced, and the memory usage rate is at a relatively high level.

[0053] Translation Lookaside Buffer (TLB): It can also be called page table cache, translation bypass cache, etc. It is a kind of CPU cache used by the memory management unit to improve the translation speed of virtual addresses to physical addresses. TLB has a fixed number of space slots for storing tag page table entries that map virtual addresses to physical addresses. Its search keyword is the virtual memory address, and its search result is the physical address. If the requested virtual address exists in the TLB, the content-addressable memory (CAM) will give a very fast match result, and then the obtained physical address can be used to access the memory. If the requested virtual address is not in the TLB, the tag page table will be used for virtual-to-real address conversion, and the access speed of the tag page table is much slower than that of the TLB.

[0054] In related technologies, in order to improve the operating efficiency of the CPU, a hardware prefetch module (HWPF) is usually implemented inside the LSU. This module moves the data required by the program flow being executed by the thread to the data cache in advance, thereby increasing the speed of data access. In order to achieve this goal, the hardware prefetch module HWPF needs to predict the addresses that may be accessed in the future based on the address sequence of the current data access. For HWPF, a common address sequence pattern is called "streaming data", that is, data is read and written to the memory in sequence in the order of increasing or decreasing virtual addresses with CL as the granularity. After the streaming data prefetch module identifies such an access sequence in the "training" stage, it enters the "prefetch" state to issue the next prefetch request to the downstream in advance according to the direction of increasing or decreasing the sequence, so as to prefetch the streaming data that may be accessed into the cache in advance.

[0055] In order to identify streaming data with different starting addresses, multiple entries are usually set in HWPF, and each entry can be "trained" separately. The pipeline depth of the training will directly affect the hardware area of ​​the prefetch module. In the actual program execution process, due to various reasons, such as the program flow itself has memory access order jumps back and forth, modern high-performance processors execute instructions in an out-of-order manner, etc., the same streaming data may be identified as multiple streaming data and allocated to multiple entries. As a result, multiple entries will repeat "training" and "prefetching", which will cause power consumption and subsequent waste of storage resources and pipeline bandwidth.

[0056] In response to the technical problems caused by repeated "training" and "prefetching" in the hardware prefetch module HWPF used for streaming data prefetching, the present disclosure provides a data prefetching method for detecting and prohibiting a part of entries that will generate repeated prefetch addresses, thereby avoiding repeated prefetch requests that waste power consumption and bandwidth, and improving prefetching performance and the overall operating performance of the device.

[0057] Specifically, using the data prefetching method provided by the embodiment of the present disclosure, for a prefetcher (e.g., HWPF), multiple entries are independently trained and streaming data prefetch requests are generated, thereby reducing the requirements for the pipeline depth of the entries, and on the basis of ensuring the rapid training of multiple entries, the hardware implementation area of ​​the multiple entries of the prefetcher can also be controlled. Furthermore, the multi-way hit detector of the prefetcher performs repeated detection on multiple entries in parallel, that is, based on the hit information of multiple entries, it is determined whether there are entries in the multiple entries that will generate repeated prefetch addresses, and a part of the entries that will generate repeated prefetch addresses are prohibited, ensuring that the subsequent prefetch process no longer repeatedly hits multiple entries, and multiple entries will not issue prefetch requests for repeated addresses, thereby avoiding the waste of power consumption and entry bandwidth caused by repeated prefetching, thereby improving the prefetch performance (Prefetch Metrics) of the prefetcher and improving the overall operating performance of the electronic device.

[0058] In order to facilitate the understanding of the scheme of the present disclosure, before describing in detail the implementation process of the data prefetching method provided by the present disclosure, the implementation process of the hardware prefetching module HWPF in the LSU and the functions involved therein will be briefly described in conjunction with the accompanying drawings. It can be understood that when any component in this document appears in more than one accompanying drawing, the component is represented by the same or similar reference numeral in each of the accompanying drawings.

[0059] As an example, Figure 1 The schematic block diagram shows the load-store unit (LSU) in the processor and its hardware prefetch module HWPF. Figure 1 First, the front end sends the load, store operation and address information (shown as ld / st op) to the LSU, and generates demand access (Demand Access) through the read-write queue LSQ. After that, these operations enter the data access pipeline (Data access pipe) through the arbiter and start execution.

[0060] Load / Store operations (ld / st op) perform address conversion on the pipeline by accessing the TLB, and compare and confirm whether it hits the L1 cache by accessing the tag array (Tag). For Load operations, if the L1 cache is hit, the corresponding data is read from the data cache and returned; if the L1 cache is not hit, it is necessary to continue to send read requests to downstream caches such as L2 caches, and save the requests in MSHR; when the downstream returns data to fill the L1 cache, wake up the original Load operation to re-enter the pipeline and return the corresponding data. For Store operations, if the L1 cache is hit and has an exclusive state, the corresponding data is written to the data cache; otherwise, it is also necessary to send a read request to the downstream L2 cache to obtain a writable state, and save the request in MSHR; when the downstream returns data to fill the L1 cache, wake up the original Store operation to re-enter the pipeline and complete the writing of the corresponding data. For example, in Figure 1 Shown in the figure is Store Data (STD).

[0061] It is understandable that a hit cache can greatly speed up the completion of the Load / Store operation. Therefore, a hardware prefetch module HWPF can also be configured in the LSU module. HWPF attempts to identify a regular memory access address sequence by grabbing the ld / st op information on the pipeline as input. Specifically, as a form of prefetcher, the streaming data prefetcher is responsible for identifying the streaming data sequence in the memory access. When the streaming data prefetcher confirms that a streaming data sequence has been identified through "training", the prefetcher enters the "prefetch" state and then starts to send prefetch requests. It is assumed here that the address in the prefetch request is a virtual address. The prefetch request and the Load / Store request are similar to each other and must pass through the arbitrator before entering the pipeline, access the TLB for address conversion, and access the tag array (Tag) to confirm whether it hits the L1 cache. If it hits the L1 cache, no prefetching is required. If the L1 cache is not hit, a corresponding request needs to be sent to the downstream L2 cache and the request is saved in the MSHR; the prefetch request is completed when the downstream returns data to fill the L1 cache.

[0062] As described above, during the actual program execution process, due to various reasons, such as the program flow itself has memory access order jumps back and forth, modern high-performance processors execute instructions in an out-of-order manner, etc., the same streaming data may be identified as multiple streaming data and stored in multiple entries. As a result, multiple entries will be repeatedly "trained" and "pre-fetched". When the pre-fetch request with the same address is put into the pipeline, it will cause power consumption and subsequent storage resources and pipeline bandwidth waste.

[0063] then, Figure 21 shows a schematic block diagram of a streaming data prefetcher. Next, a general block diagram of a streaming data prefetcher is introduced, such as Figure 2 As shown, the streaming data prefetcher can be configured with multiple entries for training multiple streaming data at the same time. Here, 32 entries are taken as an example (streaming entry 0 to streaming entry 31). After the access address (ld / stop) is sent to the input end of the entry, the access address is sent to the 32 entries at the same time for matching. Each entry is independent of each other and can be trained and send prefetch requests at the same time. Specifically, the streaming data prefetcher first works in the "training" stage. After identifying such a streaming access sequence, it will enter the "prefetch" state to issue the next prefetch request to the downstream in advance according to the direction of the sequence increase or decrease, so as to prefetch the streaming data that may be accessed into the cache in advance. The prefetch request of each streaming entry must also pass through the selector (Stream Prefetch Picker) to reach the stream prefetch generator (Stream Prefetch Generation), and finally issue a streaming data prefetch request (Prefetch Request).

[0064] In addition, in order to implement the above training and prefetching process, each entry of the streaming data prefetcher needs to store some information to record the training and prefetching information of the streaming data prefetching. Figure 3 A schematic diagram of the above streaming prefetch entry load is shown.

[0065] Figure 3 The meanings of the various parameters shown in are as follows:

[0066] Valid: This is the entry validity bit, which is set to 1 when the entry is allocated;

[0067] Dir: Direction, used to identify the increasing / decreasing direction of streaming data. This variable is created when the streaming mode sequence training is completed.

[0068] Conf: Confidence, whose value range can be from 0 to the set maximum value (for example, 3). When the training is completed, Conf is set from 0 to 1. The larger the confidence, the more times the sequence is hit, so the expected prefetch accuracy of this sequence is higher, so the offset of the prefetch address can also be set relatively larger;

[0069] BaseAddr: Base Address, used to identify the starting address of the streaming mode sequence, which is updated when training is completed and entries are refreshed;

[0070] AccVec: Access Vector, a bit vector used to track whether a block has been accessed on demand, with CL as the granularity, for example 64 bits (64B);

[0071] DmdPtr: Demand Pointer, used to track the relative position of the access address and BaseAddr. If the new access address lags behind the current DmdPtr, it will not change;

[0072] PfPtr: Current prefetch pointer (Prefetch Pointer). Based on the above parameters, the next L1 prefetch request address can be expressed as (BaseAddr + (L1PfPtr+1) * 64B).

[0073] As a specific implementation example, the present disclosure also provides Figure 4A and Figure 4B ,in Figure 4A A schematic flow chart of the training process of the streaming data prefetcher is shown. Figure 4B A schematic flow chart of the pre-fetching process of the streaming data pre-fetcher is shown. Next, the training process and the pre-fetching process of the streaming data pre-fetcher are described.

[0074] like Figure 4A As shown, when the required address enters the streaming data prefetcher (S401), it is first compared with the BaseAddr in each entry to determine whether it hits the entry (S402). If the comparison result between the required address and the BaseAddr is within a certain range (the range of the training mode and the prefetch mode may be different), the entry is considered to hit. Otherwise, if the required address does not hit the entry, for example, when certain conditions are met (such as MSHR is allocated), a new entry is allocated for it (S403), and the state of the newly allocated entry is initialized, for example, the valid bit Valid of the newly allocated entry is set to 1, the BaseAddr is set to the required address, and Conf is set to 0. At this time, the newly allocated entry enters the training mode.

[0075] Next, at S404, it is determined whether the current entry is in a training state. If it is determined to be in a training state, relevant state information can be updated according to the address (S405). For example, if the required address is within a certain range, for example, [BaseAddr-n, BaseAddr+n] (assuming n=2), the access vector AccVec is used to record the corresponding access information. AccVec can be reused here, or another hardware resource can be used to record the bit vector.

[0076] Next, in S406, it is determined whether the training of the current entry is completed. When BaseAddr-1, BaseAddr-2 or BaseAddr+1, BaseAddr+2 are all accessed, that is, three consecutive accesses with increasing / decreasing addresses are found. At this time, the training of the current entry is considered completed, the entry status is updated, and the entry enters the prefetch mode (S407). The update of the entry status here can include: setting the confidence Conf to 1, updating Dir to the corresponding value according to the increasing / decreasing rule of the address (for example, 0 represents increasing, 1 represents decreasing), updating BaseAddr to BaseAddr+ / -2, setting DmdPtr to 0, and setting PfPtr to 0. Thus, the entry enters the prefetch mode. At this time, a prefetch request can be sent starting from PfPtr=0, and the request address is BaseAddr+ / -1. If the training of the current entry is not completed, then S408 is performed, that is, the training status is updated according to the address.

[0077] For step S404, when the current entry is not in the training state, S409 is performed to determine whether the demand address exceeds the range (for example, [BaseAddr-n, BaseAddr+n]). If it exceeds the range, the entry is refreshed and the prefetch status is updated according to the address (S410). If it does not exceed the range, the relevant status is updated according to the address (S411). The update here can refer to S407 for example.

[0078] Reference Figure 4B , shows a schematic flowchart of the prefetch process of the streaming data prefetcher.

[0079] First, in S412, the entry enters the prefetch mode. Next, in S413, it can be determined whether the parameter PfPtr reaches the current maximum value. If so, wait for the entry to be refreshed or DmdPtr to be updated (S414). If not, then the subsequent S415-S417 are performed, that is, a prefetch request is generated, wait for arbitration, and update PfPtr.

[0080] After the prefetch request is sent, PfPtr is incremented. If the new PfPtr is still within the range, continue to send the next prefetch request. The maximum distance of the prefetch request is determined by DmdPtr and Conf: PfPtr<DmdPtr+Dist[Conf]; Conf determines the maximum interval Dist between PfPtr and DmdPtr. The larger Conf is, the larger Dist is; the Dist values under different Conf can be fixed in the hardware implementation, software configurable, or dynamically adjusted according to the processing situation of the current memory access request during operation.

[0081] After an entry enters the prefetch mode, the bit vector AccVec can be used to continue recording the status of the address in the streaming sequence within a certain observation window being requested by the required address; the observation window depth Depth can be implemented differently depending on the specific design. It can be a fixed value, or it can be changed based on the value of Conf, or it can be dynamically adjusted during operation according to the processing of the current memory access request. When a prefetch request is generated, if the AccVec bit corresponding to the address corresponding to PfPtr is 1, it means that this address has been accessed. At this time, PfPtr can skip this address and directly prefetch the next one. The search depth of AccVec when a prefetch request is generated can vary depending on the specific implementation, or it can remain unchanged.

[0082] After the entry enters the prefetch mode, DmdPtr records the farthest required address relative to BaseAddr. When DmdPtr exceeds the observation window depth Depth, the entry needs to be refreshed. At this time, the number of bits 1 recorded in AccVec is counted. If the count exceeds a certain threshold, Conf = Conf+1; if the count is less than a certain threshold, Conf = Conf-1; otherwise, Conf remains unchanged. If the entry is still in the prefetch mode after the refresh, other parameters in the entry are updated at the same time:

[0083] BaseAddr = BaseAddr + / -Depth

[0084] DmdPtr=DmdPtr-Depth

[0085] PfPtr=PfPtr-Depth

[0086] AccVec = AccVec << Depth

[0087] The various thresholds described above can be implemented differently depending on the specific design. They can be a fixed value, or they can change in size based on the value of Conf, or they can be dynamically adjusted during operation according to the processing of the current memory access request. When Conf drops to 0, the entry will fall back to the training mode, go through the training process described above, and re-enter the prefetch mode after meeting certain conditions. When the entry Conf>0, the entry enters the "prefetch" mode and starts to generate prefetch requests. When multiple entries enter the "prefetch" mode at the same time to generate prefetch requests, an entry is first selected through the selector, and then the corresponding prefetch request is generated according to the information in the entry. When the prefetch request is sent, the PfPtr of the selected entry is updated. Sending completion means that the request is successfully received by the next-level module. In the implementation here, the next-level module can be a prefetch request queue, or there can be other implementation methods.

[0088] It can be seen that each streaming mode prefetch entry has an independent training and prefetch process. When the required address enters the streaming data prefetcher, it is sent to each entry at the same time and trained at the same time. In some software scenarios or due to the out-of-order emission and execution of the processor, the same streaming data may be trained by multiple streaming entries at the same time. For the repeated "training" and "prefetching" of multiple entries, when the prefetch request with the same address is put into the pipeline, it will cause power consumption and subsequent storage resources and pipeline bandwidth waste.

[0089] The present disclosure provides a data pre-fetching method, which can detect and prohibit a part of entries that will generate repeated pre-fetching addresses, thereby avoiding repeated pre-fetching requests to waste power consumption and bandwidth, and improving pre-fetching performance and overall operation performance of the device.

[0090] Specifically, using the data prefetching method provided by the embodiment of the present disclosure, for a prefetcher (e.g., HWPF), multiple entries are independently trained and streaming data prefetch requests are generated, thereby reducing the requirements for the pipeline depth of the entries, and on the basis of ensuring the rapid training of multiple entries, the hardware implementation area of ​​the multiple entries of the prefetcher can also be controlled. Furthermore, the multi-way hit detector of the prefetcher performs repeated detection on multiple entries in parallel, that is, based on the hit information of multiple entries, it is determined whether there are entries in the multiple entries that will generate repeated prefetch addresses, and a part of the entries that will generate repeated prefetch addresses are prohibited, ensuring that the subsequent prefetch process no longer repeatedly hits multiple entries, and multiple entries will not issue prefetch requests for repeated addresses, thereby avoiding the waste of power consumption and entry bandwidth caused by repeated prefetching, thereby improving the prefetching performance of the prefetcher and improving the overall operating performance of the electronic device.

[0091] The data pre-fetching method of the present disclosure will be described below in conjunction with the accompanying drawings. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted.

[0092] The data prefetching method according to the embodiment of the present disclosure is applicable to an electronic device, which may include a prefetcher and a cache. The prefetcher here may refer to the streaming data prefetcher described above in conjunction with the accompanying drawings, which includes multiple entries for streaming data prefetching. Furthermore, the prefetcher according to the present disclosure may also be configured with a multi-way hit detector. As an implementation method, the multi-way hit detector may be implemented in the form of a pipeline in hardware, and a repeated sequence judgment process is performed in parallel with the entries of the prefetcher to identify multi-way hit situations of more than one entry.

[0093] Figure 5 A schematic flow chart of a data pre-fetching method according to some embodiments of the present disclosure is shown, and the method includes steps S501-S504.

[0094] Step S501: receiving a demand address for a cache using multiple entries, and performing training based on the demand address to identify streaming data patterns and generate streaming data pre-fetch requests, wherein each entry in the multiple entries is independently trained and generates streaming data pre-fetch requests.

[0095] According to some embodiments of the present disclosure, the required address is a virtual address corresponding to a load instruction or a store instruction. Specifically, this step S501 can be combined with Figure 2 Description, such as entry 0 to entry 31 all receive ld / st op information and are trained in parallel to recognize streaming data patterns and generate possible prefetch requests.

[0096] Step S502: using a multi-way hit detector to determine whether there are N entries in the multiple entries that will generate duplicate prefetch addresses based on hit information of the multiple entries, where N is an integer greater than 1.

[0097] In the solution disclosed herein, a multi-way hit detector is added to the streaming data prefetcher to specifically remove duplicate hit entries of the streaming data prefetcher, and the multi-way hit detection and processing flow is independent of the training and prefetching process of each streaming entry, and does not affect the training and prefetching pipeline of each entry.

[0098] According to some embodiments of the present disclosure, determining whether there are N entries among the multiple entries that will generate duplicate prefetch addresses based on hit information of multiple entries using a multi-way hit detector includes: determining that there are N entries that will generate duplicate prefetch addresses when the required address simultaneously hits N entries in the same direction (Dir) of the streaming data and are in prefetch mode or in training mode; or determining that there are N entries that will generate duplicate prefetch addresses when the required address simultaneously hits N entries in the same direction (Dir) of the streaming data and are in prefetch mode or in prefetch mode.

[0099] It is understandable that the judgment condition of multiple hits may be implemented differently depending on the specific design. As an example, in a certain implementation, the multiple hit detector will determine whether the required address hits multiple entries at the same time, and if it is determined that multiple entries are hit, it is determined that there is a multiple hit situation.

[0100] Next, in step S503 : when it is determined that there are N entries, a multi-way hit detector is used to determine M selected entries from the N entries based on information of the N entries, where M is an integer greater than or equal to 1 and less than N.

[0101] As an implementation, M may be equal to 1, that is, one entry is directly determined from the multi-way hit entries as the selected entry, and on this basis, the entries other than the selected entry in the N entries are all regarded as unselected entries. As another implementation, M may also be set to a value less than N according to the specific situation. For example, when N is 4, two entries may be selected as the selected entries, and the other two entries may be regarded as unselected entries.

[0102] As an implementation, M is equal to 1. In this case, using the multi-way hit detector to determine M selected entries from the N entries based on the information of the N entries includes: determining the entry with the highest confidence parameter from the N entries as the selected entry based on the information of the N entries. That is, for the N entries with multiple hits, the entry with the highest confidence Conf value is determined as the selected entry, and the remaining entries are determined as unselected entries.

[0103] As another implementation, M is equal to 1. In this case, using the multi-way hit detector to determine M selected entries from the N entries based on the information of the N entries includes: determining the entry that is allocated earliest in time from the N entries based on the information of the N entries as the selected entry. That is, for the N entries with multi-way hits, the selected entry is determined according to the allocation time of the entry.

[0104] As another implementation, M is equal to 1. In this case, using the multi-way hit detector to determine M selected entries from N entries based on information of the N entries includes: determining the entry with the smallest or largest entry number from the N entries as the selected entry based on information of the N entries. Figure 2 For N entries with multiple hits, the selected entry is determined according to the serial number value of the entry, for example, the entry with the smallest serial number is determined as the selected entry. Assuming that in step S502, entry 0 and entry 2 are determined as two entries that will generate duplicate prefetch addresses, in this implementation, entry 0 can be used as the selected entry and entry 2 can be used as the unselected entry.

[0105] Next reference Figure 5 , in step S504: using the multi-way hit detector, generating a disabling instruction for the unselected entries except the M entries among the N entries, so as to prohibit the unselected entries from generating streaming data pre-fetching requests.

[0106] According to an embodiment of the present disclosure, the multi-way hit detector first detects whether there are multiple entries hit. When multiple entries hit, the selected entry is determined according to certain rules. For the unselected entries, for example, an entry disqualification signal, or an entry invalidation signal, can be issued to stop these repeated entries from continuing to generate subsequent prefetch requests, that is, to reduce duplicate entries. As an example, the entry resources that receive the disqualification signal will be released for streaming data training and prefetching processes based on subsequent demand addresses. In addition, since the multi-way hit detector detects and disqualifies multiple entries in the hardware prefetch module, it can intervene before issuing a prefetch request, avoiding the impact of repeated prefetch requests on prefetch training, and avoiding these repeated prefetch requests from occupying resources such as pipelines and caches, which is beneficial to improving prefetch performance and improving the overall performance of the processor.

[0107] According to some embodiments of the present disclosure, the prefetcher may further include a prefetch request generator. The data prefetch method according to the embodiment of the present disclosure also includes: using the prefetch request generator to generate a streaming data prefetch request based on the M selected entries, and the streaming data prefetch request is used to perform a streaming data prefetch process based on the cache. That is to say, for the selected entry, no other operations may be performed, and the subsequent prefetch process may be continued according to the original implementation method, which is not limited here.

[0108] According to some embodiments of the present disclosure, a streaming data prefetch request is used to perform a streaming data prefetch process based on a first-level cache, a second-level cache, and a last-level cache of a cache. As described above, according to the cache location to which the target data is prefetched, the prefetcher can be divided into an L1 prefetcher, an L2 prefetcher, an LLC prefetcher, and the like. The data prefetching method according to an embodiment of the present disclosure can be applied to any of the above-mentioned L1 prefetchers, L2 prefetchers, and LLC prefetchers, that is, there is no requirement for the scope of application.

[0109] According to some embodiments of the present disclosure, the multi-way hit detector is implemented as a pipeline, independent of the multiple entries, and the multi-way hit detection is performed in parallel with the training and pre-fetching process of the multiple entries. According to the embodiments of the present disclosure, the processing flow of the multi-way hit detector may be a pipeline in actual implementation, and the pipeline of the multi-way hit detector and the pipeline of the streaming entry are independent of each other, and the pipeline levels of the two are determined by the timing of their respective specific implementation logic.

[0110] It is precisely because the detection process of the multi-way hit detector according to the present disclosure is independent of multiple entries, and the multi-way hit detection is performed in parallel with the training and pre-fetching process of multiple entries, that the pipeline levels of the detector and the entry can be further saved and the power consumption can be reduced. This is because if the judgment of multi-way hits is added to each entry in the training pipeline, it will cause additional timing pressure. In order to realize the relevant logic, the training pipeline level of each entry needs to be increased, which not only increases the resource consumption of the hardware, but also the increased pipeline level will bring greater pre-fetching delay. More importantly, for scenarios where multi-way hits do not occur, the increased logic and level will bring additional power consumption waste and performance loss.

[0111] Figure 6 FIG. 4 shows an execution flow chart of a multi-way hit detector according to an embodiment of the present disclosure, as shown in FIG. Figure 6 As shown, in step S601, the required address enters the streaming data prefetcher, and then it is determined whether the address hits multiple entries (S602). If there is a multi-way hit, the entry with the highest priority is determined from the multiple hit entries (S603), for example, the entry with the highest confidence value Conf is used as the selected entry. Then, in S604, the entry with the highest priority is retained, and other unselected entries are abolished. If there is no multi-way hit, the multi-way hit detector does not perform other operations (S605).

[0112] Next, combine Fig. 7A and Figure 7B , a specific example of implementing multi-way hit detection according to the data prefetching method disclosed in the present invention is given. Assume that each entry of the streaming data prefetcher is empty, that is, in the initial state. Next. The input demand address sequence is represented as A, A+5, A+1, A+2, A+6, A+7, A+3, A+4, A+8, A+9 in sequence. It can be seen that the sequence is a disordered streaming sequence.

[0113] First, refer to Fig. 7A The situation shown is that no parallel multi-way hit detection is added, assuming that the hit situation of the above required address sequence is as follows:

[0114] Address A is assigned entry 0; address A+5 is assigned entry 1;

[0115] Afterwards, addresses A+1, A+2 hit entry 0, and entry 0 enters prefetch mode;

[0116] Afterwards, address A+6, A+7 hits entry 0, and entry 0 updates the status AccVec and DmdPtr; at the same time, address A+6, A+7 hits entry 1, and entry 1 enters the prefetch mode;

[0117] Afterwards, addresses A+3 and A+4 hit entry 0, and entry 0 updates the state AccVec;

[0118] Afterwards, addresses A+8 and A+9 hit entry 0, and entry 0 updates the status AccVec and DmdPtr; at the same time, addresses A+8 and A+9 hit entry 1, and entry 1 updates the status AccVec and DmdPtr.

[0119] After the above required address sequence is input, finally, the BaseAddr of entry 0 is A+2, DmdPtr=7, assuming the confidence Conf of entry 0 is 1, and the interval Dist=5; then entry 0 can issue a total of 12 prefetch requests, with an address range of A+3~A+14; finally, the BaseAddr of entry 1 is A+7, DmdPtr=2, assuming the confidence Conf of entry 1 is 1, and the interval Dist=5; then entry 1 can issue a total of 7 prefetch requests, with an address range of A+8~A+14; it can be seen that the prefetch address of entry 1 is completely within the prefetch address range of entry 0, and the prefetch address requests issued by the two entries are repeated. Repeated processing of prefetch requests will inevitably cause waste of bandwidth and power consumption of subsequent execution units and loss of performance.

[0120] Next, refer to Figure 7B , which shows the training of the streaming data prefetcher after adding the multi-way hit detector, so that the hit situation of the above-mentioned demand address sequence A, A+5, A+1, A+2, A+6, A+7, A+3, A+4, A+8, A+9 is the same as Fig. 7A The situation shown is the same, namely:

[0121] Address A is assigned entry 0; address A+5 is assigned entry 1;

[0122] Afterwards, addresses A+1, A+2 hit entry 0, and entry 0 enters prefetch mode;

[0123] Afterwards, address A+6, A+7 hits entry 0, and entry 0 updates the status AccVec and DmdPtr; at the same time, address A+6, A+7 hits entry 1, and entry 1 enters the prefetch mode;

[0124] refer to Figure 7B , due to the addition of the multi-way detection process, when the address A+7 is input, the multi-way hit detector finds that the same type of entries have multiple hits. Then, for example, according to the AccVec count, entry 0 can be selected to be retained (as a selected entry) and entry 1 can be abolished (as an unselected entry). As a result, entry 1 will no longer be pre-fetched in the subsequent process;

[0125] Afterwards, addresses A+3 and A+4 hit entry 0, and entry 0 updates the state AccVec;

[0126] Afterwards, A+8 and A+9 hit entry 0, and entry 0 updates the states AccVec and DmdPtr;

[0127] After the required address sequence is input, the final entry 0 has BaseAddr=A+2, DmdPtr=7, and assuming conf=1, Dist=5; then entry 0 can issue a total of 12 prefetch requests, with addresses A+3~A+14; entry 1 is invalid.

[0128] In addition, it is understandable that because the pipeline of the multi-way hit detector is independent of the training / prefetch pipeline of the streaming data prefetch entry, there may be a certain time window from the entry entering the prefetch mode to the entry being revoked. Before the revocation, entry 1 may issue a partial prefetch request. Figure 7B In the example, it issues at most 4 prefetch requests, and the subsequent sequence will not continue to generate repeated prefetch address requests. The abolished entry 1 can be released for the training process of other required addresses. For example, when the subsequent address A+100 is received, it can be assigned to the released entry 1.

[0129] In summary, according to the data prefetching method provided by the embodiment of the present disclosure, multiple entries of the prefetcher are used to independently train and generate streaming data prefetching requests, thereby reducing the requirements for the pipeline depth of the entries. On the basis of ensuring the rapid training of multiple entries, the hardware implementation area of ​​the multiple entries of the prefetcher can also be controlled. Furthermore, the multi-way hit detector of the prefetcher performs repeated detection on multiple entries in parallel, that is, based on the hit information of multiple entries, it is determined whether there are entries in the multiple entries that will generate repeated prefetch addresses, and a part of the entries that will generate repeated prefetch addresses are prohibited, so as to ensure that the subsequent prefetching process will no longer repeatedly hit multiple entries, and multiple entries will not issue prefetching requests for repeated addresses, thereby avoiding the waste of power consumption and entry bandwidth caused by repeated prefetching, thereby improving the prefetching performance of the prefetcher and improving the overall operating performance of the electronic device.

[0130] According to another aspect of the present disclosure, an electronic device is also provided. Fig. 8A Schematic block diagram of an electronic device according to an embodiment of the present disclosure is shown. Fig. 8A As shown, the electronic device 1000 according to an embodiment of the present disclosure may include a prefetcher 1010 and a cache 1020. The prefetcher 1010 may be configured to include a plurality of entries 1011 and a multi-way hit detector 1012. According to an embodiment of the present disclosure, the prefetcher 1010 may be, for example, the streaming data prefetcher described above, for discovering streaming data access rules of addresses. The cache 1020 may be the above-mentioned three-level cache architecture, namely, L1 cache, L2 cache and LLC cache. The above-mentioned plurality of entries 1011 may have the following structure: Figure 2The hardware structure shown is used to independently perform streaming data pre-fetching and training processes.

[0131] According to some embodiments of the present disclosure, multiple entries 1011 can be configured to: receive a demand address for a cache, and perform training based on the demand address to identify streaming data patterns and generate streaming data prefetch requests, wherein each entry in the multiple entries is independently trained and generates streaming data prefetch requests.

[0132] According to some embodiments of the present disclosure, the multi-way hit detector 1012 can be configured to: determine whether there are N entries among the multiple entries that will generate duplicate prefetch addresses based on hit information of the multiple entries, where N is an integer greater than 1; in the case where it is determined that there are N entries, determine M selected entries from the N entries based on information of the N entries, where M is an integer greater than or equal to 1 and less than N; and generate an abolition instruction for unselected entries other than the M entries among the N entries, so as to prohibit the unselected entries from generating streaming data prefetch requests.

[0133] The specific implementation process of the multiple entries 1011 and the multi-way hit detector provided according to the embodiment of the present disclosure can refer to the above description of the data prefetching method according to the present disclosure, and will not be repeated here.

[0134] According to some embodiments of the present disclosure, the multi-way hit detector 1012 is implemented as a pipeline, is independent of the multiple entries 1011 , and performs multi-way hit detection in parallel with the training and pre-fetching process of the multiple entries 1011 .

[0135] According to some embodiments of the present disclosure, the required address is a virtual address corresponding to a load instruction or a store instruction. Specifically, such as Figure 2 Entries 0 to 31 in receive ld / st op information and are trained in parallel to identify streaming data patterns and generate possible pre-fetch requests.

[0136] According to some embodiments of the present disclosure, the multi-way hit detector 1012 determines whether there are N entries among the multiple entries that will generate duplicate prefetch addresses based on the hit information of the multiple entries, including: when the required address simultaneously hits N entries in the same direction of the streaming data and are in the prefetch mode, or in the training mode, determining that there are N entries that will generate duplicate prefetch addresses; or, when the required address simultaneously hits N entries in the same direction of the streaming data and are in the prefetch mode, or are in the prefetch mode, determining that there are N entries that will generate duplicate prefetch addresses.

[0137] According to some embodiments of the present disclosure, M is equal to 1, and the multi-way hit detector 1012 determines M selected entries from N entries based on the information of the N entries, including one of the following: determining the entry with the highest confidence parameter from the N entries as the selected entry based on the information of the N entries; determining the entry that is allocated earliest in time from the N entries as the selected entry based on the information of the N entries; or, determining the entry with the smallest or largest entry number from the N entries as the selected entry based on the information of the N entries.

[0138] According to some embodiments of the present disclosure, the prefetcher 1010 may further include a prefetch request generator. The prefetch request generator may be configured to: generate a streaming data prefetch request based on the M selected entries, wherein the streaming data prefetch request is used to perform a streaming data prefetch process based on a cache.

[0139] According to some embodiments of the present disclosure, a streaming data pre-fetch request is used to perform a streaming data pre-fetch process based on a first-level cache, a second-level cache, and a last-level cache of a cache.

[0140] According to some embodiments of the present disclosure, the electronic device 1000 may further include a read-write unit (LSU). The prefetcher 1010 is located in the read-write unit, and the read-write unit further includes a read-write queue (LSQ) and an arbiter. The prefetcher 1010 here can refer to Figure 1 The relationship between the hardware prefetch module HWPF and LSU and LSQ can be referred to Figure 1 The description will not be repeated here.

[0141] According to some embodiments of the present disclosure, the read / write queue LSQ may be configured to generate a demand access based on information of the read / write operation. The arbiter may be configured to generate a data access request based on the demand access of the read / write queue and the streaming data prefetch request generated by the prefetch, wherein the data access request corresponds to the demand address, wherein the prefetcher performs training and prefetching based on the demand address.

[0142] The electronic device according to the embodiment of the present disclosure can realize the specific execution process of functions such as data access and pre-fetching. In addition, the electronic device according to the embodiment of the present disclosure can specifically realize the steps of the data pre-fetching method according to some embodiments of the present disclosure described above in combination with the accompanying drawings, which will not be repeated here. The electronic device using the embodiment of the present disclosure can perform a similar data pre-fetching process and achieve similar technical effects.

[0143] As a way to achieve this, Figure 8B An example structural diagram of an electronic device according to an embodiment of the present disclosure is shown. Figure 2 and Figure 8BIt can be seen that according to the embodiment of the present disclosure, the prefetcher is also configured with a multi-way hit detector, which is independent of the entry and can perform duplicate detection on multiple entries in parallel, that is, based on the hit information of multiple entries, it is determined whether there are entries in the multiple entries that will generate duplicate prefetch addresses, for example, by providing an abolition signal to the unselected entries to prohibit a part of the entries that will generate duplicate prefetch addresses, to ensure that the subsequent prefetch process no longer repeatedly hits multiple entries, and the multiple entries will not issue prefetch requests for duplicate addresses, thereby avoiding power consumption and entry bandwidth waste caused by repeated prefetching, thereby improving the prefetching performance of the prefetcher and improving the overall operating performance of the electronic device.

[0144] According to yet another aspect of the present disclosure, an electronic device is provided. Fig. 9 A schematic block diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0145] like Fig. 9 As shown, the electronic device 2000 may include a processor 2010 and a memory 2020. According to some embodiments of the present disclosure, the memory 2020 stores computer readable codes, which, when executed by the processor 2010, may execute the steps of the data pre-fetching method provided according to the embodiments of the present disclosure.

[0146] The processor 2010 can perform various actions and processes according to the program stored in the memory 2020. Specifically, the processor 2010 can be an integrated circuit with signal processing capabilities. The general processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0147] The memory 2020 stores a computer readable code, which, when executed by the processor 2010, can cause the processor to implement the data prefetching method according to some embodiments of the present disclosure. The memory 2020 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. It should be noted that the memory described herein can be any suitable type of memory. As an example, by executing the computer readable code in the memory 2020, the processor 2010 can implement the steps of the data prefetching method described above in conjunction with the accompanying drawings.

[0148] Fig.10 FIG. 1 shows a schematic diagram of an exemplary electronic device according to an embodiment of the present disclosure. It can be understood that Fig.10 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0149] For example, Fig.10As shown, in some examples, the electronic device 3000 includes a processing device (e.g., a central processing unit, a graphics processor, etc.) 3010, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 3020 or a program loaded from a storage device 3080 to a random access memory (RAM) 3030. Various programs and data required for the operation of the computer system are also stored in the RAM 3030. The processing device 3010, the ROM 3020, and the RAM 3030 are connected to each other through a bus (Bus) 3040. An input / output (I / O) interface 3050 is also connected to the bus 3040.

[0150] For example, the following components may be connected to the I / O interface 3050: an input device 3060 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 3070 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 3080 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 3090 including a network interface card such as a LAN card, a modem, etc. The communication device 3090 may allow the electronic device 3000 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. The drive 3100 is also connected to the I / O interface 3050 as needed. Removable media 3110, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 3100 as needed, so that the computer program read therefrom is installed into the storage device 3090 as needed. Although Fig.10 The electronic device 3000 including various devices is shown, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0151] For example, the electronic device 3000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 3090 may communicate with a network and other devices through wireless communication.

[0152] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart may be implemented as a computer software program.For example, an embodiment of the present disclosure includes a computer program product including a computer program carried on a non-transitory computer-readable medium.

[0153] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the processor executes the steps of the data prefetching method according to the present disclosure.

[0154] Fig.11 Schematic block diagram of a storage medium according to an embodiment of the present disclosure is shown. Fig.11 As shown, a computer-readable storage medium 4000 stores computer-readable instructions 4010. When the computer-readable instructions 4010 are executed by a processor, the steps of the data pre-fetching method described with reference to the above figures can be executed.

[0155] It should be noted that the computer-readable storage medium provided by the present disclosure may be, for example, (but not limited to) an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In an embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. The above-mentioned computer-readable medium may be contained in the above-mentioned electronic device, or may exist alone without being assembled into the electronic device.

[0156] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0157] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0158] In addition, although the present disclosure makes various references to certain units in the electronic device and the electronic apparatus according to the embodiments of the present disclosure, any number of different units may be used and run on the client and / or the server. The units are merely illustrative, and different aspects of the method, electronic device, and the electronic apparatus may use different units.

[0159] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0160] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0161] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A data pre-fetching method, characterized in that: The method is applicable to an electronic device, the electronic device comprising a prefetcher and a cache, wherein the prefetcher comprises a plurality of entries and a multi-way hit detector, and the method comprises: Receive a demand address for the cache using the multiple entries, and perform training based on the demand address to identify streaming data regularity and generate a streaming data pre-fetch request, wherein each entry in the multiple entries independently performs the training and generates the streaming data pre-fetch request; and Determine, using the multi-way hit detector based on hit information of the plurality of entries, whether there are N entries in the plurality of entries that will generate duplicate prefetch addresses, where N is an integer greater than 1; In the case where it is determined that the N entries exist, using the multi-way hit detector to determine M selected entries from the N entries based on information of the N entries, where M is an integer greater than or equal to 1 and less than N; and The multi-way hit detector is used to generate an invalidation instruction for unselected entries other than the M entries among the N entries, so as to prohibit the unselected entries from generating streaming data prefetch requests.

2. The method according to claim 1, characterized in that The multi-way hit detector is implemented as a pipeline, independent of the multiple entries, and performs multi-way hit detection in parallel with the training and pre-fetching process of the multiple entries.

3. The method according to claim 1, characterized in that The required address is a virtual address corresponding to a load instruction or a store instruction.

4. The method according to claim 1, characterized in that: The determining, using the multi-way hit detector based on the hit information of the multiple entries, whether there are N entries in the multiple entries that will generate duplicate prefetch addresses comprises: In the case where the demand address simultaneously hits N entries in the same direction of streaming data and in the prefetch mode or in the training mode, determining that there are N entries that will generate duplicate prefetch addresses; or In the case that the demand address simultaneously hits N entries that have the same direction of streaming data and are in the prefetch mode or are in the prefetch mode, it is determined that there are N entries that will generate duplicate prefetch addresses.

5. The method according to claim 1, characterized in that M is equal to 1, and determining M selected entries from the N entries based on information of the N entries by using the multi-way hit detector includes: Based on the information of the N entries, an entry with the highest confidence parameter is determined from the N entries as the selected entry.

6. The method according to claim 1, characterized in that M is equal to 1, and determining M selected entries from the N entries based on information of the N entries by using the multi-way hit detector includes: An entry that is allocated earliest in time is determined from among the N entries based on information of the N entries as the selected entry.

7. The method according to claim 1, characterized in that M is equal to 1, and determining M selected entries from the N entries based on information of the N entries by using the multi-way hit detector includes: Based on the information of the N entries, an entry with the smallest or largest entry number is determined from the N entries as the selected entry.

8. The method according to claim 1, characterized in that The prefetcher also includes a prefetch request generator, and the method further includes: The pre-fetch request generator is used to generate a streaming data pre-fetch request based on the M selected entries, and the streaming data pre-fetch request is used to perform a streaming data pre-fetch process based on the cache.

9. The method according to claim 8, characterized in that The streaming data pre-fetch request is used to perform a streaming data pre-fetch process based on the first-level cache, the second-level cache and the last-level cache of the cache.

10. An electronic device, characterized in that: The electronic device includes a prefetcher and a cache, wherein the prefetcher is configured to include a plurality of entries and a multi-way hit detector, wherein: The plurality of entries are configured to: receive a demand address for the cache, and perform training based on the demand address to identify streaming data regularities and generate streaming data pre-fetch requests, wherein each entry in the plurality of entries independently performs the training and generates the streaming data pre-fetch requests; and The multi-way hit detector is configured as: Based on the hit information of the multiple entries, determining whether there are N entries in the multiple entries that will generate duplicate prefetch addresses, where N is an integer greater than 1; In a case where it is determined that the N entries exist, determining M selected entries from the N entries based on information of the N entries, where M is an integer greater than or equal to 1 and less than N; and A disabling instruction is generated for unselected entries other than the M entries among the N entries, so that the unselected entries are prohibited from generating streaming data prefetch requests.

11. The electronic device according to claim 10, characterized in that: The multi-way hit detector is implemented as a pipeline, independent of the multiple entries, and performs multi-way hit detection in parallel with the training and pre-fetching process of the multiple entries.

12. The electronic device according to claim 10, characterized in that: The required address is a virtual address corresponding to a load instruction or a store instruction.

13. The electronic device according to claim 10, characterized in that: The multi-way hit detector determines, based on the hit information of the multiple entries, whether there are N entries in the multiple entries that will generate duplicate prefetch addresses, including: In the case where the demand address simultaneously hits N entries in the same direction of streaming data and in the prefetch mode or in the training mode, determining that there are N entries that will generate duplicate prefetch addresses; or In the case that the demand address simultaneously hits N entries that have the same direction of streaming data and are in the prefetch mode or are in the prefetch mode, it is determined that there are N entries that will generate duplicate prefetch addresses.

14. The electronic device according to claim 10, characterized in that: M is equal to 1, and the multi-way hit detector determines M selected entries from the N entries based on the information of the N entries, including one of the following: Determining, based on information of the N entries, an entry with the highest confidence parameter from the N entries as the selected entry; Determine, based on the information of the N entries, the entry that is allocated earliest in time from among the N entries as the selected entry; or Based on the information of the N entries, an entry with the smallest or largest entry number is determined from the N entries as the selected entry.

15. The electronic device according to claim 10, characterized in that: The prefetcher also includes a prefetch request generator configured to generate a streaming data prefetch request based on the M selected entries, wherein the streaming data prefetch request is used to perform a streaming data prefetch process based on the cache.

16. The electronic device according to claim 15, characterized in that: The streaming data pre-fetch request is used to perform a streaming data pre-fetch process based on the first-level cache, the second-level cache and the last-level cache of the cache.

17. The electronic device according to claim 10, characterized in that: The electronic device further comprises a read-write unit, wherein the pre-fetcher is located in the read-write unit of the electronic device, and the read-write unit further comprises a read-write queue and an arbitrator, wherein: The read / write queue is configured to: generate demand access based on information of read / write operations; The arbiter is configured to generate a data access request based on the demand access of the read / write queue and the streaming data prefetch request generated by the prefetch, wherein the data access request corresponds to the demand address, wherein the prefetcher performs training and prefetching based on the demand address.

18. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory stores computer readable codes, which, when executed by the processor, cause the processor to perform the steps of the method according to any one of claims 1 to 9.

19. A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor is caused to perform the steps of the method according to any one of claims 1 to 9.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the processor is caused to perform the steps of the method according to any one of claims 1 to 9.

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