Data processing method, debugging controller and data processing system

Abstract

The present disclosure relates to a data processing method, a debugging controller and a data processing system, the method comprising: a receiving step, receiving a read request sent by the north bridge of the chip for reading debugging data stored in a memory, wherein the read request carries a debugging flag, the debugging flag is used to indicate that when an error occurs in the chip, the target device needs to read the debugging data from the memory via the debugging controller instead of the CPU; a reading step, reading the debugging data from the memory according to the read request; and a sending step, sending the read debugging data to the target device. Thus, the chip debugging data stored in the memory can be read more conveniently.

Description

Technical Field

[0001] The present disclosure relates to the field of chip system-level verification, and in particular to a data processing method, a debugging controller and a data processing system. Background Art

[0002] When performing chip system-level verification, silicon debugging can be performed. When performing chip debugging, some key data, such as debugging data, can be stored in a double data rate (DDR) memory.

[0003] In the related art, verification engineers need to first configure the debug controller (SOCCAP) in the chip through an external MCU, and then read the stored debugging data from the DDR memory. Since an external MCU is needed to configure the SOCCAP, each instruction issued by the MCU requires software coding. Therefore, for verification engineers, the above operations are relatively troublesome.

[0004] Therefore, how to more conveniently read the stored debugging data from the DDR memory is an issue that needs to be solved urgently. Summary of the invention

[0005] In view of this, the present disclosure proposes a data processing method, a debugging controller and a data processing system, so as to more conveniently read the debugging data stored in the memory.

[0006] According to a first aspect of the present disclosure, a data processing method is provided, comprising: a receiving step of receiving a read request sent by a north bridge of the chip for reading debug data stored in a memory, wherein the read request carries a debug flag, and the debug flag is used to indicate that when an error occurs in the chip, a target device needs to read the debug data from the memory via the debug controller instead of the CPU; a reading step of reading the debug data from the memory according to the read request; and a sending step of sending the read debug data to the target device.

[0007] According to a second aspect of the present disclosure, a debugging controller is provided, comprising: a receiving module, for receiving a read request sent by the north bridge of the chip for reading debugging data stored in a memory, wherein the read request carries a debugging flag, and the debugging flag is used to indicate that when an error occurs in the chip, a target device needs to read the debugging data from the memory via the debugging controller instead of the CPU; a reading module, for reading the debugging data from the memory according to the read request; and a sending module, for sending the read debugging data to the target device.

[0008] According to a third aspect of the present disclosure, there is provided a data processing system, comprising: the above-mentioned debugging controller; a storage module, which includes at least one memory; a target device, which is inserted into a target port of a circuit board of the chip when an error occurs in the chip, and the target port is configured in a debugging mode so that the target device sends a read request carrying a debugging flag to the north bridge of the chip via the target port under the control of an external host.

[0009] Through the data processing method, debugging controller and data processing system disclosed in the present invention, compared with the prior art that requires verification engineers to configure the debugging controller through an external MCU to read data in the memory, the verification engineer only needs to connect (insert) the target device to the circuit board of the chip. For example, the verification engineer only needs to insert a hot-swappable PCIE debugging card into a PCIE slot on the circuit board of the chip. Therefore, the stored debugging data can be read from the memory to the target device more conveniently.

[0010] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0012] Figure 1a is an architectural block diagram of a data processing system according to an embodiment of the present disclosure.

[0013] Figure 1b is an exemplary architectural block diagram of a data processing system according to an embodiment of the present disclosure.

[0014] Figure 2 It is a flowchart of a data processing method according to an embodiment of the present disclosure.

[0015] Figure 3 It is a signal flow diagram of a data processing method according to an embodiment of the present disclosure.

[0016] Figure 4 It is a flowchart of a data processing method according to an embodiment of the present disclosure.

[0017] Figure 5 FIG. 4 is a schematic diagram of reordering the read debugging data according to an embodiment of the present disclosure.

[0018] Figure 6 is a block diagram of a debugging controller according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0020] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0021] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0022] Figure 1a A block diagram of a data processing system according to an embodiment of the present disclosure is shown as follows: Figure 1a As shown, the data processing system 100 may include a target device 110, a debugging controller 130 and a storage module 150, wherein when an error occurs in the chip, the target device 110 is inserted into the target port of the circuit board of the chip, and the target port is configured in a debugging mode so that the target device 110 sends a read request carrying a debugging flag to the north bridge of the chip via the target port under the control of an external host, and the storage module 750 includes at least one memory.

[0023] In this embodiment, when an error occurs in the chip, the verification engineer can insert the target device 110 into the target port of the circuit board of the chip. In response, the target port is configured to be in debug mode. In this way, under the control of the external host, the target device 110 can send a read request carrying a debug flag to the north bridge of the chip via the target port in debug mode. The north bridge can intercept the read request carrying the debug flag, and after receiving the read request, the north bridge does not transmit the read request to the CPU, but sends the read request to the debug controller 130. In this way, the debug controller 130 executes the read request. Figure 2 The data processing method can read the debugging data from the storage module 150 to the target device 110 without the need for the CPU to perform data processing for reading the debugging data from the storage module 150 to the target device 110. The data processing method will be described in detail later.

[0024] In this way, compared with the prior art that requires verification engineers to configure the debugging controller through an external MCU to read the data in the memory to the target device, using the data processing system of this embodiment, the verification engineer only needs to connect (insert) the target device to the circuit board of the chip, so it is more convenient to read the stored debugging data from the memory to the target device.

[0025] In a possible implementation, the target device 110 includes a PCIE debug card, which is inserted into a PCIE slot on a circuit board of the chip when an error occurs in the chip, and a PCIE port corresponding to the PCIE slot is configured as the debug mode, so that the PCIE debug card sends a read request carrying a debug flag to the north bridge of the chip via the PCIE port under the control of the external host.

[0026] As an example, a PCIE debug card is used as the target device 110 to describe the data processing system of the present disclosure. Figure 1b FIG. 1 is an exemplary block diagram of the architecture of a data processing system according to an embodiment of the present disclosure. Figure 1b As shown, the data processing system may include a PCIE debug card, a debug controller SOCCAP and a DDR memory, wherein the operation mode of the SOCCAP may include a capture mode and a dump mode.

[0027] In the capture mode, while the chip is working, SOCCAP captures some key data in the working chip, and packages the captured key data and writes it into the DDR memory. The key data may include debugging data used for debugging when an error occurs in the chip. Any suitable analysis method can be used to analyze the debugging data as needed to obtain corresponding analysis results such as waveform files, through which it is possible to know what kind of error occurred in the chip. It should be noted that the present disclosure does not limit the data type, format and content of the debugging data. As long as the data can be used for debugging, it can be used in the present disclosure. In a possible implementation, the key data may include the main transmission interface bus (interface bus) and / or internal key signals.

[0028] When an error occurs in the chip, system-level verification of the chip can be performed. A PCIE debug card can be inserted into the PCIE slot on the circuit board of the chip. The verification engineer can configure the PE_DMA_SEL signal to select the PCIE slot into which the PCIE debug card is inserted, and configure the PE_DMA_ENABLE signal to enable the function for formally transmitting the request for the PCIE DMA debug cycle to the DDR memory. At this time, SOCCAP runs in dump mode.

[0029] In the dump mode, the PCIE port information corresponding to the PCIE slot into which the PCIE debug card is inserted is configured, and the PCIE debug card that initiates the read operation under the control of the external host is used to access the DDR memory via the debug path, i.e., the SOCCAP non-snoop path, to read the debug data stored in the DDR memory. In this way, it is easier to dump the debug data from the DDR memory.

[0030] It should be understood that SOCCAP runs in the dump mode to execute the data processing method of this embodiment, so that the PCIE debug card can read the debug data stored in the DDR memory. Figure 2 to Figure 6 The data processing method of this embodiment is described in detail.

[0031] Figure 2 is a flow chart of a data processing method according to an embodiment of the present disclosure. The data processing method can be applied to a chip debugging controller, for example, Figure 1a The debug controller 130 in the Figure 2 The data processing method shown in FIG. 1 can be performed by, when the target device 110 is a PCIE debugging card. Figure 1b SOCCAP in the implementation Figure 2 The data processing method shown in Figure 2 As shown, the data processing method may include the following steps:

[0032] In step S210 (corresponding to the receiving step), a read request for reading debugging data stored in a memory is received, which is sent by the north bridge of the chip, wherein the read request carries a debugging flag, and the debugging flag is used to indicate that when an error occurs in the chip, the target device 110 needs to read the debugging data from the memory via the debugging controller instead of the CPU.

[0033] In this embodiment, when an error occurs in the chip, a target device 110 for reading chip debugging data stored in the memory can be connected (inserted) on the circuit board of the chip. Under the control of the external host, the target device 110 sends a read request to the north bridge of the chip via the target port in the debugging mode, wherein all read requests sent via the target port in the debugging mode carry a flag for indicating that when an error occurs in the chip, the debug controller 130 needs to be used instead of the CPU to read the chip debugging data from the memory (for example, Figure 1a The storage module 150 in the memory reads the debugging flag of the debugging data.

[0034] The north bridge can intercept the read request carrying the debug flag, and after receiving the read request, the north bridge does not transmit the read request to the CPU, but sends the read request to the debug controller 130. Accordingly, the debug controller 130 can intercept and capture the read request carrying the debug flag, while the CPU cannot receive the read request carrying the debug flag. In this way, the CPU does not need to perform data processing for reading the debug data from the memory to the target device 110, thereby avoiding problems caused by the CPU performing the data processing.

[0035] In a possible implementation, the target device 110 includes a PCIE debugging card inserted into a PCIE slot when an error occurs in the chip.

[0036] In this embodiment, when an error occurs in the chip, a PCIE debug card can be inserted into a PCIE slot on the circuit board of the chip. For example, a PCIE debug card can be inserted into a PCIE GEN4 port. The PCIE root complex (RC) port corresponding to the PCIE slot into which the PCIE debug card is inserted is configured in debug mode.

[0037] Under the control of the external host, the PCIE debug card sends a read request to the north bridge of the chip via the PCIE RC port in debug mode, that is, a request for a DMA read cycle is transmitted to the north bridge. All read requests sent via the PCIE RC port in debug mode carry a debug flag PE_DBGRADS, so the request for a DMA read cycle transmitted to the north bridge is also called a request for a debug DMA read cycle.

[0038] The north bridge can intercept the request of the DMA read cycle carrying the debug flag PE_DBGRADS, and after receiving the request of the DMA read cycle, the north bridge does not transmit the request of the DMA read cycle to the CPU through the normal DMA path, but sends the request of the DMA read cycle to the SOCCAP. Accordingly, the SOCCAP can intercept and capture the request of the DMA read cycle carrying the debug flag PE_DBGRADS, that is, the above-mentioned read request, and relatively, the CPU cannot receive the request of the DMA read cycle carrying the debug flag PE_DBGRADS. In this way, the CPU is not required to perform data processing for reading the debug data from the DDR memory to the PCIE debug card, thereby avoiding problems caused by the CPU performing the data processing.

[0039] It should be understood that the present disclosure does not limit the target device, and the PCIE debug card is only an example of the target device. However, the present disclosure is not limited to this, and other devices in the prior art that can access (insert) the target port of the circuit board of the chip when an error occurs in the chip and need to read the chip debugging data stored in the memory can also be used.

[0040] In step S230 (corresponding to a reading step), the debugging data is read from the memory according to the read request.

[0041] In step S250 (corresponding to the sending step), the read debugging data is sent to the target device 110 .

[0042] In this embodiment, the debugging controller 130 may read the debugging data from the storage module 150 in response to receiving a read request carrying a debugging flag, and then send the read debugging data to the target device 110. For example, in response to receiving a read request carrying a debugging flag PE_DBGRADS, SOCCAP may read the debugging data from the DDR memory via the debugging path, i.e., the above-mentioned non-listening path, and return the debugging data to the PCIE debugging card.

[0043] According to this embodiment, a debugging flag PE_DBGRADS is added to the original PCIE DMA read request transmission interface. When a PCIE debugging card is inserted into a PCIE slot, the corresponding PCIE port will be configured into a debugging mode, and all DMA read cycle requests sent by the PCIE debugging card via the PCIE port will carry the debugging flag PE_DBGRADS. Therefore, compared with the prior art, the DMA read cycle request carrying the debugging flag PE_DBGRADS is intercepted by the north bridge of the chip instead of passing through the CPU path. In response to receiving the DMA read cycle request, SOCCAP reads debugging data from the DDR memory and returns the read debugging data to the PCIE debugging card.

[0044] In this way, compared with the prior art that requires verification engineers to configure SOCCAP through an external MCU to read data from the DDR memory, using the data processing method of this embodiment, the verification engineer only needs to connect (insert) the target device to the chip's circuit board. For example, the verification engineer only needs to insert a hot-swappable PCIE debug card into a PCIE slot on the chip's circuit board. Therefore, the stored debugging data can be read from the DDR memory more conveniently.

[0045] In a possible implementation, step S240 may include: SOCCAP decodes the read request to obtain a storage address of the debugging data, and accesses a corresponding memory such as a DDR memory according to the decoded storage address to read the debugging data corresponding to the storage address.

[0046] In a possible implementation, step S240 may include: decoding the read request to determine a target memory on which a read operation is to be performed, and accessing the target memory to read the debugging data.

[0047] In this embodiment, SOCCAP may support only one memory (such as DRAM NODE) ​​or at least two memories. Accordingly, when SOCCAP supports only one memory, SOCCAP can only access the one memory to read debugging data; when SOCCAP supports at least two memories, SOCCAP can cross-access the at least two memories (DRAM NODE interleave) to read debugging data. It should be understood that when the data bandwidth to be transmitted is low, SOCCAP can be selected to support only one memory, and when the data bandwidth to be transmitted is high, SOCCAP needs to be selected to support at least two memories.

[0048] Therefore, in response to receiving a read request, the read request needs to be decoded to determine whether SOCCAP supports only one memory or multiple memories. When it is determined that only one memory is supported, the one memory is directly determined as the target memory, and the debug data requested by the read request can be obtained by accessing the target memory. When it is determined that multiple memories are supported, it is further determined which memories of the multiple memories need to be accessed by the read request, and the determined memory is determined as the target memory, and the debug data requested by the read request can be obtained by accessing the target memory.

[0049] In one possible implementation, step S240 may include: decoding the read request to determine a cross enable signal (INTERLEAVE_EN signal) and a channel selection signal (CHANEL_SEL signal), wherein the cross enable signal indicates whether multiple memories need to be accessed, and the channel selection signal indicates which memory among the multiple memories only needs to be accessed; when the cross enable signal indicates that multiple memories do not need to be accessed, determining the memory identified by the channel selection signal as the target memory, and accessing the memory determined as the target memory to read the debugging data.

[0050] In this embodiment, the read request may carry an INTERLEAVE_EN signal and a CHANEL_SEL signal. For ease of understanding, the description is given by taking SOCCAP supporting two memories as an example. Figure 3 As shown, SOCCAP supports two memories, memory H0 and memory H1. By default, SOCCAP only reads debug data from memory H0, at which time INTERLEAVE_EN signal = 0 and CHANEL_SEL signal = 0. If you choose to read debug data only from memory H1, INTERLEAVE_EN signal = 0 and CHANEL_SEL signal = 1.

[0051] In one possible implementation, step S240 may include: decoding the read request to determine a cross enable signal (INTERLEAVE_EN signal) and a cross select signal (INTERLEAVE_SEL signal), wherein the cross enable signal indicates whether multiple memories need to be accessed, and the cross select signal indicates a method of cross-accessing the memories when the multiple memories need to be accessed; when the cross enable signal indicates that multiple memories need to be accessed, the multiple memories are determined as the target memories, and the multiple memories are cross-accessed according to the method indicated by the cross select signal.

[0052] For ease of understanding, combined Figure 4 The above data processing method is described in detail. Figure 4 As shown, the data processing method may include the following steps:

[0053] In step S401, a read request is received. This step can refer to the description of step S210 above, and will not be repeated here.

[0054] In step S402 , the read request is decoded to parse out the INTERLEAVE_EN signal, the CHANEL_SEL signal, and the INTERLEAVE_SEL signal.

[0055] In step S403, it is determined whether the INTERLEAVE_EN signal is equal to 1 or 0. If it is equal to 1, it means that the INTERLEAVE_EN signal is enabled, and step S407 is executed; otherwise, step S404 is executed.

[0056] In step S404, it is determined whether the CHANEL_SEL signal is equal to 1 or 0. If it is equal to 0, step S405 is executed to access only the first memory such as Figure 3 Otherwise, step S406 is executed to access only the second memory such as Figure 3 Memory H1 in.

[0057] In step S407, it is determined whether the INTERLEAVE_SEL signal is equal to 1 or 0. If the INTERLEAVE_SEL signal is equal to 0, step S408 is executed to determine whether the first flag bit, such as bit6, is equal to 1 or 0. If it is determined that bit6 is equal to 1, step S410 is executed to access the memory H1, otherwise, step S409 is executed to access the memory H0.

[0058] If the INTERLEAVE_SEL signal is equal to 1, step S411 is executed to determine whether the second flag bit, such as bit8, is equal to 1 or 0. If it is determined that bit8 is equal to 1, step S413 is executed to access the memory H1, otherwise, step S412 is executed to access the memory H0.

[0059] Therefore, in this embodiment, if the memory H0 / H1 is cross-accessed, the INTERLEAVE_EN signal = 1, and the cross-access mode of the DRAM memory can be selected by the INTERLEAVE_SEL signal. If the INTERLEAVE_SEL signal is configured to be 0, when bit6 of the storage address is 0, the SOCCAP accesses the memory H0, and when bit6 of the storage address is 1, the SOCCAP accesses the memory H1, and when the INTERLEAVE_SEL signal is configured to be 1, when bit8 of the storage address is 0, the SOCCAP accesses the memory H0, and when bit8 of the storage address is 1, the SOCCAP accesses the memory H1.

[0060] In one possible implementation, accessing the target memory to read the debugging data includes: generating a sequence identifier for identifying which read request the current read request is, and sending the read request and its corresponding sequence identifier to the first memory and the second memory together, wherein the sequence identifier corresponding to the read request is different from the PCIE DMA identifier carried by the read request; receiving data returned by the first memory and the second memory respectively, wherein the data returned by the first memory and the second memory respectively include debugging data and the sequence identifier corresponding to the debugging data; writing the received debugging data into a cross-clock domain CDC FIFO, and controlling whether the CDC FIFO pops out the debugging data according to the sequence identifier corresponding to the debugging data.

[0061] In a possible implementation, the CDCFIFO is controlled to pop out the debugging data according to the sequence identifier corresponding to the debugging data, including: judging whether the sequence identifier corresponding to the debugging data indicates that the debugging data is the first debugging data; if it indicates the first debugging data, the CDC FIFO is controlled to pop out the debugging data, and accordingly, in the sending step, the debugging data and the PCIE DMA identifier are sent to the target device such as a PCIE debugging card; if it indicates that it is not the first debugging data, the CDCFIFO is controlled to cache the debugging data.

[0062] In this embodiment, Figure 3 As shown, SOCCAP includes DMA control logic (DMA_CTRL) and decoding logic (Fd_rdecode). Figure 3The solid line path in the figure represents the sending process of the read request, which is sent from the PCIE debug card to the SOCCAP. After being processed by the SOCCAP, for example, the decoding logic decodes it to determine which memory node to access. For this example, it is determined that two memory nodes H0 and H1 are to be accessed, so the read request is sent to the two nodes H0 and H1. The dotted line path represents the return process of the debug data, which is read from the two memory nodes H0 and H1 and then returned to the SOCCAP. After being processed by the SOCCAP, it is returned to the PCIE debug card.

[0063] When SOCCAP accesses both memories H0 and H1, there is a possibility that debugging data will be returned from memories H0 and H1 at the same time. SOCCAP needs to receive the debugging data from both memories H0 and H1 at the same time, use CDCFIFO to process the simultaneously received data, and then return the debugging data to the PCIE debugging card.

[0064] That is to say, the order of the data returned by the memories H0 and H1 cannot be controlled on the memory side, and needs to be controlled by SOCCAP to reorder the data returned by the memories to be consistent with the order in the request.

[0065] SOCCAP uses ID decoding to sequence the data returned by the memory. Figure 5 It can be seen that SOCCAP reads the PCIE DMA identifier carried by the request ( Figure 5 PCIE DMA ARID in the storage, and then SOCCAP generates a new set of IDs ( Figure 5 The ARID in the read flag is sent to the memory H0 and H1. The ARID is used to identify the number of read requests. When the memory H0 and H1 receive the read request with the debug flag, they return the ARID and data. SOCCAP stores the data in the CDC FIFO ( Figure 5 DATA(FIFO) in memory H0 and H1, and then determine whether the data is the first one according to the ID returned by memory H0 and H1. For example, if the ID is 1, the data is the first one. If it is the first one, the CDC FIFO starts to pop data.

[0066] The order of read requests must be consistent with the order of returned data. If the returned data is the second record, the second record is stored in DATA FIFO until the returned data is the first record. The first record is then returned to the PCIE debug card together with PCIE DMAARID. Since the clock domain of the debug card is different from that of SOCCAP, CDCDATAFIFO is required. In other words, when the data is popped out, the stored PCIE DMA ARID is also popped out as the ID of the returned data.

[0067] Exemplarily, SOCCAP encodes the ID of the read request sent to the memory. The first read request is coded 1, the second read request is coded 2, and the third read request is coded 3. When the memory H0 and H1 return data, they also carry ID information, but the ID of the returned data may be 3, 2, 1 or 2, 1, 3. For the returned data to be reordered, SOCCAP can know which data is returned based on the ID information. If the ID is not 1, the data is written to the CDC FIFO and waits. Only when the data with ID 1 is returned, the data is read out from the CDC FIFO and returned to the PCIE debug card. Therefore, SOCCAP returns the reordered data and PCIE DMA ARID to the PCIE debug card.

[0068] According to this embodiment, compared with the prior art, the request for a DMA read cycle carrying a debug flag PE_DBGRADS is intercepted by the north bridge of the chip instead of passing through the CPU path. SOCCAP decodes the request for the DMA read cycle to determine which memory to read the debug data, and then accesses the relevant position of the determined memory to read the stored debug data. The read request carries the debug flag PE_DBGRADS and the address of the debug data. SOCCAP determines which memory to go to the corresponding address to obtain the requested debug data through the address. The memory returns the corresponding debug data to SOCCAP, and SOCCAP reorders the debug data returned by the memory to be consistent with the order in the read request, thereby returning the debug data corresponding to the read request to the PCIE debug card.

[0069] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not go into details.

[0070] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0071] Figure 6 A block diagram of a chip debugging controller according to an embodiment of the present disclosure is shown. Figure 6 As shown, the debugging controller 600 of the chip includes a receiving module 610, a reading module 630 and a sending module 650. The receiving module 610 is used to receive a read request sent by the north bridge of the chip for reading the debugging data stored in the memory, wherein the read request carries a debugging flag, and the debugging flag is used to indicate that when an error occurs in the chip, the target device needs to read the debugging data from the memory via the debugging controller instead of the CPU. The reading module 630 is connected to the receiving module 610, and is used to read the debugging data from the memory according to the read request. The sending module 650 is connected to the reading module 630, and is used to send the read debugging data to the target device.

[0072] In a possible implementation, the target device includes a PCIE debugging card inserted into a PCIE slot when an error occurs in the chip.

[0073] In one possible implementation, the read request is received by the north bridge from a PCIE root complex port configured in debug mode and corresponding to a PCIE slot in which a PCIE debug card is inserted, wherein all read requests sent by the PCIE root complex port configured in debug mode carry the debug flag.

[0074] In a possible implementation, the read module 630 is configured to: decode the read request to determine a target memory on which a read operation is to be performed, and access the target memory to read the debugging data.

[0075] In one possible implementation, the read module 630 is configured to: decode the read request to determine a cross enable signal and a channel selection signal, wherein the cross enable signal indicates whether multiple memories need to be accessed, and the channel selection signal indicates which one of the multiple memories only needs to be accessed; when the cross enable signal indicates that multiple memories do not need to be accessed, determine the memory identified by the channel selection signal as the target memory, and access the memory determined as the target memory to read the debugging data.

[0076] In one possible implementation, the read module 630 is configured to: decode the read request to determine a cross enable signal and a cross selection signal, wherein the cross enable signal indicates whether multiple memories need to be accessed, and the cross selection signal indicates a method of cross-accessing the memories when the multiple memories need to be accessed; when the cross enable signal indicates that multiple memories need to be accessed, the multiple memories are determined as the target memories, and the multiple memories are cross-accessed according to the method indicated by the cross selection signal.

[0077] In one possible implementation, the read module 630 is configured as follows: if the cross selection signal is equal to 0, then when the value of the first target bit of the storage address obtained by decoding the read request is equal to 0, the first memory among the multiple memories is accessed; when the value of the first target bit is equal to 1, the second memory among the multiple memories is accessed; if the cross selection signal is equal to 1, then when the value of the second target bit of the storage address obtained by decoding the read request is equal to 0, the first memory is accessed; when the value of the second target bit is equal to 1, the second memory is accessed.

[0078] In one possible implementation, the sending module 650 is configured to: generate a sequence identifier for identifying which read request the current read request is, and send the read request and its corresponding sequence identifier to the first memory and the second memory together, wherein the sequence identifier corresponding to the read request is different from the PCIE DMA identifier carried by the read request; receive data returned by the first memory and the second memory respectively, wherein the data returned by the first memory and the second memory respectively include debugging data and the sequence identifier corresponding to the debugging data; write the received debugging data into a cross-clock domain CDC FIFO, and control whether the CDC FIFO pops out the debugging data according to the sequence identifier corresponding to the debugging data.

[0079] In a possible implementation, the sending module 650 is configured to: determine whether the sequence identifier corresponding to the debugging data indicates that the debugging data is the first debugging data; if it indicates the first debugging data, control the CDC FIFO to pop out the debugging data, and send the debugging data and the PCIE DMA identifier to the target device such as a PCIE debugging card; if it indicates that it is not the first debugging data, control the CDC FIFO to cache the debugging data.

[0080] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0081] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A data processing method, applied to a chip debugging controller, characterized in that: include: A receiving step, receiving a read request for reading debug data stored in a memory sent by a north bridge of the chip, wherein the read request carries a debug flag, and the debug flag is used to indicate that when an error occurs in the chip, a target device needs to read the debug data from the memory via the debug controller instead of the CPU; A reading step, reading the debugging data from the memory according to the read request; The step of sending the read debugging data is sent to the target device.

2. The data processing method according to claim 1, characterized in that: The target device includes a PCIE debugging card inserted into a PCIE slot when an error occurs in the chip.

3. The data processing method according to claim 2, characterized in that: The read request is received by the north bridge from a PCIE root complex port configured in debug mode and corresponding to a PCIE slot into which a PCIE debug card is inserted, wherein all read requests sent by the PCIE root complex port configured in debug mode carry the debug flag.

4. The data processing method according to claim 1, characterized in that: The reading step includes decoding the read request to determine a target memory to be subjected to a read operation, and accessing the target memory to read the debugging data.

5. The data processing method according to claim 4, characterized in that: Decoding the read request to determine a target memory to be subjected to a read operation, and accessing the target memory to read the debug data, comprising: Decoding the read request to determine a cross enable signal and a channel selection signal, wherein the cross enable signal indicates whether a plurality of memories need to be accessed, and the channel selection signal indicates which memory of the plurality of memories only needs to be accessed; When the cross enable signal indicates that it is not necessary to access a plurality of memories, the memory identified by the channel selection signal is determined as the target memory, and the memory determined as the target memory is accessed to read the debugging data.

6. The data processing method according to claim 4, characterized in that: Decoding the read request to determine a target memory to be subjected to a read operation, and accessing the target memory to read the debug data, comprising: Decoding the read request to determine a cross enable signal and a cross select signal, wherein the cross enable signal indicates whether a plurality of memories need to be accessed, and the cross select signal indicates a cross access memory mode adopted when the plurality of memories need to be accessed; In the case where the cross enable signal indicates that a plurality of memories need to be accessed, the plurality of memories are determined as the target memories, and the plurality of memories are cross-accessed according to the manner indicated by the cross select signal.

7. The data processing method according to claim 6, characterized in that: Cross-accessing the plurality of memories in a manner indicated by the cross-select signal comprises: If the cross selection signal is equal to 0, a first memory among the multiple memories is accessed when the value of the first target bit of the storage address obtained by decoding the read request is equal to 0; and a second memory among the multiple memories is accessed when the value of the first target bit is equal to 1; If the cross selection signal is equal to 1, the first memory is accessed when the value of the second target bit of the storage address obtained by decoding the read request is equal to 0; and the second memory is accessed when the value of the second target bit is equal to 1.

8. The data processing method according to claim 7, characterized in that: In a case where the cross enable signal indicates that the first memory and the second memory need to be accessed, the sending step includes: Generate a sequence identifier for identifying which read request the current read request is, and send the read request and the sequence identifier corresponding to the read request to the first memory and the second memory, wherein the sequence identifier corresponding to the read request is different from the PCIE DMA identifier carried by the read request; receiving data returned by the first memory and the second memory, wherein the data returned by the first memory and the second memory respectively include debugging data and a sequence identifier corresponding to the debugging data; The received debugging data is written into the cross-clock domain CDC FIFO, and the CDC FIFO is controlled to eject the debugging data according to the sequence identifier corresponding to the debugging data.

9. The data processing method according to claim 8, characterized in that: Controlling whether the CDC FIFO pops out the debugging data according to the sequence identifier corresponding to the debugging data includes: determining whether the sequence identifier corresponding to the debugging data indicates that the debugging data is the first debugging data; If it indicates the first debug data, control the CDC FIFO to pop out the debug data, and send the debug data and the PCIE DMA identifier to the target device; If it indicates that the debug data is not the first one, the CDC FIFO is controlled to buffer the debug data.

10. A chip debugging controller, characterized in that: include: a receiving module, configured to receive a read request sent by the north bridge of the chip for reading debug data stored in the memory, wherein the read request carries a debug flag, and the debug flag is used to indicate that when an error occurs in the chip, the target device needs to read the debug data from the memory via the debug controller instead of the CPU; A reading module, configured to read the debugging data from the memory according to the reading request; The sending module is used to send the read debugging data to the target device.

11. The debugging controller according to claim 10, characterized in that: The target device includes a PCIE debugging card inserted into a PCIE slot when an error occurs in the chip.

12. The debugging controller according to claim 11, characterized in that: The read request is received by the north bridge from a PCIE root complex port configured in debug mode and corresponding to a PCIE slot into which a PCIE debug card is inserted, wherein all read requests sent by the PCIE root complex port configured in debug mode carry the debug flag.

13. The debugging controller according to claim 10, characterized in that: The read module is configured to decode the read request to determine a target memory to be subjected to a read operation, and access the target memory to read the debugging data.

14. The debugging controller according to claim 13, characterized in that: The reading module is configured as follows: Decoding the read request to determine a cross enable signal and a channel selection signal, wherein the cross enable signal indicates whether a plurality of memories need to be accessed, and the channel selection signal indicates which memory of the plurality of memories only needs to be accessed; When the cross enable signal indicates that it is not necessary to access a plurality of memories, the memory identified by the channel selection signal is determined as the target memory, and the memory determined as the target memory is accessed to read the debugging data.

15. The debugging controller according to claim 13, characterized in that: The reading module is configured as follows: Decoding the read request to determine a cross enable signal and a cross select signal, wherein the cross enable signal indicates whether a plurality of memories need to be accessed, and the cross select signal indicates a cross access memory mode adopted when the plurality of memories need to be accessed; In the case where the cross enable signal indicates that a plurality of memories need to be accessed, the plurality of memories are determined as the target memories, and the plurality of memories are cross-accessed according to the manner indicated by the cross select signal.

16. The debugging controller according to claim 15, characterized in that: The reading module is configured as follows: If the cross selection signal is equal to 0, accessing a first memory among the multiple memories when the value of the first target bit of the storage address obtained by decoding the read request is equal to 0; accessing a second memory among the plurality of memories when the value of the first target bit is equal to 1; If the cross selection signal is equal to 1, accessing the first memory when the value of the second target bit of the storage address obtained by decoding the read request is equal to 0; When the value of the second target bit is equal to 1, the second memory is accessed.

17. The debugging controller according to claim 16, characterized in that: The sending module is configured as follows: Generate a sequence identifier for identifying which read request the current read request is, and send the read request and the sequence identifier corresponding to the read request to the first memory and the second memory, wherein the sequence identifier corresponding to the read request is different from the PCIE DMA identifier carried by the read request; receiving data returned by the first memory and the second memory, wherein the data returned by the first memory and the second memory respectively include debugging data and a sequence identifier corresponding to the debugging data; The received debugging data is written into the cross-clock domain CDC FIFO, and the CDC FIFO is controlled to eject the debugging data according to the sequence identifier corresponding to the debugging data.

18. The debugging controller according to claim 17, characterized in that: The sending module is configured as follows: determining whether the sequence identifier corresponding to the debugging data indicates that the debugging data is the first debugging data; If it indicates the first debug data, control the CDC FIFO to pop out the debug data, and send the debug data and the PCIE DMA identifier to the target device; If it indicates that the debug data is not the first one, the CDC FIFO is controlled to buffer the debug data.

19. A data processing system, characterized in that: include: A debugging controller according to any one of claims 10 to 18; A storage module, comprising at least one memory; A target device is inserted into a target port of a circuit board of the chip when an error occurs in the chip, and the target port is configured in a debugging mode so that the target device sends a read request carrying a debugging flag to the north bridge of the chip via the target port under the control of an external host.

20. The data processing system according to claim 19, characterized in that The target device includes a PCIE debug card, which is inserted into a PCIE slot on a circuit board of the chip when an error occurs in the chip, and a PCIE port corresponding to the PCIE slot is configured as the debug mode, so that the PCIE debug card sends a read request carrying a debug flag to the north bridge of the chip via the PCIE port under the control of the external host.

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