A data synchronization method, unit, storage medium and program product

Abstract

The present invention discloses a data synchronization method, unit, storage medium and program product. A register module receives a first transmission instruction sent by a PS unit; the register module sends a first synchronization information to a data analysis module according to the first transmission instruction; the data analysis module establishes a communication connection with a memory control module of the PS unit through a transmission interconnection module according to a first start signal; the data analysis module sends a first address signal to the memory control module, so that the memory control module communicates with the memory corresponding to the first address signal, receives the first synchronization data sent by the memory corresponding to the first address signal, and sends the first synchronization data to the transmission interconnection module; the data analysis module receives the first synchronization data forwarded by the transmission interconnection module, and after parsing the first synchronization data, sends the parsed first synchronization data to the register module. The present invention uses the PS unit as the initiator of data synchronization to achieve data synchronization between an external memory and a PL unit register.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data synchronization method, unit, storage medium and program product. Background Art

[0002] The Zynq-7000 All Programmable SoC (ZYNQ) is a system-on-chip that integrates a single-chip microcomputer and a field programmable gate array (FPGA) in the same chip. ZYNQ mainly consists of two parts: the application processor (PS) and the programmable logic (PL). The PS end can mount data from an external double-rate synchronous dynamic random access memory (DDR).

[0003] At present, an operation request can be generated from the PL side and sent to the PS side, so that the PS side responds to the operation request and communicates with the external DDR, so that the PL side directly accesses or writes the data of the PL side into the data in the DDR mounted on the PS side. However, the above method is limited to initiating a request for data acquisition or data writing from the PL side. Summary of the invention

[0004] The present invention provides a data synchronization method, unit, storage medium and program product to solve the problem that the current request for data acquisition or data writing is limited to being initiated from a PL unit, realizes data synchronization based on a PS unit as the initiator of the data synchronization request, and completes the mapping of data in a memory external to the PS unit to a register module in the PL unit.

[0005] According to one aspect of the present invention, a data synchronization method is provided, which is applied to a programmable logic PL unit, wherein the PL unit includes a data parsing module and a register module that are communicatively connected, and the register module is communicatively connected to an application processor PS unit; the method includes:

[0006] The register module receives a first transmission instruction sent by the PS unit;

[0007] The register module sends first synchronization information to the data parsing module according to the first transmission instruction, wherein the first synchronization information includes a first start signal and a first address signal;

[0008] The data parsing module establishes a communication connection with the memory control module of the PS unit through the transmission interconnection module according to the first start signal, wherein the memory control module is externally connected to a plurality of memories;

[0009] The data parsing module sends the first address signal to the memory control module, so that the memory control module communicates with the memory corresponding to the first address signal, receives the first synchronization data sent by the memory corresponding to the first address signal, and sends the first synchronization data to the transmission interconnection module;

[0010] The data parsing module receives the first synchronization data forwarded by the transmission interconnection module, and after parsing the first synchronization data, sends the parsed first synchronization data to the register module.

[0011] According to another aspect of the present invention, a data synchronization device is provided, which is applied to a programmable logic PL unit, wherein the PL unit includes a data parsing module and a register module that are communicatively connected, and the register module is communicatively connected to an application processor PS unit; the device includes:

[0012] A receiving module, used for the register module to receive the first transmission instruction sent by the PS unit;

[0013] A sending module, used for the register module to send first synchronization information to the data parsing module according to the first transmission instruction, wherein the first synchronization information includes a first start signal and a first address signal;

[0014] A connection module, used for the data parsing module to establish a communication connection with the memory control module of the PS unit through the transmission interconnection module according to the first start signal, wherein the memory control module is externally connected to a plurality of memories;

[0015] A transmission module, used for the data parsing module to send the first address signal to the memory control module, so that the memory control module communicates with the memory corresponding to the first address signal, receives the first synchronization data sent by the memory corresponding to the first address signal, and sends the first synchronization data to the transmission interconnection module;

[0016] The parsing module is used for the data parsing module to receive the first synchronization data forwarded by the transmission interconnection module, and after parsing the first synchronization data, send the parsed first synchronization data to the register module.

[0017] According to another aspect of the present invention, a programmable logic PL unit is provided, the programmable logic PL unit comprising:

[0018] at least one processor; and

[0019] a memory communicatively connected to the at least one processor; wherein,

[0020] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the data synchronization method described in any embodiment of the present invention.

[0021] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data synchronization method described in any embodiment of the present invention when executed.

[0022] According to another aspect of the present invention, a computer program product is provided. The computer program product includes: a computer program. When the computer program is executed by a processor, the data synchronization method described in any embodiment of the present invention is implemented.

[0023] The data synchronization method provided by the embodiment of the present invention comprises the following steps: the register module receives the first transmission instruction sent by the PS unit; the register module sends the first synchronization information to the data analysis module according to the first transmission instruction; the data analysis module establishes a communication connection with the memory control module of the PS unit through the transmission interconnection module according to the first start signal; the data analysis module sends the first address signal to the memory control module, so that the memory control module communicates with the memory corresponding to the first address signal, receives the first synchronization data sent by the memory corresponding to the first address signal, and sends the first synchronization data to the transmission interconnection module; the data analysis module receives the first synchronization data forwarded by the transmission interconnection module, and after parsing the first synchronization data, sends the parsed first synchronization data to the register module. In the above technical solution, on the one hand, the PS unit directly sends the first transmission instruction to the register module in the PL unit, so as to realize the PS unit as the initiator of the data synchronization request, and provide the starting conditions for the subsequent implementation of mapping the data in the memory external to the PS unit to the register module in the PL unit. On the other hand, when the data parsing module receives the first start signal, the data parsing module will directly establish a communication connection with the memory control module of the PS unit based on the transmission interconnection module, and quickly realize the establishment of the data interaction connection between the PL unit and the PS unit; and the memory control module determines the memory and the first synchronization data in the memory based on the first address signal, and realizes the determination and accurate acquisition of the location of the data to be synchronized. Finally, the data parsing module is used to parse the first synchronization data of other formats, and the parsed first synchronization data that can be stored by the register module is obtained, and the data is accurately parsed, and the data in the memory external to the PS unit is mapped to the register module in the PL unit, so that the register module synchronizes the data in the memory external to the PS unit. And, the above method solves the problem that the current request for data acquisition or data writing is limited to being initiated from the PL unit, and realizes the data synchronization based on the PS unit as the initiator of the data synchronization request, and completes the mapping of the data in the memory external to the PS unit to the register module in the PL unit.

[0024] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A flowchart of a data synchronization method provided by an embodiment of the present invention;

[0027] Figure 2 A structural example diagram of a data synchronization structure provided by an embodiment of the present invention;

[0028] Figure 3 A flowchart of another data synchronization method provided by an embodiment of the present invention;

[0029] Figure 4 A flowchart of another data synchronization method provided by an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of the structure of a data synchronization device provided by an embodiment of the present invention;

[0031] Figure 6 A schematic diagram of the structure of a programmable logic PL unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] Figure 1A flow chart of a data synchronization method provided in an embodiment of the present invention. This embodiment is applicable to the situation where a register in a PL unit interacts with data in a memory mounted on a PS unit. The method can be executed by a data synchronization device, which can be implemented in the form of hardware and / or software, and can be configured in a PL unit.

[0035] In the introduction Figure 1 Before describing the data synchronization method, the data synchronization structure involved in the embodiment of the present invention is described. Figure 2 FIG. 1 is a structural example diagram of a data synchronization structure provided by an embodiment of the present invention. Figure 2 As shown, in a ZYNQ, a PL unit 10 and a PS unit 20 are included. The memory control module 201 in the PS unit is externally connected to a memory DDR (n). The external memory DDR (n) can be one memory or multiple memories. (n) represents the number of external memories. The PL unit 10 includes a register module 101 and a data parsing module 102. In addition, a transmission interconnection module 30 is provided between the PL unit 10 and the PS unit 20. A part of the transmission interconnection module 30 is located in the PL unit 10, and another part is located in the PS unit 20.

[0036] The register module 101 is a module for storing data in the PL unit. The data analysis module 102 is a module for analyzing and converting interactive data in the PL unit. The transmission interconnection module 30 is used to realize data transmission and communication between the PL unit and the PS unit. The memory control module 201 is used to realize data interaction between the PS unit and the external memory.

[0037] Continue to refer to Figure 1 ,like Figure 1 As shown, the method includes:

[0038] S101. A register module receives a first transmission instruction sent by a PS unit.

[0039] The first transmission instruction is used to instruct the register module to start data synchronization. The PL unit includes a data analysis module and a register module that are communicatively connected, and the register module is communicatively connected to the application processor PS unit.

[0040] Specifically, when the data initiator is a PS unit, that is, when the PS unit needs to transfer the data in the memory to the register module of the PL unit for storage, the PS unit can directly send a first transmission instruction to the register module in the PL unit so that the register module receives the first transmission instruction and determines that the PS unit needs to start the data synchronization operation.

[0041] In this embodiment, the PS unit directly sends the first transfer instruction to the register module in the PL unit, thereby using the PS unit as the initiator of the data synchronization request, and providing start conditions for the subsequent mapping of data in the memory external to the PS unit to the register module in the PL unit.

[0042] S102: The register module sends first synchronization information to the data analysis module according to the first transmission instruction.

[0043] The first synchronization information includes a first start signal and a first address signal.

[0044] Specifically, after the register module determines the request to start data synchronization according to the first transmission instruction, it will send the first synchronization information carrying the first start signal and the first address signal to the data analysis module.

[0045] Exemplarily, the first address signal may be used to determine which memory data needs to be synchronized in this data synchronization, and may also be used to determine which data in the target memory needs to be synchronized in this data synchronization.

[0046] S103: The data analysis module establishes a communication connection with the memory control module of the PS unit through the transmission interconnection module according to the first start signal.

[0047] The memory control module is externally connected to a plurality of memories. The first start signal is used to indicate that the data parsing module needs to communicate with the memory control module of the PS unit based on the transmission interconnection module.

[0048] Specifically, after receiving the first synchronization information, the data analysis module initiates a connection request to the transmission interconnection module according to the instruction of the first start signal, so that the transmission interconnection module establishes a communication connection with the memory control module of the PS unit.

[0049] Exemplarily, the data parsing module initiates a communication connection request to the transmission interconnection module through the communication connection line according to the first start signal, so that the transmission interconnection module can graft the data onto the communication bus of the PS unit through the communication connection interface. After the communication bus of the PS unit is successfully connected to the transmission interconnection module, the communication interface of the PS unit realizes communication connection with the memory control module in the PS unit through the dedicated module (Programmable Logic to Memory) in the PS unit that interacts with the PL unit data.

[0050] In this embodiment, when the data analysis module receives the first start signal, the data analysis module directly establishes a communication connection with the memory control module of the PS unit based on the transmission interconnection module, thereby quickly establishing a data interaction connection between the PL unit and the PS unit.

[0051] S104, the data parsing module sends the first address signal to the memory control module, so that the memory control module communicates with the memory corresponding to the first address signal, receives the first synchronization data sent by the memory corresponding to the first address signal, and sends the first synchronization data to the transmission interconnection module.

[0052] Specifically, after the data parsing module successfully establishes a communication connection with the memory control module, the first address signal in the first start signal can be directly sent to the memory control module. The memory control module can determine the memory for this data synchronization based on the first address signal, and can determine a certain data to be synchronized in the memory for this data synchronization based on the first address signal. After determination, the memory control module can receive the determined data to be synchronized in the memory, that is, the first synchronization data, and send the first synchronization data to the transmission interconnection module.

[0053] In this embodiment, the memory control module determines the memory and the first synchronization data in the memory based on the first address signal, thereby achieving the determination and accurate acquisition of the location of the data to be synchronized.

[0054] S105: The data parsing module receives the first synchronization data forwarded by the transmission interconnection module, and after parsing the first synchronization data, sends the parsed first synchronization data to the register module.

[0055] Specifically, after the transmission interconnection module obtains the first synchronization data sent by the memory control module, the transmission interconnection module can forward the first synchronization data to the data parsing module. At this time, the data parsing module needs to parse the first synchronization data in other formats and send the parsed first synchronization data to the register module so that the register module can store the parsed first synchronization data.

[0056] In this embodiment, a data parsing module is used to parse the first synchronization data in other formats to obtain the parsed first synchronization data that can be stored by the register module, thereby achieving accurate data parsing and mapping the data in the memory external to the PS unit to the register module in the PL unit, so that the register module synchronizes the data in the memory external to the PS unit.

[0057] The data synchronization method provided by the embodiment of the present invention comprises the following steps: the register module receives the first transmission instruction sent by the PS unit; the register module sends the first synchronization information to the data analysis module according to the first transmission instruction; the data analysis module establishes a communication connection with the memory control module of the PS unit through the transmission interconnection module according to the first start signal; the data analysis module sends the first address signal to the memory control module, so that the memory control module communicates with the memory corresponding to the first address signal, receives the first synchronization data sent by the memory corresponding to the first address signal, and sends the first synchronization data to the transmission interconnection module; the data analysis module receives the first synchronization data forwarded by the transmission interconnection module, and after parsing the first synchronization data, sends the parsed first synchronization data to the register module. In the above technical solution, on the one hand, the PS unit directly sends the first transmission instruction to the register module in the PL unit, so as to realize the PS unit as the initiator of the data synchronization request, and provide the starting conditions for the subsequent implementation of mapping the data in the memory external to the PS unit to the register module in the PL unit. On the other hand, when the data parsing module receives the first start signal, the data parsing module will directly establish a communication connection with the memory control module of the PS unit based on the transmission interconnection module, and quickly realize the establishment of the data interaction connection between the PL unit and the PS unit; and the memory control module determines the memory and the first synchronization data in the memory based on the first address signal, and realizes the determination and accurate acquisition of the location of the data to be synchronized. Finally, the data parsing module is used to parse the first synchronization data of other formats, and the parsed first synchronization data that can be stored by the register module is obtained, and the data is accurately parsed, and the data in the memory external to the PS unit is mapped to the register module in the PL unit, so that the register module synchronizes the data in the memory external to the PS unit. And, the above method solves the problem that the current request for data acquisition or data writing is limited to being initiated from the PL unit, and realizes the data synchronization based on the PS unit as the initiator of the data synchronization request, and completes the mapping of the data in the memory external to the PS unit to the register module in the PL unit.

[0058] Figure 3 This is a flowchart of another data synchronization method provided by an embodiment of the present invention. Based on the above embodiment, this embodiment describes a complete method for data interaction between registers in the PL unit and memory mounted on the PS unit. Figure 3 Before describing the data synchronization method, the data synchronization structure involved in the embodiment of the present invention is further described. Figure 4 FIG. 1 is another structural example diagram of data synchronization provided by an embodiment of the present invention. Figure 4As shown, the register module 101 includes a read register 1011 and a write register 1012. The PL unit 10 also includes a second timer module 103. The PS unit 20 also includes a first timer module 202. The transmission interconnection module 30 includes a slave device interface 301 and a master device interface 302. The slave device interface 301 can be located in the PL unit and is communicatively connected to the data parsing module 102. The master device interface 302 can be located in the PS unit and is communicatively connected to the PS unit 20. The read register 1011 is used to store the first synchronization data, and the write register 1012 is used to store the second synchronization data. Among them, the read register is communicatively connected to the PS unit via the input / output I / O bus. The second timer module is communicatively connected to the register module via the I / O bus.

[0059] Continue to refer Figure 3 ,like Figure 3 As shown, the method includes:

[0060] S301. A register module receives a first transmission instruction sent by a PS unit.

[0061] Specifically, a timer module may be pre-set in the PS unit, for example Figure 4 The first timer module in the register module. After the user sets the first timer module and the calling cycle, the first timer module starts timing, and when the calling cycle time arrives, the first timer module is triggered, and triggers the PS unit to generate a first transmission instruction. After generating the first transmission instruction, the PS unit transmits the first transmission instruction to the read register in the register module through the I / O bus, so that the read register receives the first transmission instruction sent by the PS unit.

[0062] In this embodiment, the PS unit is triggered based on the first timer to send a first transfer instruction to the register module, thereby automatically starting the PS unit according to a preset timing cycle to enable the register in the PL unit to interact and synchronize with the data in the memory mounted on the PS unit.

[0063] S302. The register module sends first synchronization information to the data analysis module according to the first transmission instruction.

[0064] Specifically, when receiving the first transmission instruction, the read register in the register module sends the first synchronization information carrying the first start signal and the first address signal to the data analysis module, wherein the first start signal may be "recv_data_2ddr_start" and the first address signal may be "ddr_head_addr".

[0065] S303: The data analysis module establishes a communication connection with the memory control module of the PS unit through the transmission interconnection module according to the first start signal.

[0066] Specifically, the data analysis module obtains the first start signal, and is accessed through the slave device interface in the transmission interconnection module, thereby realizing the communication connection between the data analysis module and the transmission interconnection module. Among them, the slave device interface can be an M00_AXI bus. And, after the transmission interconnection module is communicatively connected with the data analysis module, it is communicatively connected with the PS unit through the master device interface. Among them, the master device interface can be an M00_AXI interface, and the interface for communication connection with the PS unit is an S_AXI_HP0 bus. That is, the transmission interconnection module is communicatively connected with the S_AXI_HP0 bus of the PS through the M00_AXI interface. Afterwards, in order to establish a communication connection with the memory control module in the PS unit, the S_AXI_HP0 interface needs to be connected to the memory control module through the Programmable Logic to Memory module. At this point, the communication connection relationship between the data analysis module and the memory control module is established.

[0067] S304, the data parsing module sends the first address signal to the memory control module, so that the memory control module communicates with the memory corresponding to the first address signal, receives the first synchronization data sent by the memory corresponding to the first address signal, and sends the first synchronization data to the transmission interconnection module.

[0068] Specifically, the data parsing module sends the first address signal to the memory control module. The memory control module determines and obtains the first synchronization data based on the first address signal. After the memory control module obtains the first synchronization data, the memory control module sends the first synchronization data to the transmission interconnection module through the Programmable Logic to Memory module and the S_AXI_HP0 interface in sequence.

[0069] S305: The data parsing module receives the first synchronization data forwarded by the transmission interconnection module, and after parsing the first synchronization data, sends the parsed first synchronization data to the register module.

[0070] Specifically, the transmission interconnection module transmits the first synchronization data to the data parsing module via the slave device interface. The data parsing module needs to parse the first synchronization data having other formats and send the parsed first synchronization data to the read register in the register module so that the read register can store the parsed first synchronization data.

[0071] In this embodiment, the PS unit is used as the initiator of the data synchronization request. When the first timer is triggered, the communication connection request is initiated by the read register in the register module of the PL unit. After the communication connection is completed, the first synchronization data is obtained from the external memory of the PS unit and the first synchronization data is transmitted to the read register using the communication connection link, thereby realizing the data synchronization of mapping the data in the external memory of the PS unit to the data in the register module in the PL unit.

[0072] S306. The register module sends second synchronization information to the data analysis module.

[0073] The second synchronization information includes a second start signal.

[0074] Specifically, another timer module may be pre-set in the PL unit, for example Figure 4 The second timer module in the data parsing module. After the user sets the second timer module and the calling cycle, the second timer module starts timing, and when the calling cycle time arrives, the second timer module is triggered, and the write register in the register module is triggered through the I / O bus to generate the second synchronization information. After the write register generates the second synchronization information, the second synchronization information is sent to the data parsing module. Among them, the second start signal can be send_data_2board_start.

[0075] Optionally, the second timer module needs to be started after the first timer module is started.

[0076] In this embodiment, the write register in the register module of the PL unit is triggered based on the second timer, so that the write register sends the second synchronization information to the data parsing module, thereby automatically starting the write register in the register module according to a preset timing cycle to enable the register in the PL unit to interact and synchronize with the data in the memory mounted on the PS unit.

[0077] S307 . The data analysis module establishes a communication connection with the memory control module through the transmission interconnection module according to the second start signal.

[0078] Specifically, when the data analysis module obtains the second start signal, it will be connected through the slave device interface in the transmission interconnection module, thus realizing the communication connection between the data analysis module and the transmission interconnection module. Also, after the data analysis module establishes a communication connection with the transmission interconnection module through the slave device interface, it establishes a communication connection with the PS unit through the master device interface, and is connected to the memory control module through the Programmable Logic to Memory module. At this point, the communication connection relationship between the data analysis module and the memory control module is established.

[0079] S308. The register module sends second synchronization data to the data analysis module.

[0080] Specifically, after the data parsing module in the PL unit establishes a communication connection relationship with the memory control module in the PS unit, the write register in the register module can send the second synchronization data to the data parsing module.

[0081] S309: The data parsing module converts the format of the second synchronization data, and sends the second synchronization data after the format conversion to the memory control module, so that the memory control module sends the second synchronization data after the format conversion to the memory corresponding to the first address signal.

[0082] Specifically, since the data format of the second synchronization data received by the data analysis module is different from the communication transmission format, in order to ensure the transmission accuracy of subsequent data, the second synchronization data needs to be converted in format. For example, the data analysis module can convert the second synchronization data into data in AXI format and send it to the memory control module through the transmission interconnection module. Afterwards, since the communication connection relationship between the memory control module and the memory corresponding to the first address signal has been determined during the data synchronization of the first synchronization data, when the memory control module receives the second synchronization data after the format conversion, the second synchronization data after the format conversion can be directly sent to the memory corresponding to the first address signal, so that the memory stores and synchronizes the second synchronization data.

[0083] In this embodiment, after the first timer is triggered, the PS unit is used as the initiator of the data synchronization request, the first synchronization data is obtained from the memory external to the PS unit and transmitted to the read register, the second timer is waited for to be triggered, and the write register in the register module of the PL unit is turned on as the initiator of the opposite-side data synchronization, and the second synchronization data is reversely transmitted from the write register to the memory external to the PS unit. The entire data transmission process realizes automatic timing data synchronization of both parties. In addition, in the process of realizing data synchronization, in order to ensure the accuracy and efficiency of data transmission, data parsing or data format conversion will be performed on the data based on the data parsing module, thereby improving the accuracy and transmission efficiency in the process of data synchronization transmission.

[0084] The data synchronization method provided by the embodiment of the present invention, on the one hand, triggers the PS unit based on the first timer so that the PS unit sends the first transmission instruction to the register module, realizes the automatic start of the PS unit according to the preset timing cycle, so that the register in the PL unit interacts and synchronizes with the data in the memory mounted by the PS unit. And, realizes that the PS unit is used as the initiator of the data synchronization request, when the first timer is triggered, the read register in the register module of the PL unit initiates the communication connection request, and after the communication connection is completed, the first synchronization data is obtained from the memory external to the PS unit and the first synchronization data is transmitted to the read register using the communication connection link, so that the data in the memory external to the PS unit is mapped to the data synchronization in the register module in the PL unit. On the other hand, based on the second timer, the write register in the register module of the PL unit is triggered so that the write register sends the second synchronization information to the data parsing module, realizes the automatic start of the write register in the register module according to the preset timing cycle, so as to enable the register in the PL unit to interact and synchronize with the data in the memory mounted by the PS unit. And, after the first timer is triggered, the PS unit is used as the initiator of the data synchronization request, the first synchronization data is obtained from the memory external to the PS unit and transmitted to the read register, the second timer is waited for to be triggered, and the write register in the register module of the PL unit is started as the initiator of the data synchronization on the opposite side, and the second synchronization data is reversely transmitted from the write register to the memory external to the PS unit, and the entire data transmission process realizes the automatic timing data synchronization of both parties. Moreover, in the process of realizing data synchronization, in order to ensure the accuracy and efficiency of data transmission, the data will be parsed or converted in the form of data based on the data parsing module, thereby improving the accuracy and transmission efficiency in the process of data synchronization transmission. Finally, in the above technical scheme, since the first timer and the second timer are used to trigger and start data transmission from different parties respectively, the data in the memory external to the PS unit and the data in the register module in the PL unit can be automatically synchronized, ensuring the regular interactive synchronization of the data in the memory external to the PS unit and the data in the register module in the PL unit. Moreover, in this solution, each synchronization can be initiated from the PS unit or the PL unit, and during the data synchronization process, there is no need to use more complex operations such as priority strategies to establish communication connections, thereby improving the stability and real-time performance of the system.

[0085] Figure 5 A schematic diagram of the structure of a data synchronization device provided by an embodiment of the present invention. Figure 5 As shown, it is applied to a PL unit, the PL unit includes a data parsing module and a register module that are communicatively connected, and the register module is communicatively connected to an application processor PS unit; the device includes:

[0086] A receiving module 501, used for the register module to receive the first transmission instruction sent by the PS unit;

[0087] The sending module 502 is used for the register module to send the first synchronization information to the data parsing module according to the first transmission instruction, wherein the first synchronization information includes a first start signal and a first address signal;

[0088] A connection module 503 is used for the data analysis module to establish a communication connection with the memory control module of the PS unit through the transmission interconnection module according to the first start signal, wherein the memory control module is externally connected to a plurality of memories;

[0089] The transmission module 504 is used for the data analysis module to send the first address signal to the memory control module, so that the memory control module communicates with the memory corresponding to the first address signal, receives the first synchronization data sent by the memory corresponding to the first address signal, and sends the first synchronization data to the transmission interconnection module;

[0090] The parsing module 505 is used for the data parsing module to receive the first synchronization data forwarded by the transmission interconnection module, and after parsing the first synchronization data, send the parsed first synchronization data to the register module.

[0091] Optionally, the data synchronization device also includes:

[0092] A reverse sending module, used for the register module to send second synchronization information to the data parsing module, wherein the second synchronization information includes a second start signal;

[0093] A reverse connection module, used for the data parsing module to establish a communication connection with the memory control module through the transmission interconnection module according to the second start signal;

[0094] A reverse transmission module, used for the register module to send second synchronization data to the data parsing module;

[0095] The format conversion module is used for the data analysis module to convert the format of the second synchronization data, and send the second synchronization data after the format conversion to the memory control module, so that the memory control module sends the second synchronization data after the format conversion to the memory corresponding to the first address signal.

[0096] The data synchronization device provided in the embodiment of the present invention can execute the data synchronization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0097] Figure 6A schematic diagram of the structure of a programmable logic PL unit 6 provided for an embodiment of the present invention. In the present embodiment, the programmable logic PL unit 6 may be a field programmable gate array (FPGA). The programmable logic PL unit may be presented in the form of an electronic device, which is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0098] like Figure 6 As shown, the PL unit 6 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by the at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the PL unit 6 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0099] A number of components in the PL unit 6 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the PL unit 6 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0100] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a data synchronization method.

[0101] In some embodiments, the data synchronization method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the PL unit 6 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the data synchronization method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the data synchronization method in any other suitable manner (e.g., by means of firmware).

[0102] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0103] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0104] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0105] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0106] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0107] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0108] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0109] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data synchronization method, characterized in that: Applied to a programmable logic PL unit, the PL unit includes a data parsing module and a register module that are communicatively connected, and the register module is communicatively connected to an application processor PS unit; the method includes: The register module receives a first transmission instruction sent by the PS unit; The register module sends first synchronization information to the data parsing module according to the first transmission instruction, wherein the first synchronization information includes a first start signal and a first address signal; The data parsing module establishes a communication connection with the memory control module of the PS unit through the transmission interconnection module according to the first start signal, wherein the memory control module is externally connected to a plurality of memories; The data parsing module sends the first address signal to the memory control module, so that the memory control module communicates with the memory corresponding to the first address signal, receives the first synchronization data sent by the memory corresponding to the first address signal, and sends the first synchronization data to the transmission interconnection module; The data parsing module receives the first synchronization data forwarded by the transmission interconnection module, and after parsing the first synchronization data, sends the parsed first synchronization data to the register module.

2. The data synchronization method according to claim 1, characterized in that: The PS unit also includes a first timer module; the first transmission instruction is generated by the PS unit and sent to the register module when the first timer module is triggered.

3. The data synchronization method according to claim 1, characterized in that: The method further comprises: The register module sends second synchronization information to the data parsing module, wherein the second synchronization information includes a second start signal; The data parsing module establishes a communication connection with the memory control module through the transmission interconnection module according to the second start signal; The register module sends second synchronization data to the data parsing module; The data analysis module converts the format of the second synchronization data and sends the second synchronization data after the format conversion to the memory control module, so that the memory control module sends the second synchronization data after the format conversion to the memory corresponding to the first address signal.

4. The data synchronization method according to claim 3, characterized in that: The PL unit further includes a second timer module, which is communicatively connected to the register module; the second synchronization information is generated by the register module when the second timer module is triggered.

5. The data synchronization method according to claim 3, characterized in that: The register module includes a read register and a write register; The first synchronization data is stored in the read register, and the second synchronization data is stored in the write register.

6. The data synchronization method according to claim 5, characterized in that: The read register is connected to the PS unit via an input / output I / O bus; the second timer module is connected to the register module via an I / O bus.

7. The data synchronization method according to claim 4, characterized in that: The transmission interconnection module includes a slave device interface and a master device interface; Wherein, the slave device interface is communicatively connected to the data parsing module, and the master device interface is communicatively connected to the PS unit.

8. A programmable logic PL unit, characterized in that: include: one or more processors; a memory for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the data synchronization method as described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the data synchronization method according to any one of claims 1 to 7 is implemented.

10. A computer program product, characterized in that include: A computer program, which, when executed by a processor, implements the data synchronization method according to any one of claims 1 to 7.

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