SOC verification optimization method and device based on instruction stream analysis, computer equipment and medium

Abstract

The invention relates to an SOC verification optimization method and device based on instruction stream analysis, computer equipment and a medium. The method comprises the following steps: uniformly sampling subprograms of a program, and extracting Basic Block sequence information in the subprograms; the instruction information of each Basic Block is extracted; collecting the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregression language model based on the instruction sequence; based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed in a comparative learning mode; reading a plurality of slice subprograms to be operated, and obtaining semantic representations of the slice subprograms through a Basic Block program behavior representation model; and constructing a subprogram similarity matrix based on the semantic representation of the slice subprogram, and performing program selection based on the subprogram similarity matrix.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a SOC verification optimization method, apparatus, computer equipment, storage medium and computer program product based on instruction flow analysis. Background Art

[0002] SoC is an integrated circuit (IC) design technology that reduces the size and power consumption of the system while improving performance and efficiency by integrating all or most functions of a computer or electronic system on a single chip. SoC is the core technology of modern electronic devices (such as smartphones, tablets, IoT devices, etc.) and is the cornerstone of the modern information industry. SoC testing is a series of processes used to verify the correctness of SoC design. The main goal of SoC testing is to ensure that the design of SoC meets the specifications and functional requirements, and to detect and locate defects in the design.

[0003] However, in a continuous integration and continuous deployment (CI / CD) environment, test suites can become large and difficult to maintain. Test program reduction technology can simplify test suites and reduce the number of test cases or the total amount of test execution while maintaining test coverage and test quality. On the one hand, test program reduction can reduce the time of test execution and make the testing process more efficient. Reducing test cases can reduce the manpower, material and time costs associated with testing and speed up the feedback cycle. On the other hand, by removing unnecessary tests, resources can be focused on tests that are more important or more likely to find defects. Removing redundant or repeated test cases can improve the overall quality of the test suite. By reducing, it can be ensured that each test case is necessary and that the test is more targeted at key functions and risk areas on the SoC.

[0004] However, there is no effective SoC test program reduction solution in conventional technologies. Summary of the invention

[0005] Based on this, it is necessary to provide an effective SOC verification optimization method, device, computer equipment, storage medium and computer program product based on instruction stream analysis to support effective SoC test program deletion in response to the above technical problems.

[0006] In a first aspect, the present application provides a SOC verification optimization method based on instruction flow analysis. The method comprises:

[0007] uniformly sampling the subroutines of the program and extracting the Basic Block sequence information in the subroutines;

[0008] Extract the instruction information of each Basic Block;

[0009] Collecting the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0010] Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed by using a contrastive learning method;

[0011] Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model;

[0012] A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

[0013] In one embodiment, the uniform sampling of the subroutines of the program and extracting the BasicBlock sequence information in the subroutines includes:

[0014] Divide the program's execution time into several fixed-length intervals;

[0015] uniformly sampling a subroutine of the procedure based on the plurality of fixed-length intervals;

[0016] Use Qemu to extract the Basic Block sequence information in the subroutine.

[0017] In one embodiment, constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence includes:

[0018] Building a vocabulary based on the instruction sequence, and extracting a first training data set from the vocabulary;

[0019] Performing context prediction training on an initial instruction semantic sequence model based on the first training data set, wherein the initial instruction semantic sequence model is constructed based on an autoregressive language model;

[0020] Calculating the difference between the predicted instruction and the actual next instruction during the context prediction training process to construct a first objective function;

[0021] Back-propagating the first objective function and calculating the gradient of the loss value with respect to the model parameters;

[0022] The model parameters are iteratively updated using the gradient descent method, and the step of performing context prediction training on the initial instruction semantic sequence model based on the first training data set is returned to until the loss value converges or reaches a preset number of training rounds, thereby obtaining an instruction semantic sequence model.

[0023] In one embodiment, the constructing of a Basic Block program behavior representation model based on the instruction semantic sequence model by contrastive learning includes:

[0024] A read token is added at the end of the input of the instruction semantic sequence model to obtain a Basic Block program behavior representation model.

[0025] In one embodiment, the constructing of a Basic Block program behavior representation model based on the instruction semantic sequence model by contrastive learning includes:

[0026] Performing random masking processing on the instruction sequence to generate a second training data set for contrastive learning, wherein the second training data set includes positive sample pairs and negative sample pairs;

[0027] Using the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair;

[0028] Calculate the similarity between the semantic representation vector of each basic block and the positive sample pair and the negative sample pair to obtain the second objective function based on cosine similarity;

[0029] Back-propagating the second objective function to calculate the gradient of the loss value with respect to the model parameters;

[0030] The model parameters are iteratively updated using the gradient descent method, and the step of using the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair is returned until the loss value converges or reaches a preset number of training rounds, thereby obtaining a Basic Block program behavior representation model.

[0031] In one embodiment, the reading of a plurality of slice subroutines to be executed and obtaining the semantic representation of the slice subroutines through the Basic Block program behavior representation model includes:

[0032] Slice the test programs in different test suites according to the preset fixed length intervals to obtain a number of sliced ​​subprograms to be run;

[0033] further slicing the slicing subroutine into sub-segments;

[0034] Obtaining a semantic vector of each of the sub-segments through the Basic Block program behavior representation model;

[0035] The semantic vectors of the sub-segments are clustered using the KMeans clustering method to obtain the semantic representation of the slicing subroutine.

[0036] In one embodiment, the constructing a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and performing program selection based on the subroutine similarity matrix includes:

[0037] Based on the semantic representation of the slicing subprogram, the similarity between the slicing program behavior vectors is measured by the cosine method to construct a slicing program similarity matrix;

[0038] The KMeans clustering algorithm is used to cluster the slicing program similarity matrix and select representative subroutines from it.

[0039] In a second aspect, the present application also provides a SOC verification and optimization device based on instruction flow analysis. The device comprises:

[0040] A sampling module, used for uniformly sampling the subroutines of a program and extracting Basic Block sequence information in the subroutines;

[0041] Extraction module, used to extract instruction information of each Basic Block;

[0042] A first model building module, used for collecting the instruction information and the Basic Block sequence information to obtain an instruction sequence, and building an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0043] A second model building module is used to build a Basic Block program behavior representation model based on the instruction semantic sequence model by using a contrastive learning method;

[0044] A semantic processing module, used for reading a number of slice subroutines to be run, and obtaining the semantic representation of the slice subroutines through the Basic Block program behavior representation model;

[0045] The selection module is used to construct a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and perform program selection based on the subroutine similarity matrix.

[0046] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0047] uniformly sampling the subroutines of the program and extracting the Basic Block sequence information in the subroutines;

[0048] Extract the instruction information of each Basic Block;

[0049] Collecting the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0050] Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed by using a contrastive learning method;

[0051] Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model;

[0052] A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

[0053] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0054] uniformly sampling the subroutines of the program and extracting the Basic Block sequence information in the subroutines;

[0055] Extract the instruction information of each Basic Block;

[0056] Collecting the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0057] Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed by using a contrastive learning method;

[0058] Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model;

[0059] A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

[0060] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0061] uniformly sampling the subroutines of the program and extracting the Basic Block sequence information in the subroutines;

[0062] Extract the instruction information of each Basic Block;

[0063] Collecting the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0064] Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed by using a contrastive learning method;

[0065] Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model;

[0066] A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

[0067] The above-mentioned SOC verification optimization method, device, computer equipment, storage medium and computer program product based on instruction flow analysis uniformly samples the subroutines of the program and extracts the Basic Block sequence information in the subroutines; extracts the instruction information of each Basic Block; collects the instruction information and Basic Block sequence information to obtain the instruction sequence, and constructs the instruction semantic sequence model based on the autoregressive language model based on the instruction sequence; constructs the Basic Block program behavior representation model based on the instruction semantic sequence model and by contrastive learning; reads several sliced ​​subroutines to be run, and obtains the semantic representation of the sliced ​​subroutines through the BasicBlock program behavior representation model; constructs the subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and selects the program based on the subroutine similarity matrix. In the whole process, by analyzing the instruction sequence of the test program when it is executed, a hierarchical language model is established to analyze the behavior of the test program, and the program features extracted based on the instruction sequence are close to the hardware functions, which enables the dynamic analysis method to achieve more effective test program deletion in SoC testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 An application environment diagram of a SOC verification optimization method based on instruction flow analysis in one embodiment;

[0069] Figure 2 A flowchart of a SOC verification optimization method based on instruction flow analysis in one embodiment;

[0070] Figure 3 is a schematic diagram of a sub-process of S300 in an embodiment;

[0071] Figure 4 is a schematic diagram of a sub-process of S400 in one embodiment;

[0072] Figure 5 is a schematic diagram of a sub-process of S500 in one embodiment;

[0073] Figure 6 It is a structural block diagram of the SOC verification and optimization device based on instruction stream analysis in one embodiment;

[0074] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0076] In order to explain in detail the technical principles, technical solutions and effects of the SOC verification optimization method based on instruction stream analysis of the present application, the effects will first be introduced with respect to the overall inventive concept based on the prior art.

[0077] Test program reduction technology is divided into white-box testing and black-box testing according to test transparency. White-box testing is a testing method that goes deep into the internal structure and logic of the DUT. It requires testers to have a deep understanding of the internal implementation of the DUT and need to know the coverage relationship between the test program and the functional points. In contrast, black-box testing does not care about the internal structure or implementation details of the DUT, but focuses on analyzing the external test program itself. By analyzing the similarities between test programs, they can build models to reduce test programs.

[0078] The analysis methods of test programs in black box testing mainly include three types: historical behavior analysis, static analysis and dynamic analysis of test programs:

[0079] The historical behavior analysis method mainly analyzes the behavior of the test program in the previous test cycle (such as historical data such as the execution history of the test case, defect discovery records, etc.), and builds a model to predict the error behavior or defect mode that the software may exhibit in the new test cycle. Using historical error behavior, the similarity between test programs can be modeled. If two test cases showed similar failure modes in the past, they may reveal similar defects in future tests. Based on this similarity model, the selection and execution order of test cases can be optimized. The problem with the historical behavior analysis method is its data dependency, which relies on the collection of historical test data. If there is not enough historical data, the analysis results will not be accurate enough, resulting in the failure of the method. However, in a fast-iterative development environment, there may not be enough time to execute all test programs and collect data, especially in the practice of agile development and continuous integration. At the same time, in the scenario where test program deletion is required, the number of test programs themselves is large. Executing a large number of test programs to collect historical data requires significant computing resources and time, which is not feasible when resources are limited or the test cycle is tight. Therefore, the historical behavior analysis method is only applicable to regression testing, because in regression testing, testers already have a set of existing historical execution data.

[0080] Static analysis methods focus on identifying similarities between test programs by analyzing their static features without executing the programs. Static analysis usually involves reviewing the source code of the test program, evaluating the structure of the test program, including module calls, data flow, and control flow, and comparing the text content of the test program, such as comments, variable names, and function names, to analyze the test program. On the one hand, although the program is not executed, static analysis methods can predict the code paths that they may cover by analyzing the logical structure of the test cases, thereby streamlining the number of test programs. On the other hand, static analysis techniques can identify repeated or similar code patterns in test programs and reduce redundant tests. The problem with static analysis methods is that they are only applicable to the analysis of test programs with small code size. As the code size grows, the code structure becomes more complex, and static analysis will find it difficult to understand and track the logic of the program. In addition, the code quality of the test program is not always guaranteed, and low-quality code content will also affect the accuracy and consistency of static analysis.

[0081] Dynamic analysis methods focus on the behavior of the test program during actual runtime. Unlike historical behavior analysis methods, dynamic analysis methods do not need to run on a real DUT. Simulators, virtual machines, or test doubles can be used to simulate the operating environment on the DUT and collect dynamic behavior data. Dynamic analysis methods include function call graph analysis and log analysis. The function call graph analysis method mainly tracks the function call sequence during program execution and builds a function call graph, which can reveal the control flow of the program and help identify program behavior. The log analysis method mainly analyzes detailed information when the program is running. Analyzing the log can indirectly obtain the characteristics of the program running and understand the behavior of the program. In SoC test program deletion, more attention is paid to reusability. On the one hand, the deletion method does not need to change with different hardware; on the other hand, the deletion method does not need to change with the change of the test suite. Although the analysis of the function call graph can reflect the behavior information of the program to a certain extent, the function will change with the change of the test program, so it needs to be updated when the test suite changes.

[0082] This application is mainly based on the program dynamic analysis method, and proposes a hierarchical language model for instruction sequence modeling for SoC test program deletion. The core idea of ​​this model is to establish a hierarchical language model to analyze the behavior of the test program by analyzing the instruction sequence of the test program during execution. The program features extracted based on the instruction sequence are closest to the hardware functions, which enables the dynamic analysis method to achieve more effective test program deletion in SoC testing.

[0083] The main problem faced in modeling the similarity between programs through instruction sequence analysis is the long dependency problem of instruction sequences. A program with 1 billion instructions is very small and may only take a few seconds to run, but existing mathematical models such as artificial neural networks cannot effectively analyze such long sequences. To this end, this solution adopts a hierarchical analysis method to split the long instruction sequence into several Basic Block sequences, first analyze the information in the Basic Block sequence, and then integrate the representations of these Basic Block sequence fragments to form a complete representation of the instruction sequence. Basic Block is the smallest behavioral unit of a program, BasicBlock is the smallest behavioral unit in a program, and Basic Block sequence analysis can capture a variety of behaviors in a program. Therefore, this method can not only solve the dependency modeling problem of long sequences, but also capture the key behaviors of the program.

[0084] In addition, instructions are discrete tokens, which are difficult to process with traditional analysis methods. The instruction sequence needs to be converted into a continuous vector representation in order to perform effective sequence analysis. To this end, this solution adopts a language model for instruction sequence modeling to convert the instruction sequence into a continuous vector representation. Language models have achieved great success in the field of natural language processing (NLP) and can extract rich feature information from token sequences. Instruction sequences are similar to natural languages. They both have a fixed token vocabulary and the sequence itself contains certain rules. Therefore, language models can be used to model and analyze instruction sequences. Since the language model is a self-supervised learning model, it does not require annotation of training data. The training process is highly scalable. Large-scale unlabeled instruction sequences can be used to train instruction language models with large parameter scales to fully extract the features of instruction sequences.

[0085] The instruction language model can only generate representations of instructions and cannot be used directly to represent instruction sequences. Existing studies on language models have also found that the vector information output by the language model cannot be measured in a simple way. Therefore, this scheme proposes a method based on contrastive learning to fine-tune the instruction language model so that it can generate instruction sequence vectors that can calculate similarity. Contrastive learning learns to capture and understand the semantic information of the program by narrowing the similarity between Positive Pairs and widening the detailed lines between Negative Pairs, and obtains instruction sequence representations that can calculate similarity. Contrastive learning is also a self-supervised learning method that can generate a large amount of training data to train the model without manual labeling.

[0086] When processing a slice of 1 billion instructions, even if it is cut into subsequences, each subsequence is of length S, there will still be a large number of subsequences (1 billion -S ). Among these slice subsequences, only a small part has an identifying role, and most of them are noise subsequences. To this end, this scheme will design a clustering expression mechanism to extract the subsequences with identification through clustering, and combine all cluster centers to form the overall representation of the subroutine. The mechanism behind the clustering method is data compression, which compresses a large number of subsequences into cluster centers. As the representation of the subroutine, the cluster center can more accurately reflect the key features and behaviors of the program. Therefore, this process can remove a large number of noise subsequences and obtain an effective representation of the subroutine.

[0087] Based on the above inventive concept, the SOC verification optimization method based on instruction flow analysis provided in the embodiment of the present application can be applied to Figure 1In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. The terminal 102 sends a SoC test program deletion request to the server 104, and the server 104 responds to the request, uniformly samples the subroutines of the program, and extracts the Basic Block sequence information in the subroutines; extracts the instruction information of each Basic Block; collects the instruction information and the Basic Block sequence information to obtain the instruction sequence, and constructs an instruction semantic sequence model based on the autoregressive language model based on the instruction sequence; constructs a Basic Block program behavior representation model based on the instruction semantic sequence model and by contrastive learning; reads several slice subroutines to be run, and obtains the semantic representation of the slice subroutine through the BasicBlock program behavior representation model; constructs a subroutine similarity matrix based on the semantic representation of the slice subroutine, and selects the program based on the subroutine similarity matrix. The terminal 102 may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, IoT devices, and portable wearable devices. The IoT devices may be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. The portable wearable devices may be smart watches, smart bracelets, head-mounted devices, etc. The server 104 may be implemented as an independent server or a server cluster consisting of multiple servers.

[0088] In one embodiment, Figure 2 As shown in FIG. 1 , a SOC verification optimization method based on instruction flow analysis is provided to reduce the number of instruction flow analysis commands. Figure 1 Taking the server 104 in the example as an example, the following steps are included:

[0089] S100: uniformly sampling the subroutines of the program and extracting the Basic Block sequence information in the subroutines.

[0090] The subroutines of the uniformly sampled program can specifically divide the execution time of the program into several fixed-length intervals. These intervals are divided in units of the number of instructions (for example, 1 billion instructions). Each interval "segment" is a subroutine. After sampling the subroutine, extract the Basic Block sequence information therein. Basic Block is the smallest unit in the program execution control flow. The instructions in the basic block are continuous and there are no jumps. The basic block can be regarded as a node in the control flow graph, and the complex control flow of the program can be simplified into several basic blocks and their connections.

[0091] S200: Extracting instruction information of each Basic Block.

[0092] The instruction information of Basic Block can be extracted through plug-ins. Specifically, when obtaining Basic Block sequence information, Qemu can be used to extract the Basic Block sequence information in the subroutine. When extracting the instruction information in each BasicBlock, the plug-in function can be registered in the TB execution phase of QEMU simulating the target program to record all the instruction contents in TB, which is the instruction information in Basic Block.

[0093] S300: Collect instruction information and Basic Block sequence information to obtain an instruction sequence, and construct an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence.

[0094] The instruction semantic sequence model includes a word embedding layer and an encoding layer. The encoding layer uses a 12-layer Transformer encoder. The word embedding layer contains not only token content encoding, but also token position encoding to retain the order information of the sequence, and token category encoding to retain the sensitivity to different contents of the instruction. Among them, the tokens in the same instruction use the same position encoding, and the token category encoding includes five token categories such as operation code, condition code, register, operand, and operation address. The autoregressive language model is a self-supervised learning method. By training the model to effectively predict the next instruction in the program running, the model is guided to understand and represent the meaning of program instructions. Through this self-supervised learning method, the instruction semantic representation model can capture and understand the relationship and semantic information between program instructions. Based on the previous processing steps, a large amount of instruction information and Basic Block sequence information are collected from the program running process to obtain the instruction sequence. With this instruction sequence as the data basis, an instruction semantic sequence model based on the autoregressive language model is constructed.

[0095] Specifically, a language model is used here to build an instruction sequence model. Instructions are discrete tokens, which are difficult to process with traditional analysis methods. Instruction sequences need to be converted into continuous vector representations for effective sequence analysis. Language models have achieved great success in the field of natural language processing (NLP) and can extract rich feature information from token sequences. Instruction sequences are similar to natural languages, both have fixed token lexicons, and the sequences themselves contain certain rules. Therefore, language models can be used to model and analyze instruction sequences and build instruction sequence models.

[0096] S400: Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed using contrastive learning.

[0097] The Basic Block program behavior representation model is constructed based on the contrastive learning method. Specifically, the program behavior representation model is constructed based on the instruction semantic sequence model, mainly by adding a read-out token ([read-out]token) at the end of the input of the instruction semantic sequence model to integrate the output of the instructions in the basic block. The output vector of the instruction semantic sequence model on the [read-out]token will be input into a fully connected layer for feature transformation, and the vector after feature transformation will be used as the behavior representation of the basic block. The above model construction process is a self-supervised learning method. This method can compress and encode the input data by recovering the original data from the noisy data.

[0098] Specifically, contrastive learning is used here to build an instruction sequence representation model that can measure similarity. The vector information output by the language model cannot be measured in some simple ways. After fine-tuning the instruction representation model using contrastive learning, an instruction sequence representation model with measurable similarity can be built. Contrastive learning captures and understands the semantic information of the program by narrowing the similarity between positive pairs and widening the similarity between negative pairs, and obtains an instruction sequence representation that can calculate similarity.

[0099] S500: Read several slice subroutines to be run, and obtain the semantic representation of the slice subroutines through the Basic Block program behavior representation model.

[0100] The test programs in different test suites are sliced ​​at fixed-length intervals to obtain several sliced ​​subroutine snapshots to be run. In the present invention, the length interval is set to 1 billion instructions. Select a test suite containing multiple test programs, and collect the complete execution traces of the test programs in different test suites. Run each test program and record the instruction sequence it executes. Store the collected instruction execution traces in a log file for subsequent processing. Set the fixed-length interval of slicing to 1 billion instructions, count each instruction in the instruction execution trace, and slice after reaching 1 billion instructions to generate several subroutine snapshots. Repeat the above process until all instruction sequences are processed. Each subroutine snapshot contains instructions of a fixed length.

[0101] The program behavior representation model constructed by S400 is used to obtain the semantic representation of the sliced ​​subprogram. In order to accurately represent the semantic features of the sliced ​​subprogram, the sliced ​​subprogram is further divided into smaller sub-segments, and the program behavior representation model is used to semantically represent these sub-segments to obtain the local behavior features in the subprogram.

[0102] S600: constructing a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and performing program selection based on the subroutine similarity matrix.

[0103] Based on the semantic representation of the sliced ​​subroutines obtained in S500, a subroutine similarity matrix is ​​constructed to characterize the similarity between sliced ​​program behavior vectors. Then, program selection is performed based on the subroutine similarity matrix to achieve program deletion, ultimately supporting effective SoC test program deletion.

[0104] The above-mentioned SOC verification optimization method based on instruction flow analysis uniformly samples the subroutines of the program and extracts the Basic Block sequence information in the subroutines; extracts the instruction information of each Basic Block; collects the instruction information and BasicBlock sequence information to obtain the instruction sequence, and constructs the instruction semantic sequence model based on the autoregressive language model based on the instruction sequence; constructs the Basic Block program behavior representation model based on the instruction semantic sequence model and by contrastive learning; reads several sliced ​​subroutines to be run, and obtains the semantic representation of the sliced ​​subroutines through the Basic Block program behavior representation model; constructs the subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and selects the program based on the subroutine similarity matrix. In the whole process, by analyzing the instruction sequence of the test program when it is executed, a hierarchical language model is established to analyze the behavior of the test program, and the program features extracted based on the instruction sequence are close to the hardware functions, which enables the dynamic analysis method to achieve more effective test program deletion in SoC testing.

[0105] In one of the embodiments, uniformly sampling the subroutines of a program and extracting the Basic Block sequence information in the subroutines includes: dividing the execution time of the program into a number of fixed-length intervals; uniformly sampling the subroutines of the program based on the number of fixed-length intervals; and extracting the Basic Block sequence information in the subroutines using Qemu.

[0106] In this embodiment, Qemu is used to extract the Basic Block sequence information in the subroutine. Qemu is an open source emulator and virtual machine. Qemu takes the basic block of the program as the unit, establishes a TCG (tinycode generator) translation layer between the host machine and the target architecture, and translates the instructions of the target architecture into host machine instructions for execution. The code block obtained by translation is called a translation block (TB), which is equivalent to the basic block of the program execution under the target architecture. Qemu provides a plug-in mechanism to observe and record the operation of the target program. One or more plug-ins can be loaded and run in the form of a dynamic link library at startup. The plug-in function is registered in the TB execution phase of the Qemu simulation operation target program, and the instruction address of the TB is recorded as the mark of the Basic Block. The address information of these Basic Blocks will be retained, and the execution sequence information of the Basic Block will be formed in chronological order.

[0107] like Figure 3 As shown, in one embodiment, S300 includes:

[0108] S310: Collect instruction information and Basic Block sequence information to obtain an instruction sequence.

[0109] The instruction information and Basic Block sequence information obtained in the previous processing steps are collected and sorted to obtain a large number of instruction sequences.

[0110] S320: construct a vocabulary based on the instruction sequence, and extract a first training data set from the vocabulary.

[0111] In an instruction sequence, an instruction includes an opcode, an operand, and a register. Each instruction is segmented to obtain the opcode, operand, and register related to the instruction. For example, an instruction MOV R1,100 can be segmented into MOV (opcode), R1 (register), and 100 (operand). The opcode, operand, and register are regarded as tokens. All independent tokens are collected to build a vocabulary. The vocabulary can be represented by a dictionary, where the key is the token and the value is the corresponding unique index. A training data set is constructed from the collected instruction sequence. A subsequence of 128 instructions in length is randomly sampled from the instruction sequence. The length of the subsequence can be adjusted according to demand, but is fixed to 128 instructions in the present invention. Each subsequence is used as part of the training data, and each instruction in the subsequence is decomposed into a token index for input into the model.

[0112] S330: Performing context prediction training on an initial instruction semantic sequence model based on a first training data set, where the initial instruction semantic sequence model is constructed based on an autoregressive language model.

[0113] Use the initial instruction semantic model to predict the next instruction. Convert the word meta-index of the input 128 instructions into an embedding vector. Input the embedding vector of the first 128 instructions into the Transformer encoder, and the model outputs the prediction result for the next instruction, which is the 129th instruction after the 128th instruction.

[0114] S340: Calculate the difference between the predicted instruction and the actual next instruction during the context prediction training process, and construct a first objective function.

[0115] Calculate the difference between the predicted instruction and the actual next instruction. The actual next instruction contains multiple tokens (opcodes, operands, registers, etc.), and calculate the cross entropy loss for each predicted token and the actual token. Specifically, calculate the cross entropy between the predicted distribution and the actual distribution at each position. Sum the losses of all tokens as the overall loss value.

[0116] S350: Back-propagate the first objective function and calculate the gradient of the loss value with respect to the model parameters.

[0117] The objective function in S340 is back-propagated to calculate the gradient of the loss value with respect to the model parameters.

[0118] S360: Use the gradient descent method to iteratively update the model parameters, and return to step S330 until the loss value converges or reaches the preset number of training rounds to obtain the instruction semantic sequence model.

[0119] The model parameters are updated using a gradient descent algorithm. The processing steps from S300 to S350 are repeated to iteratively update the model parameters until the loss value converges or reaches a preset number of training rounds, and finally an instruction semantic sequence model is obtained.

[0120] like Figure 4 As shown, in one embodiment, S400 includes:

[0121] S410: Perform random masking processing on the instruction sequence to generate a second training data set for contrastive learning, where the second training data set includes positive sample pairs and negative sample pairs.

[0122] Training data construction. Construct a training data set from the collected instruction sequences. Generate training data for contrastive learning through random masking, including positive sample pairs and negative sample pairs. Specifically, some instructions in each Basic Block are randomly masked, that is, some tokens of some instructions are randomly selected for masking. The positive sample of the original sample is the Basic Block after some tokens of some instructions in the basic block are randomly masked. The original basic block and the basic block after random masking form a positive sample pair. In the construction of negative sample pairs, the negative samples are 63 other basic blocks randomly selected from the data set. The original basic block and the 64 randomly selected basic blocks form negative sample pairs respectively.

[0123] S420: Generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair using an instruction semantic sequence model.

[0124] The instruction semantic sequence model is used to generate a semantic representation vector for each basic block. A special [read-out] token is added at the end of each Basic Block. This token is used to extract the overall semantic representation of the Basic Block. The Basic Block containing the [read-out] token is input into the instruction semantic sequence model, and the semantic representation vector of the entire Basic Block is extracted through the [read-out] token.

[0125] S430: Calculate the similarity between each basic block semantic representation vector and the positive sample pair and the negative sample pair to obtain a second objective function based on cosine similarity.

[0126] The model is trained by maximizing the similarity of positive sample pairs and minimizing the similarity of negative sample pairs. For each basic block, the similarity of its semantic representation vector with the positive sample pair and the negative sample pair is calculated, and the cosine similarity is used to measure the similarity. The similarity is converted into a probability distribution using the Softmax function. The goal is to make the similarity probability of the positive sample pair the highest and the similarity probability of the negative sample pair the lowest, and the loss value is calculated using the comparative InfoNCE function.

[0127] S440: Perform back propagation on the second objective function to calculate the gradient of the loss value with respect to the model parameters.

[0128] Back-propagation is performed on the second objective function in S430 to calculate the gradient of the loss value with respect to the model parameters.

[0129] S450: Iteratively update the model parameters using the gradient descent method, and return to S420 until the loss value converges or reaches a preset number of training rounds, to obtain a Basic Block program behavior representation model.

[0130] The model parameters are updated using a gradient descent algorithm. S420 to S450 are repeated to iteratively update the model parameters until the loss value converges or reaches a preset number of training rounds.

[0131] like Figure 5 As shown, in one embodiment, S500 includes:

[0132] S510: Slice the test programs in different test suites according to preset fixed-length intervals to obtain a number of sliced ​​subprograms to be run.

[0133] The test programs in different test suites are sliced ​​at fixed-length intervals to obtain several sliced ​​subroutine snapshots to be run. In the present invention, the length interval is set to 1 billion instructions. Select a test suite containing multiple test programs, and collect the complete execution traces of the test programs in different test suites. Run each test program and record the instruction sequence it executes. Store the collected instruction execution traces in a log file for subsequent processing. Set the fixed-length interval of slicing to 1 billion instructions, count each instruction in the instruction execution trace, and slice after reaching 1 billion instructions to generate several subroutine snapshots. Repeat the above process until all instruction sequences are processed. Each subroutine snapshot contains instructions of a fixed length.

[0134] S520: Further divide the slice subroutine into sub-segments.

[0135] The sliced ​​subroutine is further divided into sub-segments. The sliced ​​subroutine is further divided into smaller sub-segments to capture finer-grained program features and avoid failure of program feature capture due to overly long dependencies. Select a suitable sub-segment length. In this invention, 128 Basic Blocks are used as the length of the sub-segment. The specific length can be adjusted according to actual needs and model capabilities, and the selected length should be sufficient to capture the local behavior characteristics of the program. After segmentation, a subroutine of length S will contain S-128 sub-segments.

[0136] S530: Obtaining the semantic vector of each sub-segment through the Basic Block program behavior representation model.

[0137] The semantic vector of each sub-segment is obtained through the Basic Block program behavior representation model obtained previously.

[0138] S540: clustering the semantic vectors of the sub-segments using the KMeans clustering method to obtain the semantic representation of the slice subroutine.

[0139] Program behavior representation based on feature clustering expression. In order to handle the semantic representation of large-scale sub-fragments, direct averaging may lead to feature loss or inaccuracy. In order to better capture and express the overall behavioral characteristics of the program, the KMeans clustering method is used to cluster the semantic vectors of the sub-fragments. The distance indicator used for clustering is Cosine similarity, and the number of categories in the cluster is set to 1024. Subsequently, the average value of the 1024 cluster centers is used to express the overall behavioral characteristics of the program, and the feature vector of the sub-program is obtained.

[0140] In general, a clustering expression mechanism is used here to obtain the global semantic representation of the sliced ​​subroutine. The subsequences with identifiers are extracted through clustering, and all cluster centers are combined to form the overall representation of the subroutine. The mechanism behind the clustering method is data compression, which compresses a large number of subsequences into cluster centers. The cluster centers, as the representation of the subroutine, can more accurately reflect the key features and behaviors of the program. Therefore, this process can remove a large number of noise subsequences and obtain an effective representation of the subroutine.

[0141] In one embodiment, constructing a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and performing program selection based on the subroutine similarity matrix includes:

[0142] Step 1: Based on the semantic representation of slice subroutines, the cosine method is used to measure the similarity between slice program behavior vectors and construct a slice program similarity matrix.

[0143] Subroutine similarity matrix construction. Based on the semantic representation vector of each slice subroutine obtained in the previous step, the similarity between slice program behavior vectors is measured using the cosine method to construct a slice program similarity matrix. By calculating the cosine similarity between slice program behavior vectors, a similarity matrix is ​​constructed to reflect the similarity between different slice subroutines.

[0144] Step 2: Use the KMeans clustering algorithm to cluster the slice program similarity matrix and select representative subroutines from it.

[0145] KMeans clustering to select subroutines. Use the KMeans clustering algorithm to cluster the similarity matrix and select representative subroutines from it. The KMeans algorithm can cluster similar subroutines into the same group and find the center of each group. Determine the number of cluster centers K based on the number of subroutines that need to be selected. This number is usually determined by the actual test requirements. Run the KMeans algorithm to cluster the sliced ​​subroutines into K clusters. Select the subroutines closest to the center to obtain K representative subroutines. These K subroutines are the subroutines selected for actual testing.

[0146] In general, in the above embodiments, the SOC verification optimization method based on instruction flow analysis of the present application has the following significant technical advantages:

[0147] One of the advantages of the present application is that it is highly reusable. Since the instruction set is fixed, the vocabulary of the instruction sequence representation model is also fixed. For the same instruction set, the changes in the instructions are very small and are basically fixed. Therefore, the model does not need to update the vocabulary frequently, and the same vocabulary can be used for sequence representation for a long time. Due to the fixedness of the instruction set and the vocabulary, the sequence representation model trained based on the instruction set can be reused in different projects and tests. Whether it is a newly designed SoC or an improved version of an existing SoC, as long as the instruction set remains unchanged, the model can be directly applied without retraining.

[0148] The second advantage of this application is that the length of the test program can be reduced by evenly slicing the test program according to the instruction interval. The shorter the test program, the more concentrated and clear its behavioral characteristics are, which helps to accurately match similar behaviors. Through refined similarity analysis, it is easier to find other program fragments with similar behaviors, thereby achieving effective deletion of the test program. This can reduce redundant test cases and improve test efficiency and quality.

[0149] The third advantage of this application is the analysis capability across test suites. In SoC testing, the test programs generated by different test suites will eventually run on the SoC system in the form of instruction sequences. Therefore, the analysis method based on instruction sequences can uniformly analyze and optimize the test programs across different test suites. This uniformity helps to maintain the consistency of the analysis method when managing and maintaining multiple test suites, and reduce the complexity caused by the differences between different suites.

[0150] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0151] Based on the same inventive concept, the embodiment of the present application also provides a SOC verification and optimization device based on instruction stream analysis for implementing the SOC verification and optimization method based on instruction stream analysis involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more SOC verification and optimization device embodiments based on instruction stream analysis provided below can refer to the limitations of the SOC verification and optimization method based on instruction stream analysis above, and will not be repeated here.

[0152] In one embodiment, Figure 6 As shown, a SOC verification and optimization device based on instruction flow analysis is provided, comprising:

[0153] The sampling module 100 is used to uniformly sample the subroutines of the program and extract the Basic Block sequence information in the subroutines;

[0154] An extraction module 200, used to extract instruction information of each Basic Block;

[0155] The first model building module 300 is used to collect instruction information and Basic Block sequence information to obtain an instruction sequence, and to build an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0156] The second model building module 400 is used to build a Basic Block program behavior representation model based on the instruction semantic sequence model by using a contrastive learning method;

[0157] The semantic processing module 500 is used to read a number of slice subroutines to be run, and obtain the semantic representation of the slice subroutines through the Basic Block program behavior representation model;

[0158] The selection module 600 is used to construct a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and perform program selection based on the subroutine similarity matrix.

[0159] In one of the embodiments, the sampling module 100 is further used to divide the execution time of the program into a number of fixed-length intervals; based on the several fixed-length intervals, uniformly sample the subroutines of the program; and use Qemu to extract Basic Block sequence information in the subroutines.

[0160] In one embodiment, the first model building module 300 is also used to build a vocabulary based on the instruction sequence and extract a first training data set from the vocabulary; perform context prediction training on an initial instruction semantic sequence model based on the first training data set, and the initial instruction semantic sequence model is built based on an autoregressive language model; calculate the difference between the predicted instruction and the actual next instruction during the context prediction training process, and construct a first objective function; backpropagate the first objective function, and calculate the gradient of the loss value with respect to the model parameters; iteratively update the model parameters using the gradient descent method, and return to the step of performing context prediction training on the initial instruction semantic sequence model based on the first training data set, until the loss value converges or reaches a preset number of training rounds, and obtain the instruction semantic sequence model.

[0161] In one of the embodiments, the second model building module 400 is further used to add a read token at the end of the input of the instruction semantic sequence model to obtain a Basic Block program behavior representation model.

[0162] In one embodiment, the second model building module 400 is also used to perform random masking on the instruction sequence to generate a second training data set for comparative learning, the second training data set including positive sample pairs and negative sample pairs; using the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pairs and the negative sample pairs; calculating the similarity between the semantic representation vector of each basic block and the positive sample pairs and the negative sample pairs to obtain a second objective function based on cosine similarity; backpropagating the second objective function to calculate the gradient of the loss value relative to the model parameters; using the gradient descent method to iteratively update the model parameters, returning to the step of using the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pairs and the negative sample pairs, until the loss value converges or reaches a preset number of training rounds, and obtaining a Basic Block program behavior representation model.

[0163] In one of the embodiments, the semantic processing module 500 is also used to slice the test programs in different test suites at intervals of preset fixed length to obtain a number of sliced ​​subprograms to be run; further divide the sliced ​​subprograms into sub-segments; obtain the semantic vector of each sub-segment through the Basic Block program behavior representation model; cluster the semantic vectors of the sub-segments using the KMeans clustering method to obtain the semantic representation of the sliced ​​subprogram.

[0164] In one embodiment, the selection module 600 is also used to measure the similarity between slicer program behavior vectors based on the semantic representation of the slicer subroutine using the cosine method to construct a slicer program similarity matrix; and to cluster the slicer program similarity matrix using the KMeans clustering algorithm to select representative subroutines therefrom.

[0165] Each module in the above-mentioned SOC verification and optimization device based on instruction flow analysis can be implemented in whole or in part by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0166] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 7 As shown. The computer device includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store preset data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a SOC verification optimization method based on instruction flow analysis is implemented.

[0167] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0168] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above-mentioned SOC verification optimization method based on instruction stream analysis when executing the computer program.

[0169] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned SOC verification optimization method based on instruction stream analysis is implemented.

[0170] In one embodiment, a computer program product is provided, including a computer program, which implements the above-mentioned SOC verification optimization method based on instruction stream analysis when executed by a processor.

[0171] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0172] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the above-mentioned computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0173] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0174] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A SOC verification optimization method based on instruction flow analysis, characterized in that: The method comprises: uniformly sampling the subroutines of the program and extracting the Basic Block sequence information in the subroutines; Extract the instruction information of each Basic Block; Collecting the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence; Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed by using a contrastive learning method; Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model; A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

2. The method according to claim 1, characterized in that: The subroutine of the uniform sampling program and extracting the Basic Block sequence information in the subroutine include: Divide the program's execution time into several fixed-length intervals; uniformly sampling a subroutine of the procedure based on the plurality of fixed-length intervals; Use Qemu to extract the Basic Block sequence information in the subroutine.

3. The method according to claim 1, characterized in that Constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence includes: Building a vocabulary based on the instruction sequence, and extracting a first training data set from the vocabulary; Performing context prediction training on an initial instruction semantic sequence model based on the first training data set, wherein the initial instruction semantic sequence model is constructed based on an autoregressive language model; Calculating the difference between the predicted instruction and the actual next instruction during the context prediction training process to construct a first objective function; Back-propagating the first objective function and calculating the gradient of the loss value with respect to the model parameters; The model parameters are iteratively updated using the gradient descent method, and the step of performing context prediction training on the initial instruction semantic sequence model based on the first training data set is returned to until the loss value converges or reaches a preset number of training rounds, thereby obtaining an instruction semantic sequence model.

4. The method according to claim 1, characterized in that: The method of constructing a Basic Block program behavior representation model based on the instruction semantic sequence model and using a contrastive learning method includes: A read token is added at the end of the input of the instruction semantic sequence model to obtain a Basic Block program behavior representation model.

5. The method according to claim 1, characterized in that The method of constructing a Basic Block program behavior representation model based on the instruction semantic sequence model and using a contrastive learning method includes: Performing random masking processing on the instruction sequence to generate a second training data set for contrastive learning, wherein the second training data set includes positive sample pairs and negative sample pairs; Using the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair; Calculate the similarity between the semantic representation vector of each basic block and the positive sample pair and the negative sample pair to obtain the second objective function based on cosine similarity; Back-propagating the second objective function to calculate the gradient of the loss value with respect to the model parameters; The model parameters are iteratively updated using the gradient descent method, and the step of using the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair is returned until the loss value converges or reaches a preset number of training rounds, thereby obtaining a Basic Block program behavior representation model.

6. The method according to claim 1, characterized in that The reading of a plurality of slice subroutines to be run and obtaining the semantic representation of the slice subroutines through the Basic Block program behavior representation model includes: Slice the test programs in different test suites according to the preset fixed length intervals to obtain a number of sliced ​​subprograms to be run; further slicing the slicing subroutine into sub-segments; Obtaining a semantic vector of each of the sub-segments through the Basic Block program behavior representation model; The semantic vectors of the sub-segments are clustered using the KMeans clustering method to obtain the semantic representation of the slicing subroutine.

7. The method according to claim 1, characterized in that The step of constructing a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine and performing program selection based on the subroutine similarity matrix includes: Based on the semantic representation of the slicing subprogram, the similarity between the slicing program behavior vectors is measured by the cosine method to construct a slicing program similarity matrix; The KMeans clustering algorithm is used to cluster the slicing program similarity matrix and select representative subroutines from it.

8. A SOC verification and optimization device based on instruction flow analysis, characterized in that: The device comprises: A sampling module, used for uniformly sampling the subroutines of a program and extracting Basic Block sequence information in the subroutines; Extraction module, used to extract instruction information of each Basic Block; A first model building module, used for collecting the instruction information and the Basic Block sequence information to obtain an instruction sequence, and building an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence; A second model building module is used to build a BasicBlock program behavior representation model based on the instruction semantic sequence model by using a contrastive learning method; A semantic processing module, used for reading a number of slice subroutines to be run, and obtaining the semantic representation of the slice subroutines through the Basic Block program behavior representation model; The selection module is used to construct a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and perform program selection based on the subroutine similarity matrix.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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