Method and system for generating circuit board design drawing

Abstract

The invention relates to the technical field of circuit board design data processing, in particular to a generation method and system for a circuit board design drawing. The method comprises the following steps: acquiring design requirement information of the circuit board; performing semantic analysis on the circuit board design requirement information to generate design requirement semantic data; performing circuit board design feature extraction on the design requirement semantic data to obtain circuit board design feature information; and performing circuit board performance requirement identification on the circuit board design characteristic information to generate circuit board performance requirement data. According to the invention, a data processing technology, a mode identification technology, a three-dimensional mapping technology and a deep learning technology are adopted; the problems of interlayer alignment and interlayer interconnection in the aspect of multilayer board design are solved; and impedance discontinuous characteristics caused by the via holes are optimized and adjusted, so that the stability and the reliability of the generated circuit board design drawing are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board design data processing, and in particular to a method and system for generating a circuit board design drawing. Background Art

[0002] The original circuit board design technology used metal foil to cut into line conductors, and achieved electrical interconnection between different layers by setting vias at the intersection of the lines; the development of circuit board design software has gone through the process from manual drawing to automatic wiring technology, then to split design, and finally to three-dimensional design; modern circuit board design software has a full range of circuit board design tools for design, source code control, simulation, and output, which greatly improves the design efficiency and accuracy; the generation method of modern circuit board design drawings usually involves the process of drawing a circuit diagram first and then converting it into a circuit board design drawing. However, with the increase in the number of components and the complexity of signal lines, the existing technology faces technical difficulties in inter-layer alignment and inter-layer interconnection in the design of multi-layer boards; among them, vias are used for inter-layer connections in multi-layer circuit boards, but their improper design will lead to parasitic capacitance and inductance problems in signal transmission, affecting the integrity and speed of the signal; and the presence of vias will cause impedance discontinuity, thereby causing signal reflection and delay. Summary of the invention

[0003] Based on this, it is necessary to provide a method and system for generating a circuit board design drawing to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for generating a circuit board design drawing is provided, the method comprising the following steps:

[0005] Step S1: obtaining circuit board design requirement information; performing semantic analysis on the circuit board design requirement information to generate design requirement semantic data; performing circuit board design feature extraction on the design requirement semantic data to obtain circuit board design feature information; performing circuit board performance requirement identification on the circuit board design feature information to generate circuit board performance requirement data;

[0006] Step S2: performing circuit board component identification on the circuit board design feature information to obtain circuit board component data; performing component association analysis on the circuit board component data to obtain component association data; performing circuit board interlayer structure detection based on the component association data to obtain circuit board interlayer structure information;

[0007] Step S3: performing an interlayer interconnection demand analysis on the interlayer structure information of the circuit board according to the circuit board performance requirement data to generate interlayer interconnection demand data; generating circuit board hole positions for the circuit board design feature information based on the interlayer interconnection demand data to obtain circuit board hole position data; performing a preliminary simulation of the interlayer interconnection of the circuit board according to the circuit board hole position data to obtain preliminary simulation data of the interlayer interconnection;

[0008] Step S4: performing impedance continuity detection of the circuit board hole position area on the preliminary simulation data of interlayer interconnection to obtain the circuit board impedance continuity data; adjusting the circuit board hole position data of the circuit board by using the circuit board impedance continuity data to generate circuit board hole position adjustment data; identifying the degree of interlayer alignment of the circuit board on the preliminary simulation data of interlayer interconnection to obtain the degree of interlayer registration of the circuit board; optimizing the interlayer registration of the preliminary simulation data of interlayer interconnection by using the degree of interlayer registration of the circuit board to generate interlayer registration optimization data;

[0009] Step S5: Optimize the interlayer interconnection of the circuit board based on the preliminary simulation data of the interlayer interconnection, and generate the interlayer interconnection information of the circuit board; perform circuit board design three-dimensional image mapping on the interlayer interconnection information of the circuit board according to the circuit board design feature information, and obtain the circuit board design drawing.

[0010] The present invention can accurately generate design requirement semantic data by acquiring circuit board design requirement information and performing semantic analysis, which provides accurate basic information for subsequent design; extracts features from design requirement semantic data to clarify specific parameters and requirements of the design; further identifies circuit board performance requirements to ensure that the design meets expected performance standards. Component identification is performed on circuit board design feature information, and the obtained circuit board component data provides specific component information for the design; component association analysis is performed on circuit board component data to clarify the relationship between each component; interlayer structure detection is performed based on component association data to provide physical connection details between layers for the design. Interlayer interconnection demand analysis is performed on interlayer structure information according to circuit board performance requirement data to clarify the electrical connection design of the circuit board; circuit board hole position generation is performed based on interlayer interconnection demand data to provide accurate location information for interlayer connection; preliminary simulation of circuit board interlayer interconnection is performed to provide a preliminary preview of interlayer connection effect for the design. Impedance continuity detection of hole position area is performed on preliminary simulation data of interlayer interconnection to ensure the stability of signal transmission. The hole position data is adjusted by impedance continuity data to optimize the signal transmission path; the interlayer alignment degree of the preliminary simulation data of the interlayer interconnection is identified, thereby providing a basis for precise alignment between layers; the preliminary simulation data is optimized by the interlayer registration degree, thereby improving the accuracy of the interlayer connection. The preliminary simulation data is optimized based on the circuit board hole position adjustment data and the interlayer registration optimization data, so that the interlayer interconnection information of the circuit board is optimized; the interlayer interconnection information is mapped to a three-dimensional image according to the circuit board design feature information, which can intuitively display the three-dimensional structure of the circuit board and provide a detailed visual reference for subsequent circuit board manufacturing and inspection. Therefore, the present invention solves the problems of interlayer alignment and interlayer interconnection in the design of multilayer boards through data processing technology, pattern recognition technology, three-dimensional mapping technology and deep learning technology; and optimizes and adjusts the impedance discontinuity characteristics caused by vias, thereby ensuring the stability and reliability of the generated circuit board design drawing.

[0011] Preferably, step S2 comprises the following steps:

[0012] Step S21: performing circuit board component type identification on the circuit board design feature information to obtain circuit board component type information; performing component parameter feature extraction on the circuit board component type information to obtain component parameter feature information; integrating the circuit board component type information and the component parameter feature information to obtain circuit board component data;

[0013] Step S22: locating component connection nodes on the circuit board component data to obtain component connection node information; identifying inter-device connection paths on the component connection node information to generate inter-device connection path information;

[0014] Step S23: identifying the connection relationship between components of the circuit board component data based on the component connection node information and the connection path information between components to obtain component association data;

[0015] Step S24: Identify the inter-layer connection features of the circuit board according to the component association data to obtain the inter-layer connection information of the circuit board; divide the inter-layer connection information of the circuit board into circuit board functional module layers to generate circuit board functional module layer data; perform circuit board inter-layer structure detection on the circuit board functional module layer data to obtain the inter-layer structure information of the circuit board.

[0016] The present invention identifies the component types based on the design feature information of the circuit board, and provides a specific classification of components for the design; extracts the parameter features of the components, and describes the technical specifications of the components in detail; the integrated circuit board component data includes the types and parameter features of the components, and provides data support for the subsequent component layout and connection; locates the component connection nodes, and clarifies the physical connection points between the components; identifies the connection paths between the devices, and describes the electrical connection routes between the components in detail; identifies the connection relationships between the components based on the component connection node information and the connection path information between the devices, and reveals the mutual connection relationships between the components, and provides key information for understanding the electrical network structure and optimized design of the entire circuit board; identifies the connection features between the layers of the circuit board based on the component-related data, and clarifies the electrical connection methods between different layers; divides the circuit board into functional module layers, and divides the circuit board into modules with specific functions, which is convenient for management and optimization; and detects the structure between the layers of the circuit board, which can provide detailed information on the physical connections between the layers, and is essential for ensuring the manufacturing quality and performance of the circuit board.

[0017] Preferably, step S3 comprises the following steps:

[0018] Step S31: extracting the inter-layer signal transmission rate requirement from the inter-layer structure information of the circuit board according to the circuit board performance requirement data, and obtaining the inter-layer signal transmission requirement parameters;

[0019] Step S32: Based on the circuit board performance requirement data, the power distribution efficiency requirement of the circuit board interlayer structure information is identified to obtain the interlayer power distribution requirement parameters;

[0020] Step S33: determining the interconnection density requirement of the interlayer structure information of the circuit board through the circuit board performance requirement data to obtain the interlayer interconnection density requirement parameter;

[0021] Step S34: merging the inter-layer signal transmission requirement parameters, the inter-layer power distribution requirement parameters and the inter-layer interconnection density requirement parameters into inter-layer interconnection requirement parameters to generate inter-layer interconnection requirement data;

[0022] Step S35: Based on the inter-layer interconnection requirement data, the circuit board design feature information is used to identify the circuit board hole distribution area to obtain the circuit board hole distribution area data; the circuit board hole distribution area data is used to locate the hole coordinates to generate the hole coordinate location data;

[0023] Step S36: extracting the circuit board hole size parameters from the circuit board design feature information based on the inter-layer interconnection requirement data to obtain the hole size parameters; matching the hole coordinate positioning data with the hole size parameters to obtain the circuit board hole position data;

[0024] Step S37: Perform preliminary simulation of the interconnection between layers of the circuit board according to the circuit board hole position data and the circuit board design feature information to obtain preliminary simulation data of the interconnection between layers.

[0025] The present invention extracts the signal transmission rate requirement of the interlayer structure information according to the circuit board performance requirement data, thereby ensuring that the circuit board design can meet the specific data transmission speed requirement; identifies the power distribution efficiency requirement of the interlayer structure information based on the circuit board performance requirement data, realizes the efficient distribution of power on the circuit board, and ensures the stable operation of the circuit and the optimization of power management; determines the interconnection density requirement of the interlayer structure information through the circuit board performance requirement data, provides a clear design guide for the wiring density of the circuit board, ensures that more connections are achieved in a limited space, and maintains the reliability of the design; and combines the interlayer signal transmission requirement parameters, the interlayer power distribution requirement parameters and the interlayer interconnection density requirement parameters. The parameters are merged to provide a comprehensive demand framework for the interlayer connection design of the circuit board, ensuring the comprehensiveness and coordination of the design; the hole distribution area is identified based on the circuit board design feature information based on the interlayer interconnection demand data, providing the necessary position information for the accurate punching of the circuit board; the hole size parameters are extracted based on the interlayer interconnection demand data, providing accurate size and position information for the hole design on the circuit board, which is necessary to ensure the accuracy of the interlayer connection; the preliminary simulation of the interlayer interconnection based on the circuit board hole location data and the circuit board design feature information provides a preliminary simulation effect for the interlayer connection of the circuit board, so that the feasibility and performance of the design can be verified before actual manufacturing.

[0026] Preferably, step S37 includes the following steps:

[0027] Step S371: extracting circuit board design parameters from the circuit board design feature information to obtain circuit board design parameters; arranging circuit board components according to the circuit board design parameters to generate circuit board component arrangement data; performing single-layer circuit board routing on the circuit board component arrangement data to generate single-layer circuit board routing data;

[0028] Step S372: performing inter-layer hole position connectivity simulation on the single-layer circuit board wiring data according to the circuit board hole position data to obtain a hole position connectivity simulation result; performing inter-layer signal transmission path simulation on the hole position connectivity simulation result to obtain inter-layer signal path simulation data;

[0029] Step S373: performing interlayer interconnection density simulation based on the interlayer signal path simulation data to generate interlayer interconnection density simulation data; performing interlayer fit evaluation on the interlayer interconnection density simulation data to obtain an interlayer fit value;

[0030] Step S374: Preliminary simulation of the interconnection between layers of the circuit board is performed on the circuit board design feature information through the interlayer bonding degree value to obtain preliminary simulation data of the interconnection between layers.

[0031] The present invention extracts design parameters from circuit board design feature information, and the obtained circuit board design parameters provide precise guidance for component arrangement; the circuit board component arrangement based on these parameters ensures the rationality and functionality of the component layout; the single-layer circuit board route routing based on the circuit board component arrangement data provides detailed path planning for the connection of the single-layer circuit; the inter-layer hole position connectivity simulation of the single-layer circuit board routing data is performed based on the circuit board hole position data, thereby verifying the accuracy of the hole position design; the inter-layer signal transmission path simulation based on the hole position connectivity simulation result provides a path for the transmission of signals between different layers. The path analysis ensures the continuity and reliability of signal transmission; the interlayer interconnection density simulation based on the interlayer signal path simulation data provides quantitative data for evaluating the wiring density of the circuit board; the interlayer fit evaluation based on the interlayer interconnection density simulation data provides an evaluation standard for the tightness and integrity of the interlayer connection, so as to optimize the design of the interlayer connection; the preliminary simulation of the interlayer interconnection of the circuit board based on the circuit board design feature information through the interlayer fit value provides a comprehensive simulation result for the interlayer connection of the circuit board, so as to predict and adjust the effect of the interlayer connection before actual manufacturing, and ensure the quality and performance of the final product.

[0032] Preferably, step S4 comprises the following steps:

[0033] Step S41: performing impedance characteristic identification on the preliminary simulation data of the inter-layer interconnection to obtain impedance characteristic data of the circuit board; performing impedance continuity detection of the circuit board hole area according to the impedance characteristic data of the circuit board to obtain impedance continuity data of the circuit board;

[0034] Step S42: adjusting the circuit board hole position data according to the circuit board impedance continuity data to generate circuit board hole position adjustment data;

[0035] Step S43: performing interlayer feature recognition on the preliminary simulation data of interlayer interconnection to obtain interlayer interconnection feature data; performing interlayer alignment measurement on the interlayer interconnection feature data to generate an interlayer alignment measurement value; performing interlayer fit measurement on the interlayer interconnection feature data to generate an interlayer fit measurement value;

[0036] Step S44: using the interlayer alignment calculation value and the interlayer fit measurement value to evaluate the interlayer alignment degree of the circuit board, and obtaining the interlayer registration degree of the circuit board;

[0037] Step S45: optimizing the interlayer registration of the preliminary simulation data of the interlayer interconnection according to the interlayer registration degree of the circuit board, and generating interlayer registration optimization data.

[0038] The present invention identifies the impedance characteristics of the preliminary simulation data of the interlayer interconnection, and provides key parameters for the signal integrity of the circuit board; the impedance continuity detection of the hole area of ​​the circuit board based on these data ensures the stable transmission of the signal in the hole area and avoids signal distortion and reflection problems; the hole position data is adjusted by the impedance continuity data of the circuit board, and the hole position design is optimized to meet the requirements of impedance continuity, improve the quality of signal transmission and the overall performance of the circuit board; the interlayer feature identification is performed on the preliminary simulation data of the interlayer interconnection, and a detailed description is provided for the accuracy of the interlayer connection; the interlayer alignment measurement value and the interlayer fit measurement are determined. The generation of values ​​provides a quantitative indicator for the precise alignment and fit of interlayer connections, which is crucial to ensure the reliability and stability of interlayer connections; the interlayer alignment measurement value and the interlayer fit measurement value are evaluated to provide a comprehensive evaluation result for the accuracy of interlayer connections; it helps to identify and correct potential problems in interlayer connections to improve the overall quality of circuit boards; the preliminary simulation data of interlayer interconnection is optimized through the degree of interlayer registration of circuit boards, which improves the alignment accuracy of interlayer connections; this helps to reduce errors in interlayer connections, improve the manufacturing accuracy and performance of circuit boards, and ensure that the final product can meet design specifications and performance requirements.

[0039] Preferably, step S41 includes the following steps:

[0040] Step S411: performing high-frequency signal path identification on the preliminary simulation data of the inter-layer interconnection to obtain high-frequency signal path data; performing impedance parameter extraction on the high-frequency signal path data to obtain impedance parameter information;

[0041] Step S412: performing circuit board impedance characteristic identification on the impedance parameter information to obtain circuit board impedance characteristic data; performing path impedance consistency check on the circuit board impedance characteristic data to obtain a path impedance consistency check result;

[0042] Step S413: positioning the abnormal impedance region on the path impedance consistency check result to obtain abnormal impedance region positioning data; comparing the abnormal impedance region positioning data with the preset impedance value to obtain an impedance value comparison result;

[0043] Step S414: performing impedance continuity deviation measurement on the impedance value comparison result to obtain continuity deviation measurement data; performing impedance continuity evaluation on the continuity deviation measurement data to obtain circuit board impedance continuity data.

[0044] The present invention identifies high-frequency signal paths for preliminary simulation data of inter-layer interconnection, and provides accurate path information for analyzing signal transmission characteristics; extracts impedance parameters from these path data, and provides key parameters for evaluating the electrical characteristics of the signal path; identifies circuit board impedance characteristics based on impedance parameter information, and provides a detailed description of electrical performance for the design; performs path impedance consistency verification to ensure that the impedance design of the signal path meets the expected standards and ensures signal integrity; locates impedance abnormality areas based on the results of the path impedance consistency verification, and can accurately point out problem areas in the design; compares these data with preset impedance values, and provides a basis for identifying and correcting impedance deviations in the design; measures impedance continuity deviations for the impedance value comparison results, and quantifies impedance inconsistencies; and performs impedance continuity evaluation on these data, which provides an important reference for ensuring stable signal transmission on the circuit board and improves the performance and reliability of the circuit board.

[0045] Preferably, step S42 includes the following steps:

[0046] Step S421: performing impedance continuity change detection on the impedance continuity data of the circuit board to obtain impedance continuity change data; performing abnormal change amount measurement on the impedance continuity change data to generate an impedance abnormal change amount measurement value;

[0047] Step S422: mapping the hole position data of the circuit board based on the measured value of the abnormal impedance change to generate abnormal hole position mapping information; extracting hole size parameters from the abnormal hole position mapping information to obtain abnormal hole position size parameters; identifying the hole position routing layout from the abnormal hole position mapping information to obtain abnormal hole position routing data;

[0048] Step S423: performing dispersion adjustment of the hole position of the circuit board on the abnormally changed hole position mapping information to obtain the hole position adjustment data of the circuit board; reducing the size parameters of the abnormally changed hole position to obtain the hole size reduction parameters; re-layout the hole position routing pins on the abnormally changed hole position routing data to generate the hole position routing pin layout data;

[0049] Step S424: integrating the circuit board hole position adjustment data, the hole size reduction parameters and the hole routing pin layout data to obtain the circuit board hole adjustment data.

[0050] The present invention detects changes in the impedance continuity data of the circuit board, and can reveal the distribution of impedance on the circuit board; measures the abnormal change amount of these change data, and can accurately identify areas where the impedance change exceeds expectations, which is crucial for maintaining signal integrity and circuit performance; and performs position mapping of the hole site data based on the measured value of the abnormal impedance change amount, which provides a basis for accurate adjustment of the hole position. Extracting the size parameters of these mapping information can optimize the physical size of the hole position; at the same time, identifying the routing layout of the mapping information provides the necessary information for adjusting the routing to ensure smooth signal transmission; adjusting the hole position dispersion of the abnormally changed hole position mapping information can optimize the hole position layout and reduce impedance anomalies; reducing the size parameters of the abnormally changed hole positions, thereby reducing the impedance discontinuity in the signal path; re-layouting the pins of the abnormally changed hole position routing data can improve the signal transmission path and enhance the overall performance of the circuit board; integrating the circuit board hole position adjustment data, hole size reduction parameters and hole routing pin layout data provides a comprehensive adjustment plan for the final hole position design of the circuit board, ensuring that the circuit board can achieve the expected electrical performance and mechanical precision during the manufacturing process, thereby improving the reliability and performance of the product.

[0051] Preferably, step S45 includes the following steps:

[0052] Step S451: quantifying the registration deviation of the inter-layer registration degree of the circuit board to generate registration deviation quantification data; identifying the inter-layer registration deviation distribution of the registration deviation quantification data to obtain inter-layer registration deviation distribution data;

[0053] Step S452: performing correction region detection on the inter-layer registration deviation distribution data to generate inter-layer registration correction region information; performing registration correction parameter calculation on the inter-layer registration correction region information to obtain a registration correction parameter value;

[0054] Step S453: performing interlayer interconnection angle correction on the interlayer interconnection feature data by aligning the correction parameter value to obtain interconnection angle correction data; performing interlayer interconnection displacement adjustment on the interlayer interconnection feature data according to the interconnection angle correction data to obtain interconnection displacement adjustment data;

[0055] Step S454: adjusting the interlayer interconnection structure of the preliminary simulation data of the interlayer interconnection by using the interconnection displacement adjustment data to obtain the interconnection structure adjustment data; and optimizing the interlayer registration of the preliminary simulation data of the interlayer interconnection based on the interconnection structure adjustment data to generate the interlayer registration optimization data.

[0056] The present invention quantifies the registration deviation of the registration degree between layers of the circuit board, and provides a numerical measurement for the accuracy of the interlayer alignment; the distribution of the interlayer registration deviation is identified, and the specific distribution of the registration deviation between layers is revealed; the correction area detection is performed on the interlayer registration deviation distribution data, and the specific area that needs to be corrected is clarified; the registration correction parameter calculation provides accurate correction guidance for these areas, and ensures the accuracy of the interlayer alignment; the angle correction is performed on the interlayer interconnection feature data through the registration correction parameter value, and it is ensured that the angle of the interlayer connection meets the design requirements; the interlayer interconnection displacement adjustment is performed according to the interconnection angle correction data, and the position of the interlayer connection is optimized, and the accuracy of the connection is improved; the structure of the preliminary simulation data of the interlayer interconnection is adjusted through the interconnection displacement adjustment data, and the physical connection structure between the layers is improved; the interlayer registration optimization based on the interconnection structure adjustment data further improves the accuracy of the interlayer alignment, and ensures the high performance and reliability of the circuit board.

[0057] Preferably, step S5 comprises the following steps:

[0058] Step S51: performing hole position adjustment verification on the preliminary simulation data of interlayer interconnection through the circuit board hole position adjustment data to obtain hole position adjustment verification data; performing interlayer registration optimization verification on the preliminary simulation data of interlayer interconnection through the interlayer registration optimization data to obtain interlayer registration optimization verification data;

[0059] Step S52: evaluating the circuit board interlayer adjustment verification result according to the hole position adjustment verification data and the interlayer registration optimization verification data, and generating the circuit board interlayer adjustment verification result; optimizing the circuit board interlayer interconnection on the interlayer interconnection preliminary simulation data based on the circuit board interlayer adjustment verification result, and generating the circuit board interlayer interconnection information;

[0060] Step S53: performing inter-layer design parameter space coordinate matching on the inter-layer interconnection information of the circuit board according to the circuit board design feature information to generate inter-layer design coordinate matching data; performing circuit board design three-dimensional data mapping on the inter-layer design coordinate matching data to obtain circuit board three-dimensional space mapping data;

[0061] Step S54: synthesizing the three-dimensional image of the circuit board three-dimensional space mapping data to obtain a three-dimensional design image of the circuit board; enhancing the image details of the three-dimensional design image of the circuit board to generate a circuit board design drawing.

[0062] The present invention verifies the hole position adjustment of the preliminary simulation data of the interlayer interconnection through the hole position adjustment data of the circuit board, thereby ensuring the accuracy of the hole position adjustment; verifies the interlayer registration optimization of the preliminary simulation data of the interlayer interconnection through the interlayer registration optimization data, thereby ensuring the accuracy of the interlayer registration; and these two verification steps provide data support for the subsequent optimization of the interlayer interconnection; the evaluation of the verification results of the interlayer adjustment of the circuit board based on the hole position adjustment verification data and the interlayer registration optimization verification data provides a comprehensive evaluation for the optimization of the interlayer interconnection; the optimization of the interlayer interconnection of the circuit board based on the preliminary simulation data of the interlayer interconnection based on this verification result further improves the accuracy of the interlayer registration. The performance and reliability of the connection between layers; the spatial coordinate matching of the inter-layer design parameter of the circuit board inter-layer interconnection information is carried out according to the circuit board design feature information, which provides a coordinate basis for accurate three-dimensional design; these matching data are mapped to the circuit board design three-dimensional data, and the subsequent three-dimensional image synthesis provides detailed spatial information; the three-dimensional image synthesis of the circuit board three-dimensional space mapping data can intuitively display the three-dimensional structure of the circuit board; the image details of the circuit board three-dimensional design image are enhanced, and the generated circuit board design drawing provides clear and detailed visual data for design review, manufacturing and quality control, ensuring the accurate communication and implementation of the design.

[0063] In this specification, a system for generating a circuit board design drawing is provided, which is used to execute the above-mentioned method for generating a circuit board design drawing. The system for generating a circuit board design drawing includes:

[0064] The circuit board design data acquisition module is used to obtain circuit board design requirement information; perform semantic analysis on the circuit board design requirement information to generate design requirement semantic data; perform circuit board design feature extraction on the design requirement semantic data to obtain circuit board design feature information; perform circuit board performance requirement identification on the circuit board design feature information to generate circuit board performance requirement data;

[0065] The circuit board interlayer structure analysis module is used to identify circuit board components based on circuit board design feature information to obtain circuit board component data; perform component association analysis on circuit board component data to obtain component association data; perform circuit board interlayer structure detection based on component association data to obtain circuit board interlayer structure information;

[0066] The circuit board interlayer interconnection simulation module is used to analyze the interlayer interconnection requirements of the circuit board interlayer structure information according to the circuit board performance requirement data, and generate interlayer interconnection requirement data; generate circuit board hole positions based on the circuit board design feature information based on the interlayer interconnection requirement data, and obtain circuit board hole position data; perform preliminary simulation of the circuit board interlayer interconnection according to the circuit board hole position data, and obtain preliminary simulation data of interlayer interconnection;

[0067] The circuit board interlayer interconnection optimization and adjustment module is used to perform impedance continuity detection of the circuit board hole position area on the preliminary simulation data of the interlayer interconnection to obtain the circuit board impedance continuity data; adjust the circuit board hole position data of the circuit board through the circuit board impedance continuity data to generate the circuit board hole position adjustment data; identify the degree of interlayer alignment of the circuit board on the preliminary simulation data of the interlayer interconnection to obtain the degree of interlayer registration of the circuit board; optimize the interlayer registration of the preliminary simulation data of the interlayer interconnection through the degree of interlayer registration of the circuit board to generate the interlayer registration optimization data;

[0068] The circuit board design drawing generation module is used to optimize the inter-layer interconnection of the circuit board based on the preliminary simulation data of the inter-layer interconnection, based on the circuit board hole adjustment data and the inter-layer registration optimization data, and generate the inter-layer interconnection information of the circuit board; and perform circuit board design three-dimensional image mapping on the inter-layer interconnection information of the circuit board according to the circuit board design feature information to obtain the circuit board design drawing.

[0069] The present invention obtains the circuit board design requirement information and performs semantic analysis through the circuit board design data acquisition module, and can accurately generate the design requirement semantic data, which provides accurate basic information for subsequent design; extracts features from the design requirement semantic data to clarify the specific parameters and requirements of the design; further identifies the circuit board performance requirements to ensure that the design meets the expected performance standards. Through the circuit board interlayer structure analysis module, the circuit board design feature information is identified by components, and the obtained circuit board component data provides specific component information for the design; the circuit board component data is analyzed for component association to clarify the relationship between each component; based on the component association data, the interlayer structure detection is performed to provide the design with the physical connection details between layers. Through the circuit board interlayer interconnection simulation module, the interlayer structure information is analyzed for interlayer interconnection requirements according to the circuit board performance requirement data, so as to clarify the electrical connection design of the circuit board; the circuit board hole position is generated based on the interlayer interconnection requirement data, providing accurate location information for the interlayer connection; the circuit board interlayer interconnection is simulated to provide a preliminary preview of the interlayer connection effect for the design. Through the circuit board interlayer interconnection optimization and adjustment module, the impedance continuity of the hole position area of ​​the preliminary simulation data of the interlayer interconnection is detected to ensure the stability of signal transmission. The hole position data is adjusted by impedance continuity data to optimize the signal transmission path; the interlayer alignment degree of the preliminary simulation data of the interlayer interconnection is identified, thereby providing a basis for accurate alignment between layers; the preliminary simulation data is optimized by the interlayer registration degree, thereby improving the accuracy of the interlayer connection. Through the circuit board design drawing generation module, the preliminary simulation data is optimized based on the circuit board hole position adjustment data and the interlayer registration optimization data, so that the circuit board interlayer interconnection information is optimized; according to the circuit board design feature information, the interlayer interconnection information is mapped to a three-dimensional image, which can intuitively display the three-dimensional structure of the circuit board, and provide a detailed visual reference for subsequent circuit board manufacturing and inspection. Therefore, the present invention solves the problems of interlayer alignment and interlayer interconnection in the design of multilayer boards through data processing technology, pattern recognition technology, three-dimensional mapping technology and deep learning technology; and optimizes and adjusts the impedance discontinuity characteristics caused by vias, thereby ensuring the stability and reliability of the generated circuit board design drawing. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 A schematic diagram of a process flow of a method for generating a circuit board design drawing;

[0071] Figure 2 for Figure 1 Detailed implementation steps of step S2 in the flowchart;

[0072] Figure 3 for Figure 1 Detailed implementation steps of step S5;

[0073] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0074] The technical method of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0075] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0076] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0077] To achieve this, please refer to Figures 1 to 3 , a method for generating a circuit board design drawing, the method comprising the following steps:

[0078] Step S1: obtaining circuit board design requirement information; performing semantic analysis on the circuit board design requirement information to generate design requirement semantic data; performing circuit board design feature extraction on the design requirement semantic data to obtain circuit board design feature information; performing circuit board performance requirement identification on the circuit board design feature information to generate circuit board performance requirement data;

[0079] Step S2: performing circuit board component identification on the circuit board design feature information to obtain circuit board component data; performing component association analysis on the circuit board component data to obtain component association data; performing circuit board interlayer structure detection based on the component association data to obtain circuit board interlayer structure information;

[0080] Step S3: performing an interlayer interconnection demand analysis on the interlayer structure information of the circuit board according to the circuit board performance requirement data to generate interlayer interconnection demand data; generating circuit board hole positions for the circuit board design feature information based on the interlayer interconnection demand data to obtain circuit board hole position data; performing a preliminary simulation of the interlayer interconnection of the circuit board according to the circuit board hole position data to obtain preliminary simulation data of the interlayer interconnection;

[0081] Step S4: performing impedance continuity detection of the circuit board hole position area on the preliminary simulation data of interlayer interconnection to obtain the circuit board impedance continuity data; adjusting the circuit board hole position data of the circuit board by using the circuit board impedance continuity data to generate circuit board hole position adjustment data; identifying the degree of interlayer alignment of the circuit board on the preliminary simulation data of interlayer interconnection to obtain the degree of interlayer registration of the circuit board; optimizing the interlayer registration of the preliminary simulation data of interlayer interconnection by using the degree of interlayer registration of the circuit board to generate interlayer registration optimization data;

[0082] Step S5: Optimize the interlayer interconnection of the circuit board based on the preliminary simulation data of the interlayer interconnection, and generate the interlayer interconnection information of the circuit board; perform circuit board design three-dimensional image mapping on the interlayer interconnection information of the circuit board according to the circuit board design feature information, and obtain the circuit board design drawing.

[0083] The present invention can accurately generate design requirement semantic data by acquiring circuit board design requirement information and performing semantic analysis, which provides accurate basic information for subsequent design; extracts features from design requirement semantic data to clarify specific parameters and requirements of the design; further identifies circuit board performance requirements to ensure that the design meets expected performance standards. Component identification is performed on circuit board design feature information, and the obtained circuit board component data provides specific component information for the design; component association analysis is performed on circuit board component data to clarify the relationship between each component; interlayer structure detection is performed based on component association data to provide physical connection details between layers for the design. Interlayer interconnection demand analysis is performed on interlayer structure information according to circuit board performance requirement data to clarify the electrical connection design of the circuit board; circuit board hole position generation is performed based on interlayer interconnection demand data to provide accurate location information for interlayer connection; preliminary simulation of circuit board interlayer interconnection is performed to provide a preliminary preview of interlayer connection effect for the design. Impedance continuity detection of hole position area is performed on preliminary simulation data of interlayer interconnection to ensure the stability of signal transmission. The hole position data is adjusted by impedance continuity data to optimize the signal transmission path; the interlayer alignment degree of the preliminary simulation data of the interlayer interconnection is identified, thereby providing a basis for precise alignment between layers; the preliminary simulation data is optimized by the interlayer registration degree, thereby improving the accuracy of the interlayer connection. The preliminary simulation data is optimized based on the circuit board hole position adjustment data and the interlayer registration optimization data, so that the interlayer interconnection information of the circuit board is optimized; the interlayer interconnection information is mapped to a three-dimensional image according to the circuit board design feature information, which can intuitively display the three-dimensional structure of the circuit board and provide a detailed visual reference for subsequent circuit board manufacturing and inspection. Therefore, the present invention solves the problems of interlayer alignment and interlayer interconnection in the design of multilayer boards through data processing technology, pattern recognition technology, three-dimensional mapping technology and deep learning technology; and optimizes and adjusts the impedance discontinuity characteristics caused by vias, thereby ensuring the stability and reliability of the generated circuit board design drawing.

[0084] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a schematic diagram of a step flow of a method for generating a circuit board design drawing according to the present invention. In this example, the method for generating a circuit board design drawing includes the following steps:

[0085] Step S1: obtaining circuit board design requirement information; performing semantic analysis on the circuit board design requirement information to generate design requirement semantic data; performing circuit board design feature extraction on the design requirement semantic data to obtain circuit board design feature information; performing circuit board performance requirement identification on the circuit board design feature information to generate circuit board performance requirement data;

[0086] In an embodiment of the present invention, basic parameters and performance requirements of circuit board design are extracted from design documents and specification manuals; key information such as board thickness, number of board layers, wiring layer layout and characteristic impedance value are specifically extracted; natural language processing technology, such as semantic role labeling and dependency syntax analysis, is used to perform semantic analysis on design requirements and generate semantic data of design requirements; specifically, by identifying key terms and parameters in the design documents, a semantic model is constructed to convert text information into structured data; deep learning technology, such as convolutional neural network (CNN), is used to analyze circuit board design features, specifically by analyzing the stacking structure and signal line layout of the circuit board, the performance requirements of signal integrity and electromagnetic compatibility (EMC) are identified; a CNN model is constructed, including a convolutional layer, an activation layer, a pooling layer and a fully connected layer, to extract circuit board design features and identify performance requirements; specifically, a CNN model is constructed using Python and Keras libraries, and model parameters are optimized through forward propagation and back propagation; the identified performance requirements are converted into specific performance parameters and test standards, and the impedance matching parameters of the signal line are determined according to the signal integrity requirements of the circuit board; according to the EMC requirements, the shielding design and grounding strategy of the circuit board are determined, and finally the circuit board performance requirement data is generated.

[0087] Step S2: performing circuit board component identification on the circuit board design feature information to obtain circuit board component data; performing component association analysis on the circuit board component data to obtain component association data; performing circuit board interlayer structure detection based on the component association data to obtain circuit board interlayer structure information;

[0088] In an embodiment of the present invention, an image recognition technology, such as YOLOv8, is used to process a circuit board image and identify components in the image. Specifically, the circuit board design image is input into a trained YOLOv8 model, the model extracts features through a convolutional layer, and performs classification and recognition through a subsequent fully connected layer, and outputs the location and category information of the components. Taking a specific circuit board image as an example, the input image size is 1920x1080 pixels, the model identifies components such as resistors and capacitors in the image, and outputs the bounding box coordinates and category labels of each component. The recognition result includes 10 resistors, the bounding box coordinates are [x1, y1, x2, y2], and the category label is "Resistor". An association rule learning algorithm, such as the Apriori algorithm, is used to perform association analysis on component data. The algorithm mines association rules between components by analyzing the co-occurrence relationship between components; association rules between components are constructed based on the identified component data; the power management module where the resistors and capacitors are located is specifically analyzed to generate an association rule "if there is a resistor in the circuit, there will be a capacitor in the circuit enclosure"; interlayer dislocation detection technology, such as X-ray detection, is used to detect the interlayer structure of the circuit board; specifically, the interlayer dislocation inside the circuit board is observed through X-ray perspective technology; taking a multi-layer circuit board as an example, the circuit board is detected using an X-ray device to obtain image data of the interlayer dislocation state; and the size, direction and state of the interlayer dislocation are determined through image analysis, and this information is recorded as interlayer structure information to obtain the interlayer structure information of the circuit board.

[0089] Step S3: performing an interlayer interconnection demand analysis on the interlayer structure information of the circuit board according to the circuit board performance requirement data to generate interlayer interconnection demand data; generating circuit board hole positions for the circuit board design feature information based on the interlayer interconnection demand data to obtain circuit board hole position data; performing a preliminary simulation of the interlayer interconnection of the circuit board according to the circuit board hole position data to obtain preliminary simulation data of the interlayer interconnection;

[0090] In the embodiment of the present invention, circuit simulation software is used to analyze the requirements for interlayer interconnection. Specifically, the HFSS module in the ANSYS software is used to perform electromagnetic field simulation on the interlayer structure according to the performance requirement data of the circuit board, such as signal transmission rate and power distribution, to generate interlayer interconnection requirement data. A four-layer circuit board is taken as an example, in which the performance requirement data specifies a specific signal transmission rate and power distribution. Through simulation analysis, it is determined that a blind hole needs to be added between the second layer and the third layer to meet the signal integrity requirements, thereby generating interlayer interconnection requirement data including the position and size of the blind hole. CAD software is used to generate the hole position, specifically based on the interlayer interconnection requirement data, in Altium In Designer, the precise position and size of the blind hole are determined, and the hole site data is generated; for example, the position of the blind hole is (X:50mil, Y:00mil), the diameter is 10mil, and the depth is 40mil; 3D modeling software is used to simulate the interlayer interconnection, such as using SolidWorks software, to perform 3D modeling and preliminary simulation of the interlayer interconnection of the circuit board according to the hole site data; specifically, in SolidWorks, a 3D model of a four-layer PCB is constructed based on the hole site data, and the interlayer interconnection is simulated; the simulation results show that the position and size of the blind hole meet the design requirements, and there is no short circuit or open circuit in the interlayer connection, and finally the preliminary simulation data of the interlayer interconnection is generated.

[0091] Step S4: performing impedance continuity detection of the circuit board hole position area on the preliminary simulation data of interlayer interconnection to obtain the circuit board impedance continuity data; adjusting the circuit board hole position data of the circuit board by using the circuit board impedance continuity data to generate circuit board hole position adjustment data; identifying the degree of interlayer alignment of the circuit board on the preliminary simulation data of interlayer interconnection to obtain the degree of interlayer registration of the circuit board; optimizing the interlayer registration of the preliminary simulation data of interlayer interconnection by using the degree of interlayer registration of the circuit board to generate interlayer registration optimization data;

[0092] In the embodiment of the present invention, the impedance continuity of the hole area of ​​the circuit board is detected by using the time domain reflectometry (TDR). Specifically, by sending a step signal and detecting the reflected signal, the degree of impedance change in the link is evaluated; on the TDR device, the hole area of ​​the circuit board to be tested is connected to the test equipment, and a 50-ohm step signal is sent; the reflected signal is recorded and compared with the reflection generated by the standard impedance to obtain the impedance change; if the test results show that there is an impedance discontinuity at the hole area X1, the change is 10 ohms. According to the impedance continuity data obtained by TDR, the hole position data is adjusted using CAD software; for example, in Altium Designer, according to the location of the impedance discontinuity, the size or position of the hole is adjusted to eliminate the impedance discontinuity; for example, according to the impedance discontinuity data, the diameter of the hole X1 is adjusted from 10 mil to 12 mil, thereby generating new hole adjustment data, specifically including the adjusted hole size and position. Use interlayer alignment detection equipment, such as through-hole detection equipment, to determine the degree of interlayer alignment by detecting the on-off state between the starting hole and each ranging hole; set up multiple alignment test equipment on the circuit board to be tested, each device includes an inner layer structure and an outer layer structure, and detect the on-off state between the starting hole and each ranging hole through the through-hole to determine the interlayer offset; if the measured interlayer offset is 2 mils, it indicates that there is a slight alignment deviation between the layers. According to the degree of interlayer alignment, use 3D modeling software such as SolidWorks to optimize the preliminary simulation data of interlayer interconnection, specifically by adjusting the position and angle between layers to improve the degree of interlayer alignment; in SolidWorks, adjust the interlayer interconnection simulation data according to the interlayer offset data; for example, adjust the position of the fourth layer relative to the third layer by 0.1 mm to generate interlayer registration optimization data, which includes the adjusted interlayer position and angle information.

[0093] Step S5: Optimize the interlayer interconnection of the circuit board based on the preliminary simulation data of the interlayer interconnection, and generate the interlayer interconnection information of the circuit board; perform circuit board design three-dimensional image mapping on the interlayer interconnection information of the circuit board according to the circuit board design feature information, and obtain the circuit board design drawing.

[0094] In an embodiment of the present invention, Cadence Allegro software is used to optimize interlayer interconnection, and the interlayer connection and hole layout of the circuit board are adjusted according to the hole adjustment data and the interlayer registration optimization data; for example, the position of the hole is adjusted to ensure the integrity of signal transmission and reduce crosstalk; specifically, in Cadence Allegro, for a four-layer PCB design; according to the hole adjustment data, the position of hole Hole1 is adjusted from (X: 100mil, Y: 200mil) to (X: 105mil, Y: 205mil), and according to the interlayer registration optimization data, the alignment between layer 2 and layer 3 is adjusted to ensure the accuracy of the interlayer connection; through these adjustments, optimized interlayer interconnection information is generated, which includes updated hole positions and interlayer connection details. Use SolidWorks software to perform 3D image mapping of circuit board design, and build a 3D model of the circuit board according to the design feature information and interlayer interconnection information of the circuit board. Specifically, in SolidWorks, import the 2D design data of the circuit board, and build a 3D model according to the interlayer interconnection information. For example, for a four-layer PCB design, after importing the interlayer interconnection information, build a 3D model including all layers and holes. Through 3D image mapping technology, intuitively display the internal structure and interlayer connection of the circuit board, and finally generate a circuit board design drawing; which includes displaying the blind hole connection between layer 1 and layer 4, and the buried hole connection between layer 2 and layer 3.

[0095] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes:

[0096] Step S21: performing circuit board component type identification on the circuit board design feature information to obtain circuit board component type information; performing component parameter feature extraction on the circuit board component type information to obtain component parameter feature information; integrating the circuit board component type information and the component parameter feature information to obtain circuit board component data;

[0097] Step S22: locating component connection nodes on the circuit board component data to obtain component connection node information; identifying inter-device connection paths on the component connection node information to generate inter-device connection path information;

[0098] Step S23: identifying the connection relationship between components of the circuit board component data based on the component connection node information and the connection path information between components to obtain component association data;

[0099] Step S24: Identify the inter-layer connection features of the circuit board according to the component association data to obtain the inter-layer connection information of the circuit board; divide the inter-layer connection information of the circuit board into circuit board functional module layers to generate circuit board functional module layer data; perform circuit board inter-layer structure detection on the circuit board functional module layer data to obtain the inter-layer structure information of the circuit board.

[0100] In an embodiment of the present invention, a deep learning model, such as YOLOv8, is used to identify the types of components on a circuit board; specifically, the model learns to identify different shapes and features of components through training, thereby realizing automatic classification and identification of circuit board design feature information; a two-dimensional convolutional neural network (2D-CNN) is used to automatically extract component parameter features, wherein the convolution layer of the model is used to automatically extract fault features, and the batch normalization layer is used to adjust data distribution to reduce the impact of data distribution deviation; component type information and parameter feature information are integrated to form complete circuit board component data; specifically, through image processing and natural language understanding technology, packaging parameters are automatically extracted from electronic component data manuals, and component type and parameter feature information are integrated; node positioning technology in a wireless sensor network is used to accurately locate component connection nodes, and specifically, the exact position of component connection nodes is determined through algorithm processing; automatic identification technology, such as an identification system based on electronic tags (RFID), is used to identify component connection node information and generate connection path information between devices; the electronic tag at the end of the wire is identified by an identifier, and the identification result is sent to a collection device, which is responsible for analyzing and processing the output connection relationship, thereby obtaining the connection path information between devices. By analyzing the connection node information of components and the connection path information between components, the connection relationship between components is identified; the identification results are analyzed and processed by the acquisition equipment, and the connection relationship between each terminal and the wire is output; the connection characteristics between the layers of the multi-layer circuit board are identified by using the layer deviation detection method, and the layer deviation corresponding detection ring is set; the functional module layer is divided according to the connection information between the layers of the circuit board, and the circuit board is divided into different functional module layers by analyzing the connection characteristics between the layers of the circuit board; the circuit board interlayer structure detection technology is used to detect the circuit board functional module layer data, and the automatic detection equipment is used to detect the alignment ability between the layers of the circuit board, so as to obtain the circuit board interlayer structure information.

[0101] Preferably, step S3 comprises the following steps:

[0102] Step S31: extracting the inter-layer signal transmission rate requirement from the inter-layer structure information of the circuit board according to the circuit board performance requirement data, and obtaining the inter-layer signal transmission requirement parameters;

[0103] Step S32: Based on the circuit board performance requirement data, the power distribution efficiency requirement of the circuit board interlayer structure information is identified to obtain the interlayer power distribution requirement parameters;

[0104] Step S33: determining the interconnection density requirement of the interlayer structure information of the circuit board through the circuit board performance requirement data to obtain the interlayer interconnection density requirement parameter;

[0105] Step S34: merging the inter-layer signal transmission requirement parameters, the inter-layer power distribution requirement parameters and the inter-layer interconnection density requirement parameters into inter-layer interconnection requirement parameters to generate inter-layer interconnection requirement data;

[0106] Step S35: Based on the inter-layer interconnection requirement data, the circuit board design feature information is used to identify the circuit board hole distribution area to obtain the circuit board hole distribution area data; the circuit board hole distribution area data is used to locate the hole coordinates to generate the hole coordinate location data;

[0107] Step S36: extracting the circuit board hole size parameters from the circuit board design feature information based on the inter-layer interconnection requirement data to obtain the hole size parameters; matching the hole coordinate positioning data with the hole size parameters to obtain the circuit board hole position data;

[0108] Step S37: Perform preliminary simulation of the interconnection between layers of the circuit board according to the circuit board hole position data and the circuit board design feature information to obtain preliminary simulation data of the interconnection between layers.

[0109] In the embodiment of the present invention, electromagnetic field simulation software (such as ANSYS HFSS) is used to simulate the interlayer structure of the circuit board, and the transmission delay of the signal in the circuit board wiring is calculated according to the dielectric constant and the characteristics of the board material. The calculation formula is as follows:

[0110]

[0111] where t d Indicates the transmission delay of the signal (unit: seconds); L indicates the length of the trace (unit: meter);

[0112] v p It indicates the propagation speed of the signal in the medium (unit: m / s), and its calculation formula is:

[0113]

[0114] where c is the speed of light in a vacuum (approximately 3×10 8 m / s);∈ r It is the relative dielectric constant of the dielectric material; the dielectric constant is a physical quantity that describes the material's ability to store electrical energy. For the FR4 material commonly used in circuit boards, the dielectric constant is between 4.2 and 4.4; this parameter can be obtained from the data sheet provided by the material supplier or through experimental measurement.

[0115] By using HDI circuit board technology, the power distribution network performance is analyzed to identify the power distribution efficiency requirements; specifically, HDI circuit boards can provide lower current density and more uniform power distribution, thereby reducing power loss and improving overall energy efficiency; specifically, for a mobile device circuit board, the HDI technology is used to improve the uniformity and efficiency of the power distribution network, and the power distribution efficiency requirement parameters are identified; according to the high-density interconnection (HDI) printed circuit technology, the wiring density and number of layers of the circuit board are analyzed to determine the interconnection density requirements; among them, the HDI board has the advantages of high-density wiring, high frequency and high speed, high conductivity, high insulation reliability and low cost; for a high-performance computing device circuit board, its interconnection density requirement parameters are determined to meet the requirements of high-density wiring and high frequency and high speed; by comprehensively analyzing the signal transmission rate, power distribution efficiency and interconnection density requirement parameters, an inter-layer interconnection requirement data set is generated. Use circuit board design software (such as Cadence Allegro) to identify the hole distribution area, and determine the optimal hole distribution area based on the inter-layer interconnection requirement data; accurately locate the hole coordinates within the identified hole distribution area; identify the hole distribution area in Cadence Allegro software based on the inter-layer interconnection requirement data, and locate the hole coordinates to obtain the hole coordinate positioning data; extract the hole size parameters based on the circuit board hole size standard (such as IPC-2221); match the hole coordinate positioning data with the hole size parameters to ensure that the position and size of each hole meet the design requirements; use 3D electromagnetic field simulation software (such as ANSYS SIwave) to perform preliminary simulation of the circuit board inter-layer interconnection, and evaluate the performance of the inter-layer interconnection based on the hole site data and design feature information; in ANSYS SIwave, perform preliminary simulation of the inter-layer interconnection based on the hole site data and circuit board design feature information to obtain preliminary simulation data of the inter-layer interconnection.

[0116] Preferably, step S37 includes the following steps:

[0117] Step S371: extracting circuit board design parameters from the circuit board design feature information to obtain circuit board design parameters; arranging circuit board components according to the circuit board design parameters to generate circuit board component arrangement data; performing single-layer circuit board routing on the circuit board component arrangement data to generate single-layer circuit board routing data;

[0118] Step S372: performing inter-layer hole position connectivity simulation on the single-layer circuit board wiring data according to the circuit board hole position data to obtain a hole position connectivity simulation result; performing inter-layer signal transmission path simulation on the hole position connectivity simulation result to obtain inter-layer signal path simulation data;

[0119] Step S373: performing interlayer interconnection density simulation based on the interlayer signal path simulation data to generate interlayer interconnection density simulation data; performing interlayer fit evaluation on the interlayer interconnection density simulation data to obtain an interlayer fit value;

[0120] Step S374: Preliminary simulation of the interconnection between layers of the circuit board is performed on the circuit board design feature information through the interlayer bonding degree value to obtain preliminary simulation data of the interconnection between layers.

[0121] In an embodiment of the present invention, CAD software (such as Altium Designer) is used to analyze the design feature information of the circuit board, and the design parameters are specifically extracted, including parameters such as the thickness of the board, the number of layers, the width of the trace and the spacing; according to the extracted design parameters, an algorithm (such as a genetic algorithm) is used to optimize the arrangement of components to reduce the trace length and avoid signal interference; after the components are arranged, a wiring algorithm (such as a maze wiring algorithm) is used to perform wiring of a single-layer circuit board to generate wiring data; the hole position connectivity is simulated using electromagnetic field simulation software (such as ANSYS HFSS) to ensure that the connection between the hole positions meets the design requirements; based on the hole position connectivity simulation results, the signal transmission path between the layers is further simulated to evaluate the signal integrity; according to the inter-layer signal path simulation data, the inter-layer interconnection density is simulated using simulation software to evaluate the rationality and feasibility of the wiring; the inter-layer interconnection density simulation data is analyzed to evaluate the degree of fit between the layers to ensure the reliability of the inter-layer connection; the inter-layer fit value is used, combined with the circuit board design feature information, a preliminary simulation of the inter-layer interconnection is performed to generate simulation data to provide a reference for subsequent circuit board manufacturing.

[0122] Preferably, step S4 comprises the following steps:

[0123] Step S41: performing impedance characteristic identification on the preliminary simulation data of the inter-layer interconnection to obtain impedance characteristic data of the circuit board; performing impedance continuity detection of the circuit board hole area according to the impedance characteristic data of the circuit board to obtain impedance continuity data of the circuit board;

[0124] Step S42: adjusting the circuit board hole position data according to the circuit board impedance continuity data to generate circuit board hole position adjustment data;

[0125] Step S43: performing interlayer feature recognition on the preliminary simulation data of interlayer interconnection to obtain interlayer interconnection feature data; performing interlayer alignment measurement on the interlayer interconnection feature data to generate an interlayer alignment measurement value; performing interlayer fit measurement on the interlayer interconnection feature data to generate an interlayer fit measurement value;

[0126] Step S44: using the interlayer alignment calculation value and the interlayer fit measurement value to evaluate the interlayer alignment degree of the circuit board, and obtaining the interlayer registration degree of the circuit board;

[0127] Step S45: optimizing the interlayer registration of the preliminary simulation data of the interlayer interconnection according to the interlayer registration degree of the circuit board, and generating interlayer registration optimization data.

[0128] In the embodiment of the present invention, ANSYS HFSS software is used to perform three-dimensional full-wave electromagnetic field simulation to identify the impedance characteristics of the circuit board; specifically, the propagation of electromagnetic waves in the circuit board structure is simulated to calculate the characteristic impedance of the circuit board; based on the impedance characteristic data, the impedance continuity of the hole position area is further detected, and the electromagnetic field distribution in the hole position area is analyzed to ensure the stability and continuity of signal transmission; the hole position data is adjusted according to the impedance continuity data to optimize the impedance matching, and the hole position is precisely positioned and sized to ensure the signal integrity of the circuit board; high-resolution X-ray imaging technology is used to identify the interconnection characteristics between layers, and X-ray images are analyzed to extract Geometric features and alignment features of interlayer connections; calculate the deviation value of interlayer features based on interlayer feature data to evaluate alignment accuracy; use interlayer bonding integrity detection method to determine the degree of interlayer bonding, and specifically evaluate the bonding quality by analyzing the change sequence of interlayer bonding features; combine the measured values ​​of interlayer alignment and bonding to evaluate the degree of interlayer alignment of the circuit board; determine the quality of interlayer alignment by comprehensively analyzing the deviation of interlayer features and the change of bonding features; optimize the preliminary simulation data of interlayer interconnection according to the evaluation results of interlayer alignment, and specifically adjust the geometric parameters of interlayer connection to improve the alignment accuracy and bonding quality between layers.

[0129] Preferably, step S41 includes the following steps:

[0130] Step S411: performing high-frequency signal path identification on the preliminary simulation data of the inter-layer interconnection to obtain high-frequency signal path data; performing impedance parameter extraction on the high-frequency signal path data to obtain impedance parameter information;

[0131] Step S412: performing circuit board impedance characteristic identification on the impedance parameter information to obtain circuit board impedance characteristic data; performing path impedance consistency check on the circuit board impedance characteristic data to obtain a path impedance consistency check result;

[0132] Step S413: positioning the abnormal impedance region on the path impedance consistency check result to obtain abnormal impedance region positioning data; comparing the abnormal impedance region positioning data with the preset impedance value to obtain an impedance value comparison result;

[0133] Step S414: performing impedance continuity deviation measurement on the impedance value comparison result to obtain continuity deviation measurement data; performing impedance continuity evaluation on the continuity deviation measurement data to obtain circuit board impedance continuity data.

[0134] In an embodiment of the present invention, electromagnetic field simulation software (such as ANSYS HFSS) is used to analyze preliminary simulation data of interlayer interconnection and identify high-frequency signal paths; high-frequency signal path data is extracted by simulating the propagation of electromagnetic waves in the circuit board structure. The specific operations include establishing a circuit board model in HFSS, setting a suitable simulation frequency, running the simulation and extracting the signal path; using an impedance extraction tool (such as Polar SI9000) to extract impedance parameters on the identified high-frequency signal path; simulating the impedance parameter information of the signal path by setting ports and excitation signals, including characteristic impedance and transmission line impedance; using the impedance parameter information in combination with the circuit board design rules to identify the impedance characteristics of the circuit board; specifically comparing the actual impedance parameters with the design target impedance to ensure impedance matching; analyzing the circuit board impedance characteristic data to verify whether the impedance on the path is consistent; ensuring the impedance continuity on the signal path by comparing the impedance parameters of different sections; locating the impedance abnormality area based on the path impedance consistency verification results; specifically determining the specific location of the abnormal area by analyzing the impedance discontinuity point; comparing the impedance abnormality area location data with the preset impedance value, and determining the degree of impedance abnormality by comparing the actual impedance value with the design value. Before measuring impedance continuity deviation, a preset impedance continuity deviation value is set. This value is usually determined based on PCB design specifications and signal integrity requirements. For example, for a high-speed digital circuit, the preset impedance continuity deviation is set to ±5%. Use time domain reflectometry (TDR) to measure impedance. TDR sends a fast rising edge step signal to the circuit board to be tested and detects the reflected signal to evaluate the degree of impedance change in the link. Compare the impedance data measured by TDR with the preset impedance value and calculate the deviation between the actual impedance value and the preset value. Record the impedance value of each measurement point and calculate the percentage of deviation from the preset value.

[0135] Preferably, step S42 includes the following steps:

[0136] Step S421: performing impedance continuity change detection on the impedance continuity data of the circuit board to obtain impedance continuity change data; performing abnormal change amount measurement on the impedance continuity change data to generate an impedance abnormal change amount measurement value;

[0137] Step S422: mapping the hole position data of the circuit board based on the measured value of the abnormal impedance change to generate abnormal hole position mapping information; extracting hole size parameters from the abnormal hole position mapping information to obtain abnormal hole position size parameters; identifying the hole position routing layout from the abnormal hole position mapping information to obtain abnormal hole position routing data;

[0138] Step S423: performing dispersion adjustment of the hole position of the circuit board on the abnormally changed hole position mapping information to obtain the hole position adjustment data of the circuit board; reducing the size parameters of the abnormally changed hole position to obtain the hole size reduction parameters; re-layout the hole position routing pins on the abnormally changed hole position routing data to generate the hole position routing pin layout data;

[0139] Step S424: integrating the circuit board hole position adjustment data, the hole size reduction parameters and the hole routing pin layout data to obtain the circuit board hole adjustment data.

[0140] In an embodiment of the present invention, a time domain reflectometry (TDR) is used to detect the impedance continuity data of the circuit board. Specifically, TDR sends a step signal with a fast rising edge to the circuit board to be tested and detects the reflected signal to evaluate the degree of impedance change in the link; based on the TDR detection result, the impedance continuity change data is analyzed, and the abnormal change amount is measured using the automatic balancing bridge method; by comparing the impedance values ​​of different test points, the impedance change amount is calculated, and the impedance abnormal change amount measurement value is generated; using image processing technology, such as the Canny-Zernike moment sub-pixel edge detection method, the hole position is accurately mapped to generate abnormal change hole position mapping information; the least squares method is used to fit the hole position edge, and obtain hole size parameters; identify the hole routing layout through image processing and pattern recognition technology, and obtain abnormal change hole routing data; adjust the hole position according to the abnormal change hole mapping information using computer-aided design (CAD) software to obtain circuit board hole position adjustment data; based on the abnormal change hole size parameters, adjust the hole size through CAD software to achieve size reduction and obtain hole size reduction parameters; according to the abnormal change hole routing data, re-layout the hole routing pins and generate hole routing pin layout data; comprehensively integrate the hole position adjustment data, hole size reduction parameters and hole routing pin layout data, and specifically use CAD software to integrate the data to obtain circuit board hole adjustment data.

[0141] Preferably, step S45 includes the following steps:

[0142] Step S451: quantifying the registration deviation of the inter-layer registration degree of the circuit board to generate registration deviation quantification data; identifying the inter-layer registration deviation distribution of the registration deviation quantification data to obtain inter-layer registration deviation distribution data;

[0143] Step S452: performing correction region detection on the inter-layer registration deviation distribution data to generate inter-layer registration correction region information; performing registration correction parameter calculation on the inter-layer registration correction region information to obtain a registration correction parameter value;

[0144] Step S453: performing interlayer interconnection angle correction on the interlayer interconnection feature data by aligning the correction parameter value to obtain interconnection angle correction data; performing interlayer interconnection displacement adjustment on the interlayer interconnection feature data according to the interconnection angle correction data to obtain interconnection displacement adjustment data;

[0145] Step S454: adjusting the interlayer interconnection structure of the preliminary simulation data of the interlayer interconnection by using the interconnection displacement adjustment data to obtain the interconnection structure adjustment data; and optimizing the interlayer registration of the preliminary simulation data of the interlayer interconnection based on the interconnection structure adjustment data to generate the interlayer registration optimization data.

[0146] In an embodiment of the present invention, an image processing technology, such as an image registration method, is used to quantitatively analyze the interlayer registration degree of a circuit board; by comparing the difference between the actual interlayer alignment and the standard alignment, registration deviation quantitative data is generated; using a circuit board interlayer alignment detection device and method, the registration deviation quantitative data is analyzed to identify the distribution of the interlayer registration deviation and obtain the interlayer registration deviation distribution data; based on the interlayer registration deviation distribution data, a circuit board interlayer alignment detection device is used to detect the correction area to generate interlayer registration correction area information; a mathematical model, such as an affine transformation model, is used to analyze the interlayer registration correction area information. Perform analysis and calculate registration correction parameter values; use the registration correction parameter values ​​to perform angle correction on the interlayer interconnection feature data through image processing technology to obtain interconnection angle correction data; based on the interconnection angle correction data, use the image registration method to adjust the displacement of the interlayer interconnection feature data to obtain interconnection displacement adjustment data; based on the interconnection displacement adjustment data, use the image processing technology to perform structural adjustment on the preliminary simulation data of the interlayer interconnection to obtain interconnection structure adjustment data; based on the interconnection structure adjustment data, use the image registration method to perform interlayer registration optimization on the preliminary simulation data of the interlayer interconnection to generate interlayer registration optimization data.

[0147] As an example of the present invention, refer to Figure 3 As shown, in this example, step S5 includes:

[0148] Step S51: performing hole position adjustment verification on the preliminary simulation data of interlayer interconnection through the circuit board hole position adjustment data to obtain hole position adjustment verification data; performing interlayer registration optimization verification on the preliminary simulation data of interlayer interconnection through the interlayer registration optimization data to obtain interlayer registration optimization verification data;

[0149] Step S52: evaluating the circuit board interlayer adjustment verification result according to the hole position adjustment verification data and the interlayer registration optimization verification data, and generating the circuit board interlayer adjustment verification result; optimizing the circuit board interlayer interconnection on the interlayer interconnection preliminary simulation data based on the circuit board interlayer adjustment verification result, and generating the circuit board interlayer interconnection information;

[0150] Step S53: performing inter-layer design parameter space coordinate matching on the inter-layer interconnection information of the circuit board according to the circuit board design feature information to generate inter-layer design coordinate matching data; performing circuit board design three-dimensional data mapping on the inter-layer design coordinate matching data to obtain circuit board three-dimensional space mapping data;

[0151] Step S54: synthesizing the three-dimensional image of the circuit board three-dimensional space mapping data to obtain a three-dimensional design image of the circuit board; enhancing the image details of the three-dimensional design image of the circuit board to generate a circuit board design drawing.

[0152] In an embodiment of the present invention, a circuit board hole position detection device is used to verify the preliminary simulation data of interlayer interconnection according to the hole position adjustment data; the specific operation includes inputting the hole position adjustment data into the detection device, the device automatically calibrates the hole position, and generates hole position adjustment verification data by comparing the hole position before and after the adjustment; the interlayer registration optimization data is verified by using the implementation method of the interlayer vertical interconnection structure; the operation steps include applying the registration optimization algorithm to the preliminary simulation data of interlayer interconnection, and generating interlayer registration optimization verification data by measuring the interlayer alignment before and after the registration; combining the hole position adjustment verification data and the interlayer registration optimization verification data, using a statistical analysis method to evaluate the verification result of the interlayer adjustment of the circuit board; specifically, calculating the deviation value of the hole position adjustment and the interlayer registration, and generating the verification result of the interlayer adjustment of the circuit board; according to the interlayer adjustment verification result, the preliminary simulation data of the interlayer interconnection is optimized by using the microwave multilayer board interlayer interconnection matching method; specifically adjusting the interlayer connection parameters, such as the routing width and spacing, to meet the performance requirements of the interlayer interconnection, and generating the circuit board interlayer interconnection information; using arbitrary layer interconnection HDI technology, spatial coordinate matching of inter-layer interconnection information is performed according to the design feature information of the circuit board; specifically, the design feature information is input into the HDI software, and the software automatically matches the inter-layer design parameters and spatial coordinates to generate inter-layer design coordinate matching data; using three-dimensional image synthesis technology, the inter-layer design coordinate matching data is mapped into three-dimensional space; specifically, image processing software is used to load the inter-layer design data, and the three-dimensional space mapping data of the circuit board is obtained through three-dimensional coordinate system drawing and image synthesis operations; using agricultural flexible pH chip performance optimization technology based on MSER affine transformation registration, the three-dimensional image synthesis of the three-dimensional space mapping data of the circuit board is performed; specifically, the MSER algorithm is used to extract key feature points, and image registration is achieved through affine transformation to synthesize three-dimensional images; using image enhancement technology, the details of the three-dimensional design image of the circuit board are enhanced; specifically, histogram equalization, Gaussian noise increase, non-mean filtering, contrast adjustment and sharpening and other technologies are used to enhance image details, and finally generate a circuit board design drawing.

[0153] In this specification, a system for generating a circuit board design drawing is provided, which is used to execute the above-mentioned method for generating a circuit board design drawing. The system for generating a circuit board design drawing includes:

[0154] The circuit board design data acquisition module is used to obtain circuit board design requirement information; perform semantic analysis on the circuit board design requirement information to generate design requirement semantic data; perform circuit board design feature extraction on the design requirement semantic data to obtain circuit board design feature information; perform circuit board performance requirement identification on the circuit board design feature information to generate circuit board performance requirement data;

[0155] The circuit board interlayer structure analysis module is used to identify circuit board components based on circuit board design feature information to obtain circuit board component data; perform component association analysis on circuit board component data to obtain component association data; perform circuit board interlayer structure detection based on component association data to obtain circuit board interlayer structure information;

[0156] The circuit board interlayer interconnection simulation module is used to analyze the interlayer interconnection requirements of the circuit board interlayer structure information according to the circuit board performance requirement data, and generate interlayer interconnection requirement data; generate circuit board hole positions based on the circuit board design feature information based on the interlayer interconnection requirement data, and obtain circuit board hole position data; perform preliminary simulation of the circuit board interlayer interconnection according to the circuit board hole position data, and obtain preliminary simulation data of interlayer interconnection;

[0157] The circuit board interlayer interconnection optimization and adjustment module is used to perform impedance continuity detection of the circuit board hole position area on the preliminary simulation data of the interlayer interconnection to obtain the circuit board impedance continuity data; adjust the circuit board hole position data of the circuit board through the circuit board impedance continuity data to generate the circuit board hole position adjustment data; identify the degree of interlayer alignment of the circuit board on the preliminary simulation data of the interlayer interconnection to obtain the degree of interlayer registration of the circuit board; optimize the interlayer registration of the preliminary simulation data of the interlayer interconnection through the degree of interlayer registration of the circuit board to generate the interlayer registration optimization data;

[0158] The circuit board design drawing generation module is used to optimize the inter-layer interconnection of the circuit board based on the preliminary simulation data of the inter-layer interconnection, based on the circuit board hole adjustment data and the inter-layer registration optimization data, and generate the inter-layer interconnection information of the circuit board; and perform circuit board design three-dimensional image mapping on the inter-layer interconnection information of the circuit board according to the circuit board design feature information to obtain the circuit board design drawing.

[0159] The present invention obtains the circuit board design requirement information and performs semantic analysis through the circuit board design data acquisition module, and can accurately generate the design requirement semantic data, which provides accurate basic information for subsequent design; extracts features from the design requirement semantic data to clarify the specific parameters and requirements of the design; further identifies the circuit board performance requirements to ensure that the design meets the expected performance standards. Through the circuit board interlayer structure analysis module, the circuit board design feature information is identified by components, and the obtained circuit board component data provides specific component information for the design; the circuit board component data is analyzed for component association to clarify the relationship between each component; based on the component association data, the interlayer structure detection is performed to provide the design with the physical connection details between layers. Through the circuit board interlayer interconnection simulation module, the interlayer structure information is analyzed for interlayer interconnection requirements according to the circuit board performance requirement data, so as to clarify the electrical connection design of the circuit board; the circuit board hole position is generated based on the interlayer interconnection requirement data, providing accurate location information for the interlayer connection; the circuit board interlayer interconnection is simulated to provide a preliminary preview of the interlayer connection effect for the design. Through the circuit board interlayer interconnection optimization and adjustment module, the impedance continuity of the hole position area of ​​the preliminary simulation data of the interlayer interconnection is detected to ensure the stability of signal transmission. The hole position data is adjusted by impedance continuity data to optimize the signal transmission path; the interlayer alignment degree of the preliminary simulation data of the interlayer interconnection is identified, thereby providing a basis for accurate alignment between layers; the preliminary simulation data is optimized by the interlayer registration degree, thereby improving the accuracy of the interlayer connection. Through the circuit board design drawing generation module, the preliminary simulation data is optimized based on the circuit board hole position adjustment data and the interlayer registration optimization data, so that the circuit board interlayer interconnection information is optimized; according to the circuit board design feature information, the interlayer interconnection information is mapped to a three-dimensional image, which can intuitively display the three-dimensional structure of the circuit board, and provide a detailed visual reference for subsequent circuit board manufacturing and inspection. Therefore, the present invention solves the problems of interlayer alignment and interlayer interconnection in the design of multilayer boards through data processing technology, pattern recognition technology, three-dimensional mapping technology and deep learning technology; and optimizes and adjusts the impedance discontinuity characteristics caused by vias, thereby ensuring the stability and reliability of the generated circuit board design drawing.

[0160] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0161] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A method for generating a circuit board design drawing, characterized in that: The following steps are involved: Step S1: Obtain circuit board design requirement information; Performing semantic analysis on circuit board design requirement information to generate design requirement semantic data; performing circuit board design feature extraction on the design requirement semantic data to obtain circuit board design feature information; Identify circuit board performance requirements based on circuit board design feature information and generate circuit board performance requirement data; Step S2: performing circuit board component identification on the circuit board design feature information to obtain circuit board component data; performing component association analysis on the circuit board component data to obtain component association data; performing circuit board interlayer structure detection based on the component association data to obtain circuit board interlayer structure information; Step S3: performing inter-layer interconnection requirement analysis on the inter-layer structure information of the circuit board according to the circuit board performance requirement data, and generating inter-layer interconnection requirement data; Based on the inter-layer interconnection requirement data, the circuit board hole position is generated for the circuit board design feature information to obtain the circuit board hole position data; Perform preliminary simulation of the interconnection between layers of the circuit board according to the hole position data of the circuit board to obtain preliminary simulation data of the interconnection between layers; Step S4: performing impedance continuity detection of the circuit board hole position area on the preliminary simulation data of interlayer interconnection to obtain the circuit board impedance continuity data; adjusting the circuit board hole position data of the circuit board by using the circuit board impedance continuity data to generate circuit board hole position adjustment data; identifying the degree of interlayer alignment of the circuit board on the preliminary simulation data of interlayer interconnection to obtain the degree of interlayer registration of the circuit board; optimizing the interlayer registration of the preliminary simulation data of interlayer interconnection by using the degree of interlayer registration of the circuit board to generate interlayer registration optimization data; Step S5: Optimize the interlayer interconnection of the circuit board based on the preliminary simulation data of the interlayer interconnection, and generate the interlayer interconnection information of the circuit board; perform circuit board design three-dimensional image mapping on the interlayer interconnection information of the circuit board according to the circuit board design feature information, and obtain the circuit board design drawing.

2. The method for generating a circuit board design drawing according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: performing circuit board component type identification on the circuit board design feature information to obtain circuit board component type information; performing component parameter feature extraction on the circuit board component type information to obtain component parameter feature information; integrating the circuit board component type information and the component parameter feature information to obtain circuit board component data; Step S22: locating component connection nodes on the circuit board component data to obtain component connection node information; identifying inter-device connection paths on the component connection node information to generate inter-device connection path information; Step S23: identifying the connection relationship between components of the circuit board component data based on the component connection node information and the connection path information between components to obtain component association data; Step S24: Identify the inter-layer connection features of the circuit board according to the component association data to obtain the inter-layer connection information of the circuit board; divide the inter-layer connection information of the circuit board into circuit board functional module layers to generate circuit board functional module layer data; perform circuit board inter-layer structure detection on the circuit board functional module layer data to obtain the inter-layer structure information of the circuit board.

3. The method for generating a circuit board design drawing according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: extracting the inter-layer signal transmission rate requirement from the inter-layer structure information of the circuit board according to the circuit board performance requirement data, and obtaining the inter-layer signal transmission requirement parameters; Step S32: Based on the circuit board performance requirement data, the power distribution efficiency requirement of the circuit board interlayer structure information is identified to obtain the interlayer power distribution requirement parameters; Step S33: determining the interconnection density requirement of the circuit board interlayer structure information through the circuit board performance requirement data to obtain the interlayer interconnection density requirement parameter; Step S34: merging the inter-layer signal transmission requirement parameter, the inter-layer power distribution requirement parameter and the inter-layer interconnection density requirement parameter into the inter-layer interconnection requirement parameter to generate inter-layer interconnection requirement data; Step S35: Based on the inter-layer interconnection requirement data, the circuit board design feature information is used to identify the circuit board hole distribution area to obtain the circuit board hole distribution area data; the circuit board hole distribution area data is used to locate the hole coordinates to generate the hole coordinate location data; Step S36: extracting the circuit board hole size parameters from the circuit board design feature information based on the inter-layer interconnection requirement data to obtain the hole size parameters; matching the hole coordinate positioning data with the hole size parameters to obtain the circuit board hole position data; Step S37: Perform preliminary simulation of the interconnection between layers of the circuit board according to the circuit board hole position data and the circuit board design feature information to obtain preliminary simulation data of the interconnection between layers.

4. The method for generating a circuit board design drawing according to claim 3, characterized in that: Step S37 includes the following steps: Step S371: extracting circuit board design parameters from the circuit board design feature information to obtain circuit board design parameters; arranging circuit board components according to the circuit board design parameters to generate circuit board component arrangement data; performing single-layer circuit board routing on the circuit board component arrangement data to generate single-layer circuit board routing data; Step S372: performing inter-layer hole position connectivity simulation on the single-layer circuit board wiring data according to the circuit board hole position data to obtain a hole position connectivity simulation result; performing inter-layer signal transmission path simulation on the hole position connectivity simulation result to obtain inter-layer signal path simulation data; Step S373: performing interlayer interconnection density simulation based on the interlayer signal path simulation data to generate interlayer interconnection density simulation data; performing interlayer fit evaluation on the interlayer interconnection density simulation data to obtain an interlayer fit value; Step S374: Preliminary simulation of the interconnection between layers of the circuit board is performed on the circuit board design feature information through the interlayer bonding degree value to obtain preliminary simulation data of the interconnection between layers.

5. The method for generating a circuit board design drawing according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: performing impedance characteristic identification on the preliminary simulation data of the inter-layer interconnection to obtain impedance characteristic data of the circuit board; performing impedance continuity detection of the circuit board hole area according to the impedance characteristic data of the circuit board to obtain impedance continuity data of the circuit board; Step S42: adjusting the circuit board hole position data according to the circuit board impedance continuity data to generate circuit board hole position adjustment data; Step S43: performing interlayer feature recognition on the preliminary simulation data of interlayer interconnection to obtain interlayer interconnection feature data; performing interlayer alignment measurement on the interlayer interconnection feature data to generate an interlayer alignment measurement value; performing interlayer fit measurement on the interlayer interconnection feature data to generate an interlayer fit measurement value; Step S44: using the interlayer alignment calculation value and the interlayer fit measurement value to evaluate the interlayer alignment degree of the circuit board, and obtaining the interlayer registration degree of the circuit board; Step S45: optimizing the interlayer registration of the preliminary simulation data of the interlayer interconnection according to the interlayer registration degree of the circuit board, and generating interlayer registration optimization data.

6. The method for generating a circuit board design drawing according to claim 5, characterized in that: Step S41 includes the following steps: Step S411: performing high-frequency signal path identification on the preliminary simulation data of the inter-layer interconnection to obtain high-frequency signal path data; performing impedance parameter extraction on the high-frequency signal path data to obtain impedance parameter information; Step S412: performing circuit board impedance characteristic identification on the impedance parameter information to obtain circuit board impedance characteristic data; performing path impedance consistency check on the circuit board impedance characteristic data to obtain a path impedance consistency check result; Step S413: positioning the abnormal impedance region on the path impedance consistency check result to obtain abnormal impedance region positioning data; comparing the abnormal impedance region positioning data with the preset impedance value to obtain an impedance value comparison result; Step S414: performing impedance continuity deviation measurement on the impedance value comparison result to obtain continuity deviation measurement data; performing impedance continuity evaluation on the continuity deviation measurement data to obtain circuit board impedance continuity data.

7. The method for generating a circuit board design drawing according to claim 5, characterized in that: Step S42 includes the following steps: Step S421: performing impedance continuity change detection on the impedance continuity data of the circuit board to obtain impedance continuity change data; performing abnormal change amount measurement on the impedance continuity change data to generate an impedance abnormal change amount measurement value; Step S422: mapping the hole position data of the circuit board based on the measured value of the abnormal impedance change to generate abnormal hole position mapping information; extracting hole size parameters from the abnormal hole position mapping information to obtain abnormal hole position size parameters; identifying the hole position routing layout from the abnormal hole position mapping information to obtain abnormal hole position routing data; Step S423: performing dispersion adjustment of the hole position of the circuit board on the abnormally changed hole position mapping information to obtain the hole position adjustment data of the circuit board; reducing the size parameters of the abnormally changed hole position to obtain the hole size reduction parameters; re-layout the hole position routing pins on the abnormally changed hole position routing data to generate the hole position routing pin layout data; Step S424: integrating the circuit board hole position adjustment data, the hole size reduction parameters and the hole routing pin layout data to obtain the circuit board hole adjustment data.

8. The method for generating a circuit board design drawing according to claim 5, characterized in that: Step S45 includes the following steps: Step S451: quantifying the registration deviation of the inter-layer registration degree of the circuit board to generate registration deviation quantification data; identifying the inter-layer registration deviation distribution of the registration deviation quantification data to obtain inter-layer registration deviation distribution data; Step S452: performing correction region detection on the inter-layer registration deviation distribution data to generate inter-layer registration correction region information; performing registration correction parameter calculation on the inter-layer registration correction region information to obtain a registration correction parameter value; Step S453: performing interlayer interconnection angle correction on the interlayer interconnection feature data by aligning the correction parameter value to obtain interconnection angle correction data; performing interlayer interconnection displacement adjustment on the interlayer interconnection feature data according to the interconnection angle correction data to obtain interconnection displacement adjustment data; Step S454: adjusting the interlayer interconnection structure of the preliminary simulation data of the interlayer interconnection by using the interconnection displacement adjustment data to obtain the interconnection structure adjustment data; and optimizing the interlayer registration of the preliminary simulation data of the interlayer interconnection based on the interconnection structure adjustment data to generate the interlayer registration optimization data.

9. The method for generating a circuit board design drawing according to claim 1, characterized in that: Step S5 includes the following steps: Step S51: performing hole position adjustment verification on the preliminary simulation data of interlayer interconnection through the circuit board hole position adjustment data to obtain hole position adjustment verification data; performing interlayer registration optimization verification on the preliminary simulation data of interlayer interconnection through the interlayer registration optimization data to obtain interlayer registration optimization verification data; Step S52: evaluating the circuit board interlayer adjustment verification result according to the hole position adjustment verification data and the interlayer registration optimization verification data, and generating the circuit board interlayer adjustment verification result; optimizing the circuit board interlayer interconnection on the interlayer interconnection preliminary simulation data based on the circuit board interlayer adjustment verification result, and generating the circuit board interlayer interconnection information; Step S53: performing inter-layer design parameter space coordinate matching on the inter-layer interconnection information of the circuit board according to the circuit board design feature information to generate inter-layer design coordinate matching data; performing circuit board design three-dimensional data mapping on the inter-layer design coordinate matching data to obtain circuit board three-dimensional space mapping data; Step S54: synthesizing the three-dimensional image of the circuit board three-dimensional space mapping data to obtain a three-dimensional design image of the circuit board; enhancing the image details of the three-dimensional design image of the circuit board to generate a circuit board design drawing.

10. A system for generating a circuit board design drawing, characterized in that: Used to execute the method for generating a circuit board design drawing according to claim 1, the system for generating a circuit board design drawing comprises: The circuit board design data acquisition module is used to obtain circuit board design requirement information; perform semantic analysis on the circuit board design requirement information to generate design requirement semantic data; perform circuit board design feature extraction on the design requirement semantic data to obtain circuit board design feature information; perform circuit board performance requirement identification on the circuit board design feature information to generate circuit board performance requirement data; The circuit board interlayer structure analysis module is used to identify circuit board components based on circuit board design feature information to obtain circuit board component data; perform component association analysis on circuit board component data to obtain component association data; perform circuit board interlayer structure detection based on component association data to obtain circuit board interlayer structure information; The circuit board interlayer interconnection simulation module is used to analyze the interlayer interconnection requirements of the circuit board interlayer structure information according to the circuit board performance requirement data, and generate interlayer interconnection requirement data; generate circuit board hole positions based on the circuit board design feature information based on the interlayer interconnection requirement data, and obtain circuit board hole position data; perform preliminary simulation of the circuit board interlayer interconnection according to the circuit board hole position data, and obtain preliminary simulation data of interlayer interconnection; The circuit board interlayer interconnection optimization and adjustment module is used to perform impedance continuity detection of the circuit board hole position area on the preliminary simulation data of the interlayer interconnection to obtain the circuit board impedance continuity data; adjust the circuit board hole position data of the circuit board through the circuit board impedance continuity data to generate the circuit board hole position adjustment data; identify the degree of interlayer alignment of the circuit board on the preliminary simulation data of the interlayer interconnection to obtain the degree of interlayer registration of the circuit board; optimize the interlayer registration of the preliminary simulation data of the interlayer interconnection through the degree of interlayer registration of the circuit board to generate the interlayer registration optimization data; The circuit board design drawing generation module is used to optimize the inter-layer interconnection of the circuit board based on the preliminary simulation data of the inter-layer interconnection, based on the circuit board hole adjustment data and the inter-layer registration optimization data, and generate the inter-layer interconnection information of the circuit board; and perform circuit board design three-dimensional image mapping on the inter-layer interconnection information of the circuit board according to the circuit board design feature information to obtain the circuit board design drawing.

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