Gate drive circuit and display panel

Abstract

The invention discloses a gate drive circuit and a display panel, the gate drive circuit comprises a plurality of stage circuits, and each stage circuit comprises an input module, a first output module, a second output module, a voltage stabilizing module and a first drive controller; wherein the voltage stabilizing module comprises a sixth transistor, a grid electrode of the sixth transistor is used for receiving a clock signal, the working mode of the grid driving circuit comprises a low-power-consumption mode, when the grid driving circuit is in the low-power-consumption mode, the clock signal is a first voltage, and the first voltage enables the first transistor to be conducted. According to the gate drive circuit provided by the embodiment of the invention, the power consumption of the gate drive circuit can be reduced by reducing the frequency of the clock signal, and display abnormity does not occur, so that the display problem of a display panel caused by abnormal output of the stage circuit due to the reduction of the frequency of the clock signal in the related technology is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] In a display panel, a gate driving circuit is usually used to provide corresponding gate driving signals for different transistors. The gate driving signal includes multiple stages of circuits, and each stage of the circuit outputs a gate driving signal of a corresponding stage.

[0003] In the related art, in order to reduce the power consumption of the stage circuit, the working mode of the gate circuit includes a normal mode and a low power mode. In the low power mode, the frequency of multiple input signals of the stage circuit is reduced compared with the normal mode, such as reducing the frequency of the start signal (STV) and the clock signal (CK). However, the reduction in the frequency of the clock signal will cause the control node used to control the output of the stage circuit to be in a floating state, thereby causing the voltage of the control node to leak, thereby causing the display panel to be abnormal. Summary of the invention

[0004] The present application provides a gate drive circuit and a display panel to improve a technical problem in the related art where, in a low power consumption mode, the frequency of a clock signal is reduced so that a control node used to control a stage circuit output is in a floating state, thereby causing the voltage of the control node to leak, thereby causing an abnormality in the display panel.

[0005] In a first aspect, the present application provides a gate drive circuit, the gate drive circuit comprising a plurality of cascaded stage circuits, the stage circuit comprising: an input module, the input module receiving an initial signal or a stage transmission signal output by other stage circuits, and controlling the voltage of a second node; a first output module, the first output module outputting a first gate drive signal according to the potential of a third node and the potential of a fourth node; a second output module, the second output module outputting a second gate drive signal according to the potential of the second node; a voltage stabilizing module, the voltage stabilizing module being electrically connected to a first power line and a second power line, and transmitting the voltage on the first power line or the voltage on the second power line to the second node according to the voltage of the fourth node; a first drive control module, the first drive control module controlling the voltage of the fourth node according to the voltage of the second node; wherein the voltage stabilizing module comprises a first transistor, the gate of the first transistor being used to receive a clock signal, the working mode of the gate drive circuit comprising a low power consumption mode, when the gate drive circuit is in the low power consumption mode, the clock signal is a first voltage, and the first voltage turns on the first transistor.

[0006] In one embodiment, the first transistor is an N-channel thin film transistor, and the first voltage is a high level.

[0007] In one embodiment, the first transistor is a dual-gate indium gallium zinc oxide thin film transistor, and the first gate of the first transistor and the second gate of the first transistor are both used to receive the clock signal.

[0008] In one embodiment, the voltage stabilizing module also includes a second transistor, a gate of the second transistor is electrically connected to the fourth node, one of the source or drain of the second transistor is electrically connected to the first power line, the other of the source or drain of the second transistor is electrically connected to one of the source or drain of the first transistor, and the other of the source or drain of the first transistor is electrically connected to the second node; wherein the channel types of the first transistor and the second transistor are different.

[0009] In one embodiment, when the gate driving circuit is in a low power consumption mode, the voltage at the fourth node turns on the second transistor to transmit the voltage on the first power line to one of the source or the drain of the first transistor.

[0010] In one embodiment, the voltage stabilizing module also includes a third transistor, one of the source or the drain of the third transistor is electrically connected to the second power line, the other of the source or the drain of the third transistor is electrically connected to the second node, and the gate of the third transistor is connected to the fourth node.

[0011] In one embodiment, when the gate driving circuit is in a low power consumption mode, the voltage of the fourth node turns off the third transistor.

[0012] In one embodiment, the third transistor is a dual-gate indium gallium zinc oxide thin film transistor, and the first gate of the third transistor and the second gate of the third transistor are both electrically connected to the fourth node.

[0013] In one embodiment, the stage circuit further includes: a reset module, and the reset module controls the voltage of the second node according to a reset signal.

[0014] In one embodiment, the reset module includes a fourth transistor, one of the source or the drain of the fourth transistor is connected to the first power line, the other of the source or the drain of the fourth transistor is electrically connected to the second node, and the gate of the fourth transistor receives the reset signal.

[0015] In one embodiment, in a first frame of operation of the gate driving circuit, the reset signal controls the fourth transistor to be turned on before a pulse of the start signal arrives, so that the voltage on the first power line is transmitted to the second node.

[0016] In one embodiment, the first driving control module is electrically connected to the second node and the fourth node, and the first driving control module outputs a voltage that is inversely proportional to the voltage of the second node to the fourth node.

[0017] In one embodiment, the first drive control module includes: a fifth transistor and a sixth transistor, one of a source or a drain of the fifth transistor is electrically connected to the first power line, the other of the source or the drain of the fifth transistor is electrically connected to the fourth node, one of a source or a drain of the sixth transistor is electrically connected to the third power line, the other of the source or the drain of the sixth transistor is electrically connected to the fourth node, and a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the second node;

[0018] Wherein, the fifth transistor is a P-channel thin film transistor, and the sixth transistor is an N-channel thin film transistor.

[0019] In one embodiment, the sixth transistor is a dual-gate transistor, and a first gate of the sixth transistor and a second gate of the sixth transistor are both electrically connected to the second node.

[0020] In one embodiment, when the gate driving circuit is in a low power consumption mode, the sixth transistor is turned on to output the voltage on the third power line to the fourth node.

[0021] In one embodiment, the stage circuit also includes: a second drive control module, the second drive control module is electrically connected between the second node and the third node, the control end of the second drive control module is electrically connected to the drive control line, and the second drive control module is used to control the conduction between the second node and the third node.

[0022] In one embodiment, the second driving control module is used to eliminate the first pulse of the second node appearing in a frame, and retain the second pulse of the second node appearing in the same frame.

[0023] In the second aspect, the present application provides a display panel, which includes a pixel circuit and a gate driving circuit in at least one of the above-mentioned embodiments, the pixel circuit includes a write transistor for controlling the input of a data signal and a compensation transistor for controlling the input of the data signal to the gate of the driving transistor; the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

[0024] Beneficial effects of the present invention: By setting the voltage stabilizing module to be electrically connected to the second node, when the gate drive circuit is in a low power consumption mode, the first transistor can be turned on to maintain the potential of the second node. Thus, when the clock signal is of low frequency, the potential of the second node will not drop due to leakage, and the potential of the second node can be kept at a high potential. Therefore, the gate drive circuit provided in this embodiment can reduce the power consumption of the gate drive circuit by reducing the frequency of the clock signal, and display abnormality will not occur, thereby solving the problem in the related art that the reduction of the clock signal frequency will cause the stage circuit output to be abnormal, resulting in the display problem of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0026] Figure 1 It is a schematic diagram of the structure of a gate driving circuit in the related art.

[0027] Figure 2 for Figure 1 The timing diagram of some signals in the gate drive circuit is shown.

[0028] Figure 3 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application.

[0029] Figure 4 for Figure 3 The timing diagram of some signals in the gate drive circuit is shown.

[0030] Figure 5 for Figure 1 The timing diagram of some signals in the gate drive circuit is shown.

[0031] Figure 6 for Figure 3 The timing diagram of some signals in the gate drive circuit is shown.

[0032] Figure 7 for Figure 3 The timing diagram of the gate drive circuit shown.

[0033] Figure 8 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the first stage of the process.

[0034] Fig. 9 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the second stage of the status.

[0035] Fig.10 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the third stage of the status.

[0036] Fig.11 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the fourth stage of the status.

[0037] Fig.12 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the fifth stage of the status.

[0038] Fig.13 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the sixth stage of the status.

[0039] Fig.14 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the seventh stage of the state.

[0040] Fig.15 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the eighth stage of the state.

[0041] Fig.16 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the ninth stage of the process.

[0042] Fig.17 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the status of the tenth stage.

[0043] Fig.18 for Figure 3 The gate drive circuit shown in Figure 7 Schematic diagram of the status of the eleventh stage.

[0044] Fig.19 for Figure 3 A schematic diagram of the structure of cascade connection between different stages of circuits in the gate drive circuit shown.

[0045] Fig. 20 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0046] Fig.21 for Fig. 20 A schematic structural diagram of a pixel circuit in a display panel is shown.

[0047] Fig. 22 for Fig.21 Timing diagram of the pixel circuit shown. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0049] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0050] See also Figure 1 , Figure 2 , Figure 1 Schematic diagram of the structure of a gate drive circuit in the related art. The gate drive circuit includes at least one of an input module 10, a second drive control module 70, a first drive control module 50, a first output module 20, a second output module 30 and a feedback module 40.

[0051] The first output module 20 outputs a first gate driving signal. The second output module 30 outputs a second gate driving signal. For a detailed description of the gate driving circuit, please refer to the subsequent related description.

[0052] In order to reduce the power consumption of the stage circuit, in the low power consumption mode, the frequencies of multiple input signals of the stage circuit are reduced, such as reducing the frequencies of the start signal (STV) and the clock signals (CK, XCK).

[0053] However, during the application process, the inventors found that the reduction in the frequency of the clock signal will cause abnormal display of the display panel. Figure 2As shown in a, when the clock signal is in a high potential state for a long time, transistor T2 and the first transistor T4 are all in a closed state, and the second node K is in a floating state. However, due to the leakage current of transistor T2, the potential of the second node K cannot be maintained for a long time, resulting in leakage of the second node K through transistor T2, and the potential of the second node K continues to decrease. When the potential of the second node K decreases to a certain extent, the Vgs of the fifth transistor T3 becomes smaller and smaller, and finally reaches the critical value for turning on the fifth transistor T3. When the fifth transistor T3 is turned on, point P is at a high level, and the third transistor T14 is turned on, pulling the potential of the second node K down to a low level, and finally turning on transistor T9 and outputting the second gate drive signal, resulting in output abnormality.

[0054] That is to say, Figure 1 In the gate driving circuit shown, when the clock signal frequency is reduced, the above-mentioned specific problem will occur, that is, when the clock signal frequency is reduced, the output of the stage circuit will be abnormal, resulting in display problems of the display panel.

[0055] In view of this, this embodiment provides a gate driving circuit, see Figures 1 to 22 ,like Figure 3 As shown, the gate driving circuit includes a plurality of stage circuits, and the stage circuit includes at least one of an input module 10 , a first output module 20 , a second output module 30 , a first driving control module 50 and a voltage stabilizing module 40 .

[0056] The input module 10 receives an initial signal or a stage transmission signal output by other stage circuits to control the voltage of the second node K. The first output module 20 outputs a first gate drive signal according to the potential of the third node Q and the potential of the fourth node P. The second output module 30 outputs a second gate drive signal according to the potential of the second node K. The voltage stabilizing module 40 is electrically connected to the first power line and the second power line, and transmits the voltage on the first power line or the voltage on the second power line to the second node K according to the voltage of the fourth node P. The first drive control module 50 controls the voltage of the fourth node P according to the voltage of the second node K.

[0057] The voltage stabilizing module 40 includes a first transistor T4, a gate of the first transistor T4 is used to receive a clock signal, and the working mode of the gate driving circuit includes a low power consumption mode. When the gate driving circuit is in the low power consumption mode, the clock signal is a first voltage, and the first voltage turns on the first transistor.

[0058] It can be understood that the gate drive circuit provided in this embodiment is electrically connected to the second node K by setting the voltage stabilizing module 40. When the gate drive circuit is in a low power consumption mode, the first transistor T4 can be turned on to maintain the potential of the second node K. Therefore, when the clock signal is low frequency, the potential of the second node K will not drop due to leakage, and the potential of the second node K can be kept at a high potential. Therefore, the gate drive circuit provided in this embodiment can reduce the power consumption of the gate drive circuit by reducing the frequency of the clock signal, and display abnormality will not occur, thereby solving the problem in the related art that the reduction of the clock signal frequency will cause the stage circuit output to be abnormal, resulting in the display problem of the display panel.

[0059] In one embodiment, the first transistor T4 is an N-channel thin film transistor, the clock signal includes a first clock signal (XCK), the gate of the first transistor T4 is used to receive the first clock signal, and when the gate drive circuit is in a low power consumption mode, the voltage of the first clock signal is a first voltage, the first voltage is a high level, and the first transistor T4 is turned on.

[0060] Specifically, the first transistor is a dual-gate indium gallium zinc oxide thin film transistor, and the first gate of the first transistor and the second gate of the first transistor are both used to receive the first clock signal.

[0061] It should be noted that when the first clock signal maintains a high potential state at a low frequency, the gate drive circuit in this embodiment can maintain the potential of the second node K through the first transistor T4 in the voltage stabilizing module 40, thereby reducing the frequency of the clock signal while preventing the gate drive circuit from abnormally outputting. Therefore, in this application, the power consumption of the gate drive circuit can be reduced by maintaining a high potential at a low frequency for the clock signal.

[0062] In one embodiment, the first transistor T4 is a P-channel thin film transistor. When the gate driving circuit is in a low power consumption mode, the voltage of the first clock signal is a first voltage, the first voltage is at a low level, and the first transistor T4 is turned on.

[0063] It should be noted that when the first clock signal maintains a low potential state at a low frequency, the gate drive circuit in this embodiment can maintain the potential of the second node K through the first transistor T4 in the voltage stabilizing module 40, thereby reducing the frequency of the clock signal while preventing the gate drive circuit from abnormally outputting. Therefore, in this application, the power consumption of the gate drive circuit can be reduced by maintaining a high potential at a low frequency for the clock signal.

[0064] In one embodiment, the first drive control module 50 is electrically connected to the second node K and the fourth node P, and the first drive control module 50 is used to control the voltage of the fourth node P according to the voltage of the second node K. The input end of the first drive control module 50 is electrically connected to the output end of the input module 10, and the output end of the first drive control module 50 is electrically connected to the fourth node P.

[0065] The voltage stabilizing module 40 is electrically connected to the second node K, the first power line, and the second power line. The voltage stabilizing module 40 is used to maintain the potential of the second node K at the potential on the first power line or the potential on the second power line according to the first clock signal and the potential of the fourth node P.

[0066] In one embodiment, the first drive control module 50 includes a fifth transistor T3 and a sixth transistor T1, one of the source or the drain of the fifth transistor T3 is electrically connected to the first power line, the other of the source or the drain of the fifth transistor T3 is electrically connected to one of the source or the drain of the sixth transistor T1 and the fourth node P, the other of the source or the drain of the sixth transistor T1 is electrically connected to the third power line, and the output end of the input module 10 is electrically connected to the gate of the fifth transistor T3, the first gate of the sixth transistor T1, and the second gate of the sixth transistor T1.

[0067] It should be noted that the fifth transistor T3 is a P-channel thin film transistor and the sixth transistor T1 is a dual-gate N-channel thin film transistor, which can improve the dynamic performance of the fifth transistor T3 and the sixth transistor T1, and further improve the dynamic performance of the first drive control module 50.

[0068] The voltage stabilizing module 40 includes a first transistor T4 and a second transistor T5, one of the source or the drain of the first transistor T4 is electrically connected to the output end of the input module 10 and the second node K, the gate of the first transistor T4 is electrically connected to the first clock line to receive the first clock signal, the other of the source or the drain of the first transistor T4 is electrically connected to one of the source or the drain of the second transistor T5, the other of the source or the drain of the second transistor T5 is electrically connected to the first power line, and the gate of the second transistor T5 is electrically connected to the output end of the first drive control module 50 and the fourth node P.

[0069] It should be noted that the voltage stabilizing module 40 can maintain the second node K at a high potential based on the potential of the fourth node P and the potential of the first clock line. That is, when the fourth node P is at a low potential, the first power line can control the potential of the second node K to the potential of the first power signal PVGH.

[0070] In one embodiment, the voltage stabilizing module 40 further includes a third transistor T14, one of the source or the drain of the third transistor T14 is electrically connected to the second power line, the other of the source or the drain of the third transistor T14 is electrically connected to the second node K, and the gate of the third transistor T14 is connected to the fourth node P.

[0071] It should be noted that the voltage stabilizing module 40 can maintain the potential of the second node K at a low potential according to the potential of the fourth node P. That is, when the fourth node P is at a high potential, the second power line can control the potential of the second node K to the potential of the second power signal VGL.

[0072] The third transistor T14 is an N-channel thin film transistor, and the third transistor T14 is a dual-gate thin film transistor, which can not only improve the control capability of the current flowing through itself, but also reduce the drift amplitude of the threshold voltage.

[0073] In one embodiment, the sixth transistor T1 , the first transistor T4 , and the third transistor T14 may all be indium gallium zinc oxide thin film transistors.

[0074] In one embodiment, the gate drive circuit further includes a second drive control module 70. The second drive control module 70 is electrically connected between the second node K and the third node Q. The input end of the second drive control module 70 is electrically connected to the output end of the input module 10, and the control end of the second drive control module 70 is electrically connected to the drive control line.

[0075] The input end of the second output module 30 is electrically connected to the output end of the input module 10, and the output end of the second output module 30 is electrically connected to the Nth level positive pulse gate drive line, and the number of positive pulses output by the Nth level positive pulse gate drive line in one frame is greater than the number of negative pulses output by the Nth level negative pulse gate drive line in one frame.

[0076] It should be noted that the N-th level positive pulse gate drive line is the second gate drive line, which is used to transmit the N-th level positive pulse gate drive signal Nout[N], that is, the second gate drive signal, and the second gate drive signal can be used as the level transmission signal of the level circuit. The N-th level negative pulse gate drive line is the first gate drive line, which is used to transmit the N-th level negative pulse gate drive signal Pout[N], that is, the first gate drive signal.

[0077] It should be noted that the gate drive circuit provided in this embodiment can not only output the second gate drive signal with a larger number of pulses through the input module 10 and the second output module 30, but also select the second gate drive signal as a level transmission signal between different level circuits; and the first gate drive signal with a smaller number of pulses can be output through the input module 10, the second drive control module 70, the first drive control module 50 and the first output module 20, which can meet the needs of the corresponding pixel circuit for the pulses of the gate drive signal in time, quantity, etc. in one frame, thereby driving the pixel circuit to achieve quality display.

[0078] In one embodiment, the second drive control module 70 includes a transistor T11, one of the source or the drain of the transistor T11 is electrically connected to the output end of the input module 10, the other of the source or the drain of the transistor T11 is electrically connected to the control end of the first output module 20, and the gate of the transistor T11 is electrically connected to the drive control line; wherein the transistor T11 is a P-channel thin film transistor; the drive control line is used to transmit the drive control signal RST.

[0079] It should be noted that the output end of the input module 10 is the second node K. One of the control ends of the first output module 20 is the third node Q. The other of the source or drain of the transistor T11 is the node W. The second drive control module 70 is used to reduce the double pulses appearing at the second node K in one frame to a single pulse appearing at the third node Q in one frame; specifically, the first pulse appearing at the second node K in one frame is eliminated, while the second pulse appearing in the same frame is retained.

[0080] It should be noted that this embodiment is conducive to ensuring the output stability of the Nth level negative pulse gate drive signal Pout[N], and avoids the coupling pull-down phenomenon before the negative pulse arrives.

[0081] In one embodiment, the second driving control module 70 further includes a first capacitor C2, one end of the first capacitor C2 is electrically connected to the gate of the transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the source or the drain of the transistor T11.

[0082] It should be noted that this embodiment is beneficial to further improve the output stability of the Nth stage negative pulse gate driving signal Pout[N].

[0083] It should be noted that the output end of the input module 10 is the second node K. The control end of the first output module 20 is the third node Q. The other of the source or the drain of the transistor T11 is the node W. The second drive control module 70 is used to reduce the double pulses appearing at the second node K in one frame to a single pulse appearing at the third node Q in one frame; specifically, the first pulse appearing at the second node K in one frame is eliminated, while the second pulse appearing in the same frame is retained.

[0084] In one embodiment, the first output module 20 includes a transistor T6 and a second capacitor C1, the gate of the transistor T6 is electrically connected to one of the source or drain of the transistor T11, one of the source or drain of the transistor T6 is electrically connected to the second clock line, and the other of the source or drain of the transistor T6 is electrically connected to the Nth level negative pulse gate drive line; one end of the second capacitor C1 is electrically connected to the gate of the transistor T6, and the other end of the second capacitor C1 is electrically connected to the other of the source or drain of the transistor T6; wherein the ratio of the capacity of the first capacitor C2 to the second capacitor C1 is greater than or equal to 0.5.

[0085] It should be noted that the design of the capacity ratio of the first capacitor C2 to the second capacitor C1 in this embodiment is conducive to further ensuring the output stability of the Nth level negative pulse gate drive signal Pout[N] and avoiding the coupling pull-down phenomenon before the negative pulse arrives.

[0086] Specifically, the capacity of the first capacitor C2 may be greater than or equal to 50 fF. The capacity of the second capacitor C1 may be greater than or equal to 100 fF. In some embodiments, the transistor T6 may be a P-channel thin film transistor.

[0087] In one embodiment, the first output module 20 includes a transistor T7, one of the source or drain of the transistor T7 is electrically connected to the first power line, the other of the source or drain of the transistor T7 is electrically connected to the Nth level negative pulse gate drive line, and the gate of the transistor T7 is electrically connected to the output end of the first drive control module 50, i.e., the fourth node P.

[0088] It should be noted that the transistor T7 can be a P-channel thin film transistor. Under the joint action of the first output module 20 and the first output module 20, the required Nth level negative pulse gate driving signal Pout[N] can be modulated.

[0089] In one embodiment, the input module 10 includes a transistor T2 , a transistor T13 , and a transistor T12 . One of the sources or drains of transistor T13 is electrically connected to the third power line, the other of the sources or drains of transistor T13 is electrically connected to the input end of input module 10, the first gate of transistor T13 is electrically connected to the initial control line or the NYth positive pulse gate drive line, the first gate of transistor T13 is electrically connected to the second gate of transistor T13, and transistor T13 is an N-channel thin film transistor; one of the sources or drains of transistor T12 is electrically connected to the first power line, the other of the sources or drains of transistor T12 is electrically connected to the other of the sources or drains of transistor T13, the gate of transistor T12 is electrically connected to the first gate of transistor T13, and transistor T12 is a P-channel thin film transistor, one of the sources or drains of transistor T2 is electrically connected to the output end of transistor T13 and transistor T12, the other of the sources or drains of transistor T2 is electrically connected to the input end of the second drive control module 70, and the gate of transistor T2 is electrically connected to the first clock line. In some embodiments, transistor T2 can be a P-channel thin film transistor.

[0090] It should be noted that, in this embodiment, the input module 10 not only objectively has an inverting effect, that is, the potentials of the input signal and the output signal are opposite at the same time, but also plays a role in making the Nth level positive pulse gate drive signal Nout[N] serve as a level transmission signal between level circuits. Otherwise, level transmission cannot be achieved between the various levels of circuits, resulting in the gate drive circuit being unable to normally provide the corresponding gate drive signal.

[0091] In one embodiment, the second output module 30 includes a P-channel transistor T9 and an N-channel transistor T10, a first electrode of the transistor T9 is electrically connected to the fourth power line, and a gate of the transistor T9 is electrically connected to the second node K. A first electrode of the transistor T10 is electrically connected to a second electrode of the transistor T9 to output a second gate driving signal, and a gate of the transistor T10 is electrically connected to a gate of the transistor T9.

[0092] In one embodiment, the gate of the transistor T10 includes a first gate and a second gate, and the second node K is electrically connected to the first gate of the transistor T10 and the second gate of the transistor T10.

[0093] It should be noted that in this embodiment, the transistor T10 may be a dual-gate thin film transistor, which can not only improve the control capability of the current flowing through itself, but also reduce the drift amplitude of the threshold voltage. The transistor T10 is an indium gallium zinc oxide thin film transistor.

[0094] The first power line is used to transmit a first power signal PVGH, which can control the N-channel thin film transistor to be turned on or the P-channel thin film transistor to be turned off. The second power line is used to transmit a second power signal NVGL, which can control the P-channel thin film transistor to be turned on or the N-channel thin film transistor to be turned off. The third power line is used to transmit a third power signal PVGL, and the fourth power line is used to transmit a third power signal NVGH.

[0095] In one embodiment, the third power signal PVGL is smaller than the second power signal NVGL, so that the third transistor T14 is turned off more completely when in the off state.

[0096] In one embodiment, the second output module 30 outputs a second gate driving signal according to the potential of the second node K, and the number of pulses of the second gate driving signal in one frame is greater than the number of pulses of the first gate driving signal in one frame.

[0097] The transistor T9 is a P-channel thin film transistor, and the transistor T10 is a dual-gate N-channel thin film transistor. This can improve the dynamic performance of the transistors T9 and T10, and further improve the dynamic performance of the second output module 30.

[0098] It should be noted that the Nth level positive pulse gate drive line is used to transmit the Nth level positive pulse gate drive signal Nout[N]. The Nth level negative pulse gate drive line is used to transmit the Nth level negative pulse gate drive signal Pout[N]. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The NYth level positive pulse gate drive line is used to transmit the NYth level positive pulse gate drive signal Nout[NY]. The NXth level positive pulse gate drive line is used to transmit the NXth level positive pulse gate drive signal Nout[NX]. The drive control line is used to transmit the drive control signal RST.

[0099] In one embodiment, the second drive control module 70 also includes an anti-leakage transistor T8, one of the source or the drain of the anti-leakage transistor T8 is electrically connected to the other of the source or the drain of the transistor T11, the other of the source or the drain of the anti-leakage transistor T8 is electrically connected to the control end of the first output module 20, and the gate of the anti-leakage transistor T8 is electrically connected to the anti-leakage signal line to receive the anti-leakage signal.

[0100] Among them, the leakage prevention signal line can be a positive pulse gate drive line N[nX], specifically, it can be the N-2th level positive pulse gate drive line, and the leakage prevention signal is the N-2th level positive pulse gate drive signal N[n-2].

[0101] like Figure 5 As shown in c, when the first clock signal XCK signal of transistor T2 does not start working, the second node K is in a floating state. When the second node K randomly changes to a low level state, the second output module 30 outputs a high level, thereby causing a series of level transmission reactions, resulting in abnormal output of the first frame of all rows.

[0102] To solve the above problem, in one embodiment, the N-th stage circuit further includes a reset module 60, and the reset module 60 controls the voltage of the second node according to the reset signal control. The reset module 60 includes a fourth transistor T15, one of the source or the drain of the fourth transistor T15 is connected to the first power line, the other of the source or the drain of the fourth transistor T15 is connected to the second node, and the gate of the fourth transistor T15 receives the reset signal control.

[0103] The reset signal control is turned on only once each time the gate drive circuit is powered on, that is, the fourth transistor T15 is turned on, and the potential of the second node K is pulled to a high potential. At this time, the start signal STV, the first clock signal XCK, the second clock signal CK, the leakage prevention signal N[n-2], and the drive control signal RST have not started to transmit signals.

[0104] It can be understood that the reset module 60 can ensure that the second node K is at a high level each time the gate drive circuit is powered on, so that the above-mentioned abnormal output situation will not occur. Figure 6 As shown in d.

[0105] The operation process of the above-mentioned stage circuit in one frame may include the following: Figure 7 The following stages are shown:

[0106] Stage 1 S1: Figure 7 , Figure 8 As shown, the start control signal STV, the drive control signal RST, the first clock signal XCK, and the anti-leakage signal N[n-2] are all at a low potential, the second clock signal CK is at a high potential, the first node O, the second node K and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0107] Stage 2 S2: Figure 7 , Fig. 9As shown, the start control signal STV, the second clock signal CK, and the anti-leakage signal N[n-2] are all at a low potential, the drive control signal RST and the first clock signal XCK are at a high potential, the first node O, the second node K and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0108] Stage 3 S3: Figure 7 , Fig.10 As shown, the start control signal STV, the first clock signal XCK, and the anti-leakage signal N[n-2] are all at a low potential, the drive control signal RST and the second clock signal CK are all at a high potential, the first node O, the second node K and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0109] Stage 4 S4: Figure 7 , Fig.11 As shown, the drive control signal RST and the start control signal STV are at a low potential, the first clock signal XCK, the second clock signal CK, and the leakage protection signal N[n-2] are all at a high potential, the first node O, the second node K and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0110] Stage 5 S5: Figure 7 , Fig.12 As shown, the drive control signal RST and the first clock signal XCK are all at a low potential, the start control signal STV, the second clock signal CK, and the leakage protection signal N[n-2] are all at a high potential, the third node Q and the fourth node P are all at a high potential, the first node O and the second node K are all at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0111] Stage 6 S6: Figure 7 , Fig.13 As shown, the start control signal STV, the first clock signal XCK, the second clock signal CK, and the drive control signal RST are all at a high potential, the leakage protection signal N[n-2] is at a low potential, the third node Q and the fourth node P are both at a high potential, the first node O and the second node K are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0112] Stage 7 S7: Figure 7 , Fig.14 As shown, the start control signal STV, the first clock signal XCK, and the anti-leakage signal N[n-2] are all at a low potential, the second clock signal CK and the drive control signal RST are all at a high potential, the fourth node P is all at a low potential, the first node O, the second node K, and the third node Q are at a high potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0113] Stage 8 S8: Figure 7 , Fig.15 As shown, the start control signal STV, the first clock signal XCK, and the leakage protection signal N[n-2] are all at a high potential, the drive control signal RST is at a low potential, the first node O and the fourth node P are at a low potential, the third node Q and the second node K are all at a high potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0114] Stage 9 S9: Figure 7 , Fig.16 As shown, the drive control signal RST and the first clock signal XCK are both at a low potential, the start control signal STV, the second clock signal CK, and the leakage protection signal N[n-2] are at a high potential, the first node O and the second node K are at a low potential, the fourth node P and the third node Q are both at a high potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0115] Stage 10: Figure 7 , Fig.17 As shown, the start control signal STV, the drive control signal RST, the second clock signal CK, and the leakage protection signal N[n-2] are all at a low potential, the first clock signal XCK is at a high potential, the first node O and the fourth node P are at a high potential, the third node Q and the second node K are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a low potential.

[0116] Stage 11 S11: Figure 7 , Fig.18As shown, the start control signal STV, the drive control signal RST, the first clock signal XCK, and the leakage protection signal N[n-2] are all at a low potential, the second clock signal CK is at a high potential, the fourth node P is at a low potential, the first node O, the third node Q, and the second node K are at a high potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0117] It needs to be explained that Figures 8 to 18 The “cross” in the figure indicates that the transistor covered by it is in the cut-off state, and the transistor not covered by the “cross” is in the on state.

[0118] since Figure 7 It can be seen that the N-th level positive pulse gate driving signal Nout[N] has a first positive pulse and a second positive pulse in sequence in one frame; the N-th level negative pulse gate driving signal Pout[N] has a first negative pulse in one frame.

[0119] In one frame, a duration of the second positive pulse is longer than a duration of the first negative pulse, and a duration of the first negative pulse is within a duration of the second positive pulse.

[0120] Fig.19 for Figure 3 The schematic diagram of the structure of the cascade connection between different stages of the gate driving circuit is shown, wherein the first stage circuit 101, the second stage circuit 102, the third stage circuit 103, the fourth stage circuit 104, the fifth stage circuit 105, the sixth stage circuit 106, etc. are arranged in sequence from top to bottom. The first clock line is electrically connected to each stage circuit respectively, and the second clock line is also electrically connected to each stage circuit respectively.

[0121] The first-stage circuit 101 outputs the corresponding first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1] through the first-stage negative pulse gate drive line and the first-stage positive pulse gate drive line respectively.

[0122] The second-stage circuit 102 outputs the corresponding second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2] through the second-stage negative pulse gate drive line and the second-stage positive pulse gate drive line respectively.

[0123] The third-stage circuit 103 outputs corresponding third-stage negative pulse gate drive signal Pout[3] and third-stage positive pulse gate drive signal Nout[3] through the third-stage negative pulse gate drive line and the third-stage positive pulse gate drive line respectively.

[0124] The fourth-stage circuit 104 outputs the corresponding fourth-stage negative pulse gate drive signal Pout[4] and fourth-stage positive pulse gate drive signal Nout[4] through the fourth-stage negative pulse gate drive line and the fourth-stage positive pulse gate drive line respectively.

[0125] The fifth-stage circuit 105 outputs the corresponding fifth-stage negative pulse gate drive signal Pout[5] and fifth-stage positive pulse gate drive signal Nout[5] through the fifth-stage negative pulse gate drive line and the fifth-stage positive pulse gate drive line respectively.

[0126] The sixth stage circuit 106 outputs the corresponding sixth stage negative pulse gate drive signal Pout[6] and sixth stage positive pulse gate drive signal Nout[6] through the sixth stage negative pulse gate drive line and the sixth stage positive pulse gate drive line. The other stage circuits can be deduced in the same way.

[0127] The input end (IN) of the input module 10 in the first-stage circuit 101 is electrically connected to the start control line to access the start control signal STV. The input ends (IN) of the input modules 10 in other stage circuits are all connected to the positive pulse gate drive signal of the previous stage. For example, the input end (IN) of the input module 10 in the second-stage circuit 102 is connected to the first-stage positive pulse gate drive signal Nout[1], the input end (IN) of the input module 10 in the third-stage circuit 103 is connected to the second-stage positive pulse gate drive signal Nout[2], the input end (IN) of the input module 10 in the fourth-stage circuit 104 is connected to the third-stage positive pulse gate drive signal Nout[3], the input end (IN) of the input module 10 in the fifth-stage circuit 105 is connected to the fourth-stage positive pulse gate drive signal Nout[4], and the input end (IN) of the input module 10 in the sixth-stage circuit 106 is connected to the fifth-stage positive pulse gate drive signal Nout[5]. Others can be deduced in turn. It can be understood that multiple stage circuits can also be cascaded in other number of intervals, which is not described in this application.

[0128] The control end of the second drive control module 70 (transistor T8) in the fifth-stage circuit 105 is connected to the third-stage positive pulse gate drive signal Nout[3], and the control end of the second drive control module 70 in the sixth-stage circuit 106 is connected to the fourth-stage positive pulse gate drive signal Nout[4], and the same can be said for other purposes. X can also be 3, 4, 5, 6, 7, etc., and X is taken as 2 for example.

[0129] It should be noted that since the output ends of some stage circuits are connected to virtual pixels or are suspended, the output ends of the Nth stage circuit are not connected to the Nth row of pixel circuits. Instead, the number of rows of connected pixel circuits needs to be determined based on the number of stage circuits connected to virtual pixels or suspended.

[0130] Fig. 20 The above figure is a schematic diagram of the structure of the display panel in the traditional technology, and on the left side of the display area (AA area) (non-display area or border area), gate driving circuits for providing the light-emitting control signal EM, the gate driving signal Nscan1, and the gate driving signal Pscan are respectively arranged, and on the right side of the display area (AA area) (non-display area or border area), gate driving circuits for providing the gate driving signal Pscan, the gate driving signal Nscan2, and the gate driving signal Pscan2 are respectively arranged.

[0131] Among them, each gate drive signal Pscan drives a row of pixel circuits. The working modes of the gate drive signal Nscan1 and the gate drive signal Nscan2 are also the same as the gate drive signal Pscan, but one gate drive signal Nscan1 / gate drive signal Nscan2 needs to drive two rows of pixel circuits. In the actual working process, in order to achieve a narrower border, the gate drive circuit for outputting the gate drive signal Nscan1 and the gate drive circuit for outputting the gate drive signal Nscan2 are both set to single-sided drive, however, this will cause the driving capability of the two gate drive circuits to deteriorate and the power consumption will also increase.

[0132] In view of this, this embodiment will Figure 3 The gate drive circuit shown is set up as Fig. 20 The bilateral drive shown in the figure below is to set a Figure 3 The gate drive circuit in the circuit is configured to input corresponding gate drive signals from both ends of each gate drive line at the same time. This not only improves the driving capability of the Nth level negative pulse gate drive signal Pout[N] and the positive pulse gate drive signal Nout, but also reduces power consumption and the space occupied by the frame, which is conducive to the development of a narrower frame solution.

[0133] The positive pulse gate drive signal Nout includes the Nth level positive pulse gate drive signal Nout[N] and the NLth level positive pulse gate drive signal Nout[NL]. Wherein, L can be an integer greater than or equal to 1, for example, 2, 3, 4, 5, 6, etc.

[0134] In one of the embodiments, the present embodiment provides a display panel, which includes the gate driving circuit and pixel circuit in at least one of the above-mentioned embodiments, and a row of pixel circuits is electrically connected to the Nth level positive pulse gate driving line and the Nth level negative pulse gate driving line.

[0135] It can be understood that, since the display panel provided in this embodiment includes the gate driving circuit in at least one of the above embodiments, it can also be electrically connected to the second node K through the voltage stabilizing module 40. The voltage stabilizing module 40 controls the potential of the fourth node P according to the potential of the second node K, and maintains the potential of the second node K. Therefore, when the clock signal is low-frequency, the potential of the second node K will not drop due to leakage, and the potential of the second node K can be maintained. Therefore, the gate driving circuit provided in this embodiment can reduce the power consumption of the gate driving circuit by reducing the frequency of the clock signal, and display abnormality will not occur, thereby solving the problem in the related art that the reduction of the clock signal frequency will cause the stage circuit output to be abnormal, resulting in the display problem of the display panel.

[0136] Fig.21 for Fig. 20 The schematic diagram of the structure of the pixel circuit in the display panel shown in FIG. 1 shows that, Figure 3 The gate drive circuit shown can be Fig.21 The pixel circuit shown provides a corresponding Nth level positive pulse gate driving signal Nout[N], a NLth level positive pulse gate driving signal Nout[NL] and an Nth level negative pulse gate driving signal Pout[N].

[0137] Fig.21 The pixel circuit shown may include at least one of a write transistor T2P, a drive transistor T1P, a first light emission control transistor T5P, a second light emission control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light emitting device D1, a storage capacitor Cst, and a bootstrap capacitor Cboost.

[0138] The first power line is electrically connected to the first electrode of the first light-emitting control transistor T5P and one end of the storage capacitor Cst, the second electrode of the first light-emitting control transistor T5P is electrically connected to the first electrode of the driving transistor T1P and the first electrode of the writing transistor T2P, the second electrode of the driving transistor T1P is electrically connected to the first electrode of the compensation transistor T3P and the first electrode of the second light-emitting control transistor T6P, the second electrode of the second light-emitting control transistor T6P is electrically connected to the first electrode of the second initialization transistor T7P and the anode of the light-emitting device D1, and the cathode of the light-emitting device D1 is electrically connected to the second power line. The light-emitting control line is electrically connected to the gate of the first light-emitting control transistor T5P and the gate of the second light-emitting control transistor T6P. The second electrode of the writing transistor T2P is electrically connected to the data line, and the gate of the writing transistor T2P is electrically connected to the Nth level negative pulse gate drive line (first gate drive line) and one end of the bootstrap capacitor Cboost. The second electrode of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P is electrically connected to the third gate drive line. The second pole of the compensation transistor T3P is electrically connected to the gate of the driving transistor T1P, and the gate of the compensation transistor T3P is electrically connected to the N-th level positive pulse gate drive line (the second gate drive line). The gate of the driving transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor Cboost, and the first pole of the first initialization transistor T4P. The second pole of the first initialization transistor T4P is electrically connected to the first initialization line, and the gate of the first initialization transistor T4P is electrically connected to the NL-th level positive pulse gate drive line (the second gate drive line). The first pole of the third initialization transistor T8P is electrically connected to the first pole of the driving transistor T1P, the second pole of the third initialization transistor T8P is electrically connected to the third initialization line, and the gate of the third initialization transistor T8P shares the third gate drive line with the gate of the second initialization transistor T7P.

[0139] It should be noted that the second initialization line may also be replaced by the first initialization line, which can reduce one wiring required for the pixel circuit and is beneficial to increase the density of the pixel circuit in the display panel.

[0140] The first electrode may be one of the source electrode and the drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. For example, when the first electrode is the source electrode, the second electrode is the drain electrode; or when the first electrode is the drain electrode, the second electrode is the source electrode.

[0141] Among them, the first power line is used to transmit the positive power signal VDD, the second power line is used to transmit the negative power signal VSS, and the potential of the positive power signal VDD is higher than the potential of the negative power signal VSS. The data line is used to transmit the data signal Data. The light control line is used to transmit the light control signal EM. The first initialization line is used to transmit the first initialization signal Vi1. The second initialization line is used to transmit the second initialization signal. The third initialization line is used to transmit the third initialization signal Vi3. The first gate drive line is used to transmit the Nth level negative pulse gate drive signal Pout[N]. The Nth level positive pulse gate drive line (second gate drive line) is used to transmit the Nth level positive pulse gate drive signal Nout[N]. The NLth level positive pulse gate drive line (second gate drive line) is used to transmit the NLth level positive pulse gate drive signal Nout[NL]. The third gate drive line is used to transmit the gate drive signal Pscan2.

[0142] Fig.21 The working timing of the pixel circuit in one frame is as follows: Fig. 22 As shown, under the common drive of the Nth level negative pulse gate drive signal Pout[N], the gate drive signal Pscan2, the NLth level positive pulse gate drive signal Nout[NL], the Nth level positive pulse gate drive signal Nout[N] and the light emitting control signal EM, Fig.21 The pixel circuit shown can perform normal display.

[0143] Among them, the Nth level negative pulse gate drive signal Pout[N], the NLth level positive pulse gate drive signal Nout[NL], and the Nth level positive pulse gate drive signal Nout[N] can be obtained by Figure 3 The gate drive circuit shown is provided.

[0144] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0145] The gate drive circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of cascaded stage circuits, and the stage circuits include: An input module, the input module receives an initial signal or a level transmission signal output by other level circuits to control the voltage of the second node; a first output module, wherein the first output module outputs a first gate driving signal according to the potential of the third node and the potential of the fourth node; a second output module, wherein the second output module outputs a second gate driving signal according to the potential of the second node; a voltage stabilizing module, the voltage stabilizing module being electrically connected to the first power line and the second power line, and transmitting the voltage on the first power line or the voltage on the second power line to the second node according to the voltage of the fourth node; a first driving control module, wherein the first driving control module controls the voltage of the fourth node according to the voltage of the second node; Among them, the voltage stabilization module includes a first transistor, the gate of the first transistor is used to receive a clock signal, the working mode of the gate drive circuit includes a low power consumption mode, when the gate drive circuit is in the low power consumption mode, the clock signal is a first voltage, and the first voltage turns on the first transistor.

2. The gate driving circuit according to claim 1, characterized in that: The first transistor is an N-channel thin film transistor, and the first voltage is a high level.

3. The gate driving circuit according to claim 2, characterized in that: The first transistor is a dual-gate indium gallium zinc oxide thin film transistor, and a first gate of the first transistor and a second gate of the first transistor are both used to receive the clock signal.

4. The gate driving circuit according to claim 2, characterized in that: The voltage stabilizing module further includes a second transistor, a gate of the second transistor is electrically connected to the fourth node, one of a source or a drain of the second transistor is electrically connected to the first power line, the other of the source or the drain of the second transistor is electrically connected to one of the source or the drain of the first transistor, and the other of the source or the drain of the first transistor is electrically connected to the second node; The first transistor and the second transistor have different channel types.

5. The gate driving circuit according to claim 4, characterized in that: When the gate driving circuit is in a low power consumption mode, the voltage at the fourth node turns on the second transistor to transmit the voltage on the first power line to one of the source or the drain of the first transistor.

6. The gate driving circuit according to claim 1, characterized in that: The voltage stabilizing module also includes a third transistor, one of the source or the drain of the third transistor is electrically connected to the second power line, the other of the source or the drain of the third transistor is electrically connected to the second node, and the gate of the third transistor is connected to the fourth node.

7. The gate driving circuit according to claim 6, characterized in that: When the gate driving circuit is in a low power consumption mode, the voltage of the fourth node turns off the third transistor.

8. The gate driving circuit according to claim 7, characterized in that: The third transistor is a dual-gate indium gallium zinc oxide thin film transistor, and a first gate of the third transistor and a second gate of the third transistor are both electrically connected to the fourth node.

9. The gate driving circuit according to claim 1, characterized in that: The stage circuit further includes: a reset module, which controls the voltage of the second node according to a reset signal.

10. The gate driving circuit according to claim 9, characterized in that: The reset module includes a fourth transistor, one of a source or a drain of the fourth transistor is connected to the first power line, the other of the source or the drain of the fourth transistor is electrically connected to the second node, and a gate of the fourth transistor receives the reset signal.

11. The gate driving circuit according to claim 10, characterized in that: In a first frame of operation of the gate driving circuit, the reset signal controls the fourth transistor to be turned on before a pulse of the start signal arrives, so that the voltage on the first power line is transmitted to the second node.

12. The gate driving circuit according to claim 2, characterized in that: The first driving control module is electrically connected to the second node and the fourth node, and the first driving control module outputs a voltage that is inversely proportional to the voltage of the second node to the fourth node.

13. The gate driving circuit according to claim 12, characterized in that: The first drive control module comprises: a fifth transistor and a sixth transistor, wherein one of a source or a drain of the fifth transistor is electrically connected to the first power line, the other of the source or the drain of the fifth transistor is electrically connected to the fourth node, one of a source or a drain of the sixth transistor is electrically connected to the third power line, the other of the source or the drain of the sixth transistor is electrically connected to the fourth node, and a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the second node; Wherein, the fifth transistor is a P-channel thin film transistor, and the sixth transistor is an N-channel thin film transistor.

14. The gate driving circuit according to claim 13, characterized in that: The sixth transistor is a double-gate transistor, and a first gate of the sixth transistor and a second gate of the sixth transistor are both electrically connected to the second node.

15. The gate driving circuit according to claim 14, characterized in that: When the gate driving circuit is in a low power consumption mode, the sixth transistor is turned on to output the voltage on the third power line to the fourth node.

16. The gate driving circuit according to any one of claims 1 to 14, characterized in that: The stage circuit further comprises: A second drive control module, the second drive control module is electrically connected between the second node and the third node, the control end of the second drive control module is electrically connected to the drive control line, and the second drive control module is used to control the conduction between the second node and the third node.

17. The gate driving circuit according to claim 16, characterized in that: The second driving control module is used to eliminate the first pulse of the second node appearing in a frame, and retain the second pulse of the second node appearing in the same frame.

18. A display panel, characterized in that: The display panel comprises: a pixel circuit including a write transistor for controlling input of a data signal and a compensation transistor for controlling input of the data signal to a gate of a drive transistor; and According to the gate drive circuit as described in any one of claims 1 to 17, the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

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