Display panel and display device

Abstract

According to the display panel and the display device, the display panel comprises a plurality of sub-pixels and a plurality of data lines, the sub-pixels comprise the first sub-pixels and the second sub-pixels, the first sub-pixels are electrically connected with the first data lines, and the second sub-pixels are electrically connected with the second data lines. The first data line and the second data line receive data signals in sequence, and the time when the first data line receives the data signals is at least partially overlapped with the time when the second data line is reset. According to the embodiment of the invention, the idle degree of the second data line between the start of receiving the data signal by the first data line and the start of receiving the data signal by the second data line is reduced, and preparation is made for prolonging the data writing time of the first sub-pixel and the second sub-pixel. The reset of the second data line can be completed in advance when the first data line receives the data signal, and the data write-in modules in the first sub-pixel and the second sub-pixel can be started in advance, so that the data write-in time of the first sub-pixel and the second sub-pixel can be prolonged.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Before the sub-pixels in the display panel perform the light-emitting stage, a data writing stage needs to be performed first. During the data writing stage of the sub-pixels, the data line electrically connected to the sub-pixels needs to receive the data signal first, and then the pixel circuit in the sub-pixel turns on the data writing module to write the data signal into the driving transistor. Since multiple sub-pixels are electrically connected to the same data line, the data line sequentially receives the data signals required by the sub-pixels in different rows. When the data line starts to receive the data signals required by the sub-pixels in the next row, the data line also includes the data signals required by the sub-pixels in the previous row. Therefore, there needs to be a certain time gap between the start of the data writing module in the pixel circuit in the sub-pixel and the start of the data line receiving the data signal, so that the new data signal updates the data line to the data signal state required by the sub-pixels in the current row.

[0003] Usually, multiple pixel circuits in multiple sub-pixels distributed in the same row in the display panel are electrically connected to the same data writing module control signal line. When the data writing module control signal line transmits an enable signal, multiple sub-pixels all start to receive data signals. However, if the data line electrically connected to a certain sub-pixel is not reset to the latest data signal when the data writing module is turned on, it may cause the data signal required by the sub-pixel in the previous row to be charged into the sub-pixel in the current row, so that the sub-pixel in the current row cannot receive accurate data signals. To avoid this situation, the data lines electrically connected to the sub-pixels in the same row are usually reset and then the data writing module control signal line transmits the enable signal to ensure that the data signal transmitted by the data line is accurate. However, when a multiplexer is included in the display panel, the data signals of the data lines electrically connected to the multiple sub-pixels all come from the same source data line and the multiple data lines electrically connected to the same source data line need to receive different data signals in sequence, so that the data writing module control signal line needs to wait for the source data line to reset the last data line electrically connected to it before transmitting the enable signal, thereby ensuring that the data signal received by the sub-pixel is accurate. A large amount of waiting time causes the actual opening time of the data writing module of each row of sub-pixels to be compressed. Insufficient writing time of the data signal of each sub-pixel can easily lead to inaccurate data signals received by the driving transistor and greatly increase the time cost. Summary of the invention

[0004] In view of this, the present application provides a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising a plurality of sub-pixels and a plurality of data lines, wherein the data lines are electrically connected to the sub-pixels; the sub-pixels include first sub-pixels and second sub-pixels alternately arranged along a first direction, the data lines include first data lines and second data lines, the first sub-pixels are electrically connected to the first data lines, and the second sub-pixels are electrically connected to the second data lines;

[0006] The first data line and the second data line receive the data signal in sequence, and the time when the first data line receives the data signal and the time when the second data line is reset at least partially overlap.

[0007] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0008] In the embodiment of the present application, the time when the first data line receives the data signal is set to at least partially overlap with the time when the second data line is reset, which is conducive to reducing the idleness of the second data line between the time when the first data line starts to receive the data signal and the time when the second data line starts to receive the data signal, and improving the working compactness between the first data line and the second data line, so as to prepare for extending the data writing time of the first sub-pixel and the second sub-pixel. In addition, it is conducive to completing the resetting of the second data line in advance when the first data line receives the data signal, and is conducive to opening the data writing modules in the first sub-pixel and the second sub-pixel in advance, thereby extending the data writing time of the first sub-pixel and the second sub-pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0010] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application;

[0011] Figure 2 A timing diagram of sub-pixel operation in a related technology provided in an embodiment of the present application;

[0012] Figure 3 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0013] Figure 4 A working timing diagram of a sub-pixel provided in an embodiment of the present application;

[0014] Figure 5 A schematic plan view of another display panel provided in an embodiment of the present application;

[0015] Figure 6 A schematic plan view of another display panel provided in an embodiment of the present application;

[0016] Figure 7 A schematic plan view of another display panel provided in an embodiment of the present application;

[0017] Figure 8 A schematic plan view of another display panel provided in an embodiment of the present application;

[0018] Fig. 9 A working timing diagram of another sub-pixel provided in an embodiment of the present application;

[0019] Fig.10 A schematic plan view of another display panel provided in an embodiment of the present application;

[0020] Fig.11 A schematic plan view of another display panel provided in an embodiment of the present application;

[0021] Fig.12 A schematic diagram of a comparative structure of a driving transistor and a data writing transistor provided in an embodiment of the present application;

[0022] Fig.13 A schematic plan view of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0024] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0025] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0026] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0027] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0028] It should be understood that although the terms first, second, etc. may be used to describe sub-pixels, data lines, gate switches, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish sub-pixels, data lines, gate switches, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first sub-pixel may also be referred to as the second sub-pixel, and similarly, the second sub-pixel may also be referred to as the first sub-pixel. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0029] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application, Figure 2 A timing diagram of a sub-pixel operation in a related art provided in an embodiment of the present application, Figure 3 A schematic diagram of a pixel circuit provided in an embodiment of the present application is shown in FIG. Figure 4 A sub-pixel operation timing diagram provided in an embodiment of the present application.

[0030] The present application embodiment provides a display panel 100, such as Figure 1 As shown, the display panel 100 includes a plurality of sub-pixels 10 and a plurality of data lines 20, and the data lines 20 are electrically connected to the sub-pixels 10. The sub-pixels 10 include first sub-pixels 101 and second sub-pixels 102 that are alternately arranged along a first direction X1. In the embodiment of the present application, the first direction X1 is taken as the row direction, and the first sub-pixels 101 and the second sub-pixels 102 are located in the same row as an example for explanation. The data lines 20 include a first data line 201 and a second data line 202, the first sub-pixel 101 is electrically connected to the first data line 201, and the second sub-pixel 102 is electrically connected to the second data line 202. Among them, the first data line 201 and the second data line 202 receive the data signal Vdata in sequence.

[0031] like Figure 2 As shown, in the related art, when multiple sub-pixels 10 located in the same row enter the data writing stage E1, the time when the first data line 201 receives the data signal Vdata and the time when the second data line 202 receives the data signal Vdata both include the reset time t1 and the remaining writing time t2. The reset time t1 mainly completes the work of the latest data signal Vdata covering the data signal Vdata written in the previous row, and the remaining writing time t2 mainly completes the continuous writing of the latest data signal Vdata to the data line. Figure 3As shown, since the first data line 201 and the second data line 202 need to receive data signals in sequence, and the first sub-pixel 101 and the second sub-pixel 102 are located in the same row, the first data line 201 needs to wait for at least the second data line 202 to complete the reset time t1 after receiving the data signal Vdata, and the data writing module 200A in the pixel circuit 200 in the first pixel 101 and the second sub-pixel 102 can be turned on. Assuming that the total time length of the multiple sub-pixels 10 located in the same row in the data writing phase E1 is time1, at this time, the time for the driving transistor Md in the pixel circuit 200 to write the data signal Vdata on the first data line 201 and the second data line 202 is only time1-2*t1-t2.

[0032] It should be noted that in the embodiment of the present application, the first control signal S1 is used as a control signal to control whether the first data line 201 can receive the data signal Vdata, the second control signal S2 is used as a control signal to control whether the second data line 202 can receive the data signal Vdata, and the third control signal S3 is used as a control signal to control whether the data writing module 200A in the pixel circuit 200 is turned on. In addition, the first control signal S1, the second control signal S2, and the third control signal S3 are enabled when they are at a low level.

[0033] As can be known from the above related technologies, after the first data line 201 electrically connected to the first sub-pixel 101 receives the data signal Vdata, the pixel circuit 200 in the first sub-pixel 101 cannot start receiving the data signal Vdata immediately, but waits at least for the second data line 202 electrically connected to the second sub-pixel 101 to complete the reset time t1 when receiving the data signal Vdata. In this way, the first sub-pixel 101 and the second sub-pixel 102 have less time to receive the data signal Vdata before the next row of sub-pixels enters the data writing phase E1, which is not conducive to correctly writing the data signal Vdata into the sub-pixel 10.

[0034] In order to extend the time for the sub-pixel 10 to receive the data signal and ensure the accuracy of the data signal received by the sub-pixel 10, Figure 4 As shown, in the embodiment of the present application, the time when the first data line 201 receives the data signal Vdata is set to at least partially coincide with the time when the second data line 202 is reset. Figure 2As shown, in the related art, when the first data line 201 electrically connected to the first sub-pixel 101 receives the data signal Vdata, the second data line 202 electrically connected to the second sub-pixel 102 is in the waiting stage, and the second sub-pixel 102 is not turned on at this time and the second data line 202 does not receive the data signal Vdata. Therefore, the embodiment of the present application proposes to reset the second data line 202 within the time when the first data line 201 receives the data signal Vdata, which is equivalent to resetting the second data line 202 in advance. In this way, after the first data line 201 completes the stage of receiving the data signal Vdata, there is no need to wait for the reset of the second data line 202, and the first sub-pixel 101 and the second sub-pixel 102 can be turned on to receive the data signal Vdata at the same time, so that it is possible to extend the data writing time of the first sub-pixel 101 and the second sub-pixel 102.

[0035] For example, Figure 4 As shown, when the first data line 201 starts to receive the data signal Vdata, the second data line 202 is reset, and after the first data signal line 201 and the second data signal line 202 have passed the reset time t1, the data writing modules 200A in the first sub-pixel 101 and the second sub-pixel 102 are able to be simultaneously turned on, so that the data writing time of the first sub-pixel 101 is extended to (t ime1-t1), and the data writing time of the second sub-pixel 102 is extended to (t ime1-t1-t2).

[0036] In the embodiment of the present application, the time when the first data line 201 receives the data signal Vdata is set to at least partially overlap with the time when the second data line 202 is reset, which is conducive to reducing the idleness of the second data line 202 between the first data line 201 starting to receive the data signal Vdata and the second data line 202 starting to receive the data signal Vdata, and improving the working compactness between the first data line 201 and the second data line 202, so as to prepare for extending the data writing time of the first sub-pixel 101 and the second sub-pixel 102. In addition, it is conducive to completing the resetting of the second data line 202 in advance when the first data line 201 receives the data signal Vdata, and is conducive to opening the data writing module 200A in the first sub-pixel 101 and the second sub-pixel 102 in advance, thereby extending the data writing time of the first sub-pixel 101 and the second sub-pixel 102.

[0037] In one embodiment of the present application, continue to refer to Figure 4As shown, the time when the first sub-pixel 101 receives the data signal Vdata is set to at least partially overlap with the time when the second data line 202 receives the data signal Vdata. When the first sub-pixel 101 starts to receive the data signal Vdata, since the first sub-pixel 101 and the second sub-pixel 102 are located in the same row, the data writing module 200A in the second sub-pixel 102 is also turned on at this time. In addition, the reset work of the second data line 202 is completed before the first sub-pixel 101 starts to receive the data signal Vdata. Then, the time when the second data line 202 receives the data signal Vdata is at least partially overlapped with the time when the first sub-pixel 101 receives the data signal Vdata, which is conducive to writing the data signal Vdata into the second sub-pixel 102 while the second data line 202 receives the data signal Vdata, thereby extending the time length of writing the data signal Vdata into the second sub-pixel 102.

[0038] Figure 5 A schematic plan view of another display panel provided in an embodiment of the present application.

[0039] In one embodiment of the present application, Figure 4 , Figure 5 As shown, the display panel 100 further includes a reset module 30, which is electrically connected to the second data line 202 and is used to reset the second data line 202. Optionally, the fourth control signal S4 is set as a control signal for controlling the reset module 30 to start, and the fourth control signal S4 is a valid signal when it is at a low level.

[0040] In the related art, the reset of the first data line 201 and the second data line 202 is that the source data line transmits the data signal Vdata required by the sub-pixel 10 in the current row to the data line 20 for a period of time, thereby covering the data signal Vdata transmitted by the data line 20 to the sub-pixel 10 in the previous row. The same source data line usually transmits the data signal Vdata required by the first sub-pixel 101 and the second sub-pixel 102 in sequence during operation. When the first data line 101 receives the data signal Vdata, the source data line cannot transmit the data signal Vdata required by the second data line 102 at the same time. This results in the need to wait until the first data line 201 receives the data signal Vdata before resetting the second data line 201, thereby delaying the start time of the first sub-pixel 101 and the second sub-pixel 102 receiving the data signal Vdata.

[0041] In the embodiment of the present application, the display panel 100 is provided with a reset module 30. When the first data line 201 receives the data signal Vdata, the fourth control signal S4 transmits an enable signal to control the reset module 30 to be turned on, and is used to reset the second data line 202. The embodiment of the present application uses an independent module to reset the second data line 202, which is conducive to solving the situation that the first data line 201 and the second data line 202 queue up to use the source data line for reset, and is conducive to using the reset module 30 to reset the second data line 202 while the first data line 201 receives the data signal Vdata, and is conducive to realizing the action of resetting the second data line 202 in advance, so as to advance the time when the first sub-pixel 101 and the second sub-pixel 102 start to receive the data signal Vdata, which is conducive to extending the data writing time of the first sub-pixel 101 and the second sub-pixel 102, and ensuring the accuracy of the data signal Vdata received by the first sub-pixel 101 and the second sub-pixel 102, thereby improving the accuracy of the light emitting brightness of the sub-pixel 10, and improving the display effect of the display panel 100.

[0042] Figure 6 A schematic plan view of another display panel provided in an embodiment of the present application.

[0043] In one embodiment of the present application, Figure 5 , Figure 6 As shown, the reset module 30 includes a first transistor T1, a first electrode of the first transistor T1 receives a reset signal Vref, and a second electrode is electrically connected to an input terminal 202A of the second data line 202. In the embodiment of the present application, the first transistor T1 is described as a P-type transistor.

[0044] In the embodiment of the present application, the reset module 30 includes a first transistor T1, which is conducive to using the first transistor T1 to complete the reset of the second data line 202. Optionally, when the first data line 201 starts to receive the data signal Vdata, the fourth control signal S4 transmits an enable signal to control the first transistor T1 to turn on. This allows the first transistor T1 to transmit the reset signal Vref to the second data line 202 to reset the second data line 202. Figure 4 As shown, the duration of the first transistor T1 resetting the second data line 202 can be close to the duration of the first data line 201 receiving the data signal Vdata. Because at this time the source data line only transmits the data signal Vdata required by the first sub-pixel 101, it is helpful to reduce the time when the second data line 202 is in an idle state between the time when the first data line 201 starts to receive the data signal Vdata and the time when the second data line 202 starts to receive the data signal Vdata, and setting the first transistor T1 to be turned on for a longer time is conducive to better completion of the resetting work of the second data line 202.

[0045] It should be noted that when the data writing module 200A in the first sub-pixel 101 and the second sub-pixel 102 starts after the first data line 201 completes the reset time t1, the second sub-pixel 102 receives the reset signal Vref. The potential of the reset signal Vref proposed in the embodiment of the present application is relatively low, and the process of the second data line 202 starting to receive the data signal Vdata and writing the data signal Vdata into the pixel circuit 200 can be completed smoothly, and it can be ensured that the second sub-pixel 102 can receive the accurate data signal Vdata.

[0046] In one embodiment of the present application, continue to refer to Figure 5 , Figure 6 As shown, the first electrode of the first transistor T1 is electrically connected to one of the ground terminal GND and the light-emitting test terminal V1. In the display panel 100, the ground terminal GND is a common signal terminal. When the first electrode of the first transistor T1 is electrically connected to the ground terminal GND, it is beneficial to smoothly release the signal on the second data line 202 to the ground after the first transistor T1 is turned on, thereby completing the reset of the second data line 202. In addition, using the ground terminal GND as the reset signal terminal is beneficial to reducing the number of signal terminals in the display panel 100.

[0047] The light-emitting test terminal V1 is a port used to detect whether the light-emitting device 300 can emit light normally during the preparation of the display panel 100. During the test, a virtual data signal can be set at the light-emitting test terminal V1 to drive the light-emitting device 300 to emit light. After the detection work is completed, there may be some idle light-emitting test terminals V1 retained on the display panel 100, and the light-emitting test terminal V1 can be used as a port for outputting the reset signal Vref, which is beneficial to saving the number of signal terminals prepared in the display panel 100 and reducing the preparation cost of the display panel 100. In addition, the size of the output reset signal Vref can be flexibly adjusted by using the light-emitting test terminal V1, which is beneficial to improving the applicability of the reset module 30.

[0048] In one embodiment of the present application, continue to refer to Figure 4 As shown, the working process of the sub-pixel 10 includes a data writing phase E1 and a light emitting phase E2, wherein the data writing phase E1 is performed before the light emitting phase E2. After the sub-pixel 10 ends the data writing phase E1, the pixel circuit 200 in the sub-pixel 10 receives a valid light emitting control signal EMI T, so that the pixel circuit 200 generates a light emitting driving current and transmits it to the light emitting device 300, thereby completing the display of the sub-pixel 10.

[0049] The data writing phase E1 includes:

[0050] In the first charging sub-phase E11 , the first data line 201 receives the data signal Vdata. In the first charging sub-phase E11 , the source data line transmits the data signal Vdata required by the first sub-pixel 101 to the first data line 201 .

[0051] Reset sub-stage E12: The reset sub-stage E12 is performed simultaneously with the first charging sub-stage E11. The reset module 30 transmits a reset signal Vref to the second data line 202, which is beneficial to complete the reset of the second data line 202 in advance.

[0052] The data writing sub-phase E13 is performed after the first charging sub-phase E11 starts for the first time period t3. At this time, the data writing module 200A of the pixel circuit 200 in the first sub-pixel 101 and the second sub-pixel 102 receives the enable signal transmitted by the data writing control signal line SCAN1, and the data writing module 200A is turned on. The first sub-pixel 101 starts to receive the data signal Vdata transmitted by the first data line 201, and the second sub-pixel 102 starts to receive the reset signal Vref transmitted by the second data line 202.

[0053] The second charging sub-stage E14 and the second resetting sub-stage E14 are performed after the first charging sub-stage E11 is completed, and the source data line at this time starts to transmit the data signal Vdata required by the second sub-pixel 102. At this time, the second data line 202 receives the data signal Vdata, and the data writing module 200A of the pixel circuit 200 in the second sub-pixel 102 can remain turned on, and the second sub-pixel 102 receives the data signal Vdata transmitted by the second data line 202.

[0054] Among them, the data writing sub-stage E13 is carried out some time after the start of the first charging sub-stage E11, and lasts until the next row of sub-pixels 10 starts the first charging sub-stage E11 after the end of the second charging sub-stage E14, so as to avoid writing the data signal Vdata required by the next row of sub-pixels 10 into the sub-pixels 10 in this row.

[0055] In the embodiment of the present application, the reset sub-stage E12 is set to be performed simultaneously with the first charging sub-stage E11, and the data writing sub-stage E13 is advanced to be performed between the start and end of the first charging sub-stage E11, which is beneficial to extend the time for which the data signal Vdata is written to the first sub-pixel 101 and the second sub-pixel 102, and improve the accuracy of the data signal Vdata received by the sub-pixel 10.

[0056] In one embodiment of the present application, continue to refer to Figure 4As shown, the first time period t3 is used to reset the first data line 101. The above embodiment mentioned that the time for the first data line 101 to receive the data signal Vdata includes the reset time t1 and the remaining writing time t2. The first time end t3 described here is the same as the reset time t1, and both are the time for resetting the first data line 101. During the operation of the display panel 100, it is necessary to complete the reset of the first data line 201 and the second data line 202 before starting the data writing sub-phase E13, which is conducive to ensuring the accuracy of the data signals received by the first sub-pixel 101 and the second sub-pixel 102.

[0057] Figure 7 A schematic plan view of another display panel provided in an embodiment of the present application.

[0058] In one embodiment of the present application, Figure 7 As shown, the display panel 100 also includes a multiplexer circuit 40, which is used to transmit the data signal Vdata for the first data line 201 and the second data line 202 in time-sharing. The multiplexer circuit 40 at least includes a first selection switch 401 and a second selection switch 402, wherein the first end of the first selection switch 401 is electrically connected to the source data line Sdata, and the second end is electrically connected to the input end 101A of the first data line 201, and the first end of the second selection switch 402 is electrically connected to the source data line Sdata, and the second end is electrically connected to the input end 202A of the second data line 202. In combination with the above content, it can be set in the embodiment of the present application that the first control signal S1 controls whether the first selection switch 401 is turned on, and the second control signal S2 controls whether the second selection switch 402 is turned on. The embodiment of the present application is described by taking the example that two adjacent first data lines 201 and the second data line 201 are electrically connected to the same source data line Sdata. Optionally, the first selection switch 401 and the second selection switch 402 are both switch transistors. The transistors proposed in the embodiments of the present application are all described by taking P-type transistors as examples.

[0059] The reset module 30 is electrically connected between the input terminal 202A of the second data line 202 and the second end of the second selection switch 402. When the reset module 30 is turned on, the reset signal Vref is directly transmitted to the second data line 202, which is beneficial to avoid conflicts between the signal transmitted by the reset module 30 and the signal transmitted by the source data line.

[0060] In the embodiment of the present application, a multi-way selection circuit 40 is used to transmit the data signal Vdata to the data line 20, which is beneficial to reduce the number of data signal terminals prepared in the display panel 100 and improve the space utilization rate of the display panel 100. In addition, it can be seen from the above content that when the multi-way selection circuit 40 is used in the display panel 100, it is necessary to face the situation that multiple data lines 20 electrically connected to multiple sub-pixels 10 located in the same row need to wait for the source data line Sdata to transmit the currently required data signal Vdata in turn, and the data lines 20 must be reset for a period of time before the data writing modules 200A of the pixel circuits 200 in the multiple sub-pixels 10 can be turned on. This will compress the time when the sub-pixel 10 is in the data writing sub-stage E13 due to a lot of waiting time, and the accuracy of the data signal Vdata received by the sub-pixel 10 is affected to a certain extent. In the embodiment of the present application, a reset module 30 is set, and the reset module 30 is used to cooperate with the multi-way selection circuit 40. Combined with Figure 4 As shown, when the first selection switch 401 is turned on, the source data line Sdata is connected to the first data line 101, and the data signal Vdata transmitted by the source data line Sdata resets and charges the first data line 201. At the same time, the reset module 30 is also turned on, so that the reset signal Vref is transmitted to the second data line 202, and the second data line 202 is reset. After the first data line 201 and the second data line 202 are reset, the first sub-pixel 101 and the second sub-pixel 102 located in the same row are controlled to turn on the data writing control signal line SCAN1 of the data writing module 200A to transmit the enable signal, and the first sub-pixel 101 and the second sub-pixel 102 can receive the data signal Vdata. In summary, after the display panel 100 is set to include the multiplexer circuit 40 and the reset module 30, it is beneficial to use the reset module 30 to fill the working blank time between the sub-pixels 10 in the same row, and advance the reset time of multiple sub-pixels 10, thereby providing conditions for the start time of the data writing sub-stage E13 to be advanced, and realizing the improvement of the time of the sub-pixel 10 in the data writing sub-stage E13.

[0061] Figure 8 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Fig. 9 This is another sub-pixel operation timing diagram provided in an embodiment of the present application.

[0062] For example, the multi-way selection circuit 40 proposed in the embodiment of the present application can also be as follows: Figure 8As shown, the display panel 100 also includes a plurality of sub-pixels 10 arranged along a sixth direction X6, the sixth direction X6 intersects with the first direction X1, and optionally, the sixth direction X6 is a column direction. In the embodiment of the present application, it is taken as an example that the plurality of sub-pixels 10 located in odd columns are all first sub-pixels 101, and the plurality of sub-pixels 10 located in even columns are all second sub-pixels 102. Among them, the first data line 201 for transmitting the data signal Vdata of the first sub-pixel 101 located in the same column is divided into a first sub-data line 201A and a second sub-data line 201B, the first sub-data line 201A is electrically connected to the plurality of sub-pixels located in odd rows of the first sub-pixel 101 in the same column, and the second sub-data line 201B is electrically connected to the plurality of sub-pixels located in even rows of the first sub-pixel 101 in the same column. The second data line 202 for transmitting the data signal Vdata of the second sub-pixels 102 located in the same column is divided into a third sub-data line 202A and a fourth sub-data line 202B. The third sub-data line 202A is electrically connected to multiple sub-pixels located in odd rows among the second sub-pixels 102 in the same column, and the fourth sub-data line 202B is electrically connected to multiple sub-pixels located in even rows among the second sub-pixels 102 in the same column.

[0063] Optionally, a group of first sub-data lines 201A, second sub-data lines 201B, third sub-data lines 202A, and fourth sub-data lines 202B that are electrically connected to adjacent columns of sub-pixels 10 in the first direction X1 are electrically connected to the same source data line Sdata, which helps to avoid the risk of a long waiting time when the source data line Sdata needs to sequentially transmit the data signals Vdata required by the plurality of data lines 20 when more data lines 20 are electrically connected to the same source data line Sdata, thereby improving the working efficiency of the display panel 100. In addition, the first selection switch 401 is provided to include a first sub-selection switch 401A and a second sub-selection switch 401B, the first sub-selection switch 401A controls whether the first sub-data line 201A can receive the data signal Vdata, and the second sub-selection switch 401B is used to control whether the second sub-data line 201B can receive the data signal Vdata. The second selection switch 402 is set to include a third sub-selection switch 402A and a fourth sub-selection switch 402B. The third sub-selection switch 402A controls whether the third sub-data line 202A can receive the data signal Vdata, and the fourth sub-selection switch 402B is used to control whether the fourth sub-data line 202B can receive the data signal Vdata. The first control signal S1 is set to include a first sub-control signal S11 and a second sub-control signal S12. The first sub-control signal S11 is used to control whether the first sub-selection switch 401A is turned on, and the second sub-control signal S12 is used to control whether the second sub-selection switch 401B is turned on. The second control signal S2 is set to include a third sub-control signal S21 and a fourth sub-control signal S22. The third sub-control signal S11 is used to control whether the third sub-selection switch 402A is turned on, and the fourth sub-control signal S22 is used to control whether the fourth sub-selection switch 402B is turned on.

[0064] Further, the reset module 30 is provided to include a first sub-reset module 301 and a second sub-reset module 302. Since the first sub-pixel 101 starts to receive the data signal Vdata earlier than the data line 20 electrically connected to the second sub-pixel 102, there is idle time for the operation of the second sub-pixel 102. Then, the first sub-reset module 301 is electrically connected between the third sub-data line 202A and the third sub-selection switch 402A, and the second sub-reset module 302 is electrically connected between the fourth sub-data line 202B and the fourth sub-selection switch 402B. The first sub-reset module 301 is used to reset the third sub-data line 202A, and the second sub-reset module 302 is used to reset the fourth sub-data line 202B. Optionally, the input terminals of the first sub-reset module 301 and the second sub-reset module 302 are electrically connected to the same signal terminal. The fourth control signal S4 is set to include a fifth sub-control signal S41 and a sixth sub-control signal S42. The fifth sub-control signal S41 is used to control whether the first sub-reset module 301 is turned on, and the sixth sub-control signal S42 is used to control whether the second sub-reset module 302 is turned on.

[0065] Combination Fig. 9 As shown, when the plurality of sub-pixels 10 located in the first odd-numbered row of the display panel 100 enters the data writing phase E1:

[0066] A plurality of first sub-pixels 101 located in odd-numbered columns enter the first charging sub-phase E11 , and at this time, the first sub-selection switch 401A is turned on to transmit the data signal Vdata to the first sub-data line 201A.

[0067] At the same time, a plurality of second sub-pixels 102 located in even-numbered columns enter the reset sub-phase E12, and at this time, the first sub-reset module 301 is turned on to transmit the reset signal Vref to the third sub-data line 202A.

[0068] After the first charging sub-phase E11 is performed for the first time period t3, the data writing module 200A in the sub-pixel 10 in the first odd-numbered row is controlled to receive the effective seventh sub-control signal S31, so that the first sub-pixel 101 and the second sub-pixel 102 in the first odd-numbered row both enter the data writing sub-phase E13. The third control signal S3 is set to include the seventh sub-control signal S31 and the eighth sub-control signal S81. The seventh sub-control signal S31 is used to control whether the data writing module 200A in the sub-pixel 10 in the odd-numbered row is turned on, and the eighth sub-control signal S32 is used to control whether the data writing module 200A in the sub-pixel 10 in the even-numbered row is turned on.

[0069] After the first charging sub-stage E11 ends, the second sub-pixels 102 in even-numbered columns enter the second charging sub-stage E14, when the third sub-selection switch 402A is turned on to transmit the data signal Vdata to the third sub-data line 202A. Moreover, the data signal Vdata is also transmitted to the second sub-pixels 102 at the same time.

[0070] It can be seen from the above working process that after the sub-pixels 10 in the same row enter the data writing stage E1, the first sub-data line 201A electrically connected to the first sub-pixel 101 in the odd column receives the data signal Vdata, while the third sub-data line 202A electrically connected to the second sub-pixel 102 in the even column is reset to complete the extension of the data writing sub-stage E13.

[0071] Continue to combine Fig. 9 As shown, when the plurality of sub-pixels 10 in the first even-numbered row of the display panel 100, that is, the plurality of sub-pixels 10 in the adjacent row to the plurality of sub-pixels 10 in the first odd-numbered row, enter the data writing phase E1:

[0072] A plurality of first sub-pixels 101 located in odd-numbered columns enter the first charging sub-phase E11 , and at this time, the second sub-selection switch 401B is turned on to transmit the data signal Vdata to the second sub-data line 202A.

[0073] At the same time, a plurality of second sub-pixels 102 located in even-numbered columns enter the reset sub-phase E12 , and the second sub-reset module 302 is turned on to transmit the reset signal Vref to the fourth sub-data line 202B.

[0074] After the first charging sub-stage E11 for the first time period t3, the data writing module 200A in the sub-pixel 10 in the first even row receives a valid eighth sub-control signal S32, so that the first sub-pixel 101 and the second sub-pixel 102 in the first even row both enter the data writing sub-stage E13.

[0075] After the first charging sub-stage E11 ends, the second sub-pixels 102 in even-numbered columns enter the second charging sub-stage E14, when the fourth sub-selection switch 402B is turned on to transmit the data signal Vdata to the fourth sub-data line 202B. In addition, the data signal Vdata is also transmitted to the second sub-pixels 102 at the same time.

[0076] Similarly, the sub-pixels 10 in the next odd and even rows of the display panel 100 enter the data writing phase E1 in sequence, and the running steps are similar to the working process of the sub-pixels 10 in the first odd row and the first even row mentioned above.

[0077] Fig.10A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Fig.11 A schematic plan view of another display panel provided in an embodiment of the present application.

[0078] In one embodiment of the present application, Figure 10-11 As shown, the control end of the first selection switch 401 and the control end of the reset module 30 are electrically connected to the same control signal line. It can be seen from the above embodiment that when the first selection switch 401 is turned on to transmit the data signal Vdata to the first data line 201, the reset module 30 can simultaneously transmit the reset signal Vref to the second data line 202. Therefore, the first selection switch 401 and the reset module 30 have the conditions to be turned on at the same time. In addition, the above content mentions that the first control signal S1 can control the first selection switch 401, and the fourth control signal S4 can control whether the reset module 30 is turned on. Optionally, as Fig.10 As shown, the first selection switch 401 and the reset module 30 are both electrically connected to the port of the first control signal S1. Alternatively, the first control switch 401 and the reset module 30 are both electrically connected to the port of the fourth control signal S4.

[0079] Alternatively, it can be known from the above embodiment that the first sub-control signal S11 is used to control the first sub-selection switch 401A in the first selection switch 401, and the second sub-control signal S12 is used to control the second sub-selection switch 401B in the first selection switch 401; the fifth sub-control signal S41 is used to control the first sub-reset module 301, and the sixth sub-control signal S42 is used to control the second sub-reset module 301. Optionally, as Fig.11 As shown, the first sub-selection switch 401A and the first sub-reset module 301 are both electrically connected to the port of the first sub-control signal S11. Alternatively, the first sub-selection switch 401A and the first sub-reset module 301 are both electrically connected to the port of the fifth sub-control signal S41. Fig.11 As shown, the second sub-selection switch 401B and the second sub-reset module 302 are both electrically connected to the port of the second sub-control signal S12. Alternatively, the second sub-selection switch 401B and the second sub-reset module 302 are both electrically connected to the port of the sixth sub-control signal S42.

[0080] In the embodiment of the present application, the control end 401A of the first selection switch 401 and the control end 30A of the reset module 30 are electrically connected to the same control signal line S2, which is conducive to turning on the first selection switch 401 and the reset module 30 at the same time, and is conducive to unified control of the first selection switch 401 and the reset module 30, thereby reducing the risk of confusion between the first selection switch 401 and the reset module 30. In addition, the control end 401A of the first selection switch 401 and the control end 30A of the reset module 30 are electrically connected to the same control signal line S2, which is conducive to saving the number of control signal lines prepared in the display panel 100 and reducing the preparation cost of the display panel 100.

[0081] Fig.12 A schematic diagram of the comparative structure of a driving transistor and a data writing transistor provided in an embodiment of the present application.

[0082] In one embodiment of the present application, Figure 3 As shown, the sub-pixel 10 includes a pixel circuit 200, and the pixel circuit 200 includes a driving transistor Md and a data writing transistor T2. The data writing transistor T2 is turned on in the data writing stage E1 and writes the data signal Vdata into the driving transistor Md. In combination with the above embodiments, it can be known that in the embodiment of the present application, when the pixel circuit 200 enters the data writing stage E1, when the sub-pixel 10 enters the data writing sub-stage E13, the data writing transistor T2 is turned on. At this time, the data signal Vdata flows along the data writing transistor T2 to the driving transistor Md.

[0083] Among them, Fig.12 As shown in Figure (a), the driving transistor Md includes a first active layer Md1, a first source Md2, and a first drain Md3. The extension distance of the first active layer Md1 in the second direction X2 is L1, and the extension distance of the first active layer Md1 in the third direction X3 is L2. The second direction X2 is the direction in which the first source Md2 in the first active layer Md1 extends to the first drain Md3. The third direction X3 intersects the second direction X2 and is parallel to the plane where the first active layer Md1 is located. The pixel circuit 200 also includes a threshold write transistor T3. Optionally, one electrode of the threshold write transistor T3 is electrically connected to the first drain Md3 of the driving transistor Md, and the other electrode is electrically connected to the gate of the driving transistor Md. Optionally, the data write transistor T2 is electrically connected to the first source Md2 of the driving transistor Md. After the driving transistor Md receives the data signal Vdata, the data signal Vdata is transmitted along the first source Md2 of the driving transistor Md to the first drain Md3, and then the data signal Vdata is written to the gate of the driving transistor Md through the threshold write transistor T3.

[0084] Combination Fig.12As shown in Figure (b), the data writing transistor T2 includes a second active layer T21, a second source T22, and a second drain T23. The extension distance of the second active layer T21 in the fourth direction X4 is L3, and the extension distance of the second active layer T21 in the fifth direction X5 is L4; the fourth direction X4 is the direction in which the second source T22 in the second active layer T21 extends to the second drain T23, and the fifth direction X5 intersects with the fourth direction X4 and is parallel to the plane where the second active layer T21 is located.

[0085] In the embodiment of the present application, L2 is set to be less than L1, that is, the shape of the first active layer Md1 of the driving transistor Md is such that the length in the direction in which the first source Md2 extends to the first drain Md3 is greater than the width of the first active layer Md1 in the third direction X3. Taking the direction from the source electrode to the drain electrode in the active layer of the transistor as the long direction of the active layer, and the direction intersecting the direction in which the source electrode extends to the drain electrode in the active layer as the wide direction of the active layer as an example, L2 / L1<L4 / L3 is set, so that the width-to-length ratio of the first active layer Md1 of the driving transistor Md is less than the width-to-length ratio of the second active layer T21 of the data writing transistor T2, which is conducive to making the width of the first active layer Md1 of the driving transistor Md narrower, which is conducive to slowing down the writing speed of the data signal Vdata, which is conducive to greatly improving the data writing time of the sub-pixel 10 applicable to the present solution, and is conducive to reducing the influence of the coupling effect in the pixel circuit 200 when the writing time of the data signal Vdata is too long and the writing time of the data signal is fast.

[0086] In addition, combined Figure 3 As shown, the pixel circuit 200 also includes a power supply voltage writing transistor T4, a light emitting control module 200B, and a reset module 200C. The power supply voltage writing transistor T4 is turned on after receiving a valid light emitting control signal EMI T in the light emitting stage E2, and writes the power supply voltage PVDD into the driving transistor Md, so that the driving transistor Md generates a light emitting driving current. The light emitting control module 200B is used to turn on in the light emitting stage E2 and transmit the light emitting driving current to the light emitting device 300. The reset module 200C is used to reset the light emitting device 300 after the light emitting stage E2 ends and before the next light emitting stage E2 arrives, to ensure that the light emitting driving current received by the light emitting device 300 in the light emitting stage E2 is accurate.

[0087] Fig.13 A schematic plan view of a display device provided in an embodiment of the present application.

[0088] The present application embodiment provides a display device 400, such as Fig.13 As shown, the display device 400 includes the display panel 100 in the above embodiment. The display device 400 can be a device used for display, such as a computer, a television, a mobile phone, etc.

[0089] In the display device 400, the time when the first data line 201 receives the data signal Vdata is set to at least partially overlap with the time when the second data line 202 is reset, which is conducive to reducing the idleness of the second data line 202 between the time when the first data line 201 starts to receive the data signal Vdata and the time when the second data line 202 starts to receive the data signal Vdata, and improving the working compactness between the first data line 201 and the second data line 202, so as to prepare for extending the data writing time of the first sub-pixel 101 and the second sub-pixel 102. In addition, it is conducive to completing the resetting of the second data line 202 in advance when the first data line 201 receives the data signal Vdata, and is conducive to opening the data writing module 200A in the first sub-pixel 101 and the second sub-pixel 102 in advance, so as to extend the data writing time of the first sub-pixel 101 and the second sub-pixel 102.

[0090] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a plurality of sub-pixels and a plurality of data lines, wherein the data lines are electrically connected to the sub-pixels; the sub-pixels include the first sub-pixels and the second sub-pixels arranged alternately along a first direction, the data lines include a first data line and a second data line, the first sub-pixels are electrically connected to the first data line, and the second sub-pixels are electrically connected to the second data line; The first data line and the second data line receive data signals in sequence, and the time when the first data line receives the data signal at least partially overlaps with the time when the second data line is reset.

2. The display panel according to claim 1, characterized in that: The time when the first sub-pixel receives the data signal at least partially overlaps with the time when the second data line receives the data signal.

3. The display panel according to claim 1, characterized in that: The display panel further includes a reset module, which is electrically connected to the second data line and is used to reset the second data line.

4. The display panel according to claim 3, characterized in that: The reset module includes a first transistor, a first electrode of the first transistor receives a reset signal, and a second electrode of the first transistor is electrically connected to an input end of the second data line.

5. The display panel according to claim 4, characterized in that: The first electrode of the first transistor is electrically connected to one of a ground terminal and a light emitting test terminal.

6. The display panel according to claim 3, characterized in that: The working process of the sub-pixel includes a data writing stage and a light emitting stage, wherein the data writing stage is performed before the light emitting stage; the data writing stage includes: In a first charging sub-stage, the first data line receives the data signal; a reset sub-stage, which is performed simultaneously with the first charging sub-stage, and the reset module transmits a reset signal to the second data line; The data writing sub-stage is performed after the first charging sub-stage starts for a first time period, the first sub-pixel starts to receive the data signal transmitted by the first data line, and the second sub-pixel starts to receive the reset signal transmitted by the second data line; In a second charging sub-stage, the second data line receives the data signal, and the second sub-pixel receives the data signal transmitted by the second data line; The data writing sub-phase is performed some time after the first charging sub-phase starts, and lasts until the second charging sub-phase ends and before the next first charging sub-phase arrives.

7. The display panel according to claim 6, characterized in that: The first time period is used to reset the first data line.

8. The display panel according to claim 6, characterized in that: The display panel further comprises a multi-way selection circuit, the multi-way selection circuit is used for time-sharing transmission of the data signal for the first data line and the second data line; the multi-way selection circuit at least comprises a first selection switch and a second selection switch, the first end of the first selection switch is electrically connected to the source data line, and the second end is electrically connected to the input end of the first data line, the first end of the second selection switch is electrically connected to the source data line, and the second end is electrically connected to the input end of the second data line; The reset module is electrically connected between the input end of the second data line and the second end of the second selection switch.

9. The display panel according to claim 8, characterized in that: The control end of the first selection switch and the control end of the reset module are electrically connected to the same control signal line.

10. The display panel according to claim 6, characterized in that: The sub-pixel includes a pixel circuit, and the pixel circuit includes a driving transistor and a data writing transistor, wherein the data writing transistor is turned on during the data writing phase and writes the data signal into the driving transistor; The driving transistor comprises a first active layer, a first source electrode, and a first drain electrode, wherein the first active layer extends by a distance L1 in the second direction and extends by a distance L2 in the third direction; The second direction is a direction in which the first source electrode in the first active layer extends toward the first drain electrode, and the third direction intersects the second direction and is parallel to a plane where the first active layer is located; The data writing transistor includes a second active layer, a second source electrode, and a second drain electrode. The second active layer extends by a distance L3 in a fourth direction, and extends by a distance L4 in a fifth direction. The fourth direction is a direction in which the second source electrode in the second active layer extends toward the second drain electrode. The fifth direction intersects the fourth direction and is parallel to a plane where the second active layer is located. Among them, L2<L1, and L2 / L1<L4 / L3.

11. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-10.

Images