Pixel circuit and driving method thereof

Abstract

The invention provides a pixel circuit and a driving method thereof. The pixel circuit comprises a capacitor, a reset circuit, a write-in circuit, a driving circuit and a light emitting diode. The capacitor is coupled to a node; the reset circuit is controlled by a reset signal and is used for resetting the voltage on the node according to the reference voltage; the write-in circuit is controlled by a write-in signal and used for writing the gray-scale voltage into the capacitor. The driving circuit is controlled by a driving signal and is used for generating a driving current according to the voltage of the node so as to drive the light-emitting diode; the enable period of the reset signal partially overlaps the enable period of the write signal, so that the reference voltage is applied to the node while the gray scale voltage is written to the capacitor.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit applicable to a light emitting diode. Background Art

[0002] In the prior art, display panels are widely used in various display devices, and one of the core components is the pixel circuit. The pixel circuit usually includes a plurality of transistors, one or more capacitors and a light emitting diode (LED), and these components work together to realize the function of image display. During operation, each pixel circuit will go through a plurality of different operation periods. For example, during a certain period, the grayscale voltage will be written and stored in the capacitor, and then the LED will be driven to emit light. However, in some products, the charging time of the capacitor will be shortened. For example, with the increase of display resolution and high refresh rate, the capacitor will not be fully charged within a limited time. In addition, due to the capacitive coupling phenomenon in the pixel circuit, when the voltage of the data line changes, these changes may be coupled to the capacitor, resulting in a voltage offset in the pixel circuit, thereby affecting the display effect. Summary of the invention

[0003] The present invention provides a pixel circuit and a driving method of the pixel circuit, which can solve the display abnormality problem caused by the voltage variation of the data line when the charging time is too short.

[0004] The present invention proposes a pixel circuit, including a capacitor, a reset circuit, a write circuit, a drive circuit and a light-emitting diode; the capacitor is coupled to a node; the reset circuit is controlled by at least one reset signal, and is used to reset the voltage on the node according to at least one reference voltage; the write circuit is controlled by the write signal, and is used to write a grayscale voltage into the capacitor and change the voltage on the node to respond to a critical voltage; the drive circuit is controlled by the drive signal, and is used to generate a drive current according to the voltage of the node; the light-emitting diode is coupled to the drive circuit, wherein the brightness of the light-emitting diode changes with the drive current, and the enable period of the reset signal partially overlaps the enable period of the write signal, so that the grayscale voltage is written to the capacitor while the reference voltage is applied to the node.

[0005] In one embodiment of the present invention, the reference voltage includes a first reference voltage and a second reference voltage. The reset circuit includes: a first transistor, a first end of which is coupled to the first reference voltage, a second end of which is coupled to the first end of the capacitor, and a control end of which receives a reset signal; a second transistor, a first end of which is coupled to the second end of the capacitor, a second end of which is coupled to the second reference voltage, and a control end of which receives the reset signal; and a third transistor, a first end of which is coupled to the second reference voltage, and a control end of which receives the reset signal.

[0006] In one embodiment of the present invention, the reference voltage includes a first reference voltage and a second reference voltage. The reset signal includes a first reset signal and a second reset signal. The reset circuit includes: a first transistor, a first end of which is coupled to the first reference voltage, a second end of which is coupled to the first end of the capacitor, and a control end of which receives the first reset signal; a second transistor, a first end of which is coupled to the second end of the capacitor, a second end of which is coupled to the second reference voltage, and a control end of which receives the second reset signal; and a third transistor, a first end of which is coupled to the second reference voltage, and a control end of which receives the first reset signal.

[0007] In one embodiment of the present invention, the enabling period of the first reset signal does not overlap with the enabling period of the write signal, and the enabling period of the second reset signal partially overlaps with the enabling period of the write signal.

[0008] In one embodiment of the present invention, the above-mentioned write circuit includes: a fourth transistor, whose first end is coupled to the grayscale voltage, whose second end is coupled to the first end of the capacitor, and whose control end receives the write signal; and a fifth transistor, whose first end is coupled to the third reference voltage, and whose control end receives the write signal.

[0009] In one embodiment of the present invention, the above-mentioned driving circuit includes: a sixth transistor, whose first end is coupled to the light-emitting diode, whose second end is coupled to the second end of the capacitor, and whose control end receives a driving signal; a seventh transistor, whose first end is coupled to the second end of the capacitor, whose second end is coupled to the first reference voltage, and whose control end is coupled to the second end of the third transistor and the second end of the fifth transistor; and an eighth transistor, whose first end is coupled to the first end of the capacitor, whose second end is coupled to the control end of the seventh transistor, and whose control end receives a driving signal.

[0010] In one embodiment of the present invention, the first transistor to the eighth transistor are P-type transistors, the reset signal is at a logic low level during its enable period, and the write signal is at a logic low level during its enable period.

[0011] In one embodiment of the present invention, the duration of the enable period of the write signal is longer than the duration of the enable period of the gray-scale voltage.

[0012] In one embodiment of the present invention, the enable period of the reset signal ends earlier than the enable period of the write signal.

[0013] In one embodiment of the present invention, the above-mentioned driving circuit includes: a first transistor, whose first end is coupled to the system voltage and whose control end receives a driving signal; a second transistor, whose first end is coupled to the second end of the first transistor, whose second end is coupled to the first end of the capacitor, and whose control end receives the driving signal; a third transistor, whose first end is coupled to the first end of the second transistor, whose control end is coupled to the second end of the capacitor; and a fourth transistor, whose first end is coupled to the second end of the third transistor, whose second end is coupled to the light-emitting diode, and whose control end receives the driving signal.

[0014] In one embodiment of the present invention, the reference voltage includes a first reference voltage and a second reference voltage. The reset circuit includes: a fifth transistor, a first end of which is coupled to the second end of the capacitor, a second end of which is coupled to the second reference voltage, and a control end of which receives a reset signal; and a sixth transistor, a first end of which is coupled to the first end of the capacitor, a second end of which is coupled to the first reference voltage, and a control end of which receives the reset signal.

[0015] In one embodiment of the present invention, the above-mentioned write circuit includes: a seventh transistor, whose first end is coupled to the first end of the capacitor, whose second end is coupled to the first reference voltage, and whose control end receives the write signal; an eighth transistor, whose first end is coupled to the first end of the third transistor, whose second end is coupled to the grayscale voltage, and whose control end receives the write signal; and a ninth transistor, whose first end is coupled to the first end of the fourth transistor, whose second end is coupled to the second end of the capacitor, and whose control end receives the write signal.

[0016] In one embodiment of the present invention, the first transistor to the ninth transistor are P-type transistors, the reset signal is at a logic low level during its enable period, and the write signal is at a logic low level during its enable period.

[0017] From another perspective, an embodiment of the present invention provides a driving method for a pixel circuit, comprising: controlling a reset circuit according to at least one reset signal, thereby resetting a voltage on a node according to at least one reference voltage, the node being coupled to a capacitor; controlling a write circuit according to a write signal, thereby writing a grayscale voltage to the capacitor and changing the voltage on the node in response to a threshold voltage; controlling a drive circuit according to a drive signal, thereby generating a drive current according to the voltage of the node, and driving a light emitting diode according to the drive current, wherein the brightness of the light emitting diode changes with the drive current. The enabling period of the reset signal partially overlaps the enabling period of the write signal, so that the grayscale voltage is written to the capacitor while the reference voltage is applied to the node.

[0018] In an embodiment of the driving method of the pixel circuit of the present invention, a time length of an enabling period of the write signal is greater than a time length of an enabling period of the grayscale voltage.

[0019] In an embodiment of the driving method of the pixel circuit of the present invention, the enabling period of the at least one reset signal ends earlier than the enabling period of the write signal.

[0020] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a circuit diagram of a pixel circuit according to a first embodiment.

[0022] Figure 2 is a schematic diagram illustrating a display pattern according to an embodiment.

[0023] Figure 3 is a timing diagram of various signals according to an embodiment.

[0024] Figure 4 FIG. 4 is a circuit diagram illustrating a case where a reset signal and a write signal are enabled at the same time according to the first embodiment.

[0025] Figure 5 FIG. 4 is a schematic diagram illustrating how to lengthen the enable period of a write signal according to an embodiment.

[0026] Figure 6 is a timing diagram illustrating the voltage on the node N1 and various signals according to an embodiment.

[0027] Figure 7 is a circuit diagram of a pixel circuit according to a second embodiment.

[0028] Figure 8 is a timing diagram of various signals according to the second embodiment.

[0029] Fig. 9 FIG. 8 is a circuit diagram illustrating a circuit in a second period 802 according to the second embodiment.

[0030] Fig.10 is a circuit diagram of a pixel circuit according to a third embodiment.

[0031] Fig.11 is a schematic diagram of a pixel circuit in a first period 351 according to the third embodiment.

[0032] Fig.12 is a flow chart illustrating a driving method of a pixel circuit according to an embodiment.

[0033] Wherein, the reference numerals are:

[0034] 100,1000:Pixel circuit

[0035] 110,1020: Reset circuit

[0036] 120,1030:Write circuit

[0037] 130,1010:Drive circuit

[0038] 140,1040:Test circuit

[0039] 210,220:Image

[0040] 310,320,330,341,342,510,810,820,830,840: Enablement period

[0041] 351,601,801: First period

[0042] 352,602,802: Second period

[0043] 520:Previous enabling period

[0044] 610,610p,620,620p,630,630p: Voltage curve

[0045] 1201~1203: Steps

[0046] C1, C2: capacitors

[0047] EM: driving signal

[0048] LED1, LED2: light emitting diode

[0049] N1, N2: nodes

[0050] RS, RS2: reset signal

[0051] WR: Write signal

[0052] VDD: system voltage

[0053] VSS,Vini,Vref:reference voltage

[0054] T1~T10: Transistor

[0055] Test1, Test2: Test signal

[0056] Page 5 of 5 (Invention Description) DETAILED DESCRIPTION

[0057] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More specifically, these embodiments are only examples of the systems and methods within the scope of the present invention.

[0058] The terms “first”, “second”, etc. used in this document do not particularly refer to an order or sequence, but are only used to distinguish components or operations described with the same technical terminology.

[0059] The term "coupled (or connected)" used in the entire specification of this case (including the scope of the patent application) may refer to any direct or indirect connection means. For example, if the text describes that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means.

[0060] [First embodiment]

[0061] Figure 1 is a circuit diagram of a pixel circuit according to the first embodiment. Figure 1 The pixel circuit 100 includes a capacitor C1, a light emitting diode LED1, a reset circuit 110, a write circuit 120, a drive circuit 130, and a test circuit 140. In some embodiments, the test circuit 140 may be omitted. The capacitor C1 is coupled to a node N1.

[0062] The reset circuit 110 is controlled by the reset signal RS to reset the voltage across the capacitor C1 according to the reference voltages VSS and Vini, thereby resetting the voltage on the node N1. The write circuit 120 is controlled by the write signal WR to write the grayscale voltage Vsig into the capacitor C1 and change the voltage on the node N1. The drive circuit 130 is controlled by the drive signal EM to generate a drive current Id according to the voltage on the node N1. The drive current Id drives the light emitting diode LED1, and the brightness of the light emitting diode changes with the drive current Id. The test circuit 140 is controlled by the test signal Test1 and the drive signal EM to drive the light emitting diode LED1 according to the grayscale voltage Vsig during the test period.

[0063] For example, the reset circuit 110 includes transistors T1-T3, the write circuit 120 includes transistors T4 and T5, the drive circuit 130 includes transistors T6-T8, and the test circuit 140 includes transistors T9 and T10. The first end of the transistor T1 is coupled to the reference voltage VSS, the second end is coupled to the first end of the capacitor C1, and the control end receives the reset signal RS. The first end of the transistor T4 is coupled to the grayscale voltage Vsig, the second end is coupled to the first end of the capacitor C1, and the control end receives the write signal WR. The first end of the transistor T10 is coupled to the grayscale voltage Vsig, and the control end receives the test signal Test1. The first end of the transistor T9 is coupled to the second end of the transistor T10, the second end is coupled to the cathode of the light emitting diode LED1, and the control end receives the drive signal EM. The first end of the transistor T6 is coupled to the cathode of the light emitting diode LED1, the second end is coupled to the node N1 and the second end of the capacitor C1, and the control end receives the drive signal EM. The anode of the light emitting diode LED1 is coupled to the system voltage VSS. The first end of transistor T2 is coupled to the second end of capacitor C1, the second end is coupled to reference voltage Vini, and the control end receives reset signal RS. The first end of transistor T7 is coupled to the second end of capacitor C1, the second end is coupled to reference voltage VSS, and the control end is coupled to the second end of transistor T3 and the second end of transistor T5. The first end of transistor T8 is coupled to the first end of capacitor C1, the second end is coupled to the control end of transistor T7, and the control end receives driving signal EM. The first end of transistor T3 is coupled to reference voltage Vini, the second end is coupled to the control end of transistor T7, and the control end receives reset signal RS. The first end of transistor T5 is coupled to reference voltage Vref, the second end is coupled to the control end of transistor T7, and the control end receives write signal WR.

[0064] In this embodiment, transistors T1-T10 are P-type transistors. The reset signal RS, the write signal WR, and the drive signal EM are at a logic low level during their respective enable periods to turn on the corresponding transistors. In addition, the reference voltage VSS is, for example, 0 volts, the reference voltage Vini is, for example, 10 volts, and the reference voltage Vref is, for example, 7 volts. The threshold voltage of the transistor T7 is, for example, -1.5 volts.

[0065] In some embodiments, the charging time of the pixel circuit 100 is greatly reduced, so the enabling period of the write signal WR must be extended, which will cause the grayscale voltage Vsig of the data line to change during the enabling period of the write signal WR. When the grayscale voltage Vsig changes greatly, the voltage on the node N1 will not meet expectations due to the coupling of the capacitor C1, resulting in display abnormality. Figure 2 is a schematic diagram showing a display pattern according to an embodiment. Figure 2Image 210 is the image displayed when the enable period of the write signal WR is not extended (the correct image is displayed). Image 220 is the image displayed when the enable period of the write signal WR is extended. It can be seen that at the junction of the black and white stripes, the pixel that should have displayed white displays black. Therefore, in this embodiment, the enable period of the reset signal RS is extended so that the enable period of the reset signal RS partially overlaps with the enable period of the write signal WR.

[0066] Figure 3 is a timing diagram of various signals according to an embodiment. Figure 1 and 3 , Figure 3 The horizontal axis is time, and the vertical axis is the voltage level of each signal. The enabling period 310 of the reset signal RS partially overlaps the enabling period 320 of the write signal WR and the enabling period 330 of the grayscale voltage Vsig, and the overlapping period is called the first period 351. In addition, in the second period 352, the reset signal RS is not enabled, while the write signal WR and the grayscale voltage Vsig are enabled. In other words, the enabling period 310 of the reset signal RS ends earlier than the enabling period 320 of the write signal WR.

[0067] During the enabling period 310 of the reset signal RS, the transistors T1-T3 are turned on, the reference voltage VSS is applied to the first end of the capacitor C1, and the reference voltage Vini is applied to the second end of the capacitor C1, thereby resetting the voltage across the capacitor C1 and thus resetting the voltage on the node N1.

[0068] Figure 4 FIG. 1 is a circuit diagram illustrating a case where the reset signal and the write signal are enabled at the same time according to the first embodiment. Figure 3 and Figure 4 , in the first period 351, transistors T1 to T5 are turned on, and transistors T6, T8 to T10 are turned off. The grayscale voltage Vsig is applied to the first end of the capacitor C1, and the reference voltage Vini is applied to the node N1. That is, when the grayscale voltage Vsig is written to the capacitor C1, the reference voltage Vini is also applied to the node N1. In addition, the reference voltage Vref is applied to the control end of the transistor T7. Since the voltage on the control end of the transistor T7 minus the voltage on the node N1 is less than the critical voltage of the transistor T1 (7-10<-1.5), the transistor T7 is turned on. In particular, the reference voltage Vini is applied to the node N1, so the change of the grayscale voltage Vsig is not coupled to the node N1.

[0069] Please refer to Figure 1 and Figure 3In the second period 352, transistors T1-T3, T6, T8-T10 are turned off, and transistors T4 and T5 are turned on. The grayscale voltage Vsig is applied to the first end of the capacitor C1, and the second end (node ​​N1) of the capacitor C1 is floating. The reference voltage Vref is applied to the control end of the transistor T7, and the voltage of the first end of the transistor T7 (coupled to the node N1) is the reference voltage Vref minus the threshold voltage of the transistor T7, which is calculated as 7-(-1.5)=8.5, that is, the voltage of the node N1 responds to the threshold voltage of the transistor T7.

[0070] During the enabling periods 341 and 342 of the driving signal EM, the transistors T1 to T5, T9 and T10 are turned off, and the transistors T6 to T8 are turned on. The transistor T7 is turned on and generates the driving current Id according to the voltage on the node N1 and the voltage on the first end of the capacitor C1. Since the voltage on the node N1 includes the critical voltage of the transistor T7, the critical voltage of the transistor T7 has been eliminated in the calculation formula for generating the driving current Id. This process is called critical voltage compensation. In some embodiments, the length or frequency of the enabling periods 341 and 342 of the driving signal EM can be controlled to achieve a specific display brightness.

[0071] Figure 5 FIG. 1 is a schematic diagram illustrating a method of lengthening the enable period of a write signal according to an embodiment. Figure 5 In the embodiment of the invention, the time length of the enable period 510 of the write signal WR is greater than the time length of the enable period of the grayscale voltage Vsig. For example, the time length of the enable period of the grayscale voltage Vsig is 1H, where H is a variable, and the time length of the enable period 510 of the write signal WR may be 2H, 3H, etc., but the present invention is not limited thereto. On the other hand, the previous enable period 520 of the grayscale voltage Vsig is used to drive the pixel circuit of the previous column of the same data line, and this previous enable period 520 also overlaps with the enable period 510 of the write signal WR. Therefore, the voltage change of the grayscale voltage Vsig will be coupled to the node N1 due to the capacitor C1. For example, the previous enable period 520 is to display a low-brightness pixel, and the enable period 330 is to display a high-brightness pixel. This phenomenon is like Figure 2 At the junction of the black and white stripes, the grayscale voltage Vsig will drop significantly, and the voltage of the node N1 will also drop through the coupling of the capacitor C1. In this embodiment, since the enabling period 310 of the reset signal RS also overlaps with the previous enabling period 520, the above coupling will not cause abnormal display.

[0072] Specifically, Figure 6 is a timing diagram showing the voltage on the node N1 and various signals according to an embodiment. Figure 4 and Figure 6 , the reset signal RS has two voltage curves 610 and 610p, wherein the voltage curve 610p represents the prior art, and the voltage curve 610 represents the current embodiment. Similarly, the node N1 has two voltage curves 620 and 620p, wherein the voltage curve 620p represents the prior art, and the voltage curve 620 represents the current embodiment. The voltage V GS represents the voltage difference between the control terminal of transistor T1 and node N1, voltage V GS There are also two voltage curves 630p and 630, wherein the voltage curve 630p represents the prior art, and the voltage curve 630 represents the current embodiment.

[0073] In the first period 601, the voltage curve 610p is at a logic high level, and the voltage curve 610 is at a logic low level. The write signal WR is at a logic low level. The grayscale voltage Vsig is not enabled, but in order to drive the pixel circuit of the previous row of the same data line, the voltage of the data line changes, and this change is coupled to the node N1. As a result, the voltage curve 620p is affected by the voltage change of the data line and decreases. On the contrary, please refer to the voltage curve 620. Since the reference voltage Vini is applied to the node N1 in this embodiment, the voltage of the node N1 is less affected.

[0074] During the second period 602, the voltage curves 610 and 610p are both at a logic high level. The write signal WR is at a logic low level, and the grayscale voltage Vsig is enabled. Due to the influence of the previous capacitive coupling, the voltage curve 620p is lower than the voltage curve 620, which makes the voltage curve 630p of the voltage VGS higher than the voltage curve 630. The voltage curve 630p may not properly turn on the transistor T7, which will cause display abnormality, but the voltage curve 630 generated in this embodiment can solve this problem.

[0075] In the first embodiment, when the reset signal RS and the write signal WR are both enabled, the grayscale voltage Vsig is short-circuited to the reference voltage VSS through the transistors T4 and T1, which will form a leakage current. The leakage current problem will be solved in the following second embodiment.

[0076] [Second embodiment]

[0077] Figure 7 is a circuit diagram of a pixel circuit according to the second embodiment. Figure 7 , Figure 7 and Figure 1 The difference is that the control terminal of the transistor T2 receives the reset signal RS2 , which is different from the reset signal RS.

[0078] Figure 8is a timing diagram of various signals according to the second embodiment. Figure 8 The enabling period 810 of the reset signal RS does not overlap with the enabling period 830 of the write signal WR. The enabling period 820 of the reset signal RS2 partially overlaps with the enabling period 830 of the write signal WR and the enabling period 840 of the grayscale voltage Vsig.

[0079] In the first period 801, the reset signal RS and the reset signal RS2 are both enabled. The transistors T1-T3 are turned on, and the transistors T4-T10 are turned off, thereby resetting the voltage across the capacitor C1.

[0080] Fig. 9 1 is a circuit diagram according to the second embodiment during the second period 802. During the second period 802, the reset signal RS is not enabled, and the reset signal RS2 and the write signal WR are enabled. Transistors T1, T3, T6, T8 to T10 are turned off, and transistors T2, T4, T5, and T7 are turned on. While the grayscale voltage Vsig is written to the capacitor C1, the reference voltage Vini is applied to the node N1. Therefore, the voltage change of the data line can be prevented from being coupled to the node N1. In addition, no leakage current is generated on the path from the grayscale voltage Vsig to the reference voltage VSS. For the operations in other periods, refer to the first embodiment, which will not be repeated here.

[0081] [Third embodiment]

[0082] Fig.10 is a circuit diagram of a pixel circuit according to the third embodiment. Fig.10 , the pixel circuit 1000 includes a driving circuit 1010, a reset circuit 1020, a write circuit 1030, a test circuit 1040, a capacitor C2, and a light emitting diode LED2. The capacitor C2 is coupled to the node N2. The driving circuit 1010 includes transistors T1-T4, the reset circuit 1020 includes transistors T5-T6, the write circuit 1030 includes transistors T7-T9, and the test circuit 1040 includes a transistor T10. In some embodiments, the test circuit 1040 may also be omitted.

[0083] The first end of transistor T1 is coupled to the system voltage VDD, and the control end receives the driving signal EM. The first end of transistor T2 is coupled to the second end of transistor T1, the second end is coupled to the first end of capacitor C2, and the control end receives the driving signal EM. The first end of transistor T3 is coupled to the first end of transistor T2, and the control end is coupled to the second end of capacitor C2. The first end of transistor T4 is coupled to the second end of transistor T3, the second end is coupled to the anode of light emitting diode LED2, and the control end receives the driving signal EM. The cathode of light emitting diode LED2 is coupled to the reference voltage VSS. The first end of transistor T5 is coupled to the second end of capacitor C2, the second end is coupled to the reference voltage Vini, and the control end receives the reset signal RS. The first end of transistor T6 is coupled to the first end of capacitor C2, the second end is coupled to the reference voltage Vref, and the control end receives the reset signal RS. The first end of transistor T7 is coupled to the first end of capacitor C2, the second end is coupled to the reference voltage Vref, and the control end receives the write signal WR. The first end of transistor T8 is coupled to the first end of transistor T3, the second end is coupled to the grayscale voltage Vsig, and the control end receives the write signal WR. The first end of transistor T9 is coupled to the first end of transistor T4, the second end is coupled to the second end of capacitor C2, and the control end receives the write signal WR. The first end of transistor T10 is coupled to the grayscale voltage Vsig, the second end is coupled to the anode of light emitting diode LED2, and the control end receives the test signal Test2.

[0084] In some embodiments, transistors T1-T10 are P-type transistors. The reset signal RS, the write signal WR, and the drive signal EM are at a logic low level during their respective enable periods. The timing diagram of the reset signal RS, the write signal WR, the grayscale voltage Vsig, and the drive signal EM can be referred to. Figure 3 , Figure 5 or Figure 6 In other words, the signal timing diagram of the first embodiment can be applied in the third embodiment.

[0085] Please refer to Figure 3 and Fig.10 During the enabling period 310 of the reset signal RS, the transistors T5 and T6 are turned on. The reference voltage Vref is applied to the first end of the capacitor C2, and the reference voltage Vini is applied to the second end of the capacitor C2.

[0086] Fig.11 is a schematic diagram of a pixel circuit in the first period 351 according to the third embodiment. Figure 3 and Fig.11In the first period 351, transistors T1, T2, T4, and T10 are turned off, and transistors T3, T5 to T9 are turned on. When the grayscale voltage Vsig is written to the capacitor C2 through transistors T8, T3, and T9, the reference voltage Vini is applied to the node N2.

[0087] During the second period 352, transistors T3 and T7-T9 are turned on, and the other transistors are turned off. The voltage of node N2 responds to the threshold voltage of transistor T3. During the enabling periods 341 and 342 of the driving signal EM, transistors T1-T4 are turned on, and the other transistors are turned off. Transistor T3 generates a driving current according to the voltage on node N2 to drive light emitting diode LED2.

[0088] Similar to the first embodiment, since the enabling period 310 of the reset signal RS partially overlaps with the enabling period 320 of the write signal WR, the voltage variation of the data line where the gray-scale voltage Vsig is located will not cause an abnormal voltage variation of the node N2.

[0089] Fig.12 is a flow chart of a driving method of a pixel circuit according to an embodiment. Fig.12 , Fig.12 The flowchart can be applied to Figure 1 , Figure 7 as well as Fig.10 A pixel circuit. In step 1201, a reset circuit is controlled according to a reset signal, thereby resetting a voltage on a node according to at least one reference voltage, and the node is coupled to a capacitor. In step 1202, a write circuit is controlled according to a write signal, thereby writing a grayscale voltage to the capacitor and changing the voltage on the node in response to a threshold voltage. In step 1203, a drive circuit is controlled according to a drive signal, thereby generating a drive current according to the voltage of the node, and driving a light emitting diode according to the drive current, wherein the brightness of the light emitting diode changes with the drive current. In particular, the enable period of the reset signal partially overlaps the enable period of the write signal, so that the grayscale voltage is written to the capacitor while the reference voltage is applied to the node. Fig.12 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.12 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig.12 The method can be used in conjunction with the above embodiment or can be used alone. In other words, Fig.12 Other steps may also be added between the steps.

[0090] In the above circuit and method, the enabling period of the reset signal is partially overlapped with the enabling period of the write signal, thereby solving the problem of the voltage change of the data line being coupled to the node.

[0091] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A pixel circuit, characterized in that: include: a capacitor coupled to a node; a reset circuit, controlled by at least one reset signal, for resetting the voltage on the node according to at least one reference voltage; a writing circuit, controlled by a writing signal, for writing a grayscale voltage into the capacitor and changing the voltage at the node in response to a threshold voltage; a driving circuit, controlled by a driving signal, for generating a driving current according to the voltage of the node; as well as a light emitting diode coupled to the driving circuit, wherein the brightness of the light emitting diode changes with the driving current, The enabling period of the at least one reset signal partially overlaps with the enabling period of the write signal, so that the gray-scale voltage is written into the capacitor while the at least one reference voltage is applied to the node.

2. The pixel circuit according to claim 1, wherein: The at least one reference voltage includes a first reference voltage and a second reference voltage, and the reset circuit includes: a first transistor, a first terminal of which is coupled to the first reference voltage, a second terminal of which is coupled to a first terminal of the capacitor, and a control terminal of which receives the at least one reset signal; a second transistor, a first terminal of which is coupled to a second terminal of the capacitor, a second terminal of which is coupled to the second reference voltage, and a control terminal of which receives the at least one reset signal; as well as A third transistor has a first terminal coupled to the second reference voltage and a control terminal receiving the at least one reset signal.

3. The pixel circuit according to claim 1, wherein: The at least one reference voltage includes a first reference voltage and a second reference voltage, the at least one reset signal includes a first reset signal and a second reset signal, and the reset circuit includes: a first transistor, a first terminal of which is coupled to the first reference voltage, a second terminal of which is coupled to a first terminal of the capacitor, and a control terminal of which receives the first reset signal; a second transistor, a first terminal of which is coupled to a second terminal of the capacitor, a second terminal of which is coupled to the second reference voltage, and a control terminal of which receives the second reset signal; as well as A third transistor has a first terminal coupled to the second reference voltage and a control terminal receiving the first reset signal.

4. The pixel circuit according to claim 3, characterized in that: An enabling period of the first reset signal does not overlap with the enabling period of the write signal, and an enabling period of the second reset signal partially overlaps with the enabling period of the write signal.

5. The pixel circuit according to claim 2, wherein: The writing circuit includes: a fourth transistor, a first terminal of which is coupled to the grayscale voltage, a second terminal of which is coupled to the first terminal of the capacitor, and a control terminal of which receives the write signal; and A fifth transistor has a first terminal coupled to a third reference voltage and a control terminal receiving the write signal.

6. The pixel circuit according to claim 5, characterized in that: The drive circuit includes: a sixth transistor, a first terminal of which is coupled to the light emitting diode, a second terminal of which is coupled to the second terminal of the capacitor, and a control terminal of which receives the driving signal; a seventh transistor, a first terminal of which is coupled to the second terminal of the capacitor, a second terminal of which is coupled to the first reference voltage, and a control terminal of which is coupled to the second terminal of the third transistor and the second terminal of the fifth transistor; as well as An eighth transistor has a first terminal coupled to the first terminal of the capacitor, a second terminal coupled to the control terminal of the seventh transistor, and a control terminal receiving the driving signal.

7. The pixel circuit according to claim 6, characterized in that: The first transistor to the eighth transistor are P-type transistors. The at least one reset signal is at a logic low level during the enabling period of the at least one reset signal. The write signal is at the logic low level during the enabling period of the write signal.

8. The pixel circuit according to claim 1, wherein: A time length of the enabling period of the write signal is greater than a time length of an enabling period of the gray-scale voltage.

9. The pixel circuit according to claim 1, wherein: The enabling period of the at least one reset signal ends earlier than the enabling period of the write signal.

10. The pixel circuit according to claim 1, wherein: The drive circuit includes: A first transistor, a first terminal of which is coupled to a system voltage, and a control terminal of which receives the driving signal; a second transistor, a first terminal of which is coupled to the second terminal of the first transistor, a second terminal of which is coupled to the first terminal of the capacitor, and a control terminal of which receives the driving signal; a third transistor, a first terminal of which is coupled to the first terminal of the second transistor, and a control terminal of which is coupled to the second terminal of the capacitor; as well as A fourth transistor has a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the light emitting diode, and a control terminal receiving the driving signal.

11. The pixel circuit according to claim 10, characterized in that: The at least one reference voltage includes a first reference voltage and a second reference voltage, and the reset circuit includes: a fifth transistor, a first terminal of which is coupled to the second terminal of the capacitor, a second terminal of which is coupled to the second reference voltage, and a control terminal of which receives the at least one reset signal; as well as A sixth transistor has a first terminal coupled to the first terminal of the capacitor, a second terminal coupled to the first reference voltage, and a control terminal receiving the at least one reset signal.

12. The pixel circuit according to claim 11, characterized in that: The writing circuit includes: a seventh transistor, a first terminal of which is coupled to the first terminal of the capacitor, a second terminal of which is coupled to the first reference voltage, and a control terminal of which receives the write signal; an eighth transistor, a first terminal of which is coupled to the first terminal of the third transistor, a second terminal of which is coupled to the grayscale voltage, and a control terminal of which receives the write signal; as well as A ninth transistor has a first terminal coupled to the first terminal of the fourth transistor, a second terminal coupled to the second terminal of the capacitor, and a control terminal receiving the write signal.

13. The pixel circuit according to claim 12, characterized in that: The first transistor to the ninth transistor are P-type transistors. The at least one reset signal is at a logic low level during the enabling period of the at least one reset signal. The write signal is at the logic low level during the enabling period of the write signal.

14. A method for driving a pixel circuit, characterized in that: Include: Controlling a reset circuit according to at least one reset signal, thereby resetting a voltage on a node according to at least one reference voltage, wherein the node is coupled to a capacitor; Controlling a write circuit according to a write signal, thereby writing a grayscale voltage into the capacitor and changing the voltage on the node in response to a threshold voltage; A driving circuit is controlled according to a driving signal, thereby generating a driving current according to the voltage of the node, and driving a light emitting diode according to the driving current, wherein the brightness of the light emitting diode changes with the driving current, The enabling period of the at least one reset signal partially overlaps with the enabling period of the write signal, so that the gray-scale voltage is written into the capacitor while the at least one reference voltage is applied to the node.

15. The driving method according to claim 14, characterized in that: A time length of an enabling period of the write signal is greater than a time length of an enabling period of the gray-scale voltage.

16. The driving method according to claim 14, characterized in that: The enabling period of the at least one reset signal ends earlier than the enabling period of the write signal.

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