Display device and driving method thereof

Abstract

A display device and a driving method thereof are disclosed. The display device includes a compensation voltage generator configured to output a first compensation voltage, a second compensation voltage, and a third compensation voltage. During a hold frame period, a first compensation voltage is applied to the data line. During a refresh frame period, the data voltage, the second compensation voltage, and the third compensation voltage are applied to the sub-pixels. During a hold frame period, a first compensation voltage, a second compensation voltage, and a third compensation voltage are applied to the sub-pixels.

Description

Technical Field

[0001] The present disclosure relates to a display device and a driving method thereof. Background Art

[0002] The organic light emitting display device includes an organic light emitting diode (hereinafter, referred to as "OLED"), which emits light by itself and has the advantages of fast response speed, high luminous efficiency, brightness and viewing angle. The organic light emitting display device has a fast response speed and excellent luminous efficiency, brightness and viewing angle, and has excellent contrast and color reproducibility because it can express black grayscale in full black.

[0003] Various studies are being conducted to reduce the power consumption of organic light emitting display devices. For example, under certain conditions, an organic light emitting display may reduce the driving frequency of pixels to reduce power consumption. In this case, a viewer may experience, for example, flickering of an image reproduced on a display panel. Summary of the invention

[0004] The present disclosure is directed to addressing the above-mentioned needs and / or shortcomings.

[0005] The present disclosure provides a display device capable of preventing image quality from being deteriorated when a driving frequency of pixels is reduced, and a driving method thereof.

[0006] Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other unmentioned problems will be clearly understood by those skilled in the art through the following description.

[0007] A display device according to an embodiment of the present disclosure includes: a display panel, in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, a plurality of sub-pixels, and a gate driver that provides a gate signal to the gate line are provided; a data driver configured to provide a data voltage to the data line during a refresh frame period; and a compensation voltage generator configured to output a first compensation voltage, a second compensation voltage, and a third compensation voltage. The first compensation voltage is applied to the data line during a hold frame period. During the refresh frame period, the data voltage, the second compensation voltage, and the third compensation voltage are applied to the sub-pixel. During the hold frame period, the first compensation voltage, the second compensation voltage, and the third compensation voltage are applied to the sub-pixel.

[0008] At least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage may be variable.

[0009] Each of the sub-pixels may include: a light emitting element; a driving element including a gate electrode connected to a first node, a first electrode connected to a second node, a second electrode connected to a third node, and configured to drive the light emitting element; a first switching element connected between a data line and a second node, and configured to provide a data voltage to the second node in response to a second scan signal; a second switching element connected between a first power line to which a second compensation voltage is applied and a second node, and configured to provide the second compensation voltage to the second node in response to a third scan signal; and a third switching element connected between a second power line to which a third compensation voltage is applied and an anode electrode of the light emitting element, and configured to provide the third compensation voltage to the anode electrode of the light emitting element during a refresh frame period and a hold frame period. The first switching element may maintain an off state during the hold frame period.

[0010] At least one of the second compensation voltage and the third compensation voltage may have a higher voltage level in the refresh frame period than in the hold frame period.

[0011] A voltage level of at least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage may vary within one frame period.

[0012] A voltage level of at least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage is different according to a position of a sub-pixel.

[0013] A voltage level of the first compensation voltage may continue to rise during the hold frame period. A voltage level of at least one of the second compensation voltage and the third compensation voltage may rise and then fall in the refresh frame period and the hold frame period.

[0014] At least one of the second compensation voltage and the third compensation voltage may vary in a step form or in the form of a linear voltage having a predetermined slope.

[0015] Each of the sub-pixels may include: a driving element including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a first switching element connected between a data line and a second node, and configured to provide a data voltage to the second node during a refresh frame period; a second switching element connected between a first power line to which a second compensation voltage is applied and a second node, and configured to provide the second compensation voltage to the second node during a refresh frame period and a hold frame period; a third switching element connected between a second power line to which a third compensation voltage is applied and an anode electrode of a light-emitting element, and configured to provide the third compensation voltage to the anode electrode of the light-emitting element in response to a third scan signal; and a fourth switching element connected between the first power line to which a third compensation voltage is applied and anode electrode of the light-emitting element. a fifth switching element connected between the first node and the third node and configured to connect the first node to the third node in response to the first scanning signal; a sixth switching element connected between the third power line to which the pixel driving voltage is applied and the second node and configured to provide the pixel driving voltage to the second node in response to the light emitting control signal; a seventh switching element connected between the third node and the fourth node and configured to connect the third node to the fourth node in response to the light emitting control signal; and a light emitting element having an anode electrode connected to the fourth node and a cathode electrode connected to the fourth power line to which the cathode voltage is applied.

[0016] The pixel driving voltage may be a voltage higher than the cathode voltage. The gate high voltage of the first to fourth scan signals and the light emitting control signal may be higher than the pixel driving voltage, and the gate low voltage of the first to fourth scan signals and the light emitting control signal may be lower than the cathode voltage. The initialization voltage may be a voltage lower than the lower limit voltage of the data voltage and higher than the cathode voltage.

[0017] The first switching element, the second switching element, the third switching element, the sixth switching element, and the seventh switching element may be turned on in response to the gate low voltage. The fourth switching element and the fifth switching element may be turned on in response to the gate high voltage. The first switching element, the fourth switching element, and the fifth switching element may maintain an off state during the holding frame period.

[0018] During the refresh frame period, the driving period of the pixel may be divided into a first conduction bias period, an initialization period, a sampling period, a second conduction bias period, and a light-emitting period. During the first conduction bias period, the voltages of the first scan signal, the third scan signal, and the fourth scan signal may be a gate low voltage, and the voltages of the second scan signal and the light-emitting control signal may be a gate high voltage. During the initialization period, the voltages of the first to fourth scan signals and the light-emitting control signal may be a gate high voltage. During the sampling period, the voltages of the second scan signal and the fourth scan signal may be a gate low voltage synchronized with the data voltage, and the voltages of the first scan signal, the third scan signal, and the light-emitting control signal may be a gate high voltage. During the second conduction bias period, the voltages of the first scan signal, the third scan signal, and the fourth scan signal may be a gate low voltage, and the voltages of the second scan signal and the light-emitting control signal may be a gate high voltage. During the light-emitting period of the refresh frame period, the voltages of the first scan signal, the fourth scan signal, and the light-emitting control signal may be a gate low voltage, and the voltages of the second scan signal and the third scan signal may be a gate high voltage. The first to seventh switching elements may be in a turned-off state during a floating period between the first on-bias period and the initialization period, a floating period between the sampling period and the second on-bias period, and a floating period between the second on-bias period and the refresh frame period.

[0019] During the holding frame period, the driving period of the pixel may be divided into a third conduction bias period, a fourth conduction bias period and a light emitting period. During the third conduction bias period and the fourth conduction bias period, the voltages of the first scan signal, the third scan signal and the fourth scan signal may be a gate low voltage, and the voltages of the second scan signal and the light emitting control signal may be a gate high voltage. During the light emitting period of the holding frame period, the voltages of the first scan signal, the fourth scan signal and the light emitting control signal may be a gate low voltage, and the voltages of the second scan signal and the third scan signal may be a gate high voltage. The first to seventh switching elements may be in a cut-off state during a floating period between the third conduction bias period and the fourth conduction bias period and a floating period between the fourth conduction bias period and the light emitting period of the holding frame period.

[0020] According to one embodiment of the present disclosure, a method for driving a display device includes the following steps: providing a selection signal to multiple selection lines during a refresh frame period and a hold frame period; providing a data voltage to multiple data lines during the refresh frame period, and providing a first compensation voltage, a second compensation voltage, and a third compensation voltage to a pixel circuit; and providing a first compensation voltage to the data line during the hold frame period, and providing the first compensation voltage, the second compensation voltage, and the third compensation voltage to the pixel circuit.

[0021] The method may further include the step of changing at least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage.

[0022] According to the present disclosure, it is possible to drive a display device with low power by driving pixels in a hold frame by maintaining a data voltage that has been stored in a refresh frame.

[0023] According to the present disclosure, the flicker of the pixel can be improved by applying the first compensation voltage, the second compensation voltage and the third compensation voltage to the pixel, and the difference in the brightness characteristics of the pixel in the refresh frame and the hold frame can be reduced, thereby improving the image quality of the display device when the driving frequency of the pixel is reduced.

[0024] According to the present disclosure, flickering of a pixel may be minimized by optimizing a voltage level of each of a first compensation voltage, a second compensation voltage, and a third compensation voltage according to a location of the pixel.

[0025] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0027] Figure 1 is a block diagram showing a display device according to one embodiment of the present disclosure;

[0028] Figure 2 It is shown Figure 1 A cross-sectional view of the cross-sectional structure of the display panel shown;

[0029] Figure 3 is a schematic diagram schematically illustrating a display device of a mobile terminal;

[0030] Figure 4 is a circuit diagram showing a pixel circuit according to one embodiment of the present disclosure;

[0031] Figure 5 is a waveform diagram showing a compensation voltage according to one embodiment of the present disclosure;

[0032] FIG. 6A to FIG. 6E is a waveform diagram showing brightness characteristics according to a driving frequency and a compensation voltage of a pixel;

[0033] Figure 7 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure;

[0034] Figure 8is a waveform diagram showing a strobe signal and a data voltage generated during a refresh frame;

[0035] Fig.9A is a circuit diagram illustrating the operation of a pixel circuit in a first on-bias period of a refresh frame;

[0036] Fig. 9B is a circuit diagram showing the operation of a pixel circuit in an initialization period of a refresh frame;

[0037] Fig. 9C is a circuit diagram illustrating the operation of a pixel circuit in a sampling period of a refresh frame;

[0038] Fig.9D is a circuit diagram illustrating the operation of a pixel circuit in a second on-bias period of a refresh frame;

[0039] Fig.9E is a circuit diagram showing the operation of a pixel circuit in a light emission period of a refresh frame;

[0040] Fig.10 is a waveform diagram showing a strobe signal and a first compensation voltage generated during a hold frame;

[0041] Fig.11A is a circuit diagram showing the operation of a pixel circuit in an on-bias period of a hold frame;

[0042] Fig. 11B is a circuit diagram showing the operation of a pixel circuit in a floating period of a hold frame;

[0043] Fig. 11C is a circuit diagram showing the operation of a pixel circuit in a light emission period of a refresh frame;

[0044] Fig.12 is a schematic diagram showing an example of a pixel to which different compensation voltages are applied according to the position of a display area;

[0045] Fig.13 is a waveform diagram showing a compensation voltage according to another embodiment of the present disclosure;

[0046] Fig.14 is a schematic diagram showing a compensation voltage generator according to one embodiment of the present disclosure; and

[0047] Fig.15 is a schematic diagram showing a step-variable method and a linear variable method for compensating voltage. DETAILED DESCRIPTION

[0048] From the embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for implementing the present disclosure will be more clearly understood. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only limited within the scope of the appended claims.

[0049] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, when describing the present disclosure, a detailed description of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0050] Terms such as "include," "comprise," "have," and "contain" used herein are generally intended to allow for the addition of other components unless the term is used with the term "only." Any reference to the singular may include the plural unless explicitly stated otherwise.

[0051] Even if not explicitly stated, components are interpreted as including normal margins of error.

[0052] When describing the position or interconnection relationship between two components (for example, "on", "above", "below", "adjacent to", "connected or coupled to", "crossing", "intersecting", etc.), unless "immediately" or "directly" is used, one or more other components may be inserted between the two components.

[0053] When describing a temporal sequence relationship (eg, "after," "subsequently," "next," "before," etc.), unless "immediately" or "directly" is used, it may not be continuous on a temporal basis.

[0054] The terms “first”, “second”, etc. may be used to distinguish elements from each other, but the function or structure of a component is not limited by the preceding sequence numbers or component names.

[0055] The following embodiments can be combined or combined with each other in part or in whole, and can be linked and operated in different ways in technology. These embodiments can be performed independently or in association with each other.

[0056] The pixel circuit and gate drive circuit of the display device may include a plurality of transistors. The transistor may be implemented as a thin film transistor (TFT). The transistor may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor, a low temperature polysilicon TFT (LTPS TFT) including low temperature polysilicon, etc.

[0057] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers begin to flow out from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a current direction flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0058] The gating signal swings between a gate-on voltage and a gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gating high voltage VGH, and the gate-off voltage may be a gating low voltage VGL. In the case of a p-channel transistor, the gate-on voltage may be a gating low voltage VGL, and the gate-off voltage may be a gating high voltage VGH.

[0059] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 is a block diagram showing a display device according to one embodiment of the present disclosure. Figure 2 It is shown Figure 1 A cross-sectional view of the cross-sectional structure of the display panel shown. Figure 3 is a schematic diagram schematically showing a display device of a mobile terminal.

[0061] Reference Figures 1 to 3 A display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data into pixels 101 of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit.

[0062] The display panel 100 may be made of a plastic substrate, a thin glass substrate, a metal substrate, etc. Pixels 101 are implemented on the display panel 100 .

[0063] The display panel 100 may be, but is not limited to, a panel having a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 may also include a power line commonly connected to the pixel 101. The power line is connected to a constant voltage node of the pixel circuit, and a constant voltage required to drive the pixel 101 is provided to the pixel 101.

[0064] Each of the pixels 101 can be divided into a red sub-pixel, a green sub-pixel and a blue sub-pixel for color realization. Each pixel can also include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. Each of the pixel circuits is connected to a data line, a gate line and a power line. In the following, "pixel" can be interpreted as having the same meaning as "sub-pixel".

[0065] The pixels may be arranged in the form of true color pixels and pentile pixels. Pentile pixels may achieve a higher resolution than true color pixels by driving two sub-pixels with different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for the insufficient color representation in each pixel with the color of the light emitted from its neighboring pixels.

[0066] The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes a row of pixels arranged along a row direction (X-axis direction) in the pixel array of the display panel 100. Pixels arranged in one pixel row share a gate line 103. Sub-pixels arranged in a column direction (Y) along a data line direction share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0067] The display panel 100 may be implemented with a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual object in the background is visible. The display panel 100 may be made into a flexible display panel.

[0068] like Figure 2 As shown, the cross-sectional structure of the display panel 100 may include a circuit layer CIR, a light emitting element layer EMIL, and an encapsulation layer ENC stacked on a substrate SUBS.

[0069] The circuit layer CIR may include a thin film transistor (TFT) array including pixel circuits connected to wirings such as data lines, gate lines, power lines, etc., a demultiplexer array 112, and a gate driver 120. The circuit layer CIR includes a plurality of metal layers and semiconductor material layers insulated with an insulating layer interposed therebetween.

[0070] The light emitting element layer EMIL may include a light emitting element driven by a pixel circuit. The light emitting element EL may include a light emitting element of a red sub-pixel, a light emitting element of a green sub-pixel, and a light emitting element of a blue sub-pixel. The light emitting element layer EMIL may also include a light emitting element of a white sub-pixel. The light emitting element layer EMIL of each of the sub-pixels may have a structure stacked with a light emitting element and a color filter. The light emitting element EL in the light emitting element layer EMIL may be covered by a plurality of protective layers including an organic film and an inorganic film.

[0071] The encapsulation layer ENC covers the light emitting element layer EMIL to seal the circuit layer CIR and the light emitting element layer EMIL. The encapsulation layer ENC may also have a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic film prevents the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture and oxygen becomes longer compared to a single layer, thereby effectively preventing the penetration of moisture and oxygen that affect the light emitting element layer EMIL.

[0072] A touch sensor layer (not shown) may be formed on the encapsulation layer ENC, and a polarizer or a color filter layer may be disposed thereon. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after a touch input. The touch sensor layer may include a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The insulating film may insulate the portion where the metal wiring pattern intersects, and may flatten the surface of the touch sensor layer. The polarizer may improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer. The polarizer may be implemented as a circular polarizer or a polarizer bonded to a linear polarizer and a phase delay film. The cover glass may be bonded to the polarizer. The color filter layer may include a red filter, a green filter, and a blue filter. The color filter layer may also include a black matrix pattern. The color filter layer may replace the polarizer by absorbing a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer, and improve the color purity of the image reproduced in the pixel array.

[0073] The power supply 140 generates a constant voltage (or direct current (DC) voltage) required to drive the pixel array and the display panel driving circuit of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 may adjust the level of the DC input voltage applied from the host system 200 to output constant voltages such as a gamma reference voltage, a gate high voltage, a gate low voltage, a pixel driving voltage, a cathode voltage, and an initialization voltage. The gamma reference voltage is provided to the data driver 110. The dynamic range of the data voltage output from the data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest grayscale voltage and the lowest grayscale voltage.

[0074] The gate high voltage and the gate low voltage are supplied to the level shifter 150 and the gate driver 120. Constant voltages such as a pixel driving voltage, a cathode voltage, and an initialization voltage are supplied to the pixels 101 via power lines commonly connected to the pixels 101.

[0075] The pixel driving voltage may be output from a main power source of the host system 200 and provided to the display panel 100. In this case, the power source 140 does not need to output the pixel driving voltage.

[0076] The display panel driving circuit writes pixel data of an input image into pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120. The display panel driving circuit may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0077] The demultiplexer array 112 sequentially supplies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switching elements disposed on the display panel 100. When the demultiplexer is disposed between the output terminal of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

[0078] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated into one driver integrated circuit (IC). In a mobile terminal or a wearable terminal, for example Figure 3 As shown, the timing controller 130 , the power supply 140 , the level shifter 150 , the data driver 110 , the touch sensor driver, the compensation voltage generator, etc. may be integrated into one driving IC (DIC).

[0079] The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130, and outputs a data voltage. The data driver 110 converts the pixel data of the input image into a gamma compensation voltage using a digital-to-analog converter (DAC) to output the data voltage. The gamma reference voltage (VGMA) is divided into a gamma compensation voltage for each grayscale by a voltage divider circuit in the data driver 110 and provided to the DAC. The DAC generates a data voltage as a gamma compensation voltage corresponding to the grayscale value of the pixel data. The data voltage from the DAC can be output to the data line 102 from the corresponding channel of the data driver 110 through the output buffer, or can be output to the data line 102 through the demultiplexer array 112.

[0080] The gate driver 120 may be formed in a circuit layer CIR on the display panel 100 together with the TFT array and wiring of the pixel array. The gate driver 120 may be disposed in a non-display area BZ outside the display area AA in the display panel 100, or at least a portion thereof may be disposed in the display area AA.

[0081] The gate driver 120 may include a plurality of shift registers for sequentially shifting pulses of a gate signal. The gate driver 120 may be disposed in any one of a left non-display area BZ or a right non-display area BZ outside the display area AA in the display panel 100, thereby providing a gate signal to the gate line 103 in a single-feed method. In the single-feed method, the gate signal is applied to one end of the gate line. The gate driver 120 may be disposed in the left non-display area BZ and the right non-display area BZ in the display panel 100, thereby applying a gate signal to the gate line 103 in a dual-feed method. In the dual-feed method, the gate signal is simultaneously applied to both ends of the gate line 103. At least some circuits of the gate driver 120 may be disposed in the display area AA.

[0082] The gate driver 120 sequentially outputs pulses of a gate signal to the gate line 103 under the control of the timing controller 130. The gate driver 120 may sequentially provide the gate signal to the gate line 103 by shifting the pulses of the gate signal using a shift register. The gate driver 120 may use a plurality of shift registers to output a plurality of gate signals having different phases, pulse widths, etc. In an organic light emitting display device, the gate signal may include a scan signal and a light emitting control signal (hereinafter referred to as an "EM signal").

[0083] The timing controller 130 receives the digital video data of the input image and the timing signal synchronized with the data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has an interval of one horizontal period (1H).

[0084] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a MUX control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The timing controller 130 synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0085] The gate timing control signal generated from the timing controller 130 may be input to the shift register in the gate driver 120 through the level shifter 150. The gate timing control signal may include a start pulse, a clock, etc. The level shifter 150 may receive the gate timing control signal to generate a start pulse and a shift clock, and provide them to the gate driver 120 through the clock lines CL1 to CLn. The level shifter 150 may provide a MUX control signal to the demultiplexer array 112. The input signal of the level shifter 150 may be a signal of a digital signal voltage level, and the output signal of the level shifter 150 may be an analog voltage signal swinging between a gate high voltage VGH and a gate low voltage VGL.

[0086] The host system 200 may include a mainboard of any one of a television system, a set-top box, a navigation system, a personal computer (PC), a vehicle-mounted system, a mobile terminal, or a wearable terminal. The host system may scale the image signal from the video source to match the resolution of the display panel 100, and may send it to the timing controller 130 together with the timing signal.

[0087] In a mobile system, the host system 200 may be implemented by an application processor (AP). The host system 200 may send pixel data of an input image to a processor via a mobile industry processor interface (MIPI). Figure 3 The driver IC (DIC) shown in the figure. Figure 3As shown, the host system 200 may be connected to the driver IC (DIC) through a flexible printed circuit (FPC). The driver IC may be bonded to the display panel 100 in a chip on glass (COG) process. The driver IC may be mounted on a flexible circuit film and electrically connected to wiring on the display panel 100.

[0088] The display panel driving circuit may include a compensation voltage generator 160 that outputs compensation voltages Vpark, VOBS, and VAR. At least a portion of the compensation voltage generator 160 may use resources from other components such as the power supply 140, the data driver 110, the display panel 100, etc. The compensation voltage generator 160 may change the voltage level of each of the compensation voltages Vpark, VOBS, and VAR under the control of the timing controller 130. The power supply 140 may be implemented as a single power IC together with the compensation voltage generator 160.

[0089] Each of the sub-pixels includes a driving element for driving a light emitting element and a pixel circuit including a capacitor connected to the driving element. The pixel circuit of each of the sub-pixels may include an internal compensation circuit to compensate the data voltage by a threshold voltage of the driving element.

[0090] Figure 4 is a circuit diagram showing a pixel circuit according to one embodiment of the present disclosure. Figure 5 is a waveform diagram showing a compensation voltage according to one embodiment of the present disclosure.

[0091] Reference Figure 4 and Figure 5 The pixel circuit includes a light emitting element EL, a driving element DT for driving the light emitting element EL, a plurality of switching elements M01, M02 and M03, and a capacitor Cst. The driving element DT and the switching elements M01, M02 and M03 may be implemented as transistors.

[0092] The pixel circuit may be connected to a data line DL, a plurality of gate lines, and a plurality of power lines. A gate signal is applied to Figure 4 The power lines may include a constant voltage node to which the pixel driving voltage ELVDD is applied, a power line to which the cathode voltage ELVSS is applied, and power lines PL1 and PL2 to which the compensation voltages VOBS and VAR are applied. The power lines may be commonly connected to all sub-pixels.

[0093] The driving element DT generates a current for driving the light emitting element EL according to its gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The pixel driving voltage ELVDD is applied to the second node n2. The switching element omitted in the figure may be connected to the second node n2. The switching element may provide the pixel driving voltage ELVDD to the second node n2 in response to the gate-on voltage of the gating signal.

[0094] The light emitting element EL may be implemented as an OLED or an inorganic LED. The OLED includes an anode electrode, a cathode electrode, and an organic compound layer interposed between these electrodes. The anode electrode of the light emitting element EL is electrically connected to the third node n3, and the cathode electrode thereof is provided with a cathode voltage ELVSS. Figure 7 As shown, the anode electrode of the light emitting element EL can be connected to the fourth node n4. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode electrode and the cathode electrode of the light emitting element EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons. In this case, visible light is emitted from the light emitting layer EML. The OLED can be implemented as an OLED having a tandem structure in which a plurality of light emitting layers are stacked. The OLED having a tandem structure can improve the brightness and life of the pixel.

[0095] A switching element omitted in the figure may be connected between the third node n3 and the anode electrode of the light emitting element EL. The switching element may electrically connect the third node n3 to the anode of the light emitting element EL in response to a gate-on voltage of a gate signal.

[0096] The capacitor Cst is connected between a node on the power line to which the pixel driving voltage ELVDD is applied and the first node n1 to store the gate-source voltage Vgs of the driving element DT.

[0097] The first switching element M01 is connected between the second node n2 and the data line DL. The first switching element M01 electrically connects the data line DL to the second node n2 in response to the gate-on voltage of the first selection signal. The data voltage Vdata of the pixel data or the first compensation voltage Vpark is applied to the data line DL. Therefore, the first switching element M01 provides the data voltage Vdata applied through the data line DL to the second node n2. The first switching element M01 is turned on in response to the gate-on voltage of the first selection signal during the refresh frame period, and remains in an off state during the hold frame period.

[0098] When writing pixel data to the pixel, the data voltage Vdata of the pixel data is applied to the data line DL during the refresh frame period. The first compensation voltage Vpark is set to a voltage for compensating for the brightness change of the pixel, and is applied to the data line DL during the hold frame period when no pixel data is written to the pixel. During the hold frame, the pixel 101 is driven using the data voltage Vdata charged to the capacitor Cst in the previous refresh frame.

[0099] When the data line DL and the second node n2 are electrically connected by means of the turned-on second switching element M02, the data voltage Vdata is applied to the second node n2. In the cut-off state of the first switching element M01 (i.e., in the state where the data line DL and the second node n2 are electrically disconnected), the first compensation voltage Vpark can be applied to the second node n2 as the leakage current of the second switching element M02, and can be applied to the first node n1 by means of parasitic capacitance. Here, the parasitic capacitance may include a parasitic capacitance existing between the first node n1 and the second node n2 and a parasitic capacitance existing between the first node n1 and the data line DL. The gate-source voltage Vgs of the driving element DT can be fine-tuned by the first compensation voltage Vpark.

[0100] The second switching element M02 is connected between the first power line PL1 and the second node n2. During the on-bias period set in each of the refresh frame period and the hold frame period, the second compensation voltage VOBS may be applied to the first power line PL1. The second compensation voltage VOBS may be set to increase the on-bias voltage of the gate-source voltage Vgs of the driving element DT so that the driving element DT may always be driven with the same driving characteristics.

[0101] The second switching element M02 is turned on in the OBS period of each of the refresh frame period and the hold frame period in response to the gate-on voltage of the second gate signal. When the second switching element M02 is turned on, the second compensation voltage VOBS may be applied to the second node n2 through the second switching element M02.

[0102] The third switching element M03 is connected between the second power line PL2 and the anode electrode of the light emitting element EL. The third compensation voltage VAR can be provided to the second power line PL2. The third compensation voltage VAR can be set to different voltages between the refresh frame period and the hold frame period. During the hold frame period, the third compensation voltage VAR can be applied to the anode electrode of the light emitting element EL at a higher voltage to affect the brightness of the light emitting element EL in the hold frame. The third compensation voltage VAR can reduce the brightness difference of the pixel between the refresh frame and the hold frame (specifically, the brightness difference of the low grayscale).

[0103] The third switching element M03 is turned on in response to the gate high voltage VGH of the second gate signal in the refresh frame and the hold frame. When the third switching element M03 is turned on, the third compensation voltage VAR may be applied to the anode of the light emitting element EL through the third switching element M03.

[0104] like Figure 5 As shown, the first compensation voltage Vpark may be a constant voltage or a variable voltage applied to the data line DL during the hold frame HF. During the refresh frame RF, a data voltage Vdata of the pixel data may be applied to the data line DL.

[0105] like Figure 5 As shown, the second compensation voltage VOBS and the third compensation voltage VAR can be generated as an AC voltage that changes between the refresh frame RF and the hold frame HF. The high voltage (H) in the second compensation voltage VOBS and the third compensation voltage VAR can be set to different voltages. The low voltage (L) in the second compensation voltage VOBS and the third compensation voltage VAR can be set to different voltages. The second compensation voltage VOBS and the third compensation voltage VAR can be generated as a high voltage (H) in the refresh frame RF and a low voltage (L) in the hold frame HF. Therefore, the second compensation voltage VOBS and the third compensation voltage VAR can change their voltages between the refresh frame RF and the hold frame HF.

[0106] Reference Figure 5 , the first compensation voltage Vpark may be applied to the data line DL in the hold frame HF. The second compensation voltage VOBS may be generated as a high voltage (H) in the refresh frame RF, and may be generated as a low voltage (L) in the hold frame HF. The second compensation voltage VOBS may change its voltage level during the vertical blanking period between the refresh frame RF and the hold frame HF. The third compensation voltage VAR may be generated as a high voltage (H) in the refresh frame RF, and may be generated as a low voltage (L) in the hold frame HF. The third compensation voltage VAR may increase its voltage level during the vertical blanking period between the refresh frame RF and the hold frame HF.

[0107] FIG. 6A to FIG. 6E is a waveform diagram showing brightness characteristics according to the driving frequency and compensation voltage of a pixel. Flicker can be measured based on the amount of change in brightness of a pixel on the time axis. FIG. 6A to FIG. 6D The brightness characteristics of a pixel are shown, in which flicker caused by a change in the threshold voltage characteristics of the driving element according to a change in the driving frequency of the pixel is measured in the pixel when the compensation voltages Vpark, VOBS, and VAR are not applied to the pixel. Fig. 6E 1 shows the improvement of the brightness characteristics of the pixel when the first to third compensation voltages Vpark, VOBS and VAR are applied to the pixel. FIG. 6A to FIG. 6E, "F#" indicates frame numbers from the first frame to the 120th frame (1 to 120 frames). "REF" indicates a brightness reference value representing the brightness of a pixel when a data voltage having the same white gray value is applied to the pixel.

[0108] Fig. 6A 1 shows the brightness characteristics of the pixel when the pixel is driven at a refresh frame frequency of 120 Hz. Fig. 6A In the embodiment, a data voltage Vdata having pixel data of 120 Hz per frame is provided to the pixel. In this case, because the data voltage Vdata is applied per frame, when the applied data voltage Vdata is the same, the brightness of the pixel is measured as constant, and thus the flicker is not visible. In this case, the flicker value of the pixel can be constantly measured as the same value.

[0109] Figure 6B 1 shows the brightness characteristics of the pixel when the pixel is driven at a refresh frame frequency of 10 Hz. Figure 6B In the embodiment, the data voltage Vdata is applied to the pixels in the refresh frames (1, ... 109) which are set to have a time interval of 12 frame periods in one second (1s), and the data voltage Vdata is not applied to the pixels in the hold frames (2 to 12, ... 110 to 120) between the refresh frames. The brightness of the pixels may decrease in the refresh frames (1, ... 109), and the threshold voltage Vth characteristic of the driving element DT may change during the hold frame (2 to 12, ... 110 to 120) cycle, so that the brightness of the pixels increases over time due to the change in the gate-source voltage Vgs. In this case, the brightness of the pixels fluctuates at a periodic rate of 10 Hz, so that a flicker of 10 Hz can be measured.

[0110] Figure 6C 1 shows the brightness characteristics of the pixel when the pixel is driven at a refresh frame frequency of 10 Hz, where the off-duration is set for each frame period. Here, the off-duration is the time interval during which the light emitting element EL is turned off by the gate off voltage branch of the EM signal. Figure 6C In the embodiment, the data voltage Vdata is applied to the pixels in the refresh frame which is set to have a time interval of 12 frame periods in one second (1s), and the data voltage Vdata is not applied to the pixels in the hold frames (2 to 12, ... 110 to 120). The brightness of the pixels may decrease in the refresh frames (1, ... 109), and the brightness of the pixels may change during the hold frame periods (2 to 12, ... 110 to 120) due to changes in the gate-source voltage of the driving element DT. In this case, the brightness of the pixels fluctuates at a periodic rate of 10 Hz, so that a flicker of 10 Hz can be measured. Figure 6C In FIG. 1 , the dotted circle indicates the period during which the brightness of the pixel changes.

[0111] Fig.6D 1 shows the brightness characteristics of a pixel when the pixel is driven at a refresh frame frequency of 10 Hz, where the off-duration is set for each frame period. Fig.6D In the embodiment, the data voltage Vdata is applied to the pixels in the refresh frame (1, ... 109) which is set to have a time interval of 12 frame periods in one second (1s), and the data voltage Vdata is not applied to the pixels in the hold frame (2-12, ... 110-120). When the second compensation voltage VOBS is applied to the second node n2 of the pixel circuit during the periods of the refresh frame (1, ... 109) and the hold frame (2-12, ... 110-120), the brightness difference of the pixel decreases during the period of the hold frame (2-12, ... 110-120). In this case, as shown by the dotted circle, the brightness of the pixel may be lower in the period of the refresh frame (1, ... 109) than in the period of the hold frame (2-12, ... 110-120). In this case, the brightness of the pixel fluctuates at a period rate of 10 Hz, so that a flicker of 10 Hz can be measured.

[0112] Fig. 6E 1 shows the brightness characteristics of a pixel when the pixel is driven at a refresh frame frequency of 10 Hz, where the off-duration is set for each frame period. Fig. 6E In the embodiment, the data voltage Vdata is applied to the pixels in the refresh frame (1, ... 109) set to have a time interval of 12 frame periods in one second (1s), and the data voltage Vdata is not applied to the pixels in the hold frame (2-12, ... 110-120). When the first to third compensation voltages Vpark, VOBS and VAR are applied to the pixel circuit during the period of the hold frame (2-12, ... 110-120), the brightness difference of the pixel is further reduced between the periods of the refresh frame (1, ... 109) and the hold frame (2-12, ... 110-120). In this case, the brightness difference of the pixel can be minimized to the extent that no flicker is measured during the periods of the refresh frame (1, ... 109) and the hold frame (2-12, ... 110-120).

[0113] The first compensation voltage Vpark is applied to the data line DL during the hold frame (2-12, ...110-120). The second compensation voltage VOBS and the third compensation voltage VAR may be generated as an AC voltage, where the voltage changes between the refresh frame RF and the hold frame HF, and applied to the power lines PL1 and PL2.

[0114] Figure 7 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure.

[0115] Reference Figure 7The pixel circuit includes a light emitting element EL, a driving element DT for driving the light emitting element EL, a plurality of switching elements M1 to M7, and a capacitor Cst.

[0116] The fourth switching element M4 and the fifth switching element M5 may each be implemented as an n-channel oxide TFT having a low off-current characteristic. The driving element DT and the first switching element M1, the second switching element M2, the third switching element M3, the sixth switching element M6, and the seventh switching element M7 may be implemented as a p-channel LTPS TFT having a high on-current characteristic. Figure 8 and Fig.10 As shown, the n-channel oxide TFT is turned on in response to the gate high voltage VGH, and is turned off in response to the gate low voltage VGL. Figure 8 and Fig.10 As shown, the p-channel LTPS TFT is turned on in response to the gate low voltage VGL, and is turned off in response to the gate high voltage VGH.

[0117] The pixel circuit is connected to the data line DL to which the data voltage Vdata of the pixel data and the first compensation voltage Vpark are applied, and is connected to the gate lines GL1 to GL5 to which the selection signals SC1 to SC4 and EM are applied. The data driver 110 supplies the data voltage Vdata to the data line DL in the refresh frame RF, and does not output the data voltage Vdata in the hold frame. In the hold frame, the first compensation voltage Vpark is supplied to the data line DL. The first compensation voltage Vpark may be output from the compensation voltage generator 160.

[0118] The pixel circuit may be connected to a first power line PL1 to which a second compensation voltage VOBS is applied, a second power line PL2 to which a third compensation voltage VAR is applied, a third power line PL3 to which a pixel driving voltage ELVDD is applied, a fourth power line PL4 to which a cathode voltage ELVSS is applied, and a fifth power line PL5 to which an initialization voltage Vinit is applied. On the display panel, the power lines PL1 to PL5 may be commonly connected to all pixels 101.

[0119] The pixel driving voltage ELVDD and the cathode voltage ELVSS are set to voltages that allow the driving element DT to operate in a saturation region. The pixel driving voltage ELVDD may be set to a voltage between 2 [V] and 3 [V], and the cathode voltage ELVSS may be set to a voltage between -8 [V] and -10 [V], but are not limited thereto. The gate high voltage VGH may be set to a voltage higher than the pixel driving voltage ELVDD, and the gate low voltage VGL may be set to a voltage lower than the cathode voltage ELVSS, but are not limited thereto.

[0120] The data voltage Vdata may have a dynamic range between 2 [V] and 6 [V]. Within the dynamic range, the voltage level of the data voltage Vdata is selected according to the grayscale value of the pixel data. The initialization voltage Vinit may be set to, but not limited to, a voltage lower than the lower limit of the data voltage Vdata and higher than the cathode voltage ELVSS. For example, when the data voltage Vdata has a lower limit voltage of 2 [V] and the cathode voltage ELVSS has a lower limit voltage of -9 [V], the initialization voltage Vinit may be set to a voltage between -5 [V] and -7 [V].

[0121] The first compensation voltage Vpark may be set within a voltage range within the dynamic range that is smaller than the dynamic range of the data voltage Vdata. For example, when the data voltage Vdata has a dynamic range between 2 [V] and 6 [V], the first compensation voltage Vpark may be set as follows: Figure 5 The voltage of the first compensation voltage Vpark may be varied according to the pixel position of the display area AA based on the flicker measurement value identified for each position of the display area AA, such as Fig.13 shown.

[0122] The second compensation voltage VOBS may be set within a voltage range partially overlapping with the dynamic range of the data voltage Vdata. For example, when the data voltage Vdata has a dynamic range between 2 [V] and 6 [V], the second compensation voltage VOBS may be set as follows: Figure 5 The voltage of the second compensation voltage VOBS may be varied according to the pixel position of the display area AA based on the flicker measurement value identified for each position of the display area AA, such as Fig.13 shown.

[0123] The third compensation voltage VAR may be set to a specific voltage, or may vary. For example, when the data voltage Vdata has a dynamic range between 2 [V] and 6 [V], the third compensation voltage VAR may be set to a specific voltage, or may vary. Figure 5 The third compensation voltage VAR may be set to a specific voltage between -4 [V] and -8 [V] as shown, or may vary within this voltage range. Based on the flicker measurement value identified for each position of the display area AA, the voltage of the third compensation voltage VAR may vary according to the pixel position of the display area AA, such as Fig.13 shown.

[0124] The compensation voltages Vpark, VOBS, and VAR applied to one sub-pixel present at a specific position in the display area AA may be set to different voltages.

[0125] The gate signals SC1 to SC4 and EM may include pulses swinging between a gate high voltage VGH and a gate low voltage VGL. Figure 7 In the pixel circuit shown, the gate driver 120 may include a first shift register outputting a first scan signal SC1, a second shift register outputting a second scan signal SC2, a third shift register outputting a third scan signal SC3, a fourth shift register outputting a fourth scan signal SC4, and a fifth shift register outputting an EM signal EM. Each of the first to fifth shift registers outputs a pulse and sequentially shifts the pulse during a refresh frame. The first shift register, the second shift register, and the fourth shift register have very low power consumption because they do not output a pulse during a hold frame HF.

[0126] The driving element DT includes a gate connected to a first node n1, a first electrode connected to a second node n2, and a second electrode connected to a third node n3. The capacitor Cst is connected between a node on the third power line PL3 to which the pixel driving voltage ELVDD is applied and the first node n1.

[0127] The light emitting element EL includes an anode electrode connected to the fourth node n4 and a cathode electrode connected to the fourth power line PL4 to which the cathode voltage ELVSS is applied.

[0128] The first switching element M1 is connected between the data line D1 and the second node n2. The first switching element M1 is turned on in response to the gate low voltage VGL of the second scan signal SC2. When the first switching element M1 is turned on, the data line DL to which the data voltage Vdata of the pixel data is applied is connected to the second node n2. The first switching element M1 includes a gate electrode connected to the second gate line GL2 to which the second scan signal SC2 is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0129] The second switching element M2 is connected between the second node n2 and the first power line PL1 to which the second compensation voltage VOBS is applied. The second switching element M2 is turned on in response to the gate low voltage VGL of the third scan signal SC3. When the second switching element M2 is turned on, the second compensation voltage VOBS is applied to the second node n2. The second switching element M2 includes a gate connected to the third gate line GL3 to which the third scan signal SC3 is applied, a first electrode connected to the second node n2, and a second electrode connected to the first power line PL1.

[0130] The third switch element M3 is connected between the fourth node n4 and the second power line PL2 to which the third compensation voltage VAR is applied. The third switch element M3 is turned on in response to the gate low voltage VGL of the third scan signal SC3. When the third switch element M3 is turned on, the third compensation voltage VAR is applied to the anode electrode of the light emitting element EL connected to the fourth node n4. The third switch element M3 includes a gate electrode connected to the third gate line GL3, a first electrode connected to the fourth node n4, and a second electrode connected to the second power line PL2.

[0131] The fourth switching element M4 is connected between the first node n1 and the fifth power line PL5 to which the initialization voltage Vinit is applied. The fourth switching element M4 is turned on in response to the gate high voltage VGH of the fourth scan signal SC4. When the fourth switching element M4 is turned on, the initialization voltage Vinit is applied to the gate electrode of the capacitor Cst and the driving element DT. The fourth switching element M4 includes a gate electrode connected to the fourth gate line GL4 to which the fourth scan signal SC4 is applied, a first electrode connected to the first node n1, and a second electrode connected to the fifth power line PL5.

[0132] The fifth switch element M5 is connected between the first node n1 and the third node n3. The fifth switch element M5 is turned on in response to the gate high voltage VGH of the first scan signal SC1. When the fifth switch element M5 is turned on, the first node n1 is connected to the third node n3. Therefore, when the fifth switch element M5 is turned on, the driving element DT operates as a diode, and its gate electrode is connected to the second electrode. The fifth switch element M5 includes a gate electrode connected to the first gate line GL1 to which the first scan signal SC1 is applied, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0133] The sixth switch element M6 is connected between the third power line PL3 to which the pixel driving voltage ELVDD is applied and the second node n2. The sixth switch element M6 is turned on in response to the gate low voltage VGL of the EM signal EM. When the sixth switch element M6 is turned on, the pixel driving voltage ELVDD is applied to the second node n2. The sixth switch element M6 includes a gate electrode connected to the fifth gate line GL5 to which the EM signal EM is applied, a first electrode connected to the third power line PL3, and a second electrode connected to the second node n2.

[0134] The seventh switching element M7 is connected between the third node n3 and the fourth node n4. The seventh switching element M7 is turned on in response to the gate low voltage VGL of the EM signal EM to connect the third node n3 to the fourth node n4. The seventh switching element M7 includes a gate electrode connected to the fifth gate line GL5, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0135] Figure 8 is a waveform diagram showing a strobe signal and a data voltage generated during a refresh frame RF. 9A to 9E is a circuit diagram showing the operation of the pixel circuit during a refresh frame RF in stages.

[0136] Reference Figure 8 During the refresh frame RF, the driving period of the pixel can be divided into a first conduction bias period OBS1, an initialization period INI, a sampling period SAM, a second conduction bias period OBS2 and a light emitting period EMI. The first floating period Tf1 can be set between the first conduction bias period OBS1 and the initialization period INI. The second floating period Tf2 can be set between the sampling period SAM and the second conduction bias period OBS2. The third floating period Tf3 can be set between the second conduction bias period OBS2 and the light emitting period EMI.

[0137] During the first on-bias period OBS1, the voltages of the first scan signal SC1, the third scan signal SC3, and the fourth scan signal SC4 are the gate low voltage VGL, and the voltage of the second scan signal SC2 is the gate high voltage VGH. During the first on-bias period OBS1, the voltage of the EM signal EM is the gate high voltage VGH. Therefore, during the first on-bias period OBS1, the second switching element M2 and the third switching element M3 are switched on. Fig.9A The transistor is turned on as shown to apply the second compensation voltage VOBS to the second node n2 and the third compensation voltage VAR to the fourth node n4.

[0138] During the first on-bias period OBS1, the first switch element M1, the fourth switch element M4, the fifth switch element M5, the sixth switch element M6 and the seventh switch element M7 are in the off state. Fig.9A As shown. During the first on-bias period OBS1, the driving element DT can be turned on, but because the seventh switch element M7 is in the off state, no current can be provided to the light emitting element EL. In addition, because the voltage difference between the third compensation voltage VAR and the cathode voltage ELVSS is less than the threshold voltage of the light emitting element EL, the light emitting element EL does not emit light during the first on-bias period OBS1.

[0139] During the first on-bias period OBS1, the driving element DT is turned on so that the voltages of the second node n2 and the third node n3 become the second compensation voltage VOBS, and the voltage of the fourth node n4 becomes the third compensation voltage VAR. In this case, the voltage of the first node n1 may be a voltage Vdata+Vth obtained by adding the threshold voltage Vth of the driving element DT to the previously stored data voltage Vdata.

[0140] During the first floating period Tf1, the voltages of the first scan signal SC1 and the fourth scan signal SC4 are the gate low voltage VGL, and the voltages of the second scan signal SC2 and the third scan signal SC3 are the gate high voltage VGH. During the first floating period Tf1, the voltage of the EM signal EM is the gate high voltage VGH. Therefore, during the first floating period Tf1, since the first to seventh switching elements M1 to M7 are all in the off state, the first to fourth nodes n1, n2, n3 and n4 are floated to maintain their previous states.

[0141] During the initialization period INI, the voltages of the first to fourth scan signals SC1, SC2, SC3, and SC4 and the EM signal EM are the gate high voltage VGH. Fig. 9B As shown, the fourth switching element M4 and the fifth switching element M5 are turned on to apply the initialization voltage Vinit to the first node n1 and the third node n3, and also apply the initialization voltage Vinit to the second node n2 through the driving element DT maintained in the on state. During the initialization period INI, the light emitting element EL is in the off state and does not emit light.

[0142] During the initialization period INI, the voltages of the first, second and third nodes n1, n2 and n3 are the initialization voltage Vinit. During the initialization period INI, since the third and seventh switching elements M3 and M7 are in the off state, the fourth node n4 is floated to maintain its previous state.

[0143] During the sampling period SAM, the voltage of the second scan signal SC2 is generated by a scan pulse of the gate low voltage VGL synchronized with the data voltage Vdata of the pixel data and then converted to the gate high voltage VGH. During the sampling period SAM, the voltages of the first scan signal SC1 and the third scan signal SC3 and the EM signal EM are the gate high voltage VGH, and the voltage of the fourth scan signal SC4 is the gate low voltage VGL. When the first switching element M1 is turned on in response to the gate low voltage of the scan pulse in the sampling period SAM, as shown in FIG. Fig. 9C As shown, the data voltage Vdata is applied to the second node n2, and the data voltage Vdata is also applied to the first node n1 and the third node n3 through the driving element DT in the on state. In this case, the voltage of the second node n2 is the data voltage Vdata, and the voltage of each of the first node n1 and the third node n3 is a voltage Vdata+Vth obtained by adding the threshold voltage Vth of the driving element DT to the data voltage Vdata. During the sampling period SAM, the fourth node n4 is in a floating state, and the light emitting element EL is in a cut-off state so as not to emit light.

[0144] During the second floating period Tf2, the voltages of the first scan signal SC1 and the fourth scan signal SC4 are the gate low voltage VGL, and the voltages of the second scan signal SC2 and the third scan signal SC3 are the gate high voltage VGH. During the second floating period Tf2, the voltage of the EM signal EM is the gate high voltage VGH. Therefore, during the second floating period Tf2, since the first to seventh switching elements M1 to M7 are all in the off state, the first to fourth nodes n1, n2, n3 and n4 are floated to maintain their previous states.

[0145] During the second on-bias period OBS2, the voltages of the first scan signal SC1, the third scan signal SC3, and the fourth scan signal SC4 are the gate low voltage VGL, and the voltage of the second scan signal SC2 is the gate high voltage VGH. During the second on-bias period OBS2, the voltage of the EM signal EM is the gate high voltage VGH. During the second on-bias period OBS2, the first switching element M1, the fourth switching element M4, the fifth switching element M5, the sixth switching element M6, and the seventh switching element M7 are in the off state, as shown in FIG. Fig.9D Therefore, during the second on-bias period OBS2, the second switch element M2 and the third switch element M3 are as shown. Fig.9D The transistor is turned on as shown to apply the second compensation voltage VOBS to the second node n2, and the third compensation voltage VAR to the fourth node n4. During the second on bias period OBS2, the light emitting element EL does not emit light.

[0146] During the second on bias period OBS2, the voltages of the second and third nodes n2 and n3 are the second compensation voltage VOBS, and the voltage of the fourth node n4 is the third compensation voltage VAR. In this case, the voltage of the first node n1 may remain in the previous state and thus may be the voltage Vdata+Vth.

[0147] During the third floating period Tf3, the voltages of the first scan signal SC1 and the fourth scan signal SC4 are the gate low voltage VGL, and the voltages of the second scan signal SC2 and the third scan signal SC3 are the gate high voltage VGH. During the third floating period Tf3, the voltage of the EM signal EM is the gate high voltage VGH. Therefore, during the third floating period Tf3, since the first to seventh switching elements M1 to M7 are all in the off state, the first to fourth nodes n1, n2, n3 and n4 are floated to maintain their previous states.

[0148] During the light emission period EMI of the refresh frame RF, the voltages of the first and fourth scan signals SC1 and SC4 and the EM signal EM are the gate low voltage VGL, and the voltages of the second and third scan signals SC2 and SC3 are the gate high voltage VGH. Fig.9E As shown, during the emission period EMI, the sixth switching element M6 and the seventh switching element M7 are turned on in response to the gate low voltage VGL of the EM signal EM. Therefore, during the emission period EMI, a current path is formed between the pixel driving voltage E1VSS and the light emitting element EL.

[0149] During the emission period EMI, a current determined by the gate-source voltage of the driving element DT flows through the light emitting element EL so that the light emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data. During the emission period EMI, the first to fifth switching elements M1 to M5 are in an off state.

[0150] Fig.10 is a waveform diagram showing a gate signal and a first compensation voltage generated during a hold frame HF.

[0151] Reference Fig.10 During the holding frame HF, the driving period of the pixel can be divided into a third conduction bias period OBS3, a fourth conduction bias period OBS4 and a light emitting period EMI. A fourth floating period Tf4 can be set between the third conduction bias period OBS3 and the fourth conduction bias period OBS4. A fifth floating period Tf5 can be set between the fourth conduction bias period OBS4 and the light emitting period EMI.

[0152] The data driver 110 does not output the data voltage Vdata during the sustain frame HF. During the sustain frame HF, the first compensation voltage Vpark is applied to the data line DL.

[0153] During the holding frame HF, the voltages of the first scan signal SC1 and the fourth scan signal SC4 are maintained at the gate low voltage VGL, and the voltage of the second scan signal SC2 is maintained at the gate high voltage VGH. Therefore, during the holding frame HF, the first switch element M1, the fourth switch element M4, and the fifth switch element M5 in the pixel circuit are maintained in the off state. During the holding frame HF, the pixel circuit can be driven by the capacitor voltage stored during the previous refresh frame RF.

[0154] During the third conduction bias period OBS3, the voltages of the first scan signal SC1, the third scan signal SC3, and the fourth scan signal SC4 are the gate low voltage VGL, and the voltage of the second scan signal SC2 is the gate high voltage VGH. During the third conduction bias period OBS3, the voltage of the EM signal EM is the gate high voltage VGH. Therefore, during the third conduction bias period OBS3, as shown in FIG. Fig.11A As shown, the second switch element M2 and the third switch element M3 are turned on to apply the second compensation voltage VOBS to the second node n2 and the third compensation voltage VAR to the fourth node n4. During the third on-bias period OBS3, the first switch element M1, the fourth switch element M4, the fifth switch element M5, the sixth switch element M6 and the seventh switch element M7 are in the off state. During the third on-bias period OBS3, the voltage of the first node n1 is maintained at the voltage Vdata+Vth, and the light emitting element EL does not emit light.

[0155] During the fourth floating period Tf4, the voltages of the first scan signal SC1 and the fourth scan signal SC4 are the gate low voltage VGL, and the voltages of the second scan signal SC2 and the third scan signal SC3 are the gate high voltage VGH. During the fourth floating period Tf4, the voltage of the EM signal EM is the gate high voltage VGH. Therefore, during the fourth floating period Tf4, since the first to seventh switching elements M1 to M7 are all in the off state, the first to fourth nodes n1, n2, n3 and n4 are floated to maintain their previous states.

[0156] During the fourth conduction bias period OBS4, the voltages of the first scan signal SC1, the third scan signal SC3, and the fourth scan signal SC4 are the gate low voltage VGL, and the voltage of the second scan signal SC2 is the gate high voltage VGH. During the fourth conduction bias period OBS4, the voltage of the EM signal EM is the gate high voltage VGH. Therefore, during the fourth conduction bias period OBS4, as shown in FIG. Fig.11A As shown, the second switch element M2 and the third switch element M3 are turned on to apply the second compensation voltage VOBS to the second node n2, and the third compensation voltage VAR is applied to the fourth node n4. During the fourth on-bias period OBS4, the first switch element M1, the fourth switch element M4, the fifth switch element M5, the sixth switch element M6 and the seventh switch element M7 are in the off state. During the fourth on-bias period OBS4, the voltage of the first node n1 is maintained at the voltage Vdata+Vth, and the light emitting element EL does not emit light.

[0157] During the fifth floating period Tf5, the voltages of the first scan signal SC1 and the fourth scan signal SC4 are the gate low voltage VGL, and the voltages of the second scan signal SC2 and the third scan signal SC3 are the gate high voltage VGH. During the fifth floating period Tf5, the voltage of the EM signal EM is the gate high voltage VGH. Therefore, during the fifth floating period Tf5, since the first to seventh switching elements M1 to M7 are all in the off state, the first to fourth nodes n1, n2, n3 and n4 are floated to maintain their previous states.

[0158] During the holding frame HF, the first compensation voltage Vpark is supplied to the data line DL. Since the second compensation voltage VOBS is applied to the second node n2 through the turned-on second switching element M2 during the on bias periods OBS3 and OBS4 of the holding frame HF, the first compensation voltage Vpark has little effect on the first node n1 and the second node n2 during the on bias periods OBS1 and OBS2.

[0159] During the floating periods Tf4 and Tf5 of the holding frame HF, since the switching elements M1 to M7 in the pixel circuit are all in the off state, the second compensation voltage VOBS is not applied to the second node n2. Fig. 11B As shown, during the floating periods Tf4 and Tf5 of the holding frame HF, the first compensation voltage Vpark may affect the voltages of the first node n1 and the second node n2 of the pixel circuit, thereby allowing the brightness of the pixel to be properly adjusted.

[0160] The first compensation voltage Vpark changes the voltage of the second node n2 by means of the leakage current of the first switch element M1. In addition, the first compensation voltage Vpark affects the voltage of the first node n1 by means of the parasitic capacitance (Cp) between the first node n1 and the second node n2, thereby changing the voltage of the first node n1. Fig. 6E As shown, the first compensation voltage Vpark can help to reduce the brightness difference of the pixels between the refresh frame RF and the hold frame HF.

[0161] During the light emission period EMI of the refresh frame HF, the voltages of the first and fourth scan signals SC1 and SC4 and the EM signal EM are the gate low voltage VGL, and the voltages of the second and third scan signals SC2 and SC3 are the gate high voltage VGH. During the light emission period EMI, the sixth switching element M6 and the seventh switching element M7 are turned on in response to the gate low voltage VGL of the EM signal EM. Therefore, as Fig. 11CAs shown, during the emission period EMI, a current path is formed between the pixel driving voltage ELVSS and the light emitting element EL. During the emission period EMI, the light emitting element EL can emit light by a current generated according to the gate-source voltage of the driving element DT stored in the capacitor Cst.

[0162] The inventors measured the flicker of the pixel at each position of the display area AA and found that the first compensation voltage Vpark, the second compensation voltage VOBS and the third compensation voltage VAR that minimize the flicker may be different according to the pixel position. Fig.12 and Fig.13 An example of a compensation voltage for optimizing flicker characteristics is shown in FIG. 1 , but is not limited thereto. The voltage value of the compensation voltage may vary according to a pixel structure or a driving method of a display panel.

[0163] Reference Fig.12 and Fig.13 , each of the first to third compensation voltages Vpark, VOBS, and VAR can be varied within a frame period to ensure that it is provided as an optimized voltage for each position of the pixel. Each of the first to third compensation voltages Vpark, VOBS, and VAR can be varied in the refresh frame RF period and the hold frame HF period, but is not limited thereto. For example, by changing the first to third compensation voltages Vpark, VOBS, and VAR in any one of the refresh frame RF period or the hold frame HF period, flicker can be improved relative to the prior art.

[0164] During the hold frame HF period, the voltage level of the first compensation voltage Vpark may continue to rise.The voltage levels of the second compensation voltage and the third compensation voltage may rise and then fall in each of the refresh frame RF period and the hold frame HF period.

[0165] For example, the compensation voltages Vpark, VOBS, and VAR applied to the pixels A1, A2, and A3 located in the upper portion of the display area AA may be as follows: Vpark=5.2[V], VOBS=7.2[V], VAR=-6.8[V]. In contrast, the compensation voltages Vpark, VOBS, and VAR applied to the pixels B1, B2, and B3 located in the central portion of the display area AA may be as follows: Vpark=5.4[V], VOBS=7.4[V], VAR=-6.7[V]. The compensation voltages Vpark, VOBS, and VAR applied to the pixels C1, C2, and C3 located in the lower portion of the display area AA may be as follows: Vpark=5.6[V], VOBS=7.2[V], VAR=-6.6[V].

[0166] The shift register of the gate driver 120 is Fig.12The scanning direction shown in FIG. 1 sequentially shifts the pulses of the selection signals SC1 to SC4 and EM. The second compensation voltage VOBS and the third compensation voltage VAR are sequentially applied to the pixel lines L1 to Ln along the pulse shift direction of the third scanning signal SC3. Therefore, the second compensation voltage VOBS and the third compensation voltage VAR can be applied to the pixel lines L1 to Ln along the pulse shift direction of the third scanning signal SC3. Fig.12 The same voltage is applied to pixels in the row direction X in FIG. 1 and different voltages are applied to pixels in the column direction Y with different scan timings.

[0167] Since the first compensation voltage Vpark is supplied to the data line DL in the column direction Y, it can be applied as a different voltage to each of the pixels arranged in the same row direction X. In addition, the first compensation voltage Vpark can be applied to the data line DL as a different voltage in each horizontal period in synchronization with the scanning of the pixels, so that a different voltage can be applied to each pixel arranged in the same column direction Y.

[0168] During the refresh frame RF, the data voltage Vdata of the pixel data is applied to the data line DL, and the gate signals SC1 to SC4 and EM are sequentially applied to the gate lines GL1 to GL5 on a pixel row basis along the scanning direction.

[0169] The refresh frame RF period may include time points t1, t2, and t3. At time t1, the data voltage Vdata and compensation voltages VOBS and VAR set to VOBS=7.2[V] and VAR=-6.6[V] may be applied to the first to third pixels A1, A2, and A3. The second compensation voltage VOBS and the third compensation voltage VAR applied to the first to third pixels A1, A2, and A3 may be generated as different voltages at time point t1. At time t2, the data voltage Vdata and compensation voltages VOBS and VAR set to VOBS=7.4[V] and VAR=-6.7[V] are applied to the fourth to sixth pixels B1, B2, and B3. Therefore, each of the second compensation voltage VOBS and the third compensation voltage VAR is changed to a higher voltage at time t2 than at time t1.

[0170] At time t3, the data voltage Vdata and the compensation voltages VOBS and VAR set to VOBS=7.2[V] and VAR=-6.6[V] may be applied to the seventh to ninth pixels C1, C2, and C3. Therefore, each of the second compensation voltage VOBS and the third compensation voltage VAR at time t3 is changed to a lower voltage than at time t2.

[0171] During the hold frame HF, the first compensation voltage Vpark is applied to the data line DL, and only the pulse of the third scan signal SC3 among the gate signals SC1 to SC4 and EM is sequentially applied to the third gate line GL3 on a pixel row basis along the scan direction.

[0172] The holding frame HF period may include time points t4, t5, and t6. At time t4, compensation voltages Vpark, VOBS, and VAR set to Vpark=[5.2V], VOBS=7.2[V], and VAR=-6.8[V] may be applied to the first to third pixels A1, A2, and A3. The compensation voltages Vpark, VOBS, and VAR applied to the first to third pixels A1, A2, and A3 may be generated as different voltages at time t1. At time t5, compensation voltages Vpark, VOBS, and VAR set to Vpark=5.4[V], VOBS=7.4[V], and VAR=-6.7[V] may be applied to the fourth to sixth pixels B1, B2, and B3. Therefore, each of the compensation voltages Vpark, VOBS, and VAR may be changed to a higher voltage at time t5 than at time t4.

[0173] At time t6, compensation voltages Vpark, VOBS, and VAR set to Vpark=5.6[V], VOBS=7.2[V], and VAR=-6.8[V] may be applied to the fourth to sixth pixels C1, C2, and C3. Therefore, each of the second compensation voltage VOBS and the third compensation voltage VAR may be changed to a lower voltage at time t6 than at time t5. The first compensation voltage Vpark may be changed to a higher voltage at time t6 than at time t5.

[0174] Fig.14 is a schematic diagram showing a compensation voltage generator 160 according to one embodiment of the present disclosure.

[0175] Reference Fig.14 , the compensation voltage generator 160 includes a position determination section 230 , a data storage section 210 , a control section 240 and a voltage output section 220 .

[0176] The position determination section 230 receives a timing signal SYNC synchronized with the pixel data of the input image. The position determination section 230 may include a counter that counts the timing signal SYNC as a clock. The position determination section 230 may determine the frame period and the horizontal period of the current input image by counting the timing signal SYNC. The position determination section 230 generates the frame period of the input image and the position information of the pixel to which the pixel data is written based on the counting result of the timing signal SYNC, and then provides it to the control section 240 and the voltage output section 220.

[0177] The timing signal SYNC input to the position determination unit 230 may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The pulse of the vertical synchronization signal Vsync is generated at intervals of one frame period (or vertical period) to indicate one frame period. The horizontal synchronization signal Hsync indicates one horizontal period. The pulse width of the second scanning signal SC2 for writing pixel data into a pixel may be one horizontal period. The data enable signal DE may indicate a data valid interval and a horizontal period, and includes a pulse that appears in each horizontal period in the valid interval during which pixel data is input in one frame period.

[0178] The data storage section 210 stores the compensation data set independently according to the position of each pixel. The compensation data indicating the voltage at which the flicker measurement value of each pixel is minimized can be set as a lookup table (LUT) data. The compensation data is digital data. The compensation data can be assigned to each pixel and can include first compensation data DIN1 indicating the voltage level of the first compensation voltage Vpark, second compensation data DIN2 indicating the voltage level of the second compensation voltage VOBS, and third compensation data DIN3 indicating the voltage level of the third compensation voltage VAR. Each of the compensation data DIN1, DIN2, and DIN3 can include data of a refresh frame RF and data of a hold frame HF separated by a refresh frame RF and a hold frame HF. The data storage section 210 provides the compensation data stored at an address corresponding to the position information received from the control section 240 to the control section 240.

[0179] The control part 240 supplies the compensation data DIN1, DIN2, and DIN3 selected according to the position information synchronized with the pixel data to the voltage output part 220, thereby controlling the voltage of each of the compensation voltages Vpark, VOBS, and VAR of each pixel.

[0180] Figure 1 The illustrated timing controller 130 may include or control a compensation voltage generator 160 .

[0181] The voltage output unit 220 includes a first digital-to-analog converter (DAC), a second DAC, and a third DAC. The voltage output unit 220 can be connected to Figure 1 The power supply 140 is shown embedded together in an integrated circuit, or may be mounted on a printed circuit board (PCB) together with the timing controller 130 and the power supply 140 .

[0182] The first DAC converts the first compensation data DIN1 into an analog voltage and outputs a first compensation voltage Vpark. The first compensation voltage Vpark may be applied to the data line DL through the switching element SW. The switching element SW may be implemented as a transistor, which is kept in an off state during the refresh frame RF period under the control of the control unit 240, and is turned on during the hold frame HF period. The switching element SW may be embedded in an integrated circuit together with the data driver 110, or mounted on the non-display area BZ of the display panel 100.

[0183] When the switching element SW is in the off state, the data voltage Vdata is applied to the data line DL, and when the switching element SW is turned on, the first compensation voltage Vpark is applied to the data line DL. When the switching element SW is turned on, the data driver 110 does not output the data voltage Vdata.

[0184] The second DAC converts the second compensation data DIN2 into an analog voltage and outputs the second compensation voltage VOBS to the first power line PL1. The third DAC converts the third compensation data DIN3 into an analog voltage and outputs the third compensation voltage VAR to the second power line PL2.

[0185] Since the first compensation voltage Vpark is provided to the data line DL parallel to the column direction Y, it can be applied as a different voltage to each pixel arranged in the same row direction X, and it can also be applied as a different voltage to each pixel arranged in the column direction Y.

[0186] The second compensation voltage VOBS and the third compensation voltage VAR may be applied as the same voltage in the row direction X of the display area AA, and may be applied as different voltages to pixels in the column direction Y. Fig.15 As shown, the second compensation voltage VOBS and the third compensation voltage VAR can be changed rapidly in a step form, or can be changed in the form of a linear voltage with a predetermined slope. These voltage variable schemes can be selected according to the flicker level or screen uniformity of the image reproduced in the display area AA. Fig.12 and Fig.15 In , "LN" represents the Nth row, and "L2N" represents the 2Nth row. There may be N rows of pixels between the Nth row and the 2Nth row.

[0187] The above-mentioned objects to be achieved by the present disclosure, means for achieving the objects, and effects of the present disclosure do not specify essential features of the claims, and thus the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0188] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

[0189] CROSS-REFERENCE TO RELATED APPLICATIONS

[0190] This application claims priority to Korean Patent Application No. 10-2023-0132364, filed on October 5, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display device, comprising: A display panel, wherein a plurality of data lines, a plurality of gate lines, a plurality of power lines, a plurality of sub-pixels and a gate driver for providing a gate signal to the gate lines are provided in the display panel; a data driver configured to supply a data voltage to the data line during a refresh frame period; and a compensation voltage generator, the compensation voltage generator being configured to output a first compensation voltage, a second compensation voltage and a third compensation voltage, wherein the first compensation voltage is applied to the data line during a holding frame period, During the refresh frame period, the data voltage, the second compensation voltage, and the third compensation voltage are applied to the sub-pixel, During the hold frame period, the first compensation voltage, the second compensation voltage, and the third compensation voltage are applied to the sub-pixel.

2. The display device according to claim 1, wherein: At least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage is variable.

3. The display device according to claim 1, wherein: Each of the sub-pixels comprises: Light emitting element; a driving element, the driving element including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node, and configured to drive the light emitting element; a first switching element connected between the data line and the second node and configured to provide the data voltage to the second node in response to a second scan signal; a second switching element connected between the first power line to which the second compensation voltage is applied and the second node and configured to provide the second compensation voltage to the second node in response to a third scan signal; and a third switching element connected between the second power line to which the third compensation voltage is applied and the anode electrode of the light emitting element, and configured to supply the third compensation voltage to the anode electrode of the light emitting element during the refresh frame period and the hold frame period, and The first switch element maintains a cut-off state during the holding frame period.

4. The display device according to claim 1, wherein: At least one of the second compensation voltage and the third compensation voltage has a higher voltage level in the refresh frame period than in the hold frame period.

5. The display device according to claim 1, wherein: A voltage level of at least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage varies within one frame period.

6. The display device according to claim 1, wherein: A voltage level of at least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage is different according to a position of the sub-pixel.

7. The display device according to claim 1, wherein: The voltage level of the first compensation voltage continues to rise during the holding frame period, and A voltage level of at least one of the second compensation voltage and the third compensation voltage rises and then falls in the refresh frame period and the hold frame period.

8. The display device according to claim 7, wherein: At least one of the second compensation voltage and the third compensation voltage changes in a step form or in the form of a linear voltage having a predetermined slope.

9. The display device according to claim 1, wherein: Each of the sub-pixels comprises: a driving element including a gate connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a first switching element connected between the data line and the second node and configured to provide the data voltage to the second node during the refresh frame period; a second switching element connected between the first power line to which the second compensation voltage is applied and the second node and configured to provide the second compensation voltage to the second node during the refresh frame period and the hold frame period; a third switching element connected between the second power line to which the third compensation voltage is applied and the anode electrode of the light emitting element, and configured to provide the third compensation voltage to the anode electrode of the light emitting element in response to a third scan signal; a fourth switching element connected between the first node and a fifth power line to which an initialization voltage is applied, and configured to supply the initialization voltage to the first node in response to a fourth scan signal; a fifth switching element connected between the first node and the third node and configured to connect the first node to the third node in response to a first scan signal; a sixth switching element connected between the third power line to which the pixel driving voltage is applied and the second node, and configured to supply the pixel driving voltage to the second node in response to a light emission control signal; a seventh switching element connected between the third node and a fourth node and configured to connect the third node to the fourth node in response to the light emission control signal; and A light emitting element has an anode electrode connected to the fourth node and a cathode electrode connected to a fourth power line supplied with a cathode voltage.

10. The display device according to claim 9, wherein: The pixel driving voltage is a voltage higher than the cathode voltage, A gate high voltage of the first scan signal, the second scan signal, the third scan signal, the fourth scan signal and the light emitting control signal is higher than the pixel driving voltage, and a gate low voltage of the first scan signal, the second scan signal, the third scan signal, the fourth scan signal and the light emitting control signal is lower than the cathode voltage, and The initialization voltage is a voltage lower than a lower limit voltage of the data voltage and higher than the cathode voltage.

11. The display device according to claim 10, wherein: The first switching element, the second switching element, the third switching element, the sixth switching element, and the seventh switching element are turned on in response to a gate low voltage, The fourth switching element and the fifth switching element are turned on in response to the gate high voltage, and The first switching element, the fourth switching element, and the fifth switching element maintain a turned-off state during the holding frame period.

12. The display device according to claim 11, wherein: During the refresh frame period, the driving period of the pixel is divided into a first conduction bias period, an initialization period, a sampling period, a second conduction bias period and a light emitting period, During the first on-bias period, the voltages of the first scan signal, the third scan signal, and the fourth scan signal are the gate low voltage, and the voltages of the second scan signal and the light emitting control signal are the gate high voltage, and During the initialization period, the voltage of the first to fourth scan signals and the light emitting control signal is the gate high voltage, During the sampling period, the voltages of the second scan signal and the fourth scan signal are the gate low voltage synchronized with the data voltage, and the voltages of the first scan signal, the third scan signal, and the light emitting control signal are the gate high voltage, During the second on-bias period, the voltages of the first scan signal, the third scan signal, and the fourth scan signal are the gate low voltage, and the voltages of the second scan signal and the light emitting control signal are the gate high voltage, During the light emitting period of the refresh frame period, the voltages of the first scan signal, the fourth scan signal, and the light emitting control signal are the gate low voltage, and the voltages of the second scan signal and the third scan signal are the gate high voltage, and The first to seventh switching elements are in an off state during a floating period between the first on-bias period and the initialization period, a floating period between the sampling period and the second on-bias period, and a floating period between the second on-bias period and the refresh frame period.

13. The display device according to claim 12, wherein: During the holding frame period, the driving period of the pixel is divided into a third on-bias period, a fourth on-bias period and a light emitting period, During the third on-bias period and the fourth on-bias period, the voltages of the first scan signal, the third scan signal, and the fourth scan signal are the gate low voltage, and the voltages of the second scan signal and the light emitting control signal are the gate high voltage, During the light emitting period of the holding frame period, the voltages of the first scan signal, the fourth scan signal, and the light emitting control signal are the gate low voltage, and the voltages of the second scan signal and the third scan signal are the gate high voltage, and The first to seventh switching elements are in an off state during a floating period between the third on-bias period and the fourth on-bias period and a floating period between the fourth on-bias period and the light emitting period of the holding frame period.

14. A method for driving a display device, the method comprising the following steps: providing a gate signal to the plurality of gate lines during a refresh frame period and a hold frame period; During the refresh frame period, providing a data voltage to a plurality of data lines, and providing a first compensation voltage, a second compensation voltage, and a third compensation voltage to a pixel circuit; as well as During the hold frame period, the first compensation voltage is supplied to the data line, and the first compensation voltage, the second compensation voltage, and the third compensation voltage are supplied to the pixel circuit.

15. The method according to claim 14, further comprising the steps of: At least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage is changed.

16. The method according to claim 14, wherein: Each of the second compensation voltage and the third compensation voltage has a higher voltage level in the refresh frame period than in the hold frame period.

17. The method according to claim 14, wherein: A voltage level of at least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage varies within one frame period.

18. The method according to claim 14, wherein: A voltage level of at least one of the first compensation voltage, the second compensation voltage, and the third compensation voltage is different according to a position of a sub-pixel.

19. The method according to claim 14, wherein: The voltage level of the first compensation voltage continues to rise during the holding frame period, and A voltage level of at least one of the second compensation voltage and the third compensation voltage rises and then falls in the refresh frame period and the hold frame period.

20. A display device, comprising: A display panel, the display panel comprising a pixel array, the pixel array comprising a plurality of data lines, a plurality of gate lines crossing the data lines, and pixels arranged in a matrix form, and the display panel further comprising power lines connected to constant voltage nodes of the pixels, the power lines being used to drive the pixels; A gate driver, the gate driver is used to provide a gate signal to the gate line; a data driver configured to provide a data voltage to the data line; as well as A compensation voltage generator, wherein the compensation voltage generator is configured to: outputting a first value of a first compensation voltage at a first time within a holding frame period, outputting a first value of a second compensation voltage at the first time within the holding frame period, outputting a first value of a third compensation voltage at the first time within the holding frame period, outputting a second value of the first compensation voltage different from the first value of the first compensation voltage at a second time within the holding frame period, outputting a second value of the second compensation voltage different from the first value of the second compensation voltage at the second time within the holding frame period, and A second value of the third compensation voltage different from the first value of the third compensation voltage is output at the second time within the hold frame period.

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