A display panel and display device

Abstract

The application discloses a display panel and a display device, which comprise at least two display partitions, the at least two display partitions comprising a first display partition and a second display partition, the first display partition and the second display partition being adjacent along a direction perpendicular to a data line; the at least two display partitions respectively comprising a plurality of pixel circuit groups; the display panel further comprises a first scanning circuit, a plurality of first scanning lines and a plurality of first gating circuits; the first scanning circuit is correspondingly electrically connected with the first scanning lines through the first gating circuits, and the first scanning lines are connected with corresponding pixel circuit groups; the first gating circuit is used for gating or turning off the first scanning lines and the first scanning circuit, and is also used for transmitting an off-level signal to the first scanning lines. The application can realize the multi-frequency display of the partitioned horizontal region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Organic Light Emitting Display (OLED) and flat display devices based on Light Emitting Diode (LED) technology have been widely applied to mobile phones, televisions, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices. However, the current display panel cannot realize partitioned multi-frequency display in the horizontal region. SUMMARY

[0003] The present application provides a display panel and a display device, which can realize partitioned multi-frequency display in the horizontal region.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising at least two display partitions, the at least two display partitions comprising a first display partition and a second display partition, the first display partition and the second display partition being adjacent in a direction perpendicular to a data line; the at least two display partitions each comprising a plurality of pixel circuit groups; the display panel further comprising a first scan circuit, a plurality of first scan lines and a plurality of first gating circuits; the first scan circuit being correspondingly electrically connected to the first scan lines through the first gating circuits, and the first scan lines being connected to corresponding pixel circuit groups; the first gating circuit being configured to gate on or turn off the first scan lines and the first scan circuit, and further configured to transmit an off-level signal to the first scan lines.

[0005] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel provided in any of the embodiments of the present application.

[0006] The display panel provided by the embodiment of the present application comprises a plurality of first gate circuits, which are connected with a first scanning circuit and a first scanning line respectively. The first input end of the first gate circuit receives a scanning signal output by the first scanning circuit, and the second input end is connected with an off level signal. The first gate circuit can determine the connection state between the first scanning circuit and the first scanning line in response to the signal on the gate signal line. When the first gate circuit is turned on, the scanning signal can be transmitted to the pixel circuit, so as to make the pixel switch state change; when the first gate circuit is turned off, the scanning signal is blocked, or the shift register cannot generate the scanning signal, and the pixel circuit cannot receive the scanning signal. In different display partitions, the gate signals received by the first gate circuits are different, so that the differential control of the scanning signal transmission of different partitions is realized. For example, at some time, the first gate circuit of the first display partition is turned off, and the pixel circuit of the partition cannot receive the scanning signal, while the first gate circuit of the second display partition is turned on, and the pixel circuit of the partition can normally receive the scanning signal, so that the refresh frequencies of the two partitions are different. Each display partition comprises a plurality of pixel circuit groups, and the pixel circuits in the pixel circuit groups control the display state of the pixels according to the scanning signal transmitted by the first scanning line. Due to the control of the first gate circuit on the scanning signal transmission, the frequencies at which the pixel circuits in different partitions receive the scanning signal are different. When the first gate circuit of the first display partition is turned off at a specific time period, the pixel circuit of the partition cannot receive the scanning signal and cannot perform the data writing operation; while the first gate circuit of the second display partition is in the turned-on state, the pixel circuit of the partition can normally receive the scanning signal and write data, so that different display partitions finally present different refresh frequencies, and the partition multi-frequency display of the horizontal area is realized.

[0007] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0009] Figure 1 is a structural schematic diagram of a display panel provided by the embodiment of the present application;

[0010] Figure 2 is a structural schematic diagram of another display panel provided by the embodiment of the present application;

[0011] Figure 3This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0012] Figure 4 This is a waveform diagram of a signal transmitted on a first strobe signal line and a second strobe signal line according to an embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0014] Figure 6 This is a schematic diagram of the structure of a second gating circuit provided in an embodiment of the present invention;

[0015] Figure 7 This is a schematic diagram of another second gating circuit provided in an embodiment of the present invention;

[0016] Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0017] Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0018] Figure 10 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0021] As described in the background section, existing display panels cannot achieve multi-frequency display in horizontal areas. The inventors discovered that this problem arises because display panels often use vertical multi-frequency partitioning to reduce screen power consumption. This typically involves controlling the output of the Gate In Panel (GIP) circuitry integrated within the control panel, causing the output frequency of the GIP circuitry in different areas to be inconsistent. This achieves inconsistent refresh rates at different locations on the screen. However, this principle cannot effectively achieve multi-frequency partitioning in horizontal areas.

[0022] To address the aforementioned technical problems, embodiments of the present invention provide a display panel. Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 1 As shown, the display panel includes at least two display zones, namely a first display zone AA1 and a second display zone AA2, which are adjacent to each other along the direction X perpendicular to the data lines. Each of the at least two display zones includes a plurality of pixel circuit groups 10; the display panel also includes a first scanning circuit 11, a plurality of first scanning lines GL1, and a plurality of first gating circuits 12.

[0023] The first scanning circuit 11 is electrically connected to the first scanning line GL1 via the first gating circuit 12. The first scanning line GL1 is connected to the corresponding pixel circuit group 10. The first gating circuit 12 is used to select or turn off the first scanning line GL1 and the first scanning circuit 11, and is also used to transmit the off level signal VGH to the first scanning line GL1.

[0024] Specifically, the pixel circuit group 10 includes multiple columns of pixel circuits PX, which can have the structure of any existing pixel driving circuit. The first scanning circuit 11 may include multiple cascaded shift registers 111. Each shift register 111 can be connected to a corresponding first scan line GL1 via a first gating circuit 12. The first scan line GL connects to a functional module in one or more columns of pixel circuits PX, such as a functional module in pixel circuit PX used to control the gate of the driving transistor for initialization.

[0025] The first scanning circuit 11 outputs a first scanning signal based on at least the input signal and the clock signal. The first scanning signal is transmitted to the first scanning line GL1 via the first gating circuit 12. The first scanning line GL1 transmits the first scanning signal generated by the first scanning circuit 11 to the pixel circuit group 10, thereby controlling the switching state of the pixels and realizing the progressive display of the image. For example, when the display panel includes multiple rows of pixel circuits PX, multiple shift registers in each first scanning circuit 11 are cascaded. The multiple cascaded shift registers 111 respectively provide a first scanning signal to at least one column of pixel circuits PX via their corresponding first gating circuits 12. The input signal of the first-level shift register 111 may include the input signal provided by the driver chip to the start signal line STV, and the input signals of other-level shift registers 111 may be the scanning signal output by the previous-level shift register 111.

[0026] The first scan signal output by the first scan circuit 11 may include an active level and an inactive level. The active level is the level at which the functional module in the pixel circuit is turned on, and the inactive level is the level at which the functional module in the pixel circuit is turned off. The active level can be high and the inactive level can be low; or, the active level can be low and the inactive level can be high. In this embodiment of the invention, the inactive level is high and the active level is low, as an example is used for illustration. Optionally, the inactive level is the same as the off level signal VGH.

[0027] The first gating circuit 12 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first gating circuit 12 is connected to the output terminal of the first scanning circuit 11 to receive the first scanning signal output by the first scanning circuit 11. The second input terminal of the first gating circuit 12 is connected to a turn-off level signal VGH. When the first input terminal and the output terminal of the first gating circuit 12 are connected, the first scanning signal is transmitted to the corresponding first scanning line GL1 through the output terminal of the first gating circuit 12. When the second input terminal and the output terminal of the first gating circuit 12 are connected, the turn-off level signal VGH is transmitted to the corresponding first scanning line GL1 through the output terminal of the first gating circuit 12. The turn-off level signal VGH is the cut-off potential of the functional module in the pixel circuit that receives the first scanning signal. This functional module is, for example, a functional module that controls the data voltage writing process of the driving transistor gate in the pixel circuit. When implementing multi-frequency display of horizontal area partitions, the first gating circuits 12 of different display partitions operate according to the signals on the gating signal lines. When it is necessary to stop the pixel writing voltage of a certain partition to achieve different refresh frequencies, the first gating circuit 12 transmits the off-level signal VGH to the first scan line GL1. This operation cuts off the transmission of the first scan signal, preventing the pixel circuit of the corresponding partition from receiving the first scan signal and thus preventing data writing. This results in a difference in refresh frequency compared to other partitions, enabling multi-frequency display of partitions. Furthermore, during the switching of the connection state between the first scan circuit 11 and the first scan line GL1, some residual first scan signal may remain. If these residual signals are not handled, they may interfere with the normal operation of the pixel circuit, leading to problems such as noise and ghosting in the display. Transmitting the off-level signal VGH to the first scan line GL1 effectively covers any residual first scan signal, ensuring that the level on the first scan line GL1 is in a definite off state. This avoids the residual scan signal from falsely triggering the pixel circuit, ensuring the clarity and stability of the displayed image and improving the overall performance of the display panel.

[0028] The first scanning circuit 11 is electrically connected to the first scan line GL1 via a first gating circuit 12. The first gating circuit 12 is responsible for selecting or turning off the first scan line GL1 and the first scanning circuit 11, and transmitting a turn-off level signal VGH. When the first input terminal and the output terminal of the first gating circuit 12 are connected, the first scan signal can be transmitted to the pixel circuit PX to control the on / off state of the pixel; when the first input terminal and the output terminal of the first gating circuit 12 are turned off, the first scan signal is blocked or the pixel circuit PX cannot receive the first scan signal. In this way, the first gating circuits 12 of different display zones can achieve differentiated control of the transmission of the first scan signal according to the different gating signals, thereby making the refresh rates of different display zones different.

[0029] Each display partition includes multiple pixel circuit groups 10. The pixel circuits PX within each pixel circuit group control the display state of the pixels according to the first scan signal transmitted by the first scan line GL1. Due to the control of the first scan signal by the first gating circuit 12, the pixel circuits PX in different partitions receive the first scan signal at different frequencies, thus achieving different refresh rates. For example, when the first gating circuit 12 of the first display partition AA1 is turned off at certain times, the pixel circuits PX in the first display partition AA1 cannot receive the first scan signal and do not write data. However, when the first gating circuit 12 of the second display partition AA2 is turned on, its pixel circuits PX normally receive the first scan signal and write data, resulting in a difference in refresh rates between the first display partition AA1 and the second display partition.

[0030] The display panel provided in this embodiment of the invention includes multiple first gating circuits, which are respectively connected to a first scanning circuit and a first scanning line. The first input terminal of each first gating circuit receives a first scanning signal output by the first scanning circuit, and the second input terminal receives a shutdown level signal. The first gating circuit is responsible for selecting or disabling the first scanning line from the first scanning circuit and transmitting the shutdown level signal. When the first input terminal and its output terminal of the first gating circuit are connected, the first scanning signal is transmitted to the pixel circuit, causing a change in the pixel's switching state; when the first input terminal and its output terminal are disconnected, the first scanning signal is blocked, and the pixel circuit cannot receive the first scanning signal. In different display zones, the gating signals received by the first gating circuits are different, thereby achieving differentiated control of the scanning signal transmission for different zones. For example, at certain times, the first gating circuit of the first display zone is turned off, and the pixel circuit of that zone does not receive the first scanning signal, while the first gating circuit of the second display zone is connected, and its pixel circuit normally receives the first scanning signal, causing a difference in the refresh rates of the two zones. Each display zone contains multiple pixel circuit groups. The pixel circuits in each pixel circuit group control the display state of the pixels based on the first scan signal transmitted by the first scan line. Due to the control of the first scan signal transmission by the first gating circuit, the pixel circuits of different zones receive the first scan signal at different frequencies. When the first input and output of the first gating circuit of the first display zone are turned off during a specific period, the pixel circuit of that zone cannot receive the first scan signal and does not perform data writing operations. However, when the first input and output of the first gating circuit of the second display zone are in a conducting state, its pixel circuit can normally receive the scan signal and write data, ultimately causing different display zones to exhibit different refresh rates, realizing multi-frequency display of horizontal areas.

[0031] Optionally, continue to refer to Figure 1The display panel also includes multiple clock signal lines and a driver chip. The driver chip is connected to the first scanning circuit 11 via the clock signal lines to output clock signals to the first scanning circuit. The driver chip can input clock signals to at least two clock signal lines, and the clock signal lines can transmit the clock signals to the first scanning circuit 11. Figure 1 The example illustrates a scenario where multiple clock signal lines may include a first clock signal line CK1 and a second clock signal line CK2, without any limitation. The first clock signal line CK1 can be configured to provide a first clock signal to odd-level shift registers and a second clock signal to even-level shift registers. The second clock signal line CK2 can be configured to provide a second clock signal to odd-level shift registers and a first clock signal to even-level shift registers.

[0032] Optionally, continue to refer to Figure 1 The display panel also includes multiple gating signal lines SE1, which are connected to the first gating circuit 12. The first gating circuit 12 is used to select or turn off the first scan line 12 and the first scan circuit 11 according to the signal on the gating signal line SE1, and is also used to transmit the off level signal VGH to the first scan line GL1 according to the signal on the gating signal line SE1.

[0033] Specifically, the first gating circuit 12 determines the connection state between the first scan line GL1 and the first scan circuit 11 based on the signal state on the gating signal line SE1. When the signal on the gating signal line SE1 controls the first input terminal and its output terminal of the first gating circuit 12 to be turned on, and controls the second input terminal and its output terminal of the first gating circuit 12 to be turned off, the first gating circuit 12 selects the first scan line GL1 and the first scan circuit 11. At this time, the first scan signal output by the first scan circuit 11 is transmitted to the first scan line GL1 through the first gating circuit 12, and then transmitted to the corresponding pixel circuit group 10 to control the on / off state of the pixels and realize the progressive display of the image. Conversely, when the signal on the gating signal line SE1 controls the first input terminal and its output terminal of the first gating circuit 12 to be turned off, and controls the second input terminal and its output terminal of the first gating circuit 12 to be turned on, the first gating circuit 12 will transmit the input off level signal VGH to the first scan line GL1. The off-level signal VGH is the cutoff potential of the relevant functional modules in the pixel circuit. Transmitting it to the first scan line GL1 can cut off the corresponding functional modules in the pixel circuit, ensuring that the pixel circuit is in a stable non-working state, avoiding false triggering caused by residual signals and other factors, and ensuring the accuracy and stability of the display panel's display status.

[0034] Figure 2 This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 2As shown, optionally, the strobe signal line SE1 includes a first strobe signal line SE11 and a second strobe signal line SE12.

[0035] The first gating circuit 12 includes a first gating unit 121 and a second gating unit 122. The control terminal of the first gating unit 121 is connected to the first gating signal line SE11. The first terminal of the first gating unit 121 is connected to the first scanning circuit 11. The second terminal of the first gating unit 121 is connected to the first scanning line GL1. It is used to select or turn off the first scanning line GL1 and the first scanning circuit 11 according to the signal on the first gating signal line SE11.

[0036] The control terminal of the second gating unit 122 is connected to the second gating signal line SE12. The first terminal of the second gating unit 122 is connected to the first scan line GL1. The second terminal of the second gating unit 122 is connected to the off level signal VGH, which is used to transmit the off level signal VGH to the first scan signal line GL1 according to the signal on the second gating signal line SE12.

[0037] Specifically, within at least one frame of the display cycle of the display panel, the signals transmitted on the first strobe signal line SE11 and the second strobe signal line SE12 in the first display partition AA1 are different from the signals transmitted on the first strobe signal line SE11 and the second strobe signal line SE12 in the second display partition AA2.

[0038] Specifically, the signal on the first strobe signal line SE11 determines the on or off state of the first strobe unit 121. When the signal on the first strobe signal line SE11 is at an active level, the first strobe unit 121 connects the first scanning circuit 11 and the first scanning line GL1, enabling the first scanning signal generated by the first scanning circuit 11 to be transmitted to the first scanning line GL1, providing control signals to the pixel circuit group and realizing the progressive display of the image.

[0039] The signal on the second strobe signal line SE12 controls the operating state of the second strobe unit 122. When the signal on the first strobe signal line SE11 is at an invalid level, the second strobe unit 122 is turned on, transmitting the off level signal VGH to the first scan line GL1, which cuts off the relevant functional modules in the pixel circuit, ensuring that the pixel circuit is in a stable non-working state and avoiding false triggering caused by residual signals.

[0040] Within one frame display cycle of the display panel, the signals transmitted on the first gating signal line SE11 and the second gating signal line SE12 of the first display partition AA1 and the second display partition AA2 are different. This signal difference causes the first gating circuit 12 of the two partitions to operate in different states. At a certain moment, the first gating unit 121 of the first display partition AA1 may be turned off due to the signal of the first gating signal line SE11, stopping the data writing voltage of the pixels in that partition; while the first gating unit 121 of the second display partition AA2 remains on due to the different signal, continuing to write data, thereby achieving different refresh rates for the two partitions to meet the display requirements of different scenarios. This embodiment subdivides the gating signal lines and gating units, controlling the first gating unit 121 and the second gating unit 122 respectively through different gating signal lines, improving the control accuracy of the connection between the first scanning circuit 11 and the first scanning line GL1 and the off-level signal VGH. Differentiated signal control for different partitions can more accurately control the working state of each partition, reduce signal interference, enhance the stability of the display panel, improve display quality, and reduce the occurrence of display problems such as noise and ghosting.

[0041] Optionally, the first strobe signal line SE11 in each display partition is connected to the first strobe unit 121 of all rows. This means that the signal transmitted by the first strobe signal line SE11 can simultaneously control the operating state of the first strobe unit 121 of all rows. When the signal on the first strobe signal line SE11 changes, the first strobe unit 121 of all rows will synchronously select or deselect the first scan circuit 11 and the first scan line GL1 according to the signal, thereby determining whether the first scan signal can be transmitted to each pixel circuit group.

[0042] Optionally, the second strobe signal line SE12 in each display partition is connected to the second strobe unit 122 of all rows. The signal transmitted by the second strobe signal line SE12 can simultaneously control the second strobe units 122 of all rows, determining whether to transmit the off-level signal VGH to the first scan line GL1, thereby controlling the cut-off state of the relevant functional modules in the pixel circuit. By connecting the first strobe signal line SE11 to the first strobe unit 121 of all rows, it can be ensured that the pixel circuits of all rows within the same display partition remain synchronized when receiving the first scan signal. When displaying images, there will be no problems such as asynchronous or misaligned display of different rows within the same partition, ensuring the consistency and stability of the entire partition display. The connection of the second strobe signal line SE12 to the second strobe unit 122 of all rows also ensures that the control of the off-state of the pixel circuits of all rows remains consistent, avoiding display defects caused by untimely or abnormal off-state of some rows.

[0043] As a preferred embodiment provided in this invention, Figure 3This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 3 As shown, optionally, the first gating unit 121 includes a first transistor T1, the gate of the first transistor T1 serves as the gate of the first gating unit 121, the first electrode of the first transistor T1 serves as the first terminal of the first gating unit 121, and the second electrode of the first transistor T1 serves as the second terminal of the first gating unit 121.

[0044] Specifically, when the signal transmitted through the first selection signal line SE11 causes the gate voltage of the first transistor T1 to reach the conduction threshold, the first transistor T1 is turned on. At this time, a conductive path is formed between the first terminal (connected to the first scanning circuit 11) and the second terminal (connected to the first scan line GL1) of the first transistor T1, and the first scan signal generated by the first scanning circuit 11 can be transmitted to the first scan line GL1 through the first transistor T1, providing a control signal for the pixel circuit group 10 and realizing the progressive display of the image. When the gate voltage is lower than the conduction threshold, the first transistor T1 is turned off, cutting off the connection between the first scanning circuit 11 and the first scan line GL1, and preventing the transmission of the scan signal.

[0045] Optionally, the second gating unit 122 includes a second transistor T2, the gate of the second transistor T2 serves as the control terminal of the second gating unit 122, the first electrode of the second transistor T2 serves as the first terminal of the second gating unit 122, and the second electrode of the second transistor T2 serves as the second terminal of the second gating unit 122.

[0046] Specifically, when the signal transmitted through the second strobe signal line SE12 causes the gate voltage of the second transistor T2 to meet the conduction condition, the second transistor T2 is turned on. The first terminal of the second transistor T2 is connected to the first scan line GL1, and the second terminal is connected to the turn-off level signal VGH. When on, the turn-off level signal VGH is transmitted to the first scan line GL1 through the second transistor T2, causing the relevant functional modules in the pixel circuit to be turned off, avoiding false triggering caused by residual signals, and ensuring that the pixel circuit is in a stable non-operating state. When the gate voltage does not meet the conduction condition, the second transistor T2 is turned off, stopping the transmission of the turn-off level signal VGH.

[0047] Figure 4 This is a waveform diagram of signals transmitted on a first strobe signal line and a second strobe signal line according to an embodiment of the present invention. (Reference) Figure 4 For example, the signal on the first strobe signal line SE11 is the first strobe signal E1, and the signal on the second strobe signal line SE12 is the second strobe signal E2. During the same phase, the levels of the first strobe signal E1 and the second strobe signal E2 are opposite.

[0048] refer to Figure 3 and Figure 4In the first stage P1, when the first strobe signal E1 is at an invalid level (e.g., high level) and the second strobe signal E2 is at an effective level (e.g., low level), the first transistor T1 is off, the second transistor T2 is on, and the off-level signal VGH is transmitted to the first scan line GL1. In the second stage P2, when the first strobe signal E1 is low and the second strobe signal E2 is high, the first transistor T1 is on, the first scan circuit 11 is connected to the first scan line GL1, and the scan signal can be transmitted. At this time, the second transistor T2 is off, preventing the off-level signal VGH from being transmitted to the first scan line GL1. This reversed level setting ensures that at any given time, the first scan line GL1 is either transmitting a scan signal or in a stable state controlled by the off-level signal VGH, avoiding the confusion caused by the simultaneous occurrence of both signals. If the two levels are not reversed, the first transistor T1 and the second transistor T2 may be on or off simultaneously, causing a conflict between the scan signal and the off-level signal VGH, or the first scan line GL1 may not be able to obtain the required signal in time, affecting the normal operation of the pixel circuit and causing display abnormalities.

[0049] Optionally, continue to refer to Figure 2 and Figure 3 The refresh rate of the first display partition AA1 is the first refresh rate, and the refresh rate of the second display partition AA2 is the second refresh rate. The first refresh rate is less than the second refresh rate.

[0050] Within the first frame, the signal on the first strobe signal line SE11 in the first display partition AA1 and the second display partition AA2 is at an active level, and the signal on the second strobe signal line SE12 in the first display partition AA1 and the second display partition AA2 is at an inactive level, so that the sub-pixels in the first display partition AA1 and the second display partition AA2 are all written with data voltage.

[0051] Within the second frame, the signal on the first strobe signal line SE11 in the first display partition AA1 is at an invalid level, and the signal on the second strobe signal line SE12 is at an active level. In the second display partition AA2, the signal on the first strobe signal line SE11 is at an active level, and the signal on the second strobe signal line SE12 is at an invalid level, so that the sub-pixels in the first display partition AA1 do not write data voltage, and the sub-pixels in the second display partition AA2 write data voltage.

[0052] Specifically, the display cycle of the display panel includes multiple display frames, with the first frame and the second frame being any two of them. In the first frame, the signals on the first gating signal line SE11 of both partitions are at an active level, while the signals on the second gating signal line SE12 are at an inactive level. At this time, the first transistor T1 in the first gating unit 121 is turned on, connecting the first scanning circuit 11 to the first scanning line GL1, allowing the first scanning signal to be transmitted to the pixel circuit group. Simultaneously, the second transistor T2 in the second gating unit 122 is turned off, preventing the off-level signal VGH from being transmitted to the first scanning line GL1. This allows data voltage to be written to the sub-pixels in both the first display partition AA1 and the second display partition AA2, preparing for subsequent display.

[0053] In the second frame, the first strobe signal line SE11 of the first display partition AA1 becomes inactive, while the second strobe signal line SE12 becomes active. This causes the first transistor T1 to turn off and the second transistor T2 to turn on, cutting off the scan signal and interrupting the transmission of the off-level signal VGH. No data voltage is written to the sub-pixels of this partition. Meanwhile, the second display partition AA2 maintains the first strobe signal line SE11 active and the second strobe signal line SE12 inactive, allowing the sub-pixels to continue writing data voltage. By setting the strobe signals in these two frames, data is written to the sub-pixels of different partitions at different times. Since the first display partition AA1 does not write data voltage in the second frame, while the second display partition AA2 writes normally, the second display partition AA2 writes data voltage more frequently within a display cycle. The refresh rate is related to the number of data writes per unit time; more writes result in a higher refresh rate. Therefore, by using the differentiated settings of the strobe signals for the two partitions in the first and second frames, the refresh rate of the second display partition AA2 is made higher than that of the first display partition AA1, achieving multi-frequency display of the horizontal area of ​​the display panel and meeting the refresh rate requirements of different scenarios.

[0054] Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. (Reference) Figure 5 The display panel also includes a second scanning circuit 13, multiple second scanning lines GL2, and multiple second gating circuits 14; the second scanning circuit 13 is electrically connected to the second scanning lines GL2 through the second gating circuits 14, and the second scanning lines GL2 are connected to the corresponding pixel circuit groups 10; the second gating circuits 14 are used to select or turn off the second scanning lines GL2 and the second scanning circuit 13, and are also used to transmit the off level signal VGH to the second scanning lines GL2.

[0055] Specifically, the second scanning circuit 13 outputs a second scanning signal based on at least the input signal and the clock signal. The second scanning signal is transmitted to the second scanning line GL2 via the second gating circuit 14. The second scanning line GL2 transmits the second scanning signal generated by the second scanning circuit 13 to the pixel circuit group 10, thereby controlling the switching state of the pixels and realizing the progressive display of the image. For example, when the display panel includes multiple rows of pixel circuits PX, multiple first shift registers 131 in each second scanning circuit 13 are cascaded. The multiple cascaded first shift registers 131 respectively provide second scanning signals to at least one column of pixel circuits PX through their corresponding second gating circuits 14. The input signal of the first-stage first shift register 131 may include the input signal provided by the driver chip to the first start signal line STV1, and the input signals of other stages of first shift registers 131 may be the second scanning signal output by the previous stage first shift register 131. The structures of shift register 111 and first shift register 131 may be the same or different; this embodiment of the invention does not limit this.

[0056] The first scan signal output by the second scan circuit 13 may include an active level and an inactive level. The active level is the level at which the functional module in the pixel circuit is turned on, and the inactive level is the level at which the functional module in the pixel circuit is turned off. For example, it is the level at which the initialization module in the pixel circuit PX is turned off. The active level can be high and the inactive level can be low; or, the active level can be low and the inactive level can be high. In this embodiment of the invention, the inactive level is high and the active level is low, as an example is used for explanation. Optionally, the inactive level is the same as the off level signal VGH.

[0057] The second gating circuit 14 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second gating circuit 14 is connected to the output terminal of the second scanning circuit 13 to receive the second scanning signal output by the second scanning circuit 13. The second input terminal of the second gating circuit 14 is connected to a turn-off level signal VGH. When the first input terminal and the output terminal of the second gating circuit 14 are turned on, and the second input terminal and the output terminal of the second gating circuit 14 are turned off, the second scanning signal is transmitted to the corresponding second scanning line GL2 through the output terminal of the second gating circuit 12. The second scanning signal generated by the second scanning circuit 13 can then reach the pixel circuit group 10 through the second scanning line GL2, thereby participating in the control of the pixel, for example, playing a role in the initialization operation of the pixel circuit.

[0058] When the second input and output of the first gating circuit 12 are connected, and the first input and output of the second gating circuit 14 are disconnected, the shutdown level signal VGH is transmitted to the corresponding second scan line GL2 through the output of the second gating circuit 14. The shutdown level signal VGH can cut off the functional modules in the pixel circuit (such as the initialization module), ensuring that the pixel circuit is in a stable state, avoiding false pixel triggering caused by abnormal signals, and ensuring the stability and accuracy of the displayed image.

[0059] Optionally, continue to refer to Figure 5 The display panel also includes multiple gating signal lines SE1, which are connected to the second gating circuit 14. The second gating circuit 14 is used to select or turn off the second scan line GL2 and the second scan circuit 14 according to the signal on the gating signal line SE1, and is also used to transmit the off level signal to the second scan line GL2 according to the signal on the gating signal line SE1.

[0060] Figure 6 This is a schematic diagram of a second gating circuit provided in an embodiment of the present invention. (Reference) Figure 6 Optionally, the strobe signal line SE1 includes a first strobe signal line SE11 and a second strobe signal line SE12.

[0061] The second gating circuit 14 includes a third gating unit 141 and a fourth gating unit 142. The control terminal of the third gating unit 141 is connected to the first gating signal line SE11. The first terminal of the third gating unit 141 is connected to the second scanning circuit 13. The second terminal of the third gating unit 142 is connected to the second scanning line GL2. It is used to select or turn off the second scanning line GL2 and the second scanning circuit 13 according to the signal on the first gating signal line SE1.

[0062] The control terminal of the fourth gating unit 142 is connected to the second gating signal line SE12. The first terminal of the fourth gating unit 142 is connected to the second scan line GL2. The second terminal of the fourth gating unit 142 is connected to the off level signal VGH, which is used to transmit the off level signal to the second scan line GL2 according to the signal on the second gating signal line SE12.

[0063] Specifically, the signal on the first strobe signal line SE11 determines the on or off state of the third strobe unit 141. When the signal on the first strobe signal line SE11 is at an active level, the third strobe unit 141 connects the first scanning circuit 11 and the second scanning line GL2, enabling the first scanning signal generated by the first scanning circuit 11 to be transmitted to the second scanning line GL2, providing control signals to the pixel circuit group 10, and realizing the progressive display of the image.

[0064] The signal on the second strobe signal line SE12 controls the operating state of the fourth strobe unit 142. When the signal on the first strobe signal line SE11 is at an invalid level, the fourth strobe unit 142 is turned on, transmitting the off level signal VGH to the second scan line GL2, which cuts off the relevant functional modules in the pixel circuit, ensuring that the pixel circuit is in a stable non-working state and avoiding false triggering caused by residual signals.

[0065] Optionally, the first strobe signal line SE11 in each display partition is connected to the third strobe unit 141 of all rows. This means that the signal transmitted by the first strobe signal line SE11 can simultaneously control the operating state of the third strobe unit 141 of all rows. When the signal on the first strobe signal line SE11 changes, the third strobe unit 141 of all rows will synchronously select or deselect the second scan circuit 13 and the second scan line GL2 according to the signal, thereby determining whether the second scan signal can be transmitted to each pixel circuit group.

[0066] Optionally, the second strobe signal line SE12 in each display partition is connected to the fourth strobe unit 142 of all rows. This connection means that within the same display partition, the pixel circuits of all rows can remain synchronized when receiving the off-level signal VGH. When the second strobe signal line SE12 transmits a signal to turn on the fourth strobe unit 142, the second scan lines GL2 of all rows simultaneously connect to the off-level signal VGH, causing the relevant functional modules in each pixel circuit to be synchronously turned off. This avoids display inconsistencies caused by untimely or abnormal off-leveling of some rows, ensuring a stable and flicker-free image across the entire display partition and improving display quality. When displaying static images, unified off-level control ensures that all pixels are in a stable state, preventing noise or other display defects.

[0067] As a preferred embodiment provided in this invention, Figure 7 This is a schematic diagram of another second gating circuit provided in an embodiment of the present invention. (Reference) Figure 7 Optionally, the third gate unit 141 includes a third transistor T3, the gate of the third transistor T3 serves as the gate of the third gate unit 141, the first terminal of the third transistor T3 serves as the first terminal of the third gate unit 141, and the second terminal of the third transistor T3 serves as the second terminal of the third gate unit 141.

[0068] Specifically, when the signal transmitted through the first selection signal line SE11 causes the gate voltage of the third transistor T3 to reach the conduction threshold, the third transistor T3 is turned on. At this time, a conductive path is formed between the first terminal (connected to the second scanning circuit 13) and the second terminal (connected to the second scan line GL2) of the third transistor T3. The second scan signal generated by the second scanning circuit 13 can then be transmitted to the second scan line GL2 through the third transistor T3, providing a control signal for the pixel circuit group 10 and realizing the progressive display of the image. When the gate voltage is lower than the conduction threshold, the third transistor T3 is turned off, cutting off the connection between the second scanning circuit 13 and the second scan line GL2, and preventing the transmission of the scan signal.

[0069] Optionally, the fourth gating unit 142 includes a fourth transistor T4, the gate of the fourth transistor T4 serving as the control terminal of the fourth gating unit 142, the first electrode of the fourth transistor T4 serving as the first terminal of the fourth gating unit 142, and the second electrode of the fourth transistor T4 serving as the second terminal of the fourth gating unit 142.

[0070] Specifically, when the signal transmitted through the second strobe signal line SE12 causes the gate voltage of the fourth transistor T4 to meet the conduction condition, the fourth transistor T4 is turned on. The first terminal of the fourth transistor T4 is connected to the second scan line GL2, and the second terminal is connected to the turn-off level signal VGH. When on, the turn-off level signal VGH is transmitted to the second scan line GL2 through the fourth transistor T4, causing the relevant functional modules in the pixel circuit to be turned off, avoiding false triggering due to residual signals, and ensuring that the pixel circuit is in a stable non-operating state. When the gate voltage does not meet the conduction condition, the fourth transistor T4 is turned off, stopping the transmission of the turn-off level signal VGH.

[0071] Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. (Reference) Figure 8 Optionally, the pixel circuit includes a driving module 110, a data writing module 120, and a threshold compensation module 130.

[0072] The data writing module 120 is electrically connected between the first end of the drive module 110 and the data line Data, and is used to write the data voltage provided by the data line to the control end of the drive module according to the signal on the first scan line GL1.

[0073] The threshold compensation module 130 is connected between the second end of the drive module 110 and the control end, and is used to perform threshold compensation on the drive module 110 according to the signal on the first scan line GL2.

[0074] Specifically, during the data writing and threshold compensation stages, the signal on the first scan line GL1 controls the data writing module 120 and the threshold compensation module 130 to be turned on, so that the data voltage on the data line Data can be written to the control terminal of the drive module 110 in sequence through the data writing module 120, the drive module 110 and the threshold compensation module 130, so that the voltage of the control terminal of the drive module 110 is related to both the data voltage and the threshold voltage of the drive module 110.

[0075] Optionally, the pixel circuit further includes a first initialization module 140, which is connected between the control terminal of the driving module 110 and the first initialization voltage line Vref1, and is used to write the first initialization voltage provided by the first initialization voltage line Vref1 to the control terminal of the driving module 110 according to the signal on the second scan line GL2.

[0076] Optionally, the pixel circuit further includes a light-emitting module 150 and a light-emitting control module 160. The light-emitting control module 160, the driving module 110, and the light-emitting module 150 are connected between the first power line VDD and the second power line VSS. The light-emitting control module 160 is used to control the light-emitting module to emit light according to the driving current output by the driving module 110 based on the signal on the light-emitting control signal line EM.

[0077] Optionally, the light-emitting control module 160 includes a first light-emitting control module 161 and a second light-emitting control module 162. The first light-emitting control module 161 is connected between the first end of the driving module 110 and the first power line VDD. The second light-emitting control module 162 is connected between the second end of the driving module 110 and the first end of the light-emitting module 150. The second end of the light-emitting module 160 is electrically connected to the second power line VSS.

[0078] Optionally, the pixel circuit further includes a second initialization module 170, which is connected between the control terminal of the driving module 110 and the first initialization voltage line Vref1, and is used to write the second initialization voltage provided by the second initialization voltage line Vref2 to the first terminal of the light-emitting module 150 according to the signal on the third scan line GL3.

[0079] Optionally, the pixel circuit also includes a storage module 180, which is connected between the control terminal of the drive module 110 and the first power line VDD, and is used to store the voltage of the control terminal of the drive module 110.

[0080] Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. (Reference) Figure 9 The light-emitting module 150 includes a light-emitting element D1, with the anode of the light-emitting element D1 serving as the first end of the light-emitting module 150 and the cathode of the light-emitting element D1 serving as the second end of the light-emitting module 150.

[0081] The driving module 110 may include a driving transistor DTFT, which may be an NMOS transistor or a PMOS transistor. The gate, first terminal, and second terminal of the driving transistor DTFT may serve as the control terminal, first terminal, and second terminal of the driving module 110, respectively. The driving module 110 may generate a driving current based on the voltage between its control terminal and the first terminal, and the light-emitting element D1 emits light in response to the driving current.

[0082] The data writing module 120 includes a data writing transistor M1, for example, the data writing transistor M1 is an NMOS transistor or a PMOS transistor. The first terminal of the data writing transistor M1 is connected to the first terminal of the driving module 110, the second terminal of the data writing transistor M1 is connected to the data line Data, and the gate of the data writing transistor M1 is connected to the first scan line GL1.

[0083] The threshold compensation module 130 includes a threshold compensation transistor M2, which is an NMOS transistor. The gate of the threshold compensation transistor M2 is connected to the first scan line GL1. The first terminal of the threshold compensation transistor M2 is connected to the second terminal of the driving module 110, and the second terminal of the threshold compensation transistor M2 is connected to the control terminal of the driving module 110.

[0084] Optionally, the first initialization module 140 includes a first initialization transistor M3, which is an NMOS transistor. The first terminal of the first initialization transistor M3 is connected to the control terminal of the driving module 110, the second terminal of the first initialization transistor M3 is connected to the first initialization voltage line Vref1, and the gate of the first initialization transistor M3 is connected to the second scan line GL3.

[0085] Optionally, the first light-emitting control module 161 includes a first light-emitting control transistor M4, which is a PMOS transistor or an NMOS transistor. The first terminal of the first light-emitting control transistor M4 is connected to the first terminal of the driving module 110, the second terminal of the first light-emitting control transistor M4 is connected to the first power supply line VDD, and the gate of the first light-emitting control transistor M4 is connected to the light-emitting control signal line EM. The first light-emitting control transistor M4 can be an NMOS transistor or a PMOS transistor.

[0086] Optionally, the second light-emitting control module 190 includes a second light-emitting control transistor M5, which is a PMOS transistor or an NMOS transistor. The first terminal of the second light-emitting control transistor M5 is connected to the second terminal of the driving module 110, the second terminal of the second light-emitting control transistor M5 is connected to the anode of the light-emitting element D1, and the gate of the second light-emitting control transistor M5 is connected to the light-emitting control signal line EM. The second light-emitting control transistor M5 can be an NMOS transistor or a PMOS transistor.

[0087] Optionally, the second initialization module 170 includes a second initialization transistor M6, the gate of which is connected to the third scan line GL3, the first electrode of which is connected to the second initialization voltage line Vref2, and the second electrode of the second initialization transistor T5 is connected to the anode of the light-emitting element D1. The second initialization transistor M6 may be an NMOS transistor or a PMOS transistor.

[0088] Optionally, the storage module 180 includes a storage capacitor Cst, the first terminal of which is connected to the first power supply line VDD so that the first terminal of the storage capacitor Cst is connected to the first power supply voltage, and the second terminal of the storage capacitor Cst is connected to the control terminal of the drive module 110.

[0089] Figure 10 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 10 The driving timing shown can be applied to the driver. Figure 9 The pixel circuit shown is working. The following will combine... Figure 9 and Figure 10 The working principle of the pixel circuit provided in the embodiments of the present invention will be explained. Exemplarily, the operation of the pixel circuit within a display frame includes at least a first initialization stage P1, a data writing and threshold compensation stage P2, a second initialization stage P3, and a light emission stage P4. After the (i-1)th display frame ends, the ith display frame begins. i is an integer greater than or equal to 2.

[0090] In the first initialization phase P1 of the i-th display frame, the first initialization module 140 is turned on, while the threshold compensation module 130, data writing module 120, second initialization module 170, first light emission control module 161, and second light emission control module 162 are turned off. That is, the first initialization transistor M3 is turned on, while the data writing transistor M1, threshold compensation transistor M2, second initialization transistor M6, first light emission control transistor M4, and second light emission control transistor M5 are turned off. The first initialization voltage transmitted through the first initialization voltage line Vref1 is written to the gate of the driving transistor DTFT through the first initialization transistor M3, resetting the gate voltage of the driving transistor DTFT to the first initialization voltage and controlling the driving transistor DTFT to turn on.

[0091] During the data writing and threshold compensation phase P2 of the i-th display frame, the data writing module 120 and the threshold compensation module 130 are turned on, while the first initialization module 140, the second initialization module 170, the first light-emitting control module 161, and the second light-emitting control module 162 are turned off. That is, the threshold compensation transistor M2 and the data writing transistor M1 are turned on, while the first initialization transistor M3, the second initialization transistor M6, the first light-emitting control transistor M4, and the second light-emitting control transistor M5 are turned off. The data voltage transmitted by the data line Data is sequentially written to the gate of the driving transistor DTFT through the data writing transistor M1, the driving transistor DTFT, and the threshold compensation transistor M2, making the gate voltage of the driving transistor DTFT related to both the data voltage and the threshold voltage of the driving transistor DTFT. Simultaneously, the gate voltage of the driving transistor DTFT is stored through the storage capacitor Cst.

[0092] During the light-emitting phase P3 of the i-th display frame, the second initialization module 170 is turned on, while the threshold compensation module 130, data writing module 120, first initialization module 140, first light-emitting control module 161, and second light-emitting control module 162 are turned off. That is, the second initialization transistor M6 is turned on, while the threshold compensation transistor M2, data writing transistor M1, first initialization transistor M3, first light-emitting control transistor M4, and second light-emitting control transistor M5 are turned off. The second initialization voltage transmitted via the second initialization voltage line Vref2 is written to the anode of the light-emitting element D1 through the second initialization transistor M6. The second initialization voltage transmitted via the third initialization voltage line Vref3 is written to the first electrode of the driving transistor DTFT through the third initialization transistor M5.

[0093] During the light-emitting phase P4 of the i-th display frame, the driving module 110, the first light-emitting control module 161, and the second light-emitting control module 162 are turned on, while the threshold compensation module 130, the data writing module 120, the first initialization module 140, and the second initialization module 170 are turned off. That is, the first light-emitting control transistor M4, the second light-emitting control transistor M5, and the driving transistor DTFT are turned on, while the threshold compensation transistor M2, the data writing transistor M1, the first initialization transistor M3, and the second initialization transistor M6 are turned off. The driving transistor DTFT generates a driving current based on its gate voltage, thereby driving the light-emitting element D1 to emit light at a corresponding brightness. During the light-emitting phase P4, since the gate voltage of the driving transistor DTFT is related to both the data voltage and the threshold voltage of the driving transistor DTFT, it helps to compensate for the influence of the threshold voltage of the driving transistor DTFT on the driving current, thereby improving the display uniformity during the light-emitting phase.

[0094] Based on the same inventive concept, the present invention also provides a display device, including the display panel provided in any embodiment of the present invention. It is understood that the display device provided in the embodiments of the present invention can be a mobile phone, wearable product, computer, television, vehicle display device, or other display device with display function, and the present invention does not impose specific limitations on this. The display device provided in the embodiments of the present invention has the beneficial effects of the display panel provided in the embodiments of the present invention; for details, please refer to the specific descriptions of the display in the above embodiments, which will not be repeated here.

[0095] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, It includes at least two display partitions, and the at least two display partitions include a first display partition and a second display partition, which are adjacent to each other along a direction perpendicular to the data line; At least two of the display zones each include multiple pixel circuit groups; the display panel further includes a first scanning circuit, multiple first scanning lines, and multiple first gating circuits; The first scanning circuit is electrically connected to the first scanning line via the first gating circuit, and the first scanning line is connected to the corresponding pixel circuit group; the first gating circuit is used to enable or disable the first scanning line and the first scanning circuit, and is also used to transmit a shutdown level signal to the first scanning line. The display panel further includes multiple gating signal lines, including a first gating signal line and a second gating signal line. The first gating circuit includes a first gating unit and a second gating unit. The control terminal of the first gating unit is connected to the first gating signal line, and the control terminal of the second gating unit is connected to the second gating signal line. The first gating signal line in each display partition is connected to the first gating unit of all rows in that display partition; the second gating signal line in each display partition is connected to the second gating unit of all rows in that display partition. During at least one frame of the display cycle of the display panel, the signals transmitted on the first gating signal line and the second gating signal line in the first display partition are different from the signals transmitted on the first gating signal line and the second gating signal line in the second display partition.

2. The display panel according to claim 1, characterized in that, The first end of the first gating unit is connected to the first scanning circuit, and the second end of the first gating unit is connected to the first scanning line, for selecting or turning off the first scanning line and the first scanning circuit according to the signal on the first gating signal line. The first end of the second gating unit is connected to the first scan line, and the second end of the second gating unit is connected to the off level signal, which is used to transmit the off level signal to the first scan line according to the signal on the second gating signal line.

3. The display panel according to claim 2, characterized in that, The first gating unit includes a first transistor, the gate of the first transistor serves as the gate of the first gating unit, the first electrode of the first transistor serves as the first terminal of the first gating unit, and the second electrode of the first transistor serves as the second terminal of the first gating unit.

4. The display panel according to claim 2, characterized in that, The second gating unit includes a second transistor, the gate of the second transistor serves as the control terminal of the second gating unit, the first electrode of the second transistor serves as the first terminal of the second gating unit, and the second electrode of the second transistor serves as the second terminal of the second gating unit.

5. The display panel according to claim 1, characterized in that, The signal on the first strobe signal line is the first strobe signal, and the signal on the second strobe signal line is the second strobe signal. At the same stage, the levels of the first strobe signal and the second strobe signal are opposite.

6. The display panel according to claim 1, characterized in that, The refresh rate of the first display partition is a first refresh rate, the refresh rate of the second display partition is a second refresh rate, and the first refresh rate is less than the second refresh rate; Within the first frame, the signals on the first strobe signal lines in the first display partition and the second display partition are at active levels, and the signals on the second strobe signal lines in the first display partition and the second display partition are at inactive levels, so that the sub-pixels in the first display partition and the second display partition are all written with data voltage. Within the second frame, the signal on the first strobe signal line in the first display partition is at the invalid level, and the signal on the second strobe signal line is at the valid level. The signal on the first strobe signal line in the second display partition is at the valid level, and the signal on the second strobe signal line is at the invalid level, so that the sub-pixels in the first display partition do not write data voltage, and the sub-pixels in the second display partition write data voltage.

7. The display panel according to claim 1, characterized in that, The display panel further includes a second scanning circuit, multiple second scanning lines, and multiple second gating circuits; the second scanning circuit is electrically connected to the corresponding second scanning line through the second gating circuit, and the second scanning line is connected to the corresponding pixel circuit group; the second gating circuit is used to select or turn off the second scanning line and the second scanning circuit, and is also used to transmit a turn-off level signal to the second scanning line.

8. The display panel according to claim 7, characterized in that, The gating signal line is connected to the second gating circuit. The second gating circuit is used to select or turn off the second scan line and the second scan circuit according to the signal on the gating signal line, and is also used to transmit the off level signal to the second scan line according to the signal on the gating signal line.

9. The display panel according to claim 8, characterized in that, The second gating circuit includes a third gating unit and a fourth gating unit. The control terminal of the third gating unit is connected to the first gating signal line, the first terminal of the third gating unit is connected to the second scanning circuit, and the second terminal of the third gating unit is connected to the second scanning line. It is used to select or turn off the second scanning line and the second scanning circuit according to the signal on the first gating signal line. The control terminal of the fourth gating unit is connected to the second gating signal line, the first terminal of the fourth gating unit is connected to the second scan line, and the second terminal of the fourth gating unit is connected to the off level signal, which is used to transmit the off level signal to the second scan line according to the signal on the second gating signal line.

10. The display panel according to claim 9, characterized in that, The first strobe signal line in each of the display partitions is connected to the third strobe unit of all rows; The second strobe signal line in each of the display partitions is connected to the fourth strobe unit of all rows.

11. The display panel according to claim 9, characterized in that, The third gating unit includes a third transistor, the gate of the third transistor serves as the gate of the third gating unit, the first electrode of the third transistor serves as the first terminal of the third gating unit, and the second electrode of the third transistor serves as the second terminal of the third gating unit.

12. The display panel according to claim 11, characterized in that, The fourth gating unit includes a fourth transistor, the gate of the fourth transistor serves as the control terminal of the fourth gating unit, the first electrode of the fourth transistor serves as the first terminal of the fourth gating unit, and the second electrode of the fourth transistor serves as the second terminal of the fourth gating unit.

13. The display panel according to claim 12, characterized in that, When the third transistor is turned on, the fourth transistor is turned off; or when the third transistor is turned off, the fourth transistor is turned on.

14. The display panel according to claim 1, characterized in that, The pixel circuit group includes multiple columns of pixel circuits, and the pixel circuit includes a driving module, a data writing module, and a threshold compensation module. The data writing module is electrically connected between the first end of the driving module and the data line, and is used to write the data voltage provided by the data line to the control end of the driving module according to the signal on the first scan line. The threshold compensation module is connected between the second end of the driving module and the control end, and is used to perform threshold compensation on the driving module according to the signal on the first scan line.

15. The display panel according to claim 14, characterized in that, The pixel circuit further includes a first initialization module, which is connected between the control terminal of the driving module and the first initialization voltage line, and is used to write the first initialization voltage provided by the first initialization voltage line to the control terminal of the driving module according to the signal on the second scan line.

16. The display panel according to claim 14, characterized in that, The pixel circuit further includes a light-emitting module and a light-emitting control module. The light-emitting control module, the driving module, and the light-emitting module are connected between the first power line and the second power line. The light-emitting control module is used to control the light-emitting module to emit light according to the driving current output by the driving module based on the signal on the light-emitting control signal line.

17. The display panel according to claim 16, characterized in that, The pixel circuit further includes a second initialization module, which is connected between the control terminal of the driving module and the second initialization voltage line, and is used to write the second initialization voltage provided by the second initialization voltage line to the first terminal of the light-emitting module according to the signal on the third scan line.

18. The display panel according to claim 14, characterized in that, The pixel circuit also includes a storage module, which is connected between the control terminal of the driving module and the first power line, and is used to store the voltage of the control terminal of the driving module.

19. A display device, characterized in that, Includes the display panel as described in any one of claims 1-18.

Images