Liquid crystal display and picture clearing method thereof

Abstract

A liquid crystal display comprises a display panel and a driving unit. The display panel comprises a plurality of reset areas which respectively and correspondingly display a plurality of pictures. A first voltage difference exists between one column voltage and one row voltage corresponding to one reset area, a second voltage difference exists between the other column voltage and the other row voltage corresponding to the other reset area, and the time when the second voltage difference reaches a second maximum voltage difference value has delay time compared with the time when the first voltage difference reaches the first maximum voltage difference value, so that the picture is cleared. Therefore, the surge current can be suppressed. The invention further relates to a picture clearing method of the related liquid crystal display.

Description

Technical Field

[0001] The invention relates to a liquid crystal display and a screen clearing method thereof, and in particular to a cholesterol liquid crystal display capable of reducing surge current and a screen clearing method thereof. Background Art

[0002] Driven by the pursuit of convenient life, various display technologies and devices have been developed, such as Cholesteric Liquid Crystal Display, which is often used in electronic paper, electronic billboards, etc. When the LCD screen is cleared, the power system will output the maximum voltage to complete it. However, when the voltage is output, excessive inrush current may be generated due to heavy load, causing the power system to malfunction or making the LCD screen unable to be cleared.

[0003] Therefore, how to develop a liquid crystal display and a screen clearing method thereof, which can suppress the surge current or reduce the energy of the surge current so that the power supply system and the screen of the liquid crystal display are not affected by the surge current, has become an important issue in the current market. Summary of the invention

[0004] The present invention provides a liquid crystal display and a screen clearing method thereof, wherein the display panel comprises a plurality of reset zones, wherein the reset zones correspond to displaying a plurality of screens respectively, and a first voltage difference is provided between a column voltage and a row voltage corresponding to a reset zone, and a second voltage difference is provided between another column voltage and another row voltage corresponding to another reset zone, and a time for the second voltage difference to reach a second maximum voltage difference value is delayed compared to a time for the first voltage difference to reach a first maximum voltage difference value, so as to suppress surge current while clearing the screen of the liquid crystal display.

[0005] According to one embodiment of the present invention, a liquid crystal display is provided, comprising a display panel and a driving unit. The display panel comprises a plurality of reset zones, and the reset zones correspond to displaying a plurality of images respectively. The driving unit is used to output a plurality of column voltages and a plurality of row voltages, and the column voltages correspond to the row voltages to drive the reset zones respectively. There is a first voltage difference between a column voltage and a row voltage corresponding to a reset zone, and there is a second voltage difference between another column voltage and another row voltage corresponding to another reset zone, and the time when the second voltage difference reaches a second maximum voltage difference value is delayed compared to the time when the first voltage difference reaches the first maximum voltage difference value, so as to clear the screen.

[0006] In the example of the liquid crystal display according to the aforementioned embodiment, at least one of the first maximum voltage difference value and the second maximum voltage difference value may be a vertical alignment voltage.

[0007] In an embodiment of a liquid crystal display according to the aforementioned implementation mode, the number of reset zones may be at least four, and the first voltage difference, second voltage difference, third voltage difference and fourth voltage difference between the four column voltages and the four row voltages corresponding to the four reset zones respectively achieve the first maximum voltage difference value, the second maximum voltage difference value, the third maximum voltage difference value and the fourth maximum voltage difference value in sequence with a delay time to clear the screen.

[0008] According to the embodiment of the liquid crystal display of the aforementioned implementation mode, the frame corresponding to the reset area can be cleared by the first maximum pressure difference value earlier than the second pressure difference reaches the second maximum pressure difference value.

[0009] In the example of the liquid crystal display according to the aforementioned implementation, the first maximum voltage difference value is the difference between the first maximum column voltage value and the first maximum row voltage value.

[0010] In the example of the liquid crystal display according to the aforementioned embodiment, the first pressure difference can reach a first maximum pressure difference value after passing through at least a first step pressure difference value, and the second pressure difference can reach a second maximum pressure difference value after passing through at least a second step pressure difference value.

[0011] According to another embodiment of the present invention, a screen clearing method for a liquid crystal display is provided, comprising: configuring a display panel of the liquid crystal display into multiple reset areas, wherein the reset areas correspond to displaying multiple screens respectively, and multiple column voltages correspond to multiple row voltages to drive the reset areas respectively; forming a first voltage difference between a column voltage and a row voltage corresponding to a reset area, and the first voltage difference reaches a first maximum voltage difference value; forming a second voltage difference between another column voltage and another row voltage corresponding to another reset area, and the second voltage difference reaches a second maximum voltage difference value, wherein the time for reaching the second maximum voltage difference value has a delay time compared to the time for reaching the first maximum voltage difference value; and clearing the screen by using the first maximum voltage difference value and the second maximum voltage difference value.

[0012] According to the embodiment of the screen clearing method of the liquid crystal display of the aforementioned embodiment, it may further include: forming a third voltage difference between another column voltage and another row voltage corresponding to another reset area, and the time when the third voltage difference reaches a third maximum voltage difference value has another delay time compared to the time when the second maximum voltage difference value is reached.

[0013] The embodiment of the screen clearing method of the liquid crystal display according to the aforementioned embodiment may further include: clearing a frame corresponding to the reset zone using the first maximum pressure difference value before the second pressure difference reaches the second maximum pressure difference value; and clearing another frame corresponding to another reset zone.

[0014] According to the embodiment of the screen clearing method of the liquid crystal display of the aforementioned embodiment, the first pressure difference reaching the first maximum pressure difference value can be periodically executed multiple times, and the second pressure difference reaching the second maximum pressure difference value can be periodically executed multiple times.

[0015] According to another embodiment of the present invention, a screen clearing method for a liquid crystal display is provided, comprising: configuring a display panel of the liquid crystal display into multiple reset areas, wherein the reset areas correspond to displaying multiple screens respectively, and multiple column voltages correspond to multiple row voltages to drive the reset areas respectively; forming a first voltage difference between a column voltage and a row voltage corresponding to a reset area, and at least one first step voltage difference value is achieved before the first voltage difference reaches a first maximum voltage difference value; forming a second voltage difference between another column voltage and another row voltage corresponding to another reset area, and the second voltage difference reaches a second maximum voltage difference value, wherein the time for achieving the second maximum voltage difference value has a delay time compared to the time for achieving the first maximum voltage difference value, and at least one second step voltage difference value is achieved before the second voltage difference reaches the second maximum voltage difference value; and clearing the screen by using the first maximum voltage difference value and the second maximum voltage difference value.

[0016] In an embodiment of the screen clearing method of a liquid crystal display according to the aforementioned embodiment, at least one first step voltage difference value is the difference between at least one first column step voltage value and at least one first row step voltage value, and the number of steps of at least one first column step voltage value and the number of steps of at least one first row step voltage value may be the same or different. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A A schematic diagram illustrating a cholesteric liquid crystal display according to a first embodiment of the present invention;

[0018] Figure 1B A schematic diagram showing column voltages and row voltages in a partial reset region of a cholesterol liquid crystal display according to the first embodiment;

[0019] Figure 1C A schematic diagram showing the column voltage of the cholesteric liquid crystal display of the first embodiment;

[0020] Figure 1D A flow chart showing a screen clearing method of a cholesterol liquid crystal display according to a first embodiment;

[0021] Figure 2A A schematic diagram illustrating column voltages and row voltages in a partial reset region of a cholesteric liquid crystal display according to a second embodiment of the present invention;

[0022] Figure 2B A schematic diagram illustrating the column voltage of a cholesteric liquid crystal display according to the second embodiment;

[0023] Figure 2C A flow chart showing a screen clearing method of a cholesterol liquid crystal display according to a second embodiment;

[0024] Figure 3A A schematic diagram illustrating column voltages and row voltages of a cholesteric liquid crystal display according to a third embodiment of the present invention;

[0025] Figure 3B A schematic diagram showing another row voltage and column voltage of the cholesterol liquid crystal display of the third embodiment;

[0026] Figure 3C A flow chart showing a screen clearing method of a cholesterol liquid crystal display according to a third embodiment;

[0027] Figure 4A A schematic diagram illustrating column voltages and row voltages in a partial reset region of a cholesteric liquid crystal display according to a fourth embodiment of the present invention;

[0028] Figure 4B A schematic diagram illustrating the column voltage of a cholesteric liquid crystal display according to a fourth embodiment; and

[0029] Figure 4C A flow chart of a screen clearing method of a cholesteric liquid crystal display according to a fourth embodiment is shown.

[0030] The reference numerals are described as follows:

[0031] 10: Cholesteric LCD

[0032] 11: First reset zone

[0033] 12: Second reset area

[0034] 13: Third reset zone

[0035] 14: Fourth reset zone

[0036] 15: Display Panel

[0037] 17: Column drive circuit

[0038] 18: Row drive circuit

[0039] 19: Drive unit

[0040] 100, 200, 300, 400: Screen clearing method

[0041] 110, 141, 142, 143, 144, 180, 210, 241, 242, 243, 244, 261, 262, 263, 264, 280, 321, 341, 380, 410, 421, 422, 423, 424, 441, 442, 443, 444, 480: Steps

[0042] td: delay time

[0043] tm: duration of maximum pressure difference

[0044] Vc1, Vc2, Vc3, Vc4: column voltage

[0045] Vmc1: The first maximum column voltage value

[0046] Vmc2: The second largest column voltage value

[0047] Vmc3: The third maximum column voltage value

[0048] Vmc4: the fourth maximum column voltage value

[0049] Vmr1: The first maximum row voltage value

[0050] Vmr2: The second maximum row voltage value

[0051] Vr1, Vr2: row voltage

[0052] Vref: reference voltage value

[0053] Vsc1: The first column step voltage value

[0054] Vsc2: The second column step voltage value

[0055] Vsc3: The third column step voltage value

[0056] Vsc4: The fourth column step voltage value

[0057] Vsr1: first row step voltage value

[0058] Vsr2: second row step voltage value DETAILED DESCRIPTION

[0059] The following will describe multiple embodiments of the present invention with reference to the accompanying drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in the embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be depicted in a simple schematic manner in the drawings; and repeated elements may be represented by the same number.

[0060] In addition, the terms "first" and "second" are only used to describe different components, but do not limit the components themselves. Therefore, the first component can also be called the second component. Moreover, the combination of components in this article is not a generally known, conventional or conventional combination in this field. Whether the components themselves are conventional cannot be used to determine whether their combination relationship is easy to be easily completed by ordinary knowledgeable people in the technical field.

[0061] Please refer to Figure 1AThe schematic diagram of a cholesteric liquid crystal display according to the first embodiment of the present invention is shown. The liquid crystal display according to the present invention may be, for example but not limited to, a cholesteric liquid crystal display 10, which includes a display panel 15 and a driving unit 19. The display panel 15 includes a plurality of reset areas, such as a first reset area 11 and a second reset area 12. Each of the first reset area 11 and the second reset area 12 includes a plurality of pixel matrices to display a plurality of images respectively.

[0062] Please also read Figure 1B A schematic diagram of column voltages and row voltages of a partial reset area of ​​a cholesterol liquid crystal display of the first embodiment is shown, wherein a driving unit 19 is used to output column voltages (column driving voltages) Vc1, Vc2 and row voltages (row driving voltages) Vr1, Vr2 of a first reset area 11 and a second reset area 12, wherein the column voltage Vc1 drives the first reset area 11 through the column driving circuit 17 and the row voltage Vr1 drives the row driving circuit 18 in correspondence, and the column voltage Vc2 drives the second reset area 12 through the column driving circuit 17 and the row voltage Vr2 drives the row driving circuit 18 in correspondence. There is a first voltage difference (i.e. |Vc1-Vr1|) between the column voltage Vc1 and the row voltage Vr1 corresponding to the first reset zone 11, and there is a second voltage difference (i.e. |Vc2-Vr2|) between the column voltage Vc2 and the row voltage Vr2 corresponding to the second reset zone 12. The time when the second voltage difference reaches the second maximum voltage difference value has a delay time td compared to the time when the first voltage difference reaches the first maximum voltage difference value, and the maximum voltage difference duration time tm of the first maximum voltage difference value and the second maximum voltage difference value partially overlap, which are used to clear the screens corresponding to the first reset zone 11 and the second reset zone 12 respectively. In this way, the screen corresponding to the second reset zone 12 is cleared in a very short time after the screen corresponding to the first reset zone 11 is cleared, and the surge current is suppressed by time-sharing and partition driving, which helps to successfully clear the screen, so that the screen display is normal and the cholesterol liquid crystal display 10 can operate normally. Since no additional parts are required, the low cost requirement can be met.

[0063] In detail, at least one of the first maximum voltage difference value and the second maximum voltage difference value may be a homeotropic voltage. In this way, the image corresponding to the reset area can be effectively cleared. In the first embodiment, the first maximum voltage difference value and the second maximum voltage difference value are both homeotropic voltages. In other embodiments of the present invention, each maximum voltage difference value may be greater than, less than, or equal to the homeotropic voltage, and the image corresponding to the reset area can be cleared with an appropriate maximum voltage difference duration tm.

[0064] The first maximum voltage difference value is the difference between the first maximum column voltage value Vmc1 and the first maximum row voltage value Vmr1 at the same time point, and the first maximum column voltage value Vmc1 and the first maximum row voltage value Vmr1 may have different signs relative to the reference voltage value Vref (e.g., 0 volt); the second maximum voltage difference value is the difference between the second maximum column voltage value Vmc2 and the second maximum row voltage value Vmr2 at the same time point, and the second maximum column voltage value Vmc2 and the second maximum row voltage value Vmr2 may have different signs relative to the reference voltage value Vref. Further, the reference voltage value Vref of the column voltage Vc1 and the reference voltage value Vref of the row voltage Vr1 may be the same (e.g., 0 volt) or different. Furthermore, the absolute value of the difference between the first maximum column voltage value Vmc1 and the reference voltage value Vref and the absolute value of the difference between the first maximum row voltage value Vmr1 and the reference voltage value Vref may be the same or different. The absolute value of the difference between each of the first maximum column voltage value Vmc1, the first maximum row voltage value Vmr1, the second maximum column voltage value Vmc2, and the second maximum row voltage value Vmr2 and the reference voltage value Vref is half of the vertical alignment voltage. This is conducive to providing convenience in driving voltage design. In the first embodiment, the column voltage Vc1 and the row voltage Vr1 are inverse waveforms to each other, the column voltage Vc2 and the row voltage Vr2 are inverse waveforms to each other, the column voltages Vc1 and Vc2 have the same waveform, and the waveform of the column voltage Vc2 has a delay time td relative to the waveform of the column voltage Vc1.

[0065] Please refer to Figure 1C The schematic diagram of the column voltage of the cholesterol liquid crystal display of the first embodiment is drawn. Specifically, the display panel 15 further includes a third reset zone 13 and a fourth reset zone 14, and the number and arrangement of the reset zones according to the present invention are not limited to those disclosed in the accompanying drawings. Each of the third reset zone 13 and the fourth reset zone 14 includes a plurality of pixel matrices, and respectively displays a plurality of pictures. In this way, the display panel according to the present invention may include at least four reset zones, and the same or different (independent) delay time td may be set in the power timing of each reset zone of any size, which is the reset section delay time (Reset Section Delay Time), so as to achieve an asynchronous time-sharing power-on mode to disperse the power timing of driving the display panel 15, avoid driving an excessive load and generating a surge current that the cholesterol liquid crystal display 10 cannot withstand, resulting in a control system power error or the display panel 15 cannot be cleared and / or display abnormality.

[0066] The driving unit 19 is further configured to output column voltages Vc3, Vc4 and two row voltages, wherein the column voltage Vc3 and a row voltage correspondingly drive the third reset zone 13, and the column voltage Vc4 and another row voltage correspondingly drive the fourth reset zone 14. There is a third voltage difference between the column voltage Vc3 and the row voltage corresponding to the third reset zone 13, and there is a fourth voltage difference between the column voltage Vc4 and the row voltage corresponding to the fourth reset zone 14. The time when the third voltage difference reaches the third maximum voltage difference value is delayed by a time td compared to the time when the second voltage difference reaches the second maximum voltage difference value, and the time when the fourth voltage difference reaches the fourth maximum voltage difference value is delayed by a time td compared to the time when the third voltage difference reaches the third maximum voltage difference value. Further, the first pressure difference, the second pressure difference, the third pressure difference and the fourth pressure difference sequentially reach the first maximum pressure difference value, the second maximum pressure difference value, the third maximum pressure difference value and the fourth maximum pressure difference value with the same or different delay time td, and maintain each of the first maximum pressure difference value, the second maximum pressure difference value, the third maximum pressure difference value and the fourth maximum pressure difference value in the active reset phase of the maximum pressure difference duration tm, so as to clear the screen of the cholesterol liquid crystal display 10. In addition, other details of the third reset zone 13 and the fourth reset zone 14 can refer to the contents of the first reset zone 11 and the second reset zone 12, which will not be described in detail here.

[0067] Please also read Figure 1D The flowchart of the screen clearing method of the cholesteric liquid crystal display of the first embodiment is shown. The screen clearing method 100 of the cholesteric liquid crystal display 10 specifically includes steps 110 , 141 , 142 , 143 , 144 , and 180 .

[0068] Step 110 includes configuring the display panel 15 of the cholesteric liquid crystal display 10 into a first reset area 11 , a second reset area 12 , a third reset area 13 and a fourth reset area 14 .

[0069] Step 141 includes forming a first voltage difference between the column voltage Vc1 and the row voltage Vr1 corresponding to the first reset area 11 , and causing the first voltage difference to reach a first maximum voltage difference value.

[0070] Step 142 includes forming a second voltage difference between the column voltage Vc2 and the row voltage Vr2 corresponding to the second reset area 12, and causing the second voltage difference to reach a second maximum voltage difference value, wherein the time to reach the first second maximum voltage difference value is delayed by a time td compared to the time to reach the first first maximum voltage difference value.

[0071] Step 143 includes forming a third voltage difference between the column voltage Vc3 and the row voltage corresponding to the third reset area 13, and causing the third voltage difference to reach a third maximum voltage difference value, wherein the time of reaching the first third maximum voltage difference value is delayed by a time td compared to the time of reaching the first second maximum voltage difference value.

[0072] Step 144 includes forming a fourth voltage difference between the column voltage Vc4 and the row voltage corresponding to the fourth reset area 14, and causing the fourth voltage difference to reach a fourth maximum voltage difference value, wherein the time of reaching the first fourth maximum voltage difference value is delayed by a time td compared to the time of reaching the first third maximum voltage difference value.

[0073] Furthermore, please refer to Figure 1B and Figure 1C , each of the first pressure difference reaching the first maximum pressure difference value, the second pressure difference reaching the second maximum pressure difference value, the third pressure difference reaching the third maximum pressure difference value, and the fourth pressure difference reaching the fourth maximum pressure difference value can be periodically executed multiple times. This helps to ensure that the screen is completely cleared and the inrush current is reduced. In the first embodiment, the first time the fourth pressure difference reaches the fourth maximum pressure difference value earlier than the second time the first pressure difference reaches the first maximum pressure difference value, and the present invention is not limited to this.

[0074] In the multiple times of achieving the first maximum voltage difference value, the second maximum voltage difference value, the third maximum voltage difference value and the fourth maximum voltage difference value, the first maximum column voltage value Vmc1, the first maximum row voltage value Vmr1, the second maximum column voltage value Vmc2, the second maximum row voltage value Vmr2, the third maximum column voltage value Vmc3, the third maximum row voltage value, the fourth maximum column voltage value Vmc4 and the fourth maximum row voltage value are each alternately positive and negative relative to the reference voltage value Vref. This is beneficial to completely clear the screen and reduce the complexity of circuit design.

[0075] Step 180 includes clearing the image of the cholesterol liquid crystal display 10 by using the first maximum pressure difference value, the second maximum pressure difference value, the third maximum pressure difference value and the fourth maximum pressure difference value.

[0076] Figure 2A A schematic diagram showing column voltages and row voltages in a partial reset region of a cholesteric liquid crystal display according to a second embodiment of the present invention is shown. Figure 2B A schematic diagram showing the column voltage of a cholesteric liquid crystal display according to the second embodiment is shown. Figure 2C A flow chart of a screen clearing method of a cholesterol liquid crystal display according to the second embodiment is shown. FIG. 2A to FIG. 2C The screen clearing method 200 of the cholesterol liquid crystal display of the second embodiment specifically includes steps 210, 241, 261, 242, 262, 243, 263, 244, 264, and 280.

[0077] Step 210 includes configuring the display panel of the cholesterol liquid crystal display into a first reset area, a second reset area, a third reset area and a fourth reset area. For other details of the first reset area, the second reset area, the third reset area and the fourth reset area, reference may be made to the contents of the first embodiment above and will not be described in detail here.

[0078] Step 241 includes forming a first voltage difference between the column voltage Vc1 and the row voltage Vr1 corresponding to the first reset region, and causing the first voltage difference to reach a first maximum voltage difference value and being periodically executed multiple times. Step 261 includes clearing the frame corresponding to the first reset region.

[0079] Step 242 includes forming a second voltage difference between the column voltage Vc2 and the row voltage Vr2 corresponding to the second reset area, and causing the second voltage difference to reach a second maximum voltage difference value, wherein the time when the second maximum voltage difference value is reached for the first time is delayed by a time td compared to the time when the first maximum voltage difference value is reached for the first time, and the second voltage difference reaching the second maximum voltage difference value is periodically performed multiple times. Step 262 includes clearing the screen corresponding to the second reset area.

[0080] In other words, in the second embodiment, the screen corresponding to the first reset area is cleared by the first maximum pressure difference value (step 261) earlier than the second pressure difference reaches the second maximum pressure difference value for the first time (step 242). In this way, the display panel driving design is divided into multiple reset areas or at least four reset areas, and cleared in small blocks, so that the power supply only needs to clear the panel of one small block at a time, avoiding driving too large a load at one time and generating too large a surge current, resulting in a control system power supply error or the display panel cannot be cleared and / or display abnormality. In addition, the delay time td in the screen clearing method 200 is greater than the delay time td in the screen clearing method 100.

[0081] Step 243 includes forming a third voltage difference between the column voltage Vc3 and the row voltage corresponding to the third reset area, and causing the third voltage difference to reach a third maximum voltage difference value, wherein the time when the third maximum voltage difference value is reached for the first time is delayed by a time td compared to the time when the second maximum voltage difference value is reached for the first time, and the third voltage difference reaching the third maximum voltage difference value is periodically performed multiple times. Step 263 includes clearing the screen corresponding to the third reset area.

[0082] Step 244 includes forming a fourth voltage difference between the column voltage Vc4 and the row voltage corresponding to the fourth reset zone, and causing the fourth voltage difference to reach a fourth maximum voltage difference value, wherein the time when the fourth maximum voltage difference value is reached for the first time is delayed by a time td compared to the time when the third maximum voltage difference value is reached for the first time, and the fourth voltage difference reaching the fourth maximum voltage difference value is periodically performed multiple times. Step 264 includes clearing the screen corresponding to the fourth reset zone.

[0083] Furthermore, among the multiple times of achieving the first maximum voltage difference value, the second maximum voltage difference value, the third maximum voltage difference value and the fourth maximum voltage difference value, each of the first maximum column voltage value Vmc1, the first maximum row voltage value Vmr1, the second maximum column voltage value Vmc2, the second maximum row voltage value Vmr2, the third maximum column voltage value Vmc3, the third maximum row voltage value, the fourth maximum column voltage value Vmc4 and the fourth maximum row voltage value alternates between positive and negative signs relative to the reference voltage value Vref.

[0084] Step 280 is to clear the screen of the cholesteric liquid crystal display by using the first maximum pressure difference value, the second maximum pressure difference value, the third maximum pressure difference value and the fourth maximum pressure difference value after sequentially executing the aforementioned steps 210 to 264. In other embodiments (not shown) according to the present invention, the screen of the cholesteric liquid crystal display can be cleared by combining the aforementioned screen clearing methods 100 and 200.

[0085] Figure 3A A schematic diagram showing the column voltage and row voltage of a cholesteric liquid crystal display according to a third embodiment of the present invention is shown. Figure 3B FIG. 1 is a schematic diagram showing another row voltage and a column voltage of a cholesterol liquid crystal display according to the third embodiment. Figure 3C A flow chart of a screen clearing method of a cholesterol liquid crystal display according to a third embodiment is shown. FIG. 3A to FIG. 3C The screen clearing method 300 of the cholesteric liquid crystal display of the third embodiment specifically includes steps 321, 341, and 380, and the display panel of the cholesteric liquid crystal display of the third embodiment may not be configured into a plurality of reset areas or blocks.

[0086] Step 321 includes forming a first voltage difference between the column voltage Vc1 and the row voltage Vr1 of the display panel, and causing the first voltage difference to reach at least a first step voltage difference value, specifically causing the first voltage difference to reach a plurality of first step voltage difference values ​​in sequence.

[0087] Furthermore, each first step voltage difference is the difference between the first row step voltage value Vsc1 and the first column step voltage value Vsr1 at the same time point, and the number of steps of the first row step voltage value Vsc1 and the first column step voltage value Vsr1 can be different or the same. This can improve circuit design flexibility.

[0088] Step 341 includes causing the first voltage difference to reach a first maximum voltage difference value, and before the first voltage difference reaches the first maximum voltage difference value, a plurality of first step voltage difference values ​​are reached (step 321). Furthermore, step 341 may further include causing the first voltage difference to reach the plurality of first step voltage difference values ​​in reverse timing and then reach a reference voltage value Vref after the first maximum voltage difference value continues for a maximum voltage difference duration tm. Step 380 includes clearing the screen of the cholesterol liquid crystal display by the first maximum voltage difference value. In this way, the column end and the row end of the electrodes at both ends of the display panel are driven in a multi-stage stepping manner so that the voltage difference reaches the vertical alignment driving voltage to perform the clearing action, which can reduce the surge current and effectively avoid stopping the clearing action or the screen clearing not being clean.

[0089] Figure 4A A schematic diagram showing column voltages and row voltages in a partial reset region of a cholesteric liquid crystal display according to a fourth embodiment of the present invention is shown. Figure 4B A schematic diagram showing the column voltage of a cholesteric liquid crystal display according to a fourth embodiment is shown. Figure 4C A flowchart of a screen clearing method of a cholesterol liquid crystal display according to a fourth embodiment is shown. FIG. 4A to FIG. 4C The screen clearing method 400 of the cholesterol liquid crystal display of the fourth embodiment specifically includes steps 410, 421, 422, 423, 424, 441, 442, 443, 444, and 480.

[0090] Step 410 includes configuring the display panel of the cholesterol liquid crystal display into a first reset area, a second reset area, a third reset area and a fourth reset area. For other details of the first reset area, the second reset area, the third reset area and the fourth reset area, reference may be made to the contents of the first embodiment above and will not be described in detail here.

[0091] Step 421 includes forming a first voltage difference between the column voltage Vc1 and the row voltage Vr1 corresponding to the first reset region, and causing the first voltage difference to reach at least one first step voltage difference value, specifically causing the first voltage difference to reach a plurality of first step voltage difference values ​​in sequence.

[0092] Step 422 includes forming a second voltage difference between the column voltage Vc2 and the row voltage Vr2 corresponding to the second reset region, and causing the second voltage difference to sequentially reach a plurality of second step voltage difference values.

[0093] Step 423 includes forming a third voltage difference between the column voltage Vc3 and the row voltage corresponding to the third reset region, and causing the third voltage difference to sequentially reach a plurality of third step voltage difference values.

[0094] Step 424 includes forming a fourth voltage difference between the column voltage Vc4 and the row voltage corresponding to the fourth reset region, and causing the fourth voltage difference to sequentially reach a plurality of fourth step voltage difference values.

[0095] Step 441 includes causing the first pressure difference to reach a first maximum pressure difference value, and before the first pressure difference reaches the first maximum pressure difference value, it reaches a plurality of first step pressure difference values ​​(step 421). In the fourth embodiment, the first time the fourth pressure difference reaches the first of the plurality of fourth step pressure difference values ​​earlier than the first time the first pressure difference reaches the first maximum pressure difference value, and the present invention is not limited thereto.

[0096] Step 442 includes causing the second pressure difference to reach a second maximum pressure difference value, wherein the time when the second maximum pressure difference value is reached for the first time is delayed by a time td compared to the time when the first maximum pressure difference value is reached for the first time, and the second pressure difference reaches a plurality of second step pressure difference values ​​before reaching the second maximum pressure difference value (step 422).

[0097] Step 443 includes causing the third pressure difference to reach a third maximum pressure difference value, wherein the time when the third maximum pressure difference value is reached for the first time has a delay time td compared to the time when the second maximum pressure difference value is reached for the first time, and the third pressure difference reaches a plurality of third step pressure difference values ​​before reaching the third maximum pressure difference value (step 423).

[0098] Step 444 includes causing the fourth pressure difference to reach a fourth maximum pressure difference value, wherein the time when the fourth maximum pressure difference value is reached for the first time has a delay time td compared to the time when the third maximum pressure difference value is reached for the first time, and the fourth pressure difference reaches a plurality of fourth step pressure difference values ​​before reaching the fourth maximum pressure difference value (step 424).

[0099] Furthermore, the number of steps of the first column step voltage value Vsc1 and the number of steps of the first row step voltage value Vsr1 may be different or the same, and the second column step voltage value Vsc2, the second row step voltage value Vsr2, the third column step voltage value Vsc3, the third row step voltage value, the fourth column step voltage value Vsc4 and the fourth row step voltage value may also be designed in the same manner. The first voltage difference reaches the first maximum voltage difference value, the second voltage difference reaches the second maximum voltage difference value, the third voltage difference reaches the third maximum voltage difference value, and the fourth voltage difference reaches the fourth maximum voltage difference value, each of which may be periodically executed multiple times. In the fourth embodiment, the first time the fourth voltage difference reaches the fourth maximum voltage difference value is earlier than the second time the first voltage difference reaches the first maximum voltage difference value, and the present invention is not limited thereto.

[0100] Among the multiple times of achieving the first maximum voltage difference value, the second maximum voltage difference value, the third maximum voltage difference value and the fourth maximum voltage difference value, each of the first maximum column voltage value Vmc1, the first maximum row voltage value Vmr1, the second maximum column voltage value Vmc2, the second maximum row voltage value Vmr2, the third maximum column voltage value Vmc3, the third maximum row voltage value, the fourth maximum column voltage value Vmc4 and the fourth maximum row voltage value alternates between positive and negative signs relative to the reference voltage value Vref.

[0101] Step 480 includes clearing the screen of the cholesterol liquid crystal display through the first maximum voltage difference value, the second maximum voltage difference value, the third maximum voltage difference value and the fourth maximum voltage difference value. In this way, the combination of time-sharing / partitioning and multi-stage stepping driving can further suppress the surge current and further ensure the normal operation of the cholesterol liquid crystal display.

[0102] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the following claims.

Claims

1. A liquid crystal display, characterized in that: Include: A display panel comprising a plurality of reset areas, wherein the plurality of reset areas correspond to displaying a plurality of pictures respectively; and a driving unit for outputting a plurality of column voltages and a plurality of row voltages, wherein the plurality of column voltages are matched with the plurality of row voltages to drive the plurality of reset areas respectively; Among them, there is a first voltage difference between a column voltage and a row voltage corresponding to a reset zone, and there is a second voltage difference between another column voltage and another row voltage corresponding to another reset zone. The time when the second voltage difference reaches a second maximum voltage difference value has a delay time compared to the time when the first voltage difference reaches a first maximum voltage difference value, so as to clear the multiple screens.

2. The liquid crystal display according to claim 1, wherein: At least one of the first maximum voltage difference value and the second maximum voltage difference value is a vertical alignment voltage.

3. The liquid crystal display according to claim 1, wherein: The number of the multiple reset zones is at least four, and the first voltage difference, the second voltage difference, a third voltage difference and a fourth voltage difference between the four column voltages and the four row voltages respectively corresponding to the four reset zones achieve the first maximum voltage difference value, the second maximum voltage difference value, the third maximum voltage difference value and the fourth maximum voltage difference value in sequence within the delay time to clear the multiple screens.

4. The liquid crystal display according to claim 1, wherein: The frame corresponding to the reset area is cleared by the first maximum pressure difference value earlier than the second pressure difference reaches the second maximum pressure difference value.

5. The liquid crystal display according to claim 1, wherein: The first maximum voltage difference value is a difference between a first maximum column voltage value and a first maximum row voltage value.

6. The liquid crystal display according to claim 1, wherein: The first pressure difference reaches the first maximum pressure difference value after passing through at least a first step pressure difference value, and the second pressure difference reaches the second maximum pressure difference value after passing through at least a second step pressure difference value.

7. A method for clearing a screen of a liquid crystal display, characterized in that: Include: A display panel of a liquid crystal display is configured into a plurality of reset areas, wherein the plurality of reset areas correspond to displaying a plurality of images respectively, and a plurality of column voltages are matched with a plurality of row voltages to drive the plurality of reset areas respectively; A first voltage difference is formed between a column voltage and a row voltage corresponding to a reset area, and the first voltage difference reaches a first maximum voltage difference value; A second voltage difference is formed between another row voltage and another column voltage corresponding to another reset region, and the second voltage difference reaches a second maximum voltage difference value, wherein the time to reach the second maximum voltage difference value is delayed compared to the time to reach the first maximum voltage difference value; and The plurality of frames are cleared according to the first maximum pressure difference value and the second maximum pressure difference value.

8. The screen clearing method of a liquid crystal display according to claim 7, characterized in that: Also includes: A third voltage difference is formed between the further column voltage and the further row voltage corresponding to the further reset zone, and the time when the third voltage difference reaches a third maximum voltage difference value has another delay time compared with the time when the third voltage difference reaches the second maximum voltage difference value.

9. The screen clearing method of a liquid crystal display according to claim 7, wherein: Also includes: The frame corresponding to the reset area is cleared by using the first maximum pressure difference value, before the second pressure difference reaches the second maximum pressure difference value; and Clear the corresponding another frame of the another reset area.

10. The screen clearing method of a liquid crystal display according to claim 7, characterized in that: The first pressure difference reaches the first maximum pressure difference value and is periodically executed multiple times, and the second pressure difference reaches the second maximum pressure difference value and is periodically executed multiple times.

11. A method for clearing a screen of a liquid crystal display, characterized in that: Include: A display panel of a liquid crystal display is configured into a plurality of reset areas, wherein the plurality of reset areas correspond to displaying a plurality of images respectively, and a plurality of column voltages are matched with a plurality of row voltages to drive the plurality of reset areas respectively; A first voltage difference is formed between a row voltage and a column voltage corresponding to a reset region, and the first voltage difference reaches at least a first step voltage difference value before reaching a first maximum voltage difference value; A second voltage difference is formed between another row voltage and another column voltage corresponding to another reset region, and the second voltage difference reaches a second maximum voltage difference value, wherein the time when the second maximum voltage difference value is reached has a delay time compared to the time when the first maximum voltage difference value is reached, and the second voltage difference reaches at least one second step voltage difference value before reaching the second maximum voltage difference value; and The plurality of frames are cleared according to the first maximum pressure difference value and the second maximum pressure difference value.

12. The screen clearing method of a liquid crystal display according to claim 11, characterized in that: The at least one first step voltage difference value is a difference between at least one first row step voltage value and at least one first column step voltage value, and the step number of the at least one first row step voltage value is the same as or different from the step number of the at least one first column step voltage value.

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