Sense amplifier, method of operating same, and memory device including same

Abstract

A sense amplifier connected with a bit line and a complementary bit line, the sense amplifier including: a first transistor connected between the bit line and a first node, and including a first gate terminal connected to a third node; a second transistor connected between the first node and the complementary bit line, and including a second gate terminal connected to a fourth node; a third transistor connected between the bit line and the second node, and including a third gate terminal connected to a third node; and a fourth transistor connected between the complementary bit line and the second node and including a fourth gate terminal connected to the fourth node, in which a first RC value and a second RC value observed from the sense amplifier toward the bit line and the complementary bit line are different, and in which the second transistor is configured to receive the program voltage during the first time period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0131992 filed on October 4, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor memory device and more particularly to a sense amplifier included in a semiconductor memory device and an operation method thereof. Background Art

[0004] The sense amplifier may be connected to the memory cell array through a bit line and a complementary bit line. The sense amplifier may sense and amplify a voltage difference between the bit line and the complementary bit line, wherein the voltages of the bit line and the complementary bit line are determined according to or based on data stored in the memory cell array.

[0005] However, the connection of the sense amplifier to the bit line and the complementary bit line may be unbalanced. For example, depending on the implementation method or process dispersion of the memory device, the sense amplifier may be unbalancedly connected to the bit line and the complementary bit line. In this case, the operation of the sense amplifier may fail. Summary of the invention

[0006] The present disclosure may provide solutions to one or more technical problems, including (but not limited to) the above-mentioned technical problems. More specifically, the present disclosure may provide a sense amplifier and an operating method thereof, the sense amplifier compensating for the imbalance of the connection with the bit line and the complementary bit line.

[0007] Some embodiments of the present disclosure provide a sense amplifier connected to a bit line and a complementary bit line, the sense amplifier comprising: a first transistor connected between the bit line and a first node, the first transistor comprising a first gate terminal connected to a third node; a second transistor connected between the first node and the complementary bit line, the second transistor comprising a second gate terminal connected to a fourth node; a third transistor connected between the bit line and the second node, the third transistor comprising a third gate terminal connected to the third node; and a fourth transistor connected between the complementary bit line and the second node, the fourth transistor comprising a fourth gate terminal connected to the fourth node, wherein a first resistance-capacitance (RC) value observed from the sense amplifier toward the bit line is less than a second RC value observed from the sense amplifier toward the complementary bit line, and wherein the second transistor is configured to receive a programming voltage higher than a power supply voltage during a first time period.

[0008] Some embodiments of the present disclosure provide an operating method for a sense amplifier connected to a bit line and a complementary bit line, the operating method comprising: performing a first precharging operation on the bit line and the complementary bit line; performing a first read operation on the bit line and the complementary bit line that are precharged based on the first precharging operation; and performing a first programming operation on a first transistor connected to one of the bit line and the complementary bit line in response to a voltage level of the bit line being changed to a first voltage level based on the first read operation.

[0009] Some embodiments of the present disclosure provide a memory device, the memory device comprising: a memory cell array connected to a bit line and a complementary bit line; and a sense amplifier connected to the bit line through a first conductive line, and connected to the complementary bit line through a second conductive line having a length different from that of the first conductive line. The sense amplifier may include: a first transistor and a second transistor connected in series between the first conductive line and the second conductive line and having a first channel type; and a third transistor and a fourth transistor connected in series between the first conductive line and the second conductive line and having a second channel type, wherein the threshold voltages of the first transistor and the second transistor are different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram of a memory device according to some embodiments of the present disclosure is shown.

[0011] Figure 2 Shows Figure 1 Detailed block diagram of the sense amplifier.

[0012] Figure 3 According to some embodiments Figure 2 Detailed circuit diagram of the sense amplifier.

[0013] Figure 4A , Figure 4B and Figure 4C A method of compensating for imbalance in the connection of a sense amplifier to a bit line and a complementary bit line is shown according to some embodiments of the present disclosure.

[0014] Figure 5 Shows Figure 3 Detailed diagram of a charge trapping transistor.

[0015] Figure 6 Shows Figure 5 A graph showing the relationship between the total programming time and the threshold voltage of a charge trapping transistor.

[0016] Figure 7 Shown according to Figure 3 The programming number of the charge trap transistor is the readout standard of the sense amplifier.

[0017] Figure 8 Shows Figure 1 A flow chart of the operation of a memory device.

[0018] Fig. 9 Shows Figure 8 Detailed flowchart of step S120.

[0019] Fig.10 The present invention is shown in some embodiments. Figure 3 Detailed circuit diagram of the sense amplifier.

[0020] Fig.11 Shows Fig.10 Timing diagram of the operation of the sense amplifier.

[0021] Fig.12 The present invention is shown in some embodiments. Figure 3 Detailed circuit diagram of the sense amplifier.

[0022] Fig.13 Shows Fig.12 Timing diagram of the operation of the sense amplifier.

[0023] Fig.14 The present invention is shown in some embodiments. Figure 2 of the sense amplifier.

[0024] Fig.15 Shown according to Fig.14 The programming number of the charge trap transistor is the readout standard of the sense amplifier.

[0025] Fig.16 The embodiment shown in FIG. Figure 2 of the sense amplifier.

[0026] Fig.17 The present invention is shown in some embodiments. Figure 2 Detailed circuit diagram of the sense amplifier.

[0027] Fig.18A and Fig.18B Shows Fig.17 Timing diagram of the operation of the sense amplifier.

[0028] Fig.19 Some embodiments of the present disclosure are shown Fig.17 Timing diagram of the operation of the sense amplifier.

[0029] Fig. 20 Shown according to Fig.19 The timing diagram is implemented Figure 8 Detailed flowchart of step S120.

[0030] Fig.21The present invention is shown in some embodiments. Figure 2 Detailed circuit diagram of the sense amplifier.

[0031] Fig. 22 Some embodiments of the present disclosure are shown Figure 1 A block diagram of some components of a memory device.

[0032] Fig.23 The present invention is shown in some embodiments. Figure 1 A perspective view of a storage device.

[0033] Fig.24 Shows Fig.23 A top view of the storage cell area (CELL).

[0034] Fig.25 Shown along Fig.23 and Fig.24 A cross-sectional view taken along line CC'. DETAILED DESCRIPTION

[0035] Hereinafter, some embodiments of the present disclosure will be described in detail and clearly enough to allow those skilled in the art to implement the present disclosure. Only some details (e.g., various components and structures described in the specification) are provided to help fully understand the examples of the embodiments currently provided herein. Therefore, it should be clear to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. In addition, for the sake of clarity and brevity, the description of known functions and structures can be omitted. In the drawings or in the following specific embodiments, in addition to the components described as being unconnectable as shown in the drawings or described in the specific embodiments, some components may be connected to any other components. The terms used herein may include terms defined in view of various functions without being limited to specific functions. The definition of terms should be determined based on the content throughout the specification.

[0036] Some components (e.g., components described in the detailed description with reference to terms "driver", "controller", "block", etc.) can be implemented in software, hardware, or a combination thereof. For example, software can be or can include machine code, firmware, embedded code, and application software. For example, hardware can be or can include circuits, electronic circuits, processors, microprocessors, computers, integrated circuit cores, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), and / or passive components, or a combination of two or more thereof.

[0037] Figure 1 FIG. 1 is a block diagram of a memory device according to some embodiments of the present disclosure. Figure 1, the memory device 100 may include a memory cell array 110 , a row decoder 120 , a sense amplifier (S / A) array 130 , an input / output (I / O) circuit 140 , and a control logic circuit 150 .

[0038] The memory cell array 110 may include a plurality of memory cells arranged in row and column directions. The plurality of memory cells may be connected to a plurality of word lines WL extending in the row direction and a plurality of bit lines BL extending in the column direction.

[0039] Hereinafter, for a more concise description, an example of an embodiment in which each of the plurality of memory cells is a dynamic random access memory (DRAM) cell will be mainly described. However, the scope of the present disclosure is not limited thereto, and each of the plurality of memory cells may be any type of volatile memory cell (e.g., a static random access memory (SRAM) cell), or any type of non-volatile memory cell (e.g., a flash memory cell). That is, the scope of the present disclosure is not limited to the DRAM type memory device 100 described herein.

[0040] The row decoder 120 may control a plurality of word lines WL. For example, the row decoder 120 may be based on a plurality of word lines WL. Figure 1 The address ADDR (not shown) is provided to the control logic circuit 150 to activate some of the plurality of word lines WL.

[0041] The sense amplifier array 130 may include a plurality of sense amplifiers SA. For example, the sense amplifier array 130 may include first to nth sense amplifiers SA1 to SAn.

[0042] Each of the plurality of sense amplifiers SA may be connected to a plurality of bit lines BL. For example, each of the plurality of sense amplifiers SA may be connected to a bit line and a bit line complementary to the bit line (hereinafter referred to as a complementary bit line). Each of the plurality of sense amplifiers SA may sense and amplify a voltage level change of the bit line BL connected to each of the sense amplifiers SA based on a voltage level difference between the bit line and the complementary bit line connected to the bit line.

[0043] In some embodiments, the connection of each of the plurality of sense amplifiers SA to the bit line and the connection to the complementary bit line may be unbalanced. For example, due to the structural or process dispersion of the memory device 100, each of the plurality of sense amplifiers SA may be unbalancedly connected to the bit line and the complementary bit line. In this case, the voltage levels of the bit line and the complementary bit line may be amplified differently from the expected or desired voltage levels (e.g., amplified in a manner different from the expected or desired voltage levels that exist when the bit line and the complementary bit line are connected to the sense amplifier SA in a balanced manner). That is, due to the unbalanced connection of each of the plurality of sense amplifiers SA to the bit line and the complementary bit line, errors may occur in the operation of the sense amplifiers.

[0044] In some embodiments, each of the plurality of sense amplifiers SA may include one or more charge trapping transistors. In this case, depending on the amount of charge trapped in the charge trapping transistors, the imbalance of the connection of each of the plurality of sense amplifiers SA to the bit line and the complementary bit line may be compensated or mitigated. A more detailed configuration and operation of the sense amplifier SA will be provided herein.

[0045] The input / output circuit 140 may output data corresponding to a change in a voltage level of the bit line BL amplified by the sense amplifier array 130 to the outside (eg, an external device) and / or may receive data from the outside (eg, an external device or an external source).

[0046] The control logic circuit 150 may receive a command CMD and an address ADDR, for example, from an external source or an external device. The control logic circuit 150 may control the overall operation of the memory device 100 based on the command CMD and the address ADDR.

[0047] In some embodiments, the control logic circuit 150 may provide a plurality of control signals to the sense amplifier array 130. For example, the control logic circuit 150 may provide a plurality of control signals to the sense amplifier array 130 to control the operation of each of the plurality of sense amplifiers SA. However, the present disclosure is not limited thereto.

[0048] Figure 2 Shows Figure 1 Detailed block diagram of a sense amplifier (ie, one sense amplifier SA among a plurality of sense amplifiers of the sense amplifier array 130) is shown. Figure 1 and Figure 2 Representative description Figure 1 Configuration of one of the plurality of sense amplifiers SA shown.

[0049] The sense amplifier SA may be connected to the bit line BL and the complementary bit line BLB. That is, the sense amplifier SA may be connected to the memory cell array 110 through both the bit line BL and the complementary bit line BLB.

[0050] The sense amplifier SA may include a sense circuit 131 and an equalizer circuit 132. Each of the sense circuit 131 and the equalizer circuit 132 may be connected between a bit line BL and a complementary bit line BLB.

[0051] The equalization circuit 132 may perform a precharge operation on the bit line BL and the complementary bit line BLB. For example, the equalization circuit 132 may provide a precharge voltage to the bit line BL and the complementary bit line BLB. That is, the equalization circuit 132 may precharge the bit line BL and the complementary bit line BLB based on a single precharge voltage.

[0052] After performing the precharge operation, the memory device 100 may perform a memory cell activation operation. For example, the memory device 100 may activate one of the memory cells included in the memory cell array 110 by activating any word line WL. In this case, the voltage level of the bit line BL may change based on the amount of charge stored in the activated memory cell. That is, when performing the memory cell activation operation, charge sharing may occur between the memory cell and the bit line BL.

[0053] After charge sharing is completed, the readout circuit 131 may perform a readout operation. For example, the readout circuit 131 may read and amplify a change in the voltage level of the bit line BL based on the voltage levels of the bit line BL and the complementary bit line BLB, which may be increased or decreased by charge sharing.

[0054] As a more detailed example, when performing a read operation, the read circuit 131 may raise the voltage level of a first line (one of the bit line BL and the complementary bit line BLB) having a relatively high voltage level to a power supply voltage, and may lower the voltage level of a second line (the other of the bit line BL and the complementary bit line BLB) having a relatively low voltage level to a ground voltage. In this case, the input / output circuit 140 may output data corresponding to the voltage level of the bit line BL changed to the power supply voltage or the ground voltage (i.e., the amplified voltage level of the bit line BL) to an external target.

[0055] In some embodiments, the read operation may also be referred to as a read amplification operation. However, the present disclosure is not limited thereto.

[0056] Hereinafter, for a more concise description, the voltage levels of the bit line BL and the complementary bit line BLB that are raised or lowered when performing a read operation may be referred to as the voltage levels of the amplified bit line BL and the complementary bit line BLB. In this case, the amplified voltage levels of the bit line BL and the complementary bit line BLB may be a power supply voltage or a ground voltage. However, the present disclosure is not limited to these terms.

[0057] Meanwhile, the sense amplifier SA may be unbalancedly connected to the bit line BL and the complementary bit line BLB. For example, the product of the resistance value of the memory cell array 110 observed through the bit line BL in the sense amplifier SA and the capacitance value of the memory cell array 110 observed through the bit line BL in the sense amplifier SA may be referred to as a first resistance-capacitance (RC) value; and the product of the resistance value of the memory cell array 110 observed through the complementary bit line BLB in the sense amplifier SA and the capacitance value of the memory cell array 110 observed through the complementary bit line BLB in the sense amplifier may be referred to as a second RC value. In this case, the first RC value and the second RC value may be different.

[0058] In some embodiments, the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB may be caused by the physical structure of the memory device 100 or the process dispersion of the memory device 100. Figure 23 to Figure 25 The imbalance caused by the physical structure of the memory device 100 is described in more detail. However, the present disclosure is not limited to the cause of the imbalance.

[0059] When the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB is unbalanced, the operation of the sense circuit 131 based on the voltage level difference between the bit line BL and the complementary bit line BLB may fail. FIG. 4A to FIG. 4C An error in the operation of the sensing circuit 131 caused by the imbalance of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB is described in more detail.

[0060] The readout circuit 131 according to some embodiments of the present disclosure may include a charge trap transistor CTT. In this case, the imbalance of the connection of the sense amplifier SA with the bit line BL and the complementary bit line BLB can be compensated or mitigated based on the amount of charge trapped in the charge trap transistor CTT. Hereinafter, the configuration and operation of the sense amplifier SA that compensates or mitigates the imbalance of the connection of the sense amplifier SA with the bit line BL and the complementary bit line BLB based on the charge trap transistor CTT will be described.

[0061] In some embodiments, the charge trap transistor CTT may be connected to one of the bit line BL and the complementary bit line BLB.

[0062] In an embodiment, the charge trapping transistor CTT may be implemented as a high-k transistor. For example, the charge trapping transistor CTT may include a high dielectric layer including a ZrO 2 , HfO 2 、TiO 2 、 2 O 5 ,La 2 O 3 , Y 2 O 3 and Al 2 O 3 The following will refer to high dielectric constant materials (i.e., high-k materials). Figure 5 A more detailed configuration of the charge trap transistor CTT is described in more detail.

[0063] In some embodiments, the operation of trapping charges in the charge trapping transistor CTT may be referred to as a programming operation. However, the present disclosure is not limited thereto.

[0064] The charge trap transistor CTT may be programmed based on the voltage levels of the bit line BL and the complementary bit line BLB. For example, the memory device 100 may provide a programming voltage to the charge trap transistor CTT based on the voltage levels of the bit line BL and the complementary bit line BLB amplified by the read operation. In this case, charges may be trapped in the charge trap transistor CTT, and the imbalance of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB may be compensated or mitigated according to the amount of the trapped charges.

[0065] In some embodiments, after precharging the bit line BL and the complementary bit line BLB, the memory device 100 may perform (e.g., immediately perform) a read operation on the bit line BL and the complementary bit line BLB, for example, without performing a memory cell activation operation. For example, the sense amplifier SA may sense and amplify the voltage levels of the precharged bit line BL and the complementary bit line BLB. That is, according to some embodiments of the present disclosure, a read operation may be performed on the voltage levels of the precharged bit line BL and the complementary bit line BLB (rather than on the voltage levels of the charge-sharing bit line BL and the complementary bit line BLB). However, the present disclosure is not limited thereto, and various operations such as an offset cancellation operation may be performed between the precharge operation and the read operation.

[0066] In some embodiments, when a read operation is performed on the voltage levels of the precharged bit line BL and the complementary bit line BLB, due to the imbalance of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB, the voltage level of one of the bit line BL and the complementary bit line BLB may rise to the power supply voltage, while the voltage level of the other one may fall to the ground voltage. Therefore, the imbalance of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB can be identified based on the amplified voltage levels of the bit line BL and the complementary bit line BLB. In this case, based on the identified imbalance of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB, charges can be captured in the charge trap transistor CTT.

[0067] In some embodiments, the programming voltage may be provided from the equalizer circuit 132. For example, the input / output circuit 140 may provide data corresponding to the voltage level of the amplified bit line BL to the control logic circuit 150, and the control logic circuit 150 may control the equalizer circuit 132 to provide the programming voltage to the charge trap transistor CTT. Fig. 22 An embodiment of providing a program voltage to the charge trap transistor CTT is described in more detail. However, the present disclosure is not limited to a specific method of providing a program voltage to the charge trap transistor CTT based on the amplified voltage level of the bit line BL.

[0068] The following will refer to Figures 5 to 9 A more detailed method of programming the charge trapping transistor CTT is described in more detail.

[0069] In some embodiments, after sensing and amplifying the voltage level of the bit line BL, the equalization circuit 132 may equalize the voltage levels of the bit line BL and the complementary bit line BLB. For example, the equalization circuit 132 may electrically connect the bit line BL and the complementary bit line BLB. However, the present disclosure is not limited thereto.

[0070] In some embodiments, a CTT register mode may be defined, which is used to identify or detect the imbalance of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB and to capture a voltage in the charge trap transistor CTT. In this case, in the CTT register mode, the memory device 100 may perform a precharge operation on the bit line BL and the complementary bit line BLB, and then may immediately perform a read operation without activating the word line WL, and program the charge trap transistor CTT. However, the present disclosure is not limited thereto.

[0071] Figure 3 According to some embodiments Figure 2 A detailed circuit diagram of the sense amplifier. Figures 1 to 3 , the readout circuit 131 may include first to fourth readout transistors ST1 to ST4.

[0072] The first readout transistor ST1 may be connected between the bit line BL and the first node N1. The second readout transistor ST2 may be connected between the complementary bit line BLB and the first node N1. The third readout transistor ST3 may be connected between the bit line BL and the second node N2. The fourth readout transistor ST4 may be connected between the complementary bit line BLB and the second node N2.

[0073] The first and second readout transistors ST1 and ST2 may be implemented as N-channel transistors, and the third and fourth readout transistors ST3 and ST4 may be implemented as P-channel transistors.

[0074] Gate terminals of the first and third readout transistors ST1 and ST3 may be connected to each other through a third node N3. Gate terminals of the second and fourth readout transistors ST2 and ST3 may be connected to each other through a fourth node N4.

[0075] The third node N3 may be connected to the complementary bit line BLB. The fourth node N4 may be connected to the bit line BL.

[0076] That is, the first to fourth readout transistors ST1 to ST4 may constitute a cross-coupled differential amplifier. In other words, the readout circuit 131 may include a cross-coupled differential amplifier including the first to fourth readout transistors ST1 to ST4.

[0077] The first node N1 may receive a first driving signal LAB, and the second node N2 may receive a second driving signal LA.

[0078] The equalization circuit 132 may include a first equalization transistor EQT1 , a second equalization transistor EQT2 , and a precharge transistor PRET.

[0079] The first equalization transistor EQT1 may be connected between the bit line BL and the middle node MN. The second equalization transistor EQT2 may be connected between the complementary bit line BLB and the middle node MN.

[0080] The gate terminal of the first equalization transistor EQT1 may be connected to the equalization node EQN. The gate terminal of the second equalization transistor EQT2 may be connected to the equalization node EQN. The equalization node EQN may receive the equalization signal EQ. That is, the first and second equalization transistors EQT1 and EQT2 may operate in response to the equalization signal EQ.

[0081] The precharge transistor PRET may be connected between the intermediate node and the precharge voltage VPRE. The precharge transistor PRET may operate in response to a precharge signal PRE.

[0082] In some embodiments, the precharge voltage VPRE may be lower than the power supply voltage and higher than the ground voltage (i.e., between the ground voltage and the power supply voltage). In the following, for a more concise description, it is assumed that the precharge voltage VPRE is an intermediate value between the power supply voltage and the ground voltage. However, the present disclosure is not limited thereto.

[0083] In some embodiments, a logic high may represent a voltage level corresponding to a power supply voltage VDD, and a logic low may represent a voltage level corresponding to a ground voltage GND. However, the present disclosure is not limited thereto. For example, a logic high may represent any voltage level that turns on a transistor, and a logic low may represent any voltage level that turns off a transistor.

[0084] When the precharge operation is performed, the precharge signal PRE and the equalization signal EQ may be turned to logic high. The first equalization transistor EQT1 and the second equalization transistor EQT2 may be turned on in response to the equalization signal EQ, and the precharge transistor PRET may be turned on in response to the precharge signal PRE. In this case, the precharge voltage VPRE may be provided to the bit line BL and the complementary bit line BLB through the middle node MN.

[0085] In some embodiments, when a precharge operation is performed on the bit line BL and the complementary bit line BLB, the first and second driving signals LAB and LA may have a voltage level corresponding to the precharge voltage VPRE.

[0086] After performing the precharge operation, both the bit line BL and the complementary bit line BLB may have a voltage level corresponding to the precharge voltage VPRE.

[0087] In some embodiments, when a read operation is performed under ideal or nominal conditions, the voltage level of a line with a relatively high voltage level among the bit line BL and the complementary bit line BLB may be raised to the power supply voltage VDD, while the voltage level of a line with a relatively low voltage level may be lowered to the ground voltage GND. Therefore, when a read operation is performed under ideal or nominal conditions, the voltage levels of the precharged bit line BL and the complementary bit line BLB may be the same, so that when a read operation is performed on the precharged bit line BL and the complementary bit line BLB, it may not be clear which voltage level (e.g., the voltage level of the bit line BL or the complementary bit line BLB) will be raised to the power supply voltage. That is, when a read operation is performed on the precharged bit line BL and the complementary bit line BLB under ideal or nominal conditions, the voltage levels of the bit line BL and the complementary bit line BLB may be in a balanced state, but it may be an unstable state. Therefore, the voltage levels of the bit line BL and the complementary bit line BLB will randomly change to the power supply voltage or the ground voltage, which is a bistable voltage.

[0088] However, as previously referenced Figure 2As described, when the connection of the bit line BL and the complementary bit line BLB of the sense amplifier SA is unbalanced, an error may occur in the operation of the read circuit 131 based on the voltage level difference between the bit line BL and the complementary bit line BLB. Therefore, even if the voltage levels of the precharged bit line BL and the complementary bit line BLB are the same, only one of the bit line BL and the complementary bit line BLB may be converted to the power supply voltage by the read operation.

[0089] For example, a first RC value of the memory cell array 110 observed through the bit line BL in the sense amplifier SA may be smaller than a second RC value of the memory cell array 110 observed through the complementary bit line BLB in the sense amplifier SA. In this case, even if the bit line BL and the complementary bit line BLB are precharged to the same voltage, when a read operation is performed on the precharged bit line BL and the complementary bit line BLB, the voltage level of the complementary bit line BLB may be increased to the power supply voltage, and the voltage level of the bit line BL may be decreased to the ground voltage. On the contrary, when the first RC value is greater than the second RC value, when a read operation is performed on the precharged bit line BL and the complementary bit line BLB, the voltage level of the bit line BL may be increased to the power supply voltage, and the voltage level of the complementary bit line BLB may be decreased to the ground voltage.

[0090] For a more concise description, an example of an embodiment of compensating or mitigating the imbalance when the first RC value is less than the second RC value will be representatively described below. However, the present disclosure is not limited thereto. For example, even when the first RC value is greater than the second RC value, the imbalance can be compensated or mitigated in a similar manner.

[0091] In addition, hereinafter, for a more concise description, an example of an embodiment in which the charge trapping transistor CTT is a transistor having an N-type channel will be representatively described. However, the present disclosure is not limited thereto, and the charge trapping transistor CTT may be a transistor having a P-type channel.

[0092] The second readout transistor ST2 may operate as a charge trap transistor CTT. For example, the second readout transistor ST2 may be implemented as a high-k transistor.

[0093] The charge trap transistor CTT may be programmed in response to the programming voltage VPGM. For example, the charge trap transistor CTT may trap charges based on the programming voltage VPGM. In this case, the threshold voltage of the charge trap transistor CTT may be increased. Therefore, according to some embodiments of the present disclosure, the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB may be compensated.

[0094] FIG. 4A to FIG. 4CA method of compensating or mitigating the imbalance of the connection of the sense amplifier to the bit line and the complementary bit line according to some embodiments of the present disclosure is shown. Figure 4A The sensing operation of the sense amplifier SA according to the ideal embodiment will be described with reference to Figure 4B The sensing operation of the sense amplifier SA according to the non-ideal embodiment will be described, and reference will be made to Figure 4C Methods of compensating for or mitigating imbalance in the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB according to some embodiments of the present disclosure are described. FIG. 4A to FIG. 4C The horizontal axis represents the complementary bit line voltage level VBLB, and the vertical axis represents the bit line voltage level VBL.

[0095] First, refer to Figures 1 to 3 as well as Figure 4A , the voltage levels of the bit line BL and the complementary bit line BLB can be precharged to the same level. For example, after the precharge operation is completed, both the complementary bit line voltage level VBLB and the bit line voltage level VBL can be the precharge voltage VPRE.

[0096] Thereafter, when the word line connected to the memory cell array 110 is activated, charge sharing may occur between the bit line BL and the memory cell. For example, the voltage level of the bit line BL may be finely increased or decreased based on the amount of charge stored in the memory cell. However, hereinafter, for a more concise description, an example of an embodiment in which data corresponding to "1" is stored in a memory cell connected to the bit line BL (i.e., in the case where a voltage higher than the precharge voltage is stored in the memory cell) will be representatively described. In this case, when charge sharing occurs, the bit line voltage level VBL may increase, while the voltage level of the complementary bit line BLB may remain unchanged. That is, through charge sharing, a potential difference may occur between the bit line BL and the complementary bit line BLB.

[0097] Thereafter, when the readout circuit 131 performs a readout operation, the potential difference between the bit line BL and the complementary bit line BLB can be amplified. For example, by comparing the complementary bit line voltage level VBLB with the bit line voltage level VBL, the readout circuit 131 can amplify the voltage level of the line with a relatively high voltage level to the power supply voltage VDD, and amplify the voltage level of the line with a relatively low voltage level to the ground voltage GND.

[0098] That is, when the coordinates of the complementary bit line voltage level VBLB and the bit line voltage level VBL are located in a region higher than the ideal read standard CRT_ideal, the read circuit 131 may increase the bit line voltage level VBL to the power supply voltage VDD and decrease the complementary bit line voltage level VBLB to the ground voltage GND. On the other hand, when the coordinates of the complementary bit line voltage level VBLB and the bit line voltage level VBL are located in a region lower than the ideal read standard CRT_ideal, the read circuit 131 may decrease the bit line voltage level VBL to the ground voltage GND and increase the complementary bit line voltage level VBLB to the power supply voltage VDD.

[0099] In this case, a sense margin SM_ideal for comparing the voltage levels of the bit line BL and the complementary bit line BLB may correspond to the voltage level of the bit line BL boosted by charge sharing.

[0100] On the other hand, reference Figures 1 to 3 as well as Figure 4B Due to the unbalanced connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB, the sense amplifier SA performs a read operation based on the non-ideal read standard CRT_realistic.

[0101] For example, when the coordinates of the complementary bit line voltage level VBLB and the bit line voltage level VBL are located in a region higher than the non-ideal read standard CRT_realistic, the read circuit 131 may increase the bit line voltage level VBL to the power supply voltage VDD, and may decrease the complementary bit line voltage level VBLB to the ground voltage GND. On the other hand, when the coordinates of the complementary bit line voltage level VBLB and the bit line voltage level VBL are located in a region lower than the non-ideal read standard CRT_realistic, the read circuit 131 may decrease the bit line voltage level VBL to the ground voltage GND, and increase the complementary bit line voltage level VBLB to the power supply voltage VDD.

[0102] That is, the sense amplifier SA raises the bit line BL to the power supply voltage VDD only when the bit line voltage level VBL is higher than the complementary bit line voltage level VBLB by "ΔVreality". In this case, after charge sharing occurs, the sense margin SM_reality for comparing and amplifying the bit line voltage level VBL and the complementary bit line voltage level VBLB can be reduced. For example, the sense margin SM_reality can be smaller than the sense margin SM_ideal by "ΔVreality".

[0103] Therefore, when the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB is unbalanced, the operation accuracy of the sense amplifier SA may be reduced.

[0104] Next, refer to Figures 1 to 3 as well as Figure 4C When programming the charge trap transistor CTT, the sense amplifier SA can perform a read operation based on the compensated read standard CRT_compensated. That is, when programming the charge trap transistor CTT, the sense amplifier SA can perform a read operation based on the compensated read standard CRT_compensated instead of the non-ideal read standard CRT_realistic.

[0105] The compensated readout standard CRT_compensated may be substantially similar to the ideal readout standard CRT_ideal. Therefore, when the charge trap transistor CTT is programmed according to some embodiments of the present disclosure, the readout margin of the bit line voltage level VBL raised by charge sharing may be increased or maximized, so that the sense amplifier SA may operate more accurately. Figure 7 A specific method of compensating for the sensing standard when the sense amplifier SA performs the sensing operation is described in more detail.

[0106] Figure 5 Shows Figure 3 Detailed diagram of a charge trap transistor. Figures 1 to 3 as well as Figure 5 , the charge trapping transistor CTT may include a substrate SUB, a high-k dielectric layer DL, and a gate layer GL.

[0107] The high-k dielectric layer DL may be between the substrate SUB and the gate layer GL. The high-k dielectric layer DL may include a ZrO 2 , HfO 2 、TiO 2 、 2 O 5 ,La 2 O 3 , Y 2 O 3 、Al 2 O 3 One or more of various high-k materials, etc.

[0108] The gate layer GL may form a gate electrode of the charge trap transistor CTT. For example, the gate layer GL may include a conductive material such as metal, a metal compound, or polysilicon.

[0109] A first doping region DPR1 and a second doping region DPR2 may be included on the substrate SUB. The first doping region DPR1 may form a drain electrode of the charge trapping transistor CTT. The second doping region DPR2 may form a source electrode of the charge trapping transistor CTT.

[0110] In some embodiments, when the charge trapping transistor CTT is implemented as a P-type transistor, the first doping region DPR1 and the second doping region DPR2 may be doped with a P-type doping material. When the charge trapping transistor CTT is implemented as an N-type transistor, the first doping region DPR1 and the second doping region DPR2 may be doped with an N-type doping material. However, hereinafter, for a more concise description, an example of an embodiment in which the charge trapping transistor CTT is implemented as an N-type transistor will be representatively described. However, the present disclosure is not limited thereto.

[0111] When a high voltage is applied to the drain electrode and the gate electrode of the charge trapping transistor CTT, the charge CHG may be trapped in the high-k dielectric layer DL. For example, when a ground voltage is applied to the source electrode of the charge trapping transistor CTT and a programming voltage VPGM having a voltage level higher than the power supply voltage is applied to the gate electrode and the drain electrode of the charge trapping transistor CTT, the charge CHG may be trapped in the high-k dielectric layer DL. However, the present disclosure is not limited to a specific method in which the charge trapping transistor CTT is programmed in response to the programming voltage VPGM.

[0112] In some embodiments, when the voltage level of the drain electrode of the charge trapping transistor CTT is approximately 1.5 V or more higher than the voltage level of the source electrode thereof, and the voltage level of the gate electrode of the charge trapping transistor CTT is approximately 2.0 V or more higher than the voltage level of the source electrode thereof, charges CHG may be trapped in the high-k dielectric layer DL.

[0113] In some embodiments, a threshold voltage of the charge trapping transistor CTT may be determined based on the amount of charges CHG trapped in the high-k dielectric layer DL.

[0114] In some embodiments, the amount of charges CHG trapped in the high-k dielectric layer DL may be determined according to the time when the program voltage VPGM is applied to the charge trap transistor CTT.

[0115] Figure 6 Shows Figure 5 A graph showing the relationship between the total programming time and the threshold voltage of a charge trapping transistor. Figure 6 The horizontal axis represents the length of time during which the program voltage VPGM is supplied to the charge trap transistor CTT, and the vertical axis represents the threshold voltage level of the charge trap transistor CTT.

[0116] refer to Figures 1 to 3 , Figure 5 and Figure 6The threshold voltage of the charge trap transistor CTT may increase according to the time when the programming voltage VPGM is applied to the charge trap transistor CTT. For example, the threshold voltage of the charge trap transistor CTT may increase logarithmically according to the time when the programming voltage VPGM is applied to the charge trap transistor CTT.

[0117] Therefore, according to some embodiments of the present disclosure, depending on the total time that the programming voltage VPGM is applied to the charge trap transistor CTT, the degree of compensating or mitigating the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB can be adjusted. For example, by applying the programming voltage VPGM to the charge trap transistor CTT for a plurality of unit programming times, the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB can be relatively finely adjusted.

[0118] More specifically, in the memory device 100, after the programming voltage VPGM is applied to the charge trapping transistor CTT within a single unit programming time, the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB can be adjusted (e.g., finely adjusted) by repeatedly performing a determination as to whether the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB has been sufficiently compensated or mitigated.

[0119] Figure 7 Shown according to Figure 3 The programming number of the charge trap transistor is the readout standard of the sense amplifier. Figure 7 The horizontal axis represents the complementary bit line voltage level VBLB, and the vertical axis represents the bit line voltage level VBL.

[0120] refer to Figures 1 to 7 , the charge trap transistor CTT may be programmed stepwise (eg, incrementally) by receiving the program voltage VPGM a plurality of times within each single unit programming time.

[0121] First, when the charge trap transistor CTT is not programmed (i.e., when the charge trap transistor CTT has been programmed “0” times or zero times), the sense amplifier SA may perform a sense operation based on the 0th sense standard CRTa_P0. For example, the sense amplifier SA may perform a sense operation on the precharged bit line BL and the complementary bit line BLB based on the 0th sense standard CRTa_P0. In this case, since the coordinates of the precharged complementary bit line voltage level VBLB and the precharged bit line voltage level VBL (hereinafter, for a more concise description, these coordinates are referred to as precharge points PT_pre) are located in a region lower than the 0th sense standard CRTa_P0, the sense circuit 131 may lower the bit line voltage level VBL to the ground voltage GND, and may raise the complementary bit line voltage level VBLB to the power supply voltage VDD.

[0122] In some embodiments, the 0th readout standard CRTa_P0 may correspond to the above reference Figure 4B The non-ideal readout standard CRT_realistic is described. However, the present disclosure is not limited thereto.

[0123] Thereafter, when the bit line BL turns to logic low, the sense amplifier SA may provide the program voltage VPGM to the charge trap transistor CTT within a unit programming time.

[0124] When the charge trap transistor CTT is programmed within the first unit programming time (i.e., when the charge trap transistor CTT is programmed within "1" unit programming time), the sense amplifier SA may perform a read operation based on the first read standard CRTa_P1. For example, similar to the previous description, the read circuit 131 may lower the bit line voltage level VBL to the ground voltage GND, and may raise the complementary bit line voltage level VBLB to the power supply voltage VDD.

[0125] In this embodiment, when a read operation is performed on the bit line BL raised by charge sharing based on the first read standard CRTa_P1, the read margin of the read amplifier SA can be relatively large compared to the case where a read operation is performed on the bit line BL raised by charge sharing based on the 0th read standard CRTa_P0.

[0126] Thereafter, when the bit line voltage level VBL is lowered to the ground voltage, the sense amplifier SA may provide the program voltage VPGM to the charge trap transistor CTT within a unit program time.

[0127] In this manner, in response to lowering the bit line voltage level VBL to the ground voltage GND by the read operation, the sense amplifier SA can provide the program voltage VPGM to the charge trap transistor CTT (e.g., the second read transistor ST2) within the unit programming time. In this case, as the number of times the program voltage VPGM is provided to the charge trap transistor CTT increases, the read standard at which the sense amplifier SA performs the read operation can approach and / or become similar to the ideal read standard CRT_ideal.

[0128] For example, when the charge trap transistor CTT is programmed for the "(n-1)th time" within each unit programming time, the sense amplifier SA can perform a read operation based on the (n-1)th read standard CRTa_Pn-1. In this case, since the precharge point PT_pre is located in a region lower than the (n-1)th read standard CRTa_Pn-1, the read circuit 131 can lower the bit line voltage level VBL to the ground voltage GND and can raise the complementary bit line voltage level VBLB to the power supply voltage VDD.

[0129] Thereafter, when the charge trap transistor CTT is reprogrammed "once" within the unit time (i.e., when the charge trap transistor CTT is programmed within "n" unit programming time), the sense amplifier SA may perform a read operation based on the nth read standard CRTa_Pn. However, in this case, unlike the read operation previously performed based on the first read standard CRTa_P1 to the (n-1)th read standard CRTa_Pn-1, since the precharge point PT_pre is located in a region higher than the nth read standard CRTa_Pn, the bit line voltage level VBL may be raised to the power supply voltage VDD, and the complementary bit line voltage level VBLB may be lowered to the ground voltage GND.

[0130] That is, unlike the case where the charge trap transistor CTT is programmed within "n-1" unit programming time, when the charge trap transistor CTT is programmed within "n" unit programming time, the bit line voltage level VBL can be increased to the power supply voltage VDD when performing a read operation.

[0131] When the bit line voltage level VBL rises to the power supply voltage VDD, the sense amplifier SA may terminate the programming operation on the charge trap transistor CTT. For example, after performing the read operation based on the nth read standard CRTa_Pn, the sense amplifier SA may be suspended and may not provide the programming voltage VPGM to the charge trap transistor CTT. In this case, the nth read standard CRTa_Pn may correspond to the above reference 1. Figure 4C Describes the compensated readout standard CRT_compensated.

[0132] In some embodiments, when the sense amplifier SA performs a read operation based on the (n-1)th read standard CRTa_Pn-1, a tendency to turn the complementary bit line BLB to a logic high is more likely to occur than when the sense amplifier SA operates based on the ideal read standard CRT_ideal. Conversely, when the sense amplifier SA performs a read operation based on the nth read standard CRTa_Pn, a tendency to turn the bit line BL to a logic high is more likely to occur than when the sense amplifier SA operates based on the ideal sensing standard CRT_ideal. That is, the ideal read standard CRT_ideal may be between the (n-1)th read standard CRTa_Pn-1 and the nth read standard CRTa_Pn.

[0133] The unit programming time may be relatively short (e.g., sufficiently short). Therefore, the amount of change in the threshold voltage of the charge trap transistor CTT caused by providing the programming voltage VPGM within a single unit programming time may be relatively small (e.g., very small). In this case, the (n-1)th readout standard CRTa Pn-1 and the nth readout standard CRTa Pn may be substantially similar. Therefore, the nth readout standard CRTa_Pn (i.e., the compensated readout standard CRT_compensated) may be very similar (e.g., the same or almost the same) to the ideal readout standard CRT_ideal.

[0134] Therefore, according to some embodiments of the present disclosure, by programming the charge trap transistor CTT, the sense amplifier SA can perform a sense operation based on a compensated sense standard CRT_compensated that can be very similar to an ideal sense standard CRT_ideal. In this case, since the imbalance of the bit line BL and the complementary bit line BLB of the sense amplifier SA can be finely compensated, the sense margin of the sense amplifier SA can be increased or maximized.

[0135] Figure 8 Shows Figure 1 A flowchart of the operation of the memory device. Figures 1 to 3 as well as Figure 8 In operation S110, the memory device 100 may enter the CTT register mode. For example, the memory device 100 may enter the CTT register mode from an idle state. In this case, the memory device 100 may perform a precharge operation on the bit line BL and the complementary bit line BLB, and then may immediately perform a read operation without activating the word line WL.

[0136] In operation S120, the memory device 100 may program the charge trap transistor CTT of each sense amplifier SA. For example, the memory device 100 may provide a programming voltage VPGM to the charge trap transistor CTT included in each sense amplifier SA. Fig. 9 A method of programming the charge trap transistor CTT by the memory device 100 is described in more detail.

[0137] In some embodiments, the memory device 100 may provide a different number of programming voltages VPGM to the charge trap transistor CTT of each of the plurality of sense amplifiers SA included in the sense amplifier array 130. For example, the memory device 100 may provide a different number of programming voltages VPGM to each charge trap transistor CTT included in each sense amplifier SA. However, the present disclosure is not limited thereto.

[0138] In operation S130, the memory device 100 may exit the CTT register mode. For example, the memory device 100 may enter an idle state from the CTT register mode. However, the present disclosure is not limited thereto.

[0139] In some embodiments, the above operations S110 to S130 may be performed once (eg, only once) in a production step or a setting step of the memory device 100. However, the present disclosure is not limited thereto.

[0140] Fig. 9 Shows Figure 8 Refer to the detailed flow chart of operation S120. Figures 1 to 3 as well as Figures 8 to 9 In operation S121, the memory device 100 may precharge the bit line BL and the complementary bit line BLB. For example, the equalization circuit 132 may provide a precharge voltage VPRE to the bit line BL and the complementary bit line BLB.

[0141] In operation S122, the memory device 100 may perform a read operation on the bit line BL and the complementary bit line BLB. For example, the read circuit 131 may raise or lower the voltage level of each of the precharged bit line BL and the complementary bit line BLB to a bistable voltage. That is, the read circuit 131 may raise one of the voltage levels of the precharged bit line BL and the complementary bit line BLB to a power supply voltage, and may lower the other of the voltage levels of the bit line BL and the complementary bit line BLB to a ground voltage.

[0142] That is, according to some embodiments of the present disclosure, after the bit line BL and the complementary bit line BLB are precharged, a read operation may be performed immediately without sharing charges for memory cells.

[0143] In operation S123, the memory device 100 may determine whether the bit line voltage level VBL is higher than the complementary bit line voltage level VBLB. For example, the memory device 100 may determine whether the bit line voltage level VBL is a power supply voltage.

[0144] When the bit line voltage level VBL is lower than or equal to the complementary bit line voltage level VBLB (“No” branch of operation S123 ), the following operation S124 may be performed.

[0145] In operation S124, the memory device 100 may provide a programming voltage VPGM to the charge trap transistor CTT within a unit programming time. For example, the memory device 100 may provide a programming voltage VPGM to the charge trap transistor CTT within a unit programming time. For example, the memory device 100 may program the second readout transistor ST2 by providing the programming voltage VPGM to the second readout transistor ST2 within a unit programming time.

[0146] After performing step S124, the above operations S121, S122, and S123 may be repeatedly performed. In this way, the memory device 100 may perform (e.g., repeatedly perform) the step of providing the program voltage VPGM to the charge trap transistor CTT in each unit programming time. In this case, each time operation S124 is performed, the amount of charge trapped in the charge trap transistor CTT may gradually increase. Therefore, as with the above reference Figure 7 Similar to the description of , the criterion for performing the sensing operation by the sense amplifier SA may vary according to the number of times operation S124 is performed, so that the imbalance of the connection of the sense amplifier SA to the BL bit line and the complementary bit line BLB may be relatively accurately compensated or mitigated.

[0147] Meanwhile, in operation S123, when the voltage level of the bit line BL is higher than the voltage level of the complementary bit line BLB ("Yes" branch of operation S123), the program operation of the charge trap transistor CTT may be exited. For example, the memory device 100 may perform the above-described operation S130.

[0148] In some embodiments, after performing operation S130, the sense amplifier SA may perform a sense operation based on the compensated sense standard CRT_compensated. For example, after completing the precharge operation and the charge sharing, the sense amplifier SA may perform a sense operation based on the compensated sense standard CRT_compensated for the bit line voltage level VBL and the complementary bit line voltage level VBLB. In this case, as previously described with reference to Figure 7 As described, the sensing margin of the sense amplifier SA can be increased or maximized.

[0149] Fig.10It shows that some embodiments can be implemented Figure 3 A detailed circuit diagram of the sense amplifier. Figures 1 to 3 as well as Fig.10 , the readout circuit 131 may be implemented as a readout circuit 131 a , and the equalization circuit 132 may be implemented as an equalization circuit 132 a .

[0150] The readout circuit 131a may include first to fourth readout transistors ST1 to ST4. The equalization circuit 132a may include a first equalization transistor EQT1, a second equalization transistor EQT2, and a precharge transistor PRET. The configuration and operation of the first to fourth readout transistors ST1 to ST4, the first equalization transistor EQT1, the second equalization transistor EQT2, and the precharge transistor PRET are similar to those of the reference circuit 131a. Figure 3 The configuration and operation described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0151] The equalizer circuit 132a may further include a programming transistor PGMT. The programming transistor PGMT may be connected between the middle node MN and the programming voltage VPGM.

[0152] The programming transistor PGMT may provide a programming voltage VPGM to the charge trapping transistor CTT in response to a programming signal PGM. For example, when a programming operation is performed on the charge trapping transistor CTT, the programming transistor PGMT may be turned on in response to the programming signal PGM, the first equalization transistor EQT1 and the second equalization transistor EQT2 may be turned on in response to the equalization signal EQ, and the precharge transistor PRET may be turned on in response to the precharge signal PRE. In this case, the voltage levels of the middle node MN, the bit line BL, and the complementary bit line BLB may be raised to the programming voltage VPGM.

[0153] When the voltage levels of the bit line BL and the complementary bit line BLB are increased to the programming voltage VPGM, the voltage level of the fourth node N4 may also be increased to the programming voltage VPGM. Therefore, a relatively high voltage (e.g., the programming voltage VPGM) higher than the power supply voltage may be provided to the gate terminal (i.e., the fourth node N4) and the drain terminal (i.e., the complementary bit line BLB) of the charge trap transistor CTT.

[0154] When a relatively high voltage is supplied to the gate terminal and the drain terminal of the charge trap transistor CTT, similar to the reference Figure 5 As described above, charges can be trapped in the high-k dielectric layer DL of the charge trapping transistor CTT, so the threshold voltage of the charge trapping transistor CTT can be increased. Fig.10Some embodiments of the present disclosure may compensate for or mitigate the imbalance in the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB.

[0155] In some embodiments, when the first readout transistor ST1 is implemented as a high-k transistor, a protection transistor PTT may be further included between the third node N3 and the complementary bit line BLB. Fig.12 and Fig.13 An example of an embodiment in which the first readout transistor ST1 is implemented as a high-k transistor is described in more detail.

[0156] Fig.11 Shows Fig.10 The timing diagram of the operation of the sense amplifier. Figures 1 to 3 , Fig.10 and Fig.11 , during the first time point t1 to the second time point t2, the sense amplifier SA may perform a precharge operation (precharge). For example, during the first time point t1 to the second time point t2, the equalization signal EQ and the precharge signal PRE may be logic high, and the programming signal PGM may be logic low. In this case, the voltage levels of the bit line BL and the complementary bit line BLB may correspond to the precharge voltage VPRE.

[0157] In some embodiments, when a precharge operation (precharge) is performed, the first drive signal LAB and the second drive signal LA may have a voltage level corresponding to the precharge voltage VPRE. However, the present disclosure is not limited thereto.

[0158] During the second time point t2 to the third time point t3, the sense amplifier SA may perform a sense operation (sense). For example, during the second time point t2 to the third time point t3, the first drive signal LAB and the second drive signal LA may be logic high, and the equalization signal EQ may be logic low.

[0159] In some embodiments, when a read operation (READ) is performed, the precharge signal PRE and the program signal PGM may be logic low. However, the present disclosure is not limited thereto.

[0160] In some embodiments, when the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB is unbalanced, the sense amplifier SA may not perform a sense operation based on the ideal sense standard CRT_ideal. That is, during the second time point t2 to the third time point t3, the sense amplifier SA may perform a sense operation based on the non-ideal sense standard CRT_realistic (e.g., the 0th sense standard CRTa_P0). In this case, even if the bit line voltage level VBL and the complementary bit line voltage level VBLB have the same voltage level during the first time point t1 to the second time point t2, the voltage level of the bit line BL may rise to the power supply voltage VDD during the second time point t2 to the third time point t3.

[0161] During the period from the third time point t3 to the fourth time point t4, the sense amplifier SA may perform a programming operation (programming). For example, during the period from the third time point t3 to the fourth time point t4, the equalization signal EQ and the programming signal PGM may be logic high, and the precharge signal PRE may be logic low. In this case, the voltage levels of the bit line BL and the complementary bit line BLB may be raised to the programming voltage VPGM. Therefore, a relatively high voltage may be provided to the gate terminal and the drain terminal of the second read transistor ST2, and the second read transistor ST2 may be programmed.

[0162] In some embodiments, when a program operation (program) is performed, the first drive signal LAB may be logic low, and the second drive signal LA may be logic high. However, the present disclosure is not limited thereto.

[0163] In some embodiments, the time interval between the third time point t3 and the fourth time point t4 may be a “unit programming time”.

[0164] In some embodiments, when a program operation (PROGRAM) is performed, the equalization signal EQ may have a voltage level higher than a power supply voltage. However, the present disclosure is not limited thereto.

[0165] After the fourth time point t4, similar to the first time point t1 to the fourth time point t4, the sense amplifier SA can repeatedly program the second read transistor ST2. For example, the sense amplifier SA can perform a precharge operation (precharge) during the fourth time point t4 to the fifth time point t5, the sense amplifier SA can perform a read operation (read) during the fifth time point t5 to the sixth time point t6, and the sense amplifier SA can perform a programming operation (program) during the sixth time point t6 to the seventh time point t7. In this way, the sense amplifier SA can repeatedly program the second read transistor ST2. In this case, as the second read transistor ST2 is repeatedly programmed, the read standard of the sense amplifier SA will gradually become similar to or close to the ideal read standard CRT_ideal.

[0166] In some embodiments, the time interval between the sixth time point t6 and the seventh time point t7 may be a "unit programming time". That is, the time interval between the sixth time point t6 and the seventh time point t7 may be the same as the time interval between the third time point t3 and the fourth time point t4. In this way, the sense amplifier SA may repeatedly program the second read transistor ST2 within each "unit programming time". However, the present disclosure is not limited thereto.

[0167] In some embodiments, the precharge operation (precharge), the read operation (read), and the programming operation (program) together may be considered as one programming cycle. For example, the first time point t1 to the fourth time point t4 may be referred to as a first programming cycle, and the fourth time point t4 to the seventh time point t7 may be referred to as a second programming cycle. That is, the sense amplifier SA may repeatedly perform a plurality of programming cycles to program the charge trap transistor CTT. However, the present disclosure is not limited thereto.

[0168] However, each time the read operation is performed before the eighth time point t8, even if the second read transistor ST2 is repeatedly programmed, the voltage level of the complementary bit line BLB may be increased to the power supply voltage VDD, and the voltage level of the bit line BL may be decreased to the ground voltage GND. Figure 7 Similar to the description, when a read operation is performed on the precharged bit line BL and the complementary bit line BLB until the second read transistor ST2 is programmed for the "n-1"th time, the voltage level of the voltage level complementary bit line BLB can be increased to the power supply voltage VDD, and the voltage level of the bit line BL can be decreased to the ground voltage GND.

[0169] Thereafter, during the eighth time point t8 to the ninth time point t9, the sense amplifier SA may perform a precharge operation (precharge). For example, during the eighth time point t8 to the ninth time point t9, the equalization signal EQ and the precharge signal PRE may be logic high, and the program signal PGM may be logic low.

[0170] After the ninth time point t9, the sense amplifier SA may perform a sense operation (sense). In this case, even if the bit line voltage level VBL and the complementary bit line voltage level VBLB have the same voltage level during the eighth time point t8 to the ninth time point t9, the voltage level of the bit line BL may be increased to the power supply voltage VDD after the ninth time point t9. That is, unlike the sense operation (sense) performed between the first time point t1 to the eighth time point t8, after the ninth time point t9, the voltage level of the complementary bit line BLB may be decreased to the ground voltage GND, and the voltage level of the bit line BL may be increased to the power supply voltage VDD.

[0171] In some embodiments, when the voltage level of the bit line BL is raised to the power supply voltage VDD as the read operation is performed, the voltage level of the bit line BL is increased to the power supply voltage VDD as compared to the previous reference voltage. Figure 7 Similar to the description, the sense amplifier SA can be in a state capable of performing a read operation based on a read standard that is quite similar or approximate to the ideal read standard CRT_ideal. In other words, the charge trapping transistor CTT can be in a state of capturing an amount of charge sufficient to enable the sense amplifier SA to perform a read operation in a manner similar to the ideal read standard CRT_ideal. That is, in this case, the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB can be fully compensated or mitigated according to the amount of charge captured in the charge trapping transistor CTT. Therefore, after the ninth time point t9, the sense amplifier SA can exit the programming operation of the charge trapping transistor CTT.

[0172] Fig.12 It shows that some embodiments can be implemented Figure 3 A detailed circuit diagram of the sense amplifier. Figures 1 to 3 as well as Fig.12 , the readout circuit 131 may be implemented as the readout circuit 131 b , and the equalizer circuit 132 may be implemented as the equalizer circuit 132 b .

[0173] The readout circuit 131b may include first to fourth readout transistors ST1 to ST4. The equalization circuit 132b may include a first equalization transistor EQT1, a second equalization transistor EQT2, a precharge transistor PRET, and a programming transistor PGMT. The configuration and operation of the first to fourth readout transistors ST1 to ST4, the first equalization transistor EQT1, the second equalization transistor EQT2, the precharge transistor PRET, and the programming transistor PGMT are similar to those described previously with reference to FIG. Figure 3 and Fig.10 The configuration and operation described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0174] The readout circuit 131a may further include a protection transistor PTT. The protection transistor PTT may be connected between the third node N3 and the complementary bit line BLB.

[0175] The protection transistor PTT may operate in response to the protection signal PT. When a programming operation is performed on the charge trap transistor CTT, the protection transistor PTT may be turned off. In this case, even if the programming voltage VPGM is supplied to the bit line BL and the complementary bit line BLB, the programming voltage VPGM is not supplied to the gate terminal (i.e., the third node N3) of the first read transistor ST1. In this case, even if the first read transistor ST1 is implemented as a high-k transistor, a programming operation may be performed only on the second read transistor ST2.

[0176] Fig.13 Shows Fig.12 The timing diagram of the operation of the sense amplifier. Figures 1 to 3 , Fig.12 and Fig.13 , the sense amplifier SA may perform a plurality of programming cycles during the first time point t1 to the eighth time point t8. That is, the sense amplifier SA may repeatedly perform a precharge operation (precharge), a read operation (read), and a programming operation (program) during the first time point t1 to the eighth time point t8. The method in which the sense amplifier SA performs the precharge operation (precharge) and the read operation (read) may be the same as that previously described with reference to Fig.11 The methods described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0177] When the sense amplifier SA performs a programming operation (programming), the protection signal PT may be logic low. For example, between the third time point t3 and the fourth time point t4 and between the sixth time t6 and the seventh time t7, the protection signal PT may be logic low. In this case, since the protection transistor PTT is turned off when the programming operation (programming) is performed, the programming voltage (VPGM) is not provided to the gate terminal (i.e., the third node N3) of the first read transistor ST1. Therefore, even if the first read transistor ST1 is implemented as a high-k transistor, the programming operation may be selectively performed only on the second read transistor ST2.

[0178] In some embodiments, when the sense amplifier SA performs a precharge operation (precharge) or a read operation (read), the protection signal PT may be logic high. In this case, when the sense amplifier SA performs a precharge operation (precharge) or a read operation (read), the third node N3 may be electrically connected to the complementary bit line BLB. However, the present disclosure is not limited thereto.

[0179] In some embodiments, when a program operation (program) is performed, the protection signal PT may have a voltage level higher than a power supply voltage. However, the present disclosure is not limited thereto.

[0180] Fig.14 The embodiment shown in FIG. Figure 2 The sense amplifier. Figure 1 , Figure 2 and Fig.14 , the readout circuit 131 may be implemented as the readout circuit 231 , and the equalizer circuit 132 may be implemented as the equalizer circuit 232 .

[0181] The readout circuit 231 may include first to fourth readout transistors ST1 to ST4. The equalization circuit 232 may include a first equalization transistor EQT1, a second equalization transistor EQT2, and a precharge transistor PRET. The configuration and operation of the first to fourth readout transistors ST1 to ST4, the first equalization transistor EQT1, the second equalization transistor EQT2, and the precharge transistor PRET may be the same as previously described. Figure 3 The configuration and operation described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0182] The first readout transistor ST1 can operate as a charge trapping transistor CTT. For example, the first readout transistor ST1 can be implemented as a high-k transistor. That is, as previously described with reference to Figure 3 Conversely to the description, the first sensing transistor ST1 may be programmed in response to the program voltage VPGM.

[0183] Fig.15 Shown according to Fig.14 The programming number of the charge trap transistor is the readout standard of the sense amplifier. Figure 7 The horizontal axis represents the complementary bit line voltage level VBLB, and the vertical axis represents the bit line voltage level VBL.

[0184] refer to Figure 1 , Figure 2 , Fig.14 and Fig.15 The charge trap transistor CTT ( Fig.14 The first read-out transistor ST1) is programmed step by step.

[0185] First, when the charge trap transistor CTT is not programmed (i.e., when the charge trap transistor CTT has been programmed "0" times), the sense amplifier SA may perform a read operation based on the 0th read standard CRTb_P0. For example, the sense amplifier SA may perform a read operation on the precharged bit line BL and the complementary bit line BLB based on the 0th read standard CRTa_P0. In this case, since the precharge point PT_pre is located in a region higher than the 0th read standard CRTb_P0, the read circuit 231 may raise the bit line voltage level VBL to the power supply voltage VDD and lower the complementary bit line voltage level VBLB to the ground voltage GND.

[0186] When the charge trap transistor CTT is programmed “once” within the unit programming time (i.e., when the charge trap transistor CTT is programmed within “1” unit programming time), the sense amplifier SA may perform a read operation based on the first read standard CRTb_P1. For example, similar to the above description, the read circuit 231 may increase the bit line voltage level VBL to the power supply voltage VDD, and may decrease the complementary bit line voltage level VBLB to the ground voltage GND.

[0187] In this manner, as the number of times the program voltage VPGM is supplied to the charge trap transistor CTT (eg, the first sensing transistor ST1 ) increases, a sensing standard at which the sense amplifier SA performs a sensing operation may become similar to or approximate an ideal sensing standard CRT_ideal.

[0188] For example, when the charge trap transistor CTT is programmed for the "(m-1)th time" within each unit programming time, the sense amplifier SA can perform a read operation based on the (m-1)th read standard CRTb_Pm-1. In this case, since the precharge point PT_pre is located in a region higher than the (m-1)th read standard CRTa_Pm-1, the read circuit 231 can increase the bit line voltage level VBL to the power supply voltage VDD and reduce the complementary bit line voltage level VBLB to the ground voltage GND.

[0189] Thereafter, when the charge trap transistor CTT is reprogrammed "once" within the unit programming time (i.e., when the charge trap transistor CTT is programmed "m" unit programming times), the sense amplifier SA may perform a read operation based on the mth read standard CRTb_Pm. However, in this case, unlike the read operation previously performed based on the first to (n-1)th read standards CRTb_P1 to CRTb_Pm-1, since the precharge point PT_pre is located in a region lower than the mth read standard CRTb_Pm, the bit line voltage level VBL may be lowered to the ground voltage GND, and the complementary bit line voltage level VBLB may be raised to the power supply voltage VDD.

[0190] That is, unlike the case where the charge trap transistor CTT is programmed the "m-1"th time in each unit programming time, when the charge trap transistor CTT is programmed the "m"th time in each unit programming time, the bit line voltage level VBL can be lowered to the ground voltage GND when performing a read operation. In this case, as previously described with reference to Figure 7 Similarly, the mth readout standard CRTa_Pm can be very similar to the ideal readout standard CRT_ideal. Therefore, according to some embodiments of the present disclosure, since the imbalance between the sense amplifier SA and the bit line BL and the complementary bit line BLB can be compensated or mitigated in a relatively fine manner, the readout margin of the sense amplifier SA can be increased or maximized.

[0191] Fig.16 The embodiment shown in FIG. Figure 2 The sense amplifier. Figure 1 , Figure 2 and Fig.16 , the readout circuit 131 may be implemented as the readout circuit 331 , and the equalizer circuit 132 may be implemented as the equalizer circuit 332 .

[0192] The readout circuit 331 may include first to fourth readout transistors ST1 to ST4. The equalization circuit 332 may include a first equalization transistor EQT1, a second equalization transistor EQT2, and a precharge transistor PRET. The configuration and operation of the first to fourth readout transistors ST1 to ST4, the first equalization transistor EQT1, the second equalization transistor EQT2, and the precharge transistor PRET may be the same as previously described. Figure 3 The configuration and operation described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0193] The third readout transistor ST3 can operate as a charge trapping transistor CTT. For example, the third readout transistor ST3 can be implemented as a high-k transistor. In this case, as previously described with reference to Figure 3 Unlike the case described above, the third sensing transistor ST3 can be programmed in response to the programming voltage VPGM. The method of compensating for the imbalance of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB in response to the third sensing transistor ST3 being programmed can be similar to the method described above, so for the sake of brevity, its detailed description is omitted here.

[0194] In some embodiments, the third readout transistor ST3 may be implemented to be programmed by trapping holes in response to the program voltage VPGM. However, the present disclosure is not limited to the method of programming the third readout transistor ST3.

[0195] In some embodiments, the third readout transistor ST3 may be programmed in response to the program voltage VPGM having a negative voltage level. However, the present disclosure is not limited to the method of programming the third readout transistor ST3.

[0196] In some embodiments, the third readout transistor ST3 may be programmed in response to a program voltage VPGM having a negative voltage level supplied to a gate terminal. However, the present disclosure is not limited to a method of programming the third readout transistor ST3.

[0197] In some embodiments, the third readout transistor ST3 may be implemented to capture holes in response to a relatively high voltage applied to the drain electrode of the third readout transistor ST3 and a negative voltage applied to the gate electrode of the third readout transistor ST3. However, the present disclosure is not limited to the method of programming the third readout transistor ST3.

[0198] Fig.17 It shows that some embodiments can be implemented Figure 2 A detailed circuit diagram of the sense amplifier. Figure 1 , Figure 2 and Fig.17, the readout circuit 131 may be implemented as the readout circuit 431 , and the equalizer circuit 132 may be implemented as the equalizer circuit 432 .

[0199] The readout circuit 431 may include first to fourth readout transistors ST1 to ST4. The equalization circuit 432 may include a first equalization transistor EQT1, a second equalization transistor EQT2, a precharge transistor PRET, and a programming transistor PGMT. The configuration and operation of the first to fourth readout transistors ST1 to ST4 and the equalization circuit 432 may be the same as previously described. Figure 3 The configuration and operation described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0200] The first readout transistor ST1 and the second readout transistor ST2 may operate as a charge trap transistor CTT. For example, the first readout transistor ST1 may operate as a first charge trap transistor CTT1, and the second readout transistor ST2 may operate as a second charge trap transistor CTT2.

[0201] The programming transistor PGMT may provide a programming voltage VPGM to the first and second charge trapping transistors CTT1 and CTT2. The first and second charge trapping transistors CTT1 and CTT2 may trap charges in response to the programming voltage VPGM.

[0202] The first charge trapping transistor CTT1 and the second charge trapping transistor CTT2 may compensate or alleviate the imbalance of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB.

[0203] First, due to the unbalanced nature of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB, the sense operation performed by the sense amplifier SA may be more inclined to raise the bit line voltage level VBL to the power supply voltage VDD than the complementary bit line voltage level VBLB. For example, even if the bit line BL and the complementary bit line BLB are precharged with the same voltage, the sense amplifier SA may perform the sense operation and the bit line voltage level VBL may be raised to the power supply voltage VDD. In this case, since the sense amplifier SA is connected to the bit line BL and the complementary bit line BLB with the same voltage as previously described, the sense amplifier SA may perform the sense operation and the bit line voltage level VBL may be raised to the power supply voltage VDD. Fig.15 The first charge trapping transistor CTT1 is programmed in a similar manner to that described, thereby compensating or alleviating the imbalance in the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB.

[0204] On the contrary, due to the unbalanced connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB, the sense operation performed by the sense amplifier SA may be more inclined to raise the complementary bit line voltage level VBLB to the power supply voltage VDD than the bit line voltage level VBL. For example, even if the bit line BL and the complementary bit line BLB are precharged with the same voltage, the sense amplifier SA may perform the sense operation and the complementary bit line voltage level VBLB may be raised to the power supply voltage VDD. In this case, since the sense amplifier SA is connected to the bit line BL and the complementary bit line BLB with the same voltage as previously described, the sense amplifier SA may perform the sense operation and the complementary bit line voltage level VBLB may be raised to the power supply voltage VDD. Figure 7 The second charge trapping transistor CTT2 is programmed in a similar manner to that described, thereby compensating for or alleviating the imbalance in the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB.

[0205] The readout circuit 431 may include a first protection transistor PTT1 and a second protection transistor PTT2. The first protection transistor PTT1 may be connected between the third node N3 and the complementary bit line BLB. The second protection transistor PTT2 may be connected between the fourth node N4 and the bit line BL.

[0206] The first protection transistor PTT1 may operate in response to the first protection signal PT1. When a programming operation is performed on the second charge trapping transistor CTT2, the first protection transistor PTT1 may be turned off. In this case, even if the programming voltage VPGM is supplied to the bit line BL and the complementary bit line BLB, the programming voltage VPGM is not supplied to the gate terminal (i.e., the third node N3) of the first charge trapping transistor CTT1.

[0207] The second protection transistor PTT2 may operate in response to the second protection signal PT2. When the programming operation is performed on the first charge trapping transistor CTT1, the second protection transistor PTT2 may be turned off. In this case, even if the programming voltage VPGM is supplied to the bit line BL and the complementary bit line BLB, the programming voltage VPGM is not supplied to the gate terminal (i.e., the third node N3) of the second charge trapping transistor CTT2.

[0208] That is, according to Fig.17 In some embodiments, the first charge trapping transistor CTT1 and the second charge trapping transistor CTT2 may be selectively programmed. In this case, the programming voltage VPGM may be repeatedly provided to the first charge trapping transistor CTT1 or the second charge trapping transistor CTT2, so that the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB may be compensated or alleviated. Fig.18A and Fig.18B A method of programming the first charge trapping transistor CTT1 and the second charge trapping transistor CTT2 is described in more detail.

[0209] In some embodiments, the sense amplifier SA may program the first charge trapping transistor CTT1 and the second charge trapping transistor CTT2 in a binary search method to compensate for or mitigate the imbalance of the connection with the bit line BL and the complementary bit line BLB. Fig.19 and Fig. 20 The operation of the sense amplifier SA for programming the first charge trap transistor CTT1 and the second charge trap transistor CTT2 in the binary search method is described in more detail.

[0210] Fig.18A and Fig.18B Shows Fig.17 Hereinafter, reference will be made to the timing diagram of the operation of the sense amplifier. Fig.18A An example of an embodiment in which the first charge trapping transistor CTT1 is programmed is described and reference will be made to Fig.18B An example of an embodiment is described in which the second charge trap transistor CTT2 is programmed.

[0211] First, refer to Figure 1 , Figure 2 , Fig.17 and Fig.18A , the sense amplifier SA may perform a plurality of programming cycles on the first charge trapping transistor CTT1 during the first time point t1 to the eighth time point t8. That is, the sense amplifier SA may repeatedly perform a precharge operation (precharge), a read operation (readout), and a programming operation (program) during the first time point t1 to the eighth time point t8. The method in which the sense amplifier SA performs the precharge operation (precharge) and the read operation (readout) is the same as that previously described with reference to FIG. Fig.13 The methods described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0212] When the sense amplifier SA performs a programming operation (programming) on ​​the first charge trap transistor CTT1, the first protection signal PT1 may be logic high and the second protection signal PT2 may be logic low. For example, between the third time point t3 and the fourth time point t4 and between the sixth time t6 and the seventh time t7, the second protection signal PT2 may be logic low. In this case, when the programming operation (programming) is performed on the first charge trap transistor CTT1, the programming voltage VPGM may not be provided to the gate terminal (i.e., the fourth node N4) of the second charge trap transistor CTT2.

[0213] On the other hand, reference Figure 1 , Figure 2 , Fig.17 and Fig.18B, the sense amplifier SA can perform a plurality of programming cycles on the second charge trapping transistor CTT2 during the first time point t1 to the eighth time point t8. That is, the sense amplifier SA can repeatedly perform a precharge operation (precharge), a read operation (readout), and a programming operation (program) during the first time point t1 to the eighth time point t8. The method in which the sense amplifier SA performs the precharge operation (precharge) and the read operation is the same as that previously described with reference to Fig.13 The methods described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0214] When the sense amplifier SA performs a programming operation (programming) on ​​the second charge trapping transistor CTT2, the second protection signal PT2 may be logic high and the first protection signal PT1 may be logic low. For example, between the third time point t3 and the fourth time point t4 and between the sixth time t6 and the seventh time t7, the first protection signal PT1 may be logic low. In this case, when the programming operation (programming) is performed on the second charge trapping transistor CTT2, the programming voltage VPGM may not be provided to the gate terminal (i.e., the third node N3) of the first charge trapping transistor CTT1.

[0215] Fig.19 According to some embodiments Fig.17 The timing diagram of the operation of the sense amplifier. Figure 1 , Figure 2 , Fig.17 and Fig.19 , the sense amplifier SA may perform a plurality of programming cycles during the eleventh time point t11 ​​to the twentieth time point t20. That is, the sense amplifier SA may repeatedly perform a precharge operation (Precharge), a read operation (Read), and a program operation (Program) during the eleventh time point t11 ​​to the twentieth time point t20.

[0216] More specifically, the sense amplifier SA may perform a programming operation (programming) between the thirteenth time point t13 and the fourteenth time point t14 depending on the bit line voltage level VBL between the twelfth time point t12 and the thirteenth time point t13. For example, when the bit line voltage level VBL rises to the power supply voltage VDD between the twelfth time point t12 and the thirteenth time point t13 (i.e., when the complementary bit line voltage level VBLB falls to the ground voltage GND), the sense amplifier SA may program the first charge trap transistor CTT1 between the thirteenth time point t13 and the fourteenth time point t14. On the contrary, when the bit line voltage level VBL falls to the ground voltage GND between the twelfth time point t12 and the thirteenth time point t13 (i.e., when the complementary bit line voltage level VBLB rises to the power supply voltage VDD), the sense amplifier SA may program the second charge trap transistor CTT2 between the thirteenth time point t13 and the fourteenth time point t14.

[0217] Similarly, the sense amplifier SA may perform a programming operation (Programming) between the sixteenth time point t16 and the seventeenth time point t17 and between the nineteenth time point t19 and the twentieth time point t20. The method in which the sense amplifier SA performs a precharge operation (Precharge) and a read operation (Read) may be the same as that described previously with reference to FIG. Fig.11 The methods described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0218] The sense amplifier SA may provide the programming voltage VPGM for different time lengths in each of the plurality of programming cycles. For example, the interval between the thirteenth time point t13 and the fourteenth time point t14 may be the first time length TL1, the interval between the sixteenth time point t16 and the seventeenth time point t17 may be the second time length TL2, and the interval between the nineteenth time point t19 and the twentieth time point t20 may be the third time length TL3.

[0219] The first time length TL1 may be longer than the second time length TL2. The second time length TL2 may be longer than the third time length TL3. That is, the sense amplifier SA may gradually reduce the time for providing the programming voltage VPGM to the charge trap transistor CTT. In this case, the imbalance of the connection of the sense amplifier SA to the bit line BL and the complementary bit line BLB may be adjusted in a relatively rough manner and then in a relatively fine manner.

[0220] In some embodiments, the time during which the sense amplifier SA provides the programming voltage VPGM in each programming cycle of a plurality of programming cycles may be halved. For example, the second time length TL2 may be "1 / 2" of the first time length TL1, and the third time length TL3 may be "1 / 2" of the second time length TL2. That is, the sense amplifier SA may program the first charge trapping transistor CTT1 and the second charge trapping transistor CTT2 using a binary search method. In this case, the first charge trapping transistor CTT1 and the second charge trapping transistor CTT2 may be programmed sequentially, so that the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB may be relatively accurately compensated or mitigated.

[0221] Fig. 20 Shown according to Fig.19 The timing diagram is implemented Figure 8 Refer to the detailed flow chart of operation S120. Figure 1 , Figure 2 , Figure 8 , Fig.17 , Fig.19 and Fig. 20 , operation S120 may include the following operations (or sub-operations) S221 to S228.

[0222] In operation S221 , the variable (i) may be set to “N.” The variable (i) is used herein only to describe how the charge trap transistor CTT is repeatedly programmed and does not limit the scope of the present disclosure.

[0223] In some embodiments, "N" may be an integer greater than or equal to 2.

[0224] In operation S222, the memory device 100 may precharge the bit line BL and the complementary bit line BLB. In operation S223, the sense amplifier SA may perform a sense operation on the bit line BL and the complementary bit line BLB. Operations S222 and S223 may be performed with reference to Fig. 9 The described operations S121 and S122 are similar, so their detailed descriptions are omitted here for the sake of brevity.

[0225] In operation S224, the memory device 100 may determine whether the variable (i) is "0". When the variable (i) is "0" (the "yes" branch of operation S224), operation S120 may exit. When the variable (i) is not "0" (the "no" branch of operation S224), the following operation S225 may be performed.

[0226] In operation S225, the memory device 100 may determine whether the bit line voltage level VBL is higher than the complementary bit line voltage level VBLB. That is, the memory device 100 may determine whether the bit line voltage level VBL is the power supply voltage VDD.

[0227] When the bit line voltage level VBL is higher than the complementary bit line voltage level VBLB ("Yes" branch of operation S225), the following operation S226 may be performed. In other words, in response to the voltage level of the bit line BL being greater than the voltage level of the complementary bit line BLB ("Yes" branch of operation S225), the following operation S227 may be performed.

[0228] When the voltage level of the bit line BL is lower than or equal to the voltage level of the complementary bit line BLB (the "No" branch of operation S225), the following operation S227 may be performed. In other words, in response to the voltage level of the bit line BL being lower than or equal to the voltage level of the complementary bit line BLB (the "No" branch of operation S225), the following operation S227 may be performed.

[0229] In operation S226, the memory device 100 may program the memory device 100 at a time which is 2 times the unit programming time. i The programming voltage VPGM is provided to the first charge trapping transistor CTT1 for a time length corresponding to times.

[0230] In operation S227, the memory device 100 may program the memory device 100 at a time which is 2 times the unit programming time. i The programming voltage VPGM is provided to the second charge trapping transistor CTT2 for a time length corresponding to times.

[0231] In operation S228, the memory device 100 may reduce the variable (i) by "1". Thereafter, the above operation S222 may be repeatedly performed. In this manner, the first charge trap transistor CTT1 and the second charge trap transistor CTT2 may be sequentially programmed so that the sense amplifier SA may perform a read operation based on the ideal read standard CRT_ideal.

[0232] Fig.21 The embodiment shown in FIG. Figure 2 A detailed circuit diagram of the sense amplifier. Figure 1 , Figure 2 and Fig.21 , the readout circuit 131 may be implemented as the readout circuit 531 , and the equalization circuit 132 may be implemented as the equalization circuit 532 .

[0233] The readout circuit 531 may include first to fourth readout transistors ST1 to ST4. The equalization circuit 532 may include a first equalization transistor EQT1, a second equalization transistor EQT2, and a precharge transistor PRET. The configuration and operation of the first to fourth readout transistors ST1 to ST4, the first equalization transistor EQT1, the second equalization transistor EQT2, and the precharge transistor PRET may be the same as previously described with reference to FIG. Figure 3 The configuration and operation described are similar, so for the sake of brevity, their detailed description will be omitted here.

[0234] The second readout transistor ST2 may operate as a charge trap transistor CTT. For example, the second readout transistor ST2 may trap charges.

[0235] The second readout transistor ST2 may receive a deprogramming voltage VDPGM. The second readout transistor ST2 may de-trap charges in response to the deprogramming voltage VDPGM. For example, in response to a negative voltage being provided to the gate terminal and a high voltage being provided to the drain terminal, the second readout transistor ST2 may de-trap charges. However, the present disclosure is not limited to a specific method in which the second readout transistor ST2 de-traps charges.

[0236] That is, according to Fig.21 In some embodiments shown, the second sensing transistor ST2 can compensate or alleviate the imbalance of the connection between the sense amplifier SA and the bit line BL and the complementary bit line BLB by detrapping the charge trapped in the second sensing transistor ST2. However, the present disclosure is not limited thereto.

[0237] Fig. 22 According to some embodiments Figure 1 A block diagram of some components of a memory device. Figure 1 and Fig.21 , the control logic circuit 150 may control each sense amplifier SA included in the sense amplifier array 130 to perform a precharge operation, a read operation, and a program operation. For example, the control logic circuit 150 may provide a precharge signal PRE, a protection signal PT, an equalization signal EQ, and a program signal PGM to the sense amplifier array 130. However, hereinafter, for a more concise description, an embodiment in which the control logic circuit 150 controls one sense amplifier SA will be representatively described.

[0238] The sense amplifier SA included in the sense amplifier array 130 may perform a precharge operation and a sense operation on the connected bit line BL and the complementary bit line BLB. For example, based on the voltage levels of the precharged bit line BL and the complementary bit line BLB, the sense amplifier SA may raise the voltage levels of the bit line BL and the complementary bit line BLB to the power supply voltage VDD, or lower them to the ground voltage GND.

[0239] After performing the read operation, the input / output circuit 140 may store the bit line level data BLLV corresponding to the bit line voltage level VBL. For example, when the bit line voltage level VBL is the power supply voltage VDD, the bit line level data BLLV may indicate "1", and when the bit line BL has the ground voltage GND level, the bit line level data BLLV may indicate "0".

[0240] The input / output circuit 140 may provide the bit line level data BLLV to the control logic circuit 150. That is, after performing a read operation, the input / output circuit 140 may provide the control logic circuit 150 with data indicating a bit line voltage level VBL.

[0241] The control logic circuit 150 may adjust logic levels of the protection signal PT and the program signal PGM in response to the bit line level data BLLV.

[0242] For a more concise description, Fig. 22 , an embodiment in which the control logic circuit 150 controls the operation of the sense amplifier SA in response to the bit line level data BLLV stored in the input / output circuit 140 is representatively described, but the present disclosure is not limited thereto. For example, the control logic circuit 150 may receive (e.g., directly receive) the voltage level of the bit line BL and control the operation of the sense amplifier SA based on the received voltage level.

[0243] Fig.23 The embodiment shown in FIG. Figure 1 A perspective view of a storage device. Figures 1 to 23 , the memory device 100 may include a peripheral circuit region PERI and a memory cell region CELL. The memory cell region CELL may be three-dimensionally stacked on the peripheral circuit region PERI along a third direction D3. That is, the memory device 100 may have a cell-on-periphery (CoP) structure.

[0244] The memory cell region CELL may include a memory cell array 110. The peripheral circuit region PERI may include a row decoder 120, a sense amplifier array 130, an input / output circuit 140, and a control logic circuit 150.

[0245] Fig.24 Shows Fig.23 A top view of the memory cell area (CELL). Figures 1 to 24 , the memory cell region CELL may include a memory cell array 110. The memory cell array 110 may include a plurality of sub-memory cell arrays 111 to 114.

[0246] Each of the plurality of sub-memory cell arrays 111 to 114 may be in a matrix structure along the first direction D1 and the second direction D2. The plurality of sub-memory cell arrays 111 to 114 may be spaced apart from each other, respectively. However, the present disclosure is not limited thereto, and the plurality of sub-memory cell arrays 111 to 114 may be adjacent to each other.

[0247] The sub-memory cell array 111 and the sub-memory cell array 112 may share one or more sense amplifiers SA. For example, a first sense amplifier shared by the sub-memory cell array 111 and the sub-memory cell array 112 may be connected to a bit line BL connected to the sub-memory cell array 111 and a complementary bit line BLB connected to the sub-memory cell array 112.

[0248] Fig.25 Shown along Fig.23 and Fig.24 A cross-sectional view taken along line CC'. Figures 1 to 25 , each of the sub-memory cell array 111 and the sub-memory cell array 112 may include a plurality of memory cells MC. In this case, Fig.25 Each of the illustrated plurality of memory cells MC may be a memory cell arranged in the same column of the memory cell array 110 .

[0249] Each of the plurality of memory cells MC may include a capacitor structure CAP, a capacitor contact 1104 , a memory channel layer 1105 , and a gate electrode 1106 .

[0250] The capacitor structure CAP may include a lower electrode 1101, a capacitor dielectric layer 1102, and an upper electrode 1103. The lower electrode 1101 may be electrically connected to a capacitor contact 1104. The lower electrode 1101 may be formed as a pillar type extending in the third direction D3. However, the present disclosure is not limited thereto.

[0251] The capacitor contact 1104 may be on the storage channel layer 1105. That is, the capacitor contact 1104 may be stacked on the storage channel layer 1105 along the third direction D3.

[0252] The gate electrode 1106 may extend in the first direction D1 at both sides of the storage channel layer 1105 .

[0253] The first interlayer insulating film ISL1 may be between the gate electrode 1106 and the storage channel layer 1105. For a more concise description, the first interlayer insulating film ISL1 is Fig.25 1 is shown as one continuous material layer, but the present disclosure is not limited thereto, and the first interlayer insulating film ISL1 may be formed of a plurality of insulating patterns.

[0254] A plurality of memory cells MC included in the sub memory cell array 111 may be connected to a first bit line BLa. A plurality of memory cells MC included in the sub memory cell array 113 may be connected to a second bit line BLb. The first and second bit lines BLa and BLb may extend in a second direction D2.

[0255] The first bit line BLa may be connected to the peripheral circuit region PERI through the first layer contact LCa. For example, the first bit line BLa may be connected to the first bit line contact BCa through the first layer contact LCa.

[0256] The second bit line BLb may be connected to the peripheral circuit region PERI through the second layer contact LCb. For example, the second bit line BLb may be connected to the second bit line contact BCb through the second layer contact LCb.

[0257] For a more concise description, Fig.24 , an embodiment in which the first layer contact portion LCa and the second layer contact portion LCb are included in the peripheral circuit region PERI is representatively described, but the present disclosure is not limited thereto. For example, the first layer contact portion LCa and the second layer contact portion LCb may be included in the memory cell region CELL.

[0258] The peripheral circuit region PERI may include a substrate SUB, a second interlayer insulating film ISL2, and a plurality of circuit elements CE formed on the substrate SUB. The peripheral circuit region PERI may include a first metal layer ML1 and a second metal layer ML2 connected to the plurality of circuit elements CE.

[0259] To describe it more concisely, Fig.24 Only the first metal layer ML1 and the second metal layer ML2 are shown in the figure, but the present disclosure is not limited thereto, and one or more metal layers may also be formed on the second metal layer ML2. In this case, at least some of the one or more metal layers formed on the second metal layer ML2 may be made of a material with a lower resistance than that of the material forming the second metal layer ML2.

[0260] The plurality of circuit elements CE included in the peripheral circuit region PERI may form a sense amplifier SA. The sense amplifier SA may be connected to a first bit line BLa and a second bit line BLb through a first layer contact LCa and a second layer contact LCb, respectively. In this case, the first bit line BLa may be a bit line BL relative to the sense amplifier SA, and the second bit line BLb may be a complementary bit line BLB relative to the sense amplifier SA. However, the present disclosure is not limited thereto.

[0261] In some embodiments, the lengths of the first layer contact LCa and the second layer contact LCb may be different. For example, the first layer contact LCa may be longer than the second layer contact LCb. In this case, the value of the resistor connected between the sense amplifier SA and the first bit line BLa may be greater than the value of the resistor connected between the sense amplifier SA and the second bit line BLb. That is, compared with the reference Figure 22 to Figure 24 Similar to the description of , when the memory device 100 is implemented in a CoP structure, the connection of the sense amplifier SA to the first bit line BLa and the second bit line BLb may be unbalanced.

[0262] In some embodiments, the imbalance of the connection of the sense amplifier SA to the first and second bit lines BLa and BLb may be compensated or mitigated by additionally connecting a resistor or a capacitor to the first and second bit lines BLa or BLb. However, in this case, the design complexity of the memory device 100 may increase.

[0263] In some embodiments, the sense amplifier SA may include a charge trapping transistor CTT. For example, the sense amplifier SA may include a charge trapping transistor CTT that traps charge, for compensating for or mitigating the imbalance of the connection between the sense amplifier SA and the first bit line BLa and the second bit line BLb. In this case, even if the memory device 100 is implemented in a CoP structure, the imbalance of the connection between the sense amplifier SA and the first bit line BLa and the second bit line BLb may be compensated for or mitigated. That is, according to some embodiments of the present disclosure, even if the design complexity of the memory device 100 is minimized, the imbalance of the connection between the sense amplifier SA and the first bit line BLa and the second bit line BLb may be compensated for or mitigated.

[0264] The above is a specific embodiment for implementing the present disclosure. The present disclosure will not only include the above-mentioned embodiments, but also include embodiments that include relatively simple design changes or other easily implemented changes. In addition, the present disclosure will also include technologies that can be easily modified and implemented by using examples of the embodiments. Although the present disclosure has been described with reference to some examples of the embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A sense amplifier connected to a bit line and a complementary bit line, comprising: a first transistor connected between the bit line and the first node, the first transistor including a first gate terminal connected to a third node; a second transistor connected between the first node and the complementary bit line, the second transistor including a second gate terminal connected to a fourth node; a third transistor connected between the bit line and the second node, the third transistor including a third gate terminal connected to the third node; as well as a fourth transistor connected between the complementary bit line and the second node, the fourth transistor comprising a fourth gate terminal connected to the fourth node, wherein a first resistance-capacitance (RC) value observed from the sense amplifier toward the bit line is smaller than a second RC value observed from the sense amplifier toward the complementary bit line, and The second transistor is configured to receive a programming voltage higher than a power supply voltage during a first time period.

2. The sense amplifier according to claim 1, wherein: The bit line and the complementary bit line are further configured to receive a precharge voltage between the power supply voltage and a ground voltage during a second time period prior to the first time period.

3. The sense amplifier according to claim 2, wherein: The first node is configured to receive a first drive signal during the first time period, the first drive signal having a voltage level corresponding to the ground voltage, and The second node is configured to receive a second drive signal during the first time period, the second drive signal having a voltage level corresponding to the power supply voltage.

4. The sense amplifier according to claim 3, wherein: During a third period between the first period and the second period in which a first sensing operation is performed on the bit line and the complementary bit line, a voltage level of the complementary bit line is higher than a voltage level of the bit line.

5. The sense amplifier according to claim 4, wherein: The first sensing operation is performed based on voltage levels of the bit line and the complementary bit line that are precharged during the second period.

6. The sense amplifier according to claim 2, wherein: The second transistor is configured to receive the programming voltage through the fourth node and the complementary bit line during the first time period.

7. The sense amplifier according to claim 6, wherein: The second transistor is further configured to receive the programming voltage during a fourth time period after the first time period.

8. The sense amplifier according to claim 7, wherein: The bit line and the complementary bit line are further configured to receive the precharge voltage during a fifth time period between the first time period and the fourth time period, and During a sixth time period between the fourth time period and the fifth time period in which a second sensing operation is performed on the bit line, a voltage level of the complementary bit line is higher than a voltage level of the bit line.

9. The sense amplifier of claim 8, wherein: The bit line and the complementary bit line are further configured to receive the precharge voltage during a seventh time period after the fourth time period, and During an eighth time period after the seventh time period in which a third sensing operation is performed on the bit line, a voltage level of the bit line is higher than a voltage level of the complementary bit line.

10. The sense amplifier according to claim 6, further comprising a protection transistor connected between the third node and the complementary bit line, wherein The protection transistor is turned off during the first period of time.

11. The sense amplifier of claim 1 , wherein: The first transistor and the second transistor are N-type transistors, The third transistor and the fourth transistor are P-type transistors, and The second transistor is a high-k transistor.

12. A method for operating a sense amplifier connected to a bit line and a complementary bit line, the method comprising: performing a first precharge operation on the bit line and the complementary bit line; performing a first sensing operation on the bit line and the complementary bit line precharged based on the first precharging operation; as well as In response to a voltage level of the bit line being changed to a first voltage level based on the first sensing operation, a first programming operation is performed on a first transistor connected to one of the bit line and the complementary bit line.

13. The operating method according to claim 12, after performing the first programming operation, the operating method further comprises: performing a second precharging operation on the bit line and the complementary bit line; performing a second sensing operation on the bit line and the complementary bit line precharged based on the second precharging operation; as well as In response to the voltage level of the bit line being changed to the first voltage level based on the second sensing operation, a second programming operation is performed on the first transistor.

14. The operating method according to claim 13, wherein: In response to a voltage level of the bit line being changed to a second voltage level different from the first voltage level based on the second sensing operation, performing a program operation on the first transistor is stopped.

15. The operating method according to claim 13, wherein: A first length of time for performing the first programming operation is the same as a second length of time for performing the second programming operation.

16. The operating method according to claim 12, wherein: The first precharge operation and the first sensing operation are continuously performed.

17. The operating method according to claim 12, wherein: The sense amplifier comprises a cross-coupled differential amplifier, and The first transistor is one of a plurality of transistors included in the cross-coupled differential amplifier.

18. The operating method according to claim 12, further comprising: In response to a voltage level of the bit line being changed to a second voltage level different from the first voltage level based on the first sensing operation, a second transistor connected to one of the bit line and the complementary bit line is programmed.

19. A storage device comprising: a memory cell array connected to the bit lines and complementary bit lines; as well as a sense amplifier connected to the bit line via a first conductive line and connected to the complementary bit line via a second conductive line having a different length than the first conductive line, Wherein, the readout amplifier comprises: a first transistor and a second transistor connected in series between the first conductive line and the second conductive line and having a first channel type; and a third transistor and a fourth transistor connected in series between the first conductive line and the second conductive line and having a second channel type, The threshold voltages of the first transistor and the second transistor are different from each other. 20 . The memory device of claim 19 , further comprising a fifth transistor connected between a gate terminal of the first transistor and the second conductive line.

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