A current latching type sense amplifier resistant to single event upsets
By introducing redundant nodes and feedback mechanisms into the current latch-type sensitive amplifier, the problem of latch output flipping under high-energy particle bombardment is solved, thus achieving the reliability and accuracy of SRAM read operations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2024-11-20
- Publication Date
- 2026-07-28
AI Technical Summary
Traditional current-latch sensitive amplifiers are prone to latch output flipping under high-energy particle impact, leading to SRAM data read errors.
A current-latch sensitive amplifier, comprising a pre-charge circuit, a 4P unit, a 2P2N unit, a bit-line input circuit, and an enable transistor circuit, is designed. It utilizes redundant nodes and a feedback mechanism to restore the circuit state during high-energy particle bombardment, ensuring the stability of the output node.
It effectively prevents single-event flips, ensuring the reliability and accuracy of SRAM read operations. A self-recovery mechanism is implemented through redundant node design to avoid read errors.
Smart Images
Figure CN119785840B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a current-latch sensitive amplifier resistant to single-event upsets. Background Technology
[0002] Single-event effects (SEE) refer to the interaction between high-energy particles (such as those produced by cosmic rays, solar wind, or the decay of radioactive materials) and materials in semiconductor devices, causing localized, transient charge deposition and leading to transient or permanent malfunctions in electronic devices. Single-event upsets (SEUs) occur when high-energy particles, through memory or logic circuits, alter the state of a specific memory cell, causing the stored data to flip. This effect is transient, but may require rewriting the data to restore normal operation.
[0003] SRAM and its peripheral circuits built using fully depleted silicon-on-insulator (FDSOI) technology have significant advantages in combating single-event effects. The key is that the buried oxide layer effectively isolates charges, reducing charge injection into the source and drain regions of the device caused by high-energy particle impacts, thereby significantly mitigating charge collection problems caused by single-event effects. This directly reduces the probability of single-event flips and single-event latch-up (SELs).
[0004] A sense amplifier is a crucial circuit module in Static Random-Access Memory (SRAM). Its main function is to quickly detect and amplify this tiny voltage difference transmitted between the bit lines and the inverted bit lines during data reading. This voltage difference is extremely small, making direct reading very difficult. The sense amplifier can transform this minute differential voltage into a standard signal level that can be processed by logic circuits, thus ensuring the correctness of the read data. Current-latch sense amplifiers are widely used due to their high speed, low power consumption, and ability to adapt to smaller bit line oscillations. However, the latching structure of traditional current-latch sense amplifiers consists of two interlocked inverters. When a high-energy particle strikes its sensitive node, the resulting transient pulse current causes the latch output to flip, leading to errors when reading SRAM data. Summary of the Invention
[0005] To address the aforementioned problems in the prior art, this invention provides a current-latch sensitive amplifier that is resistant to single-event upsets.
[0006] According to a first aspect of the present invention, a current latch-type sensitive amplifier resistant to single-event upsets is provided, comprising: a precharge circuit, a 4P unit, a 2P2N unit, a bit line input circuit, and an enable transistor circuit;
[0007] The precharge circuit is used to stabilize the output node OUT and output node OUTN to a high level through the power supply VDD when the precharge signal PRE is low before the SRAM performs a read operation, and to make the output node OUT and output node OUTN have the same high level.
[0008] The bit line input circuit and the enable transistor circuit are used to adjust the voltage of the output node OUT and the output node OUTN according to the voltage difference between the bit line signal BL and the inverted bit line signal BLN when the SRAM performs a read operation, so as to amplify the voltage change of the output node OUT and the output node OUTN.
[0009] The 4P unit and the 2P2N unit are used to restore the circuit to its original state based on the redundant node S0 and the redundant node S1 when a single-particle flip occurs in the circuit; wherein the redundant node S0 and the redundant node S1 are obtained based on the 4P unit and the 2P2N unit.
[0010] Optionally, the pre-charge circuit includes transistors P7, P8, and P9; the gates of transistors P7, P8, and P9 are all connected to the pre-charge signal PRE; the source of transistor P7 is connected to the power supply VDD; the drain of transistor P7 is connected to the source of transistor P9 and connected to the output node OUTN; the source of transistor P8 is connected to the power supply VDD; and the drain of transistor P8 is connected to the drain of transistor P9 and connected to the output node OUT.
[0011] Optionally, the 4P unit includes: transistor P1, transistor P2, transistor P5, and transistor P6; the sources of transistors P1 and P2 are both connected to the power supply VDD, the drain of transistor P1 is connected to the source of transistor P5 and serves as the redundant node S0, the drain of transistor P2 is connected to the source of transistor P6 and serves as the redundant node S1, the gate of transistor P1 is connected to the redundant node S1, and the gate of transistor P2 is connected to the redundant node S0; the drains of transistors P5 and P6 are both grounded, transistor P5 is connected to the output node OUTN, and transistor P6 is connected to the output node OUT.
[0012] Optionally, the 2P2N unit includes: transistor P3, transistor P4, transistor N1, and transistor N2; the sources of transistors P3 and P4 are both connected to the power supply VDD, the drain of transistor P3 is connected to the drain of transistor N1 and connected to the output node OUTN, the drain of transistor P4 is connected to the drain of transistor N2 and connected to the output node OUT, the gate of transistor P3 is connected to the redundant node S1, and the gate of transistor P4 is connected to the redundant node S0; the sources of transistors N1 and N2 are connected to the bit line input circuit, the gate of transistor N1 is connected to the output node OUT, and the gate of transistor N2 is connected to the output node OUTN.
[0013] Optionally, the bit line input circuit includes: transistor N3 and transistor N4; the drain of transistor N3 is connected to the source of transistor N1, the drain of transistor N4 is connected to the source of transistor N2, the sources of transistor N3 and transistor N4 are both connected to the enable transistor circuit, the gate of transistor N3 is connected to the bit line signal BL, and the gate of transistor N4 is connected to the inverted bit line signal BLN.
[0014] Optionally, the enable transistor circuit includes: transistor N5; the source of transistor N5 is grounded, the drain of transistor N5 is connected to the source of transistor N3 and transistor N4, and the gate of transistor N5 is connected to the enable signal SAE.
[0015] The technical solution provided by this invention may include the following beneficial effects:
[0016] The above technical solution, consisting of a precharge circuit, 4P cells, 2P2N cells, a bit line input circuit, and an enable transistor circuit, can maintain stable output during SRAM read operations. The precharge circuit keeps the output node at a high level when the precharge signal is low. During the read operation, the circuit adjusts the voltage of the output node based on the voltage difference between the bit line signal and the inverted bit line signal to rapidly amplify minute voltage changes. Simultaneously, the circuit utilizes 4P and 2P2N cells to implement a self-recovery mechanism to cope with single-event upsets. When high-energy particles bombard the circuit, the state of related devices may be affected, resulting in a single-event upset. However, through the design of redundant nodes in the circuit, it can effectively recover to its original state, ensuring the reliability and read accuracy of the circuit.
[0017] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description
[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof. In the drawings:
[0019] Figure 1 This is a schematic diagram of the structure of a current latch-type sensitive amplifier that is resistant to single-event upsets, according to an exemplary embodiment.
[0020] Figure 2 This is a timing diagram illustrated by an example.
[0021] Figure 3 This is another timing diagram illustrated by an example.
[0022] Figure 4 This is yet another timing diagram illustrated by an example.
[0023] Explanation of reference numerals in the attached figures
[0024] 10. Precharge circuit; 2. 4P unit; 3. 2P2N unit; 4. Bit line input circuit; 5. Enable transistor circuit. Detailed Implementation
[0025] Figure 1 This is a schematic diagram illustrating the structure of a current-latch sensitive amplifier resistant to single-event upsets, according to an exemplary embodiment. Figure 1 As shown, it includes: a pre-charge circuit 10, a 4P unit 20, a 2P2N unit 30, a bit line input circuit 40, and an enable transistor circuit 50;
[0026] The precharge circuit 10 is used to stabilize the output nodes OUT and OUTN to a high level through the power supply VDD when the precharge signal PRE is low before the SRAM performs a read operation, and to make the output nodes OUT and OUTN have the same high level.
[0027] The bit line input circuit 40 and the enable transistor circuit 50 are used to adjust the voltage of the output node OUT and the output node OUTN according to the voltage difference between the bit line signal BL and the inverted bit line signal BLN when the SRAM is performing a read operation, so as to amplify the voltage change of the output node OUT and the output node OUTN.
[0028] The 4P unit 20 and the 2P2N unit 30 are used to restore the circuit to its original state based on the redundant node S0 and the redundant node S1 when a single-particle flip occurs in the circuit; wherein the redundant node S0 and the redundant node S1 are obtained based on the 4P unit 20 and the 2P2N unit 30.
[0029] Optionally, the pre-charge circuit 10 includes transistors P7, P8, and P9; the gates of transistors P7, P8, and P9 are all connected to the pre-charge signal PRE; the source of transistor P7 is connected to the power supply VDD; the drain of transistor P7 is connected to the source of transistor P9 and connected to the output node OUTN; the source of transistor P8 is connected to the power supply VDD; and the drain of transistor P8 is connected to the drain of transistor P9 and connected to the output node OUT.
[0030] For details, please refer to Figure 1 When the precharge signal PRE is low (usually logic "0"), transistors P7 and P8 are turned on. With transistors P7 and P8 on, the power supply VDD is directly connected to the output nodes OUT and OUTN, stabilizing them at a high level (usually logic "1"). Transistor P9, being a balancing transistor, is also turned on at this time to ensure that the output nodes OUT and OUTN have the same high level.
[0031] Optionally, the 4P unit 20 includes: transistor P1, transistor P2, transistor P5, and transistor P6; the sources of transistors P1 and P2 are both connected to the power supply VDD, the drain of transistor P1 is connected to the source of transistor P5 and serves as a redundant node S0, the drain of transistor P2 is connected to the source of transistor P6 and serves as a redundant node S1, the gate of transistor P1 is connected to the redundant node S1, and the gate of transistor P2 is connected to the redundant node S0; the drains of transistors P5 and P6 are both grounded, transistor P5 is connected to the output node OUTN, and transistor P6 is connected to the output node OUT.
[0032] Optionally, the 2P2N unit 30 includes: transistor P3, transistor P4, transistor N1, and transistor N2; the sources of transistors P3 and P4 are both connected to the power supply VDD, the drain of transistor P3 is connected to the drain of transistor N1 and connected to the output node OUTN, the drain of transistor P4 is connected to the drain of transistor N2 and connected to the output node OUT, the gate of transistor P3 is connected to the redundant node S1, and the gate of transistor P4 is connected to the redundant node S0; the sources of transistors N1 and N2 are connected to the bit line input circuit 40, the gate of transistor N1 is connected to the output node OUT, and the gate of transistor N2 is connected to the output node OUTN.
[0033] Optionally, the bit line input circuit 40 includes: transistor N3 and transistor N4; the drain of transistor N3 is connected to the source of transistor N1, the drain of transistor N4 is connected to the source of transistor N2, the sources of transistor N3 and transistor N4 are both connected to enable transistor circuit 50, the gate of transistor N3 is connected to bit line signal BL, and the gate of transistor N4 is connected to inverted bit line signal BLN.
[0034] Optionally, the enable transistor circuit 50 includes: transistor N5; the source of transistor N5 is grounded, the drain of transistor N5 is connected to the source of transistor N3 and transistor N4, and the gate of transistor N5 is connected to the enable signal SAE.
[0035] In one implementation, a sensitive amplifier is used when performing a read operation on the SRAM. The SRAM's bit line signal BL and inverted bit line signal BLN are connected to the differential input of the sensitive amplifier, and the amplified signal is read from the output node OUTN and the OUT output node, thus completing the SRAM read operation.
[0036] Figure 2 According to an exemplary timing diagram, before an SRAM read operation, when the enable signal SAE is low, transistor N5 is turned off, and the circuit is not enabled. At this time, the precharge signal PRE is low, and transistors N7, N8, and N9 are turned on. Output nodes OUT and OUTN are simultaneously precharged to a high level. When the SRAM performs a read operation, the enable signal SAE and the precharge signal PRE rise, transistor N5 turns on, and transistors N7, N8, and N9 turn off. The bit line signal BL and the inverted bit line signal BLN are connected to transistors N3 and N4, respectively. When the SRAM reads "1", the voltage of the bit line signal BL is greater than the voltage of the inverted bit line signal BLN. Since the gate voltages of transistors N3 and N4 are different, the currents in their two branches are also different, so the voltage drop rates of output nodes OUTN and OUT are also different. The branch current corresponding to transistor N3, which has a high gate voltage, is larger, and the voltage of its corresponding output node OUTN drops faster. Consequently, transistor P5 turns on first, the voltage of redundant node S0 decreases, transistors P2 and P4 turn on, and the output node OUT and redundant node S1 are connected to the power supply VDD. The voltage no longer drops and remains at a high level. The high-level output node OUT is connected to the gate of transistor N1, thus keeping transistor N1 continuously turned on and discharging. Through this feedback process, the output node OUTN is quickly pulled low, amplifying the small voltage difference between the bit line signal BL and the inverted bit line signal BLN to the power supply VDD and GND. This amplifies the originally small voltage difference between the bit line signal BL and the inverted bit line signal BLN to the power supply VDD (800 millivolts) to GND (0 millivolts). (See reference...) Figure 2 The time ranges from 12 to 15 nanoseconds.
[0037] When reading "0" from the SRAM, the bit line signal BL is less than the inverted bit line signal BLN. Because the gate voltages of transistors N3 and N4 are different, the currents in their two branches are also different, resulting in different voltage drop rates for output nodes OUTN and OUT. Transistor N4, with its higher gate voltage, has a larger branch current, causing its corresponding output node OUT to drop faster. Consequently, transistor P6 turns on first, reducing the voltage of redundant node S1. Transistors P1 and P3 then turn on, connecting output node OUTN and redundant node S0 to the power supply VDD. The voltage no longer drops and remains at a high level. The high-level output node OUTN is connected to the gate of transistor N2, keeping transistor N2 continuously on and discharging. Through this feedback process, output node OUT is quickly pulled low.
[0038] In another implementation, when a device is bombarded by high-energy particles, the resulting transient current may cause a single-event flip at the sensitive node. When a PMOS transistor is bombarded by high-energy particles, only an upward transient current can be generated, resulting in a "0" to "1" or "1" to "1" flip; when an NMOS transistor is bombarded by high-energy particles, only a downward transient current can be generated, resulting in a "1" to "0" or "0" to "0" flip.
[0039] Reference Figure 1 When reading "1" from SRAM, if a single-event upset (SE) occurs in redundant node S0, changing it from "0" to "1", transistors P2 and P4 will be temporarily turned off. However, transistors P6 and N2 will also be turned off. The states of redundant node S1 and output node OUT will not change. With the help of the conducting transistor P5, redundant node S0 will be restored. If a SE is triggered in redundant node S1, since the PMOS transistor can only generate an upward transient current, only a "1" to "1" transient pulse can be generated at redundant node S1. This will not change the logic value of redundant node S1, so redundant node S1 is not a sensitive node at this time.
[0040] Reference Figure 1 and Figure 2During the reading of a "1" from SRAM, if a single-event upset (S&E) occurs at the output node OUT (since the output node OUT is currently "1", only transistor N2 needs to be considered), meaning the drain of transistor N2 is bombarded by a high-energy particle, generating a downward transient current, the output node OUT changes from "1" to "0". At this time, transistor N1 will temporarily turn off, and transistor P6 will turn on, but transistor P2 will remain on. Since transistor P2 is larger than transistor P6, the redundant node S1 will not be pulled low by transistor P6, but will remain high. Therefore, transistors P3 and P1 will not turn on, and thus the redundant node S0 and the output node OUTN will remain low. The redundant node OUT will be pulled back high by the turned-on transistor P4 and the turned-off transistor N2, realizing the self-recovery process of the S&E at this node. This correctly amplifies the voltage difference between the bit line and the inverted bit line, avoiding errors during read operations. (See reference...) Figure 2 The timing diagram shows the time interval from 16 nanoseconds to 18 nanoseconds.
[0041] Figure 3 This is another timing diagram illustrated by an example, referencing Figure 1 and Figure 3 During the SRAM read of a "1", if a single-event upset (S&E) occurs at the output node OUTN (since the value of OUTN is "0" at this time, only transistor P3 needs to be considered), i.e., the drain of transistor P3 is bombarded by a high-energy particle, generating an upward transient current, and the output node OUTN changes from "0" to "1". At this time, transistor P5 is temporarily turned off, and transistor N2 is temporarily turned on. However, transistor P4 is also turned on, and transistor P5 is turned off. Due to the capacitance effect, the redundant node S0 remains unchanged, so transistor P4 can remain on. Since the size of transistor P4 is larger than that of transistor N2, the output node OUTN is pulled back to a high level by transistor P4 after a brief voltage drop, causing transistor N1 to turn on again. The output node OUTN is pulled down to a low level by transistor N1, realizing the S&E recovery process of this node, thereby correctly amplifying the voltage difference between the bit line and the inverted bit line and avoiding errors in the read operation. (See reference...) Figure 3 The timing diagram shows the time interval from 16 nanoseconds to 18 nanoseconds.
[0042] Figure 4 This is yet another timing diagram illustrated by an example, with reference to... Figure 1 and Figure 4During a read of "1" from SRAM, if both output nodes OUT and OUTN experience a single-event upset (SET), as described above, only transistor N2 needs to be considered at output node OUT, and transistor P3 at output node OUTN. At this time, the drain of transistor N2 is bombarded by a high-energy particle, generating a downward transient current; the drain of transistor P3 is bombarded by a high-energy particle, generating an upward transient current. Output node OUT changes from "1" to "0", and output node OUTN changes from "0" to "1". Transistors N1 and P5 are temporarily turned off, while transistors N2 and P6 are temporarily turned on. Redundant node S1, due to the larger size of transistor P2 than transistor P6,... Although transistors P2 and P6 are turned on simultaneously, the larger and more powerful transistor P2 keeps redundant node S1 at a high level, thus keeping transistor P1 off and redundant node S0 at a low level. Transistor P3 also remains off, preventing a continuous and stable high level from being provided to output node OUTN. Under the influence of the larger and more powerful transistor P4, output node OUT is pulled back to a high level, which in turn turns transistor N1 back on, restoring output node OUTN to a low level. This completes the dual-node anti-single-event process for output nodes OUT and OUTN, correctly amplifying the voltage difference between the bit line and the inverted bit line, and preventing read operation errors. (See reference...) Figure 4 The timing diagram shows the time interval from 16 nanoseconds to 18 nanoseconds.
[0043] Refer again Figure 1It should be noted that the circuit structure in this example is completely symmetrical. When the SRAM reads "0", the working principle and anti-single-event upset principle of the sensitive amplifier in this example are similar to those when the SRAM reads "1". During the SRAM read "0", if both output nodes OUT and OUTN experience a single-event upset simultaneously, as described above, only transistor P4 needs to be considered at output node OUT, and only transistor N1 needs to be considered at output node OUTN. At this time, the drain of transistor N1 is bombarded by a high-energy particle, generating a downward transient current, and the drain of transistor P4 is bombarded by a high-energy particle, generating an upward transient current. Output node OUTN changes from "1" to "0", and output node OUT changes from "0" to "1". Transistors N2 and P6 are temporarily turned off, and transistors N1 and P6... Transistor P5 is temporarily turned on. Because transistor P1 is larger than transistor P5, redundant node S0 remains at a high level due to the larger and more powerful transistor P1, even though both transistors P1 and P5 are turned on simultaneously. This keeps transistor P2 off, and redundant node S1 remains at a low level. Transistor P4 also remains off, thus preventing a continuous and stable high level from being provided to output node OUT. Output node OUTN is pulled back to a high level by transistor P3, which is larger and has a stronger driving capability. This then turns transistor N2 back on, and output node OUT returns to a low level. This completes the dual-node anti-single-event process for output nodes OUT and OUTN, thereby correctly amplifying the voltage difference between the bit line and the inverted bit line and preventing errors in the read operation.
[0044] The above technical solution provides a current-latch sensitive amplifier resistant to single-event upsets. Its structure includes multiple PMOS and NMOS transistors to achieve anti-interference capability against transient currents induced by high-energy particles. It maintains output stability during SRAM read operations. The pre-charge circuit keeps the output node at a high level in a low-level state. During the read operation, the circuit adjusts the voltage of the output node according to the voltage difference between the input bit line signal and the inverted bit line signal to rapidly amplify minute voltage changes. Simultaneously, the circuit incorporates a self-recovery mechanism to cope with single-event upset events. When high-energy particles bombard the circuit, the state of the relevant transistors may be affected, but through the circuit's redundancy design and feedback mechanism, it can effectively recover to its original state, ensuring circuit reliability and read accuracy.
[0045] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.
[0046] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.
[0047] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.
Claims
1. A current-latch sensitive amplifier resistant to single-event upsets, characterized in that, include: The circuit includes a precharge circuit (10), a 4P unit (20), a 2P2N unit (30), a bit line input circuit (40), and an enable transistor circuit (50). The precharge circuit (10) is used to stabilize the output node OUT and the output node OUTN to a high level through the power supply VDD when the precharge signal PRE is low before the SRAM performs a read operation, and to make the output node OUT and the output node OUTN have the same high level. The bit line input circuit (40) and the enable transistor circuit (50) are used to adjust the voltage of the output node OUT and the output node OUTN according to the voltage difference between the bit line signal BL and the inverted bit line signal BLN when the SRAM performs a read operation, so as to amplify the voltage change of the output node OUT and the output node OUTN. The 4P unit (20) and the 2P2N unit (30) are used to restore the circuit to its original state based on the redundant node S0 and the redundant node S1 when a single-particle flip occurs in the circuit; wherein the redundant node S0 and the redundant node S1 are obtained based on the 4P unit (20) and the 2P2N unit (30). The 4P unit (20) includes transistors P1, P2, P5, and P6. The sources of transistors P1 and P2 are connected to the power supply VDD. The drain of transistor P1 is connected to the source of transistor P5 and serves as the redundant node S0. The drain of transistor P2 is connected to the source of transistor P6 and serves as the redundant node S1. The gate of transistor P1 is connected to the redundant node S1, and the gate of transistor P2 is connected to the redundant node S0. The drains of transistors P5 and P6 are grounded. Transistor P5 is connected to the output node OUTN, and transistor P6 is connected to the output node OUT. The 2P2N unit (30) includes: transistor P3, transistor P4, transistor N1 and transistor N2; the sources of transistor P3 and transistor P4 are both connected to the power supply VDD, the drain of transistor P3 is connected to the drain of transistor N1 and connected to the output node OUTN, the drain of transistor P4 is connected to the drain of transistor N2 and connected to the output node OUT, the gate of transistor P3 is connected to the redundant node S1, and the gate of transistor P4 is connected to the redundant node S0; the sources of transistor N1 and transistor N2 are connected to the bit line input circuit (40), the gate of transistor N1 is connected to the output node OUT, and the gate of transistor N2 is connected to the output node OUTN; The sensitive amplifier is implemented using fully depleted silicon-on-insulator (SiI) technology. The size of transistor P2 is larger than that of transistor P6, and the size of transistor P4 is larger than that of transistor N2. When both output nodes OUT and OUTN experience a single-event upset, the larger size of transistor P2 compared to transistor P6 keeps redundant node S1 at a high level, transistor P1 remains off, and redundant node S0 remains at a low level. The larger size of transistor P4 compared to transistor N2 pulls output node OUT back to a high level, and transistor N1 is turned on again to restore output node OUTN to a low level.
2. The current-latch sensitive amplifier resistant to single-event upsets according to claim 1, characterized in that, The pre-charge circuit (10) includes transistors P7, P8, and P9; the gates of transistors P7, P8, and P9 are all connected to the pre-charge signal PRE; the source of transistor P7 is connected to the power supply VDD; the drain of transistor P7 is connected to the source of transistor P9 and connected to the output node OUTN; the source of transistor P8 is connected to the power supply VDD; and the drain of transistor P8 is connected to the drain of transistor P9 and connected to the output node OUT.
3. The current-latch sensitive amplifier resistant to single-event upsets according to claim 1, characterized in that, The bit line input circuit (40) includes: transistor N3 and transistor N4; the drain of transistor N3 is connected to the source of transistor N1, the drain of transistor N4 is connected to the source of transistor N2, the sources of transistor N3 and transistor N4 are both connected to the enable transistor circuit (50), the gate of transistor N3 is connected to the bit line signal BL, and the gate of transistor N4 is connected to the inverted bit line signal BLN.
4. The current-latch sensitive amplifier resistant to single-event upsets according to claim 3, characterized in that, The enable transistor circuit (50) includes: transistor N5; the source of transistor N5 is grounded, the drain of transistor N5 is connected to the source of transistor N3 and transistor N4, and the gate of transistor N5 is connected to enable signal SAE.