Bit line interference suppression circuit and method and memory

Abstract

The embodiment of the invention provides a bit line interference suppression circuit and method and a memory, and relates to the technical field of semiconductors. The bit line interference suppression circuit comprises a plurality of switch modules, the switch modules are in one-to-one correspondence with bit lines in a memory, one end of each switch module is electrically connected with the corresponding bit line, and the other end of each switch module is grounded; and the switch module is switched on under the condition that the corresponding bit line is not selected, and is switched off under the condition that the corresponding bit line is selected. As the switch module is switched on under the condition that the corresponding bit line is not selected, the unselected bit line is equivalent to be directly grounded, even if the voltage on the selected bit line close to the switch module is coupled to the unselected bit line, the voltage can quickly flow to the ground through the switch module, and the voltage on the selected bit line close to the switch module can be directly grounded. And the bit lines which are not selected are not interfered, so that the reliability of the memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a bit line disturbance suppression circuit, method and memory. Background Art

[0002] Non-volatile memory (such as NOR Flash) is widely used in various products, such as storage and communication devices such as mobile phones, notebooks, PDAs and solid-state drives, due to its advantages such as data retention in the event of power failure and the ability to erase and write data multiple times.

[0003] With the continuous advancement of semiconductor technology, the distance between memory cells and bit lines (BL to BL) in memory is gradually reduced. However, the reduction in the distance between bit lines will lead to enhanced capacitive coupling between bit lines that are closer, so that the voltage on the selected bit line can be coupled to the unselected bit line that is closer, thereby interfering with the unselected bit line. For example, when a memory cell is programmed, the voltage on the bit line where the memory cell is located may be coupled to other bit lines that are closer, thereby causing programming interference to other memory cells on the word line where the memory cell is located. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a bit line disturbance suppression circuit, method and memory to solve the bit line disturbance problem in the memory and improve the reliability of the memory.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, the present invention provides a bit line interference suppression circuit, which is applied to a memory, and the bit line interference suppression circuit includes a plurality of switch modules, each of which corresponds to a bit line in the memory one by one, one end of each switch module is electrically connected to the corresponding bit line, and the other end of each switch module is grounded; the switch module is turned on when the corresponding bit line is not selected, and is turned off when the corresponding bit line is selected.

[0007] In an optional implementation manner, a gating module is correspondingly arranged on each of the bit lines, and the switch module corresponding to each of the bit lines is mutually exclusive with the gating module.

[0008] In an optional implementation, the gating module is an NMOS tube, and one end of the switch module is electrically connected to the source of the gating module on the corresponding bit line.

[0009] In an optional embodiment, the switch module is a PMOS tube, the gate of the switch module is electrically connected to the gate of the selection module to receive the same control signal, the source of the switch module is grounded, and the drain of the switch module is electrically connected to the source of the selection module.

[0010] In an optional embodiment, the switch module is an NMOS tube, the gate of the switch module and the gate of the gating module receive different control signals respectively, the source of the switch module is grounded, and the drain of the switch module is electrically connected to the source of the gating module.

[0011] In a second aspect, the present invention provides a memory, comprising a plurality of bit lines and the bit line interference suppression circuit described in any one of the aforementioned embodiments.

[0012] In an optional embodiment, the memory further includes a plurality of word lines and a plurality of memory cells arranged in an array, the memory cells in the same row are electrically connected to the same word line, and the memory cells in the same column are electrically connected to the same bit line.

[0013] In an optional embodiment, each of the storage cells includes a floating gate transistor, a control gate of the floating gate transistor is electrically connected to the corresponding word line, a drain of the floating gate transistor is electrically connected to the corresponding bit line, and a source of the floating gate transistor is electrically connected to the corresponding source line.

[0014] In an optional embodiment, each of the memory cells includes a selection transistor and a storage transistor, the drain of the storage transistor is electrically connected to the source of the selection transistor, the drain of the selection transistor is electrically connected to the corresponding bit line, the control gate of the storage transistor is electrically connected to the corresponding word line, the gate of the selection transistor is electrically connected to the corresponding selection line, and the source of the storage transistor is electrically connected to the corresponding source line.

[0015] In a third aspect, the present invention provides a method for suppressing bit line interference, for suppressing interference between bit lines in a memory in any one of the aforementioned embodiments, the method comprising:

[0016] For any target bit line to be selected, controlling the gating module on the target bit line to be turned on and the switch module corresponding to the target bit line to be turned off;

[0017] The gating modules on the other bit lines in the memory except the target bit line are controlled to be disconnected and the switch modules corresponding to the other bit lines are controlled to be turned on.

[0018] The bit line interference suppression circuit, method and memory provided by the embodiment of the present invention, the bit line interference suppression circuit includes a plurality of switch modules, the switch modules correspond to the bit lines in the memory one by one, one end of the switch module is electrically connected to the corresponding bit line, and the other end of the switch module is grounded; the switch module is turned on when the corresponding bit line is not selected, and is turned off when the corresponding bit line is selected. Since the switch module is turned on when the corresponding bit line is not selected, the unselected bit line is equivalent to being directly grounded, so even if the voltage on the selected bit line with a short distance is coupled to the unselected bit line, the voltage can quickly flow to the ground through the switch module, so as not to cause interference to the unselected bit line, thereby improving the reliability of the memory.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic diagram of the structure of a memory provided by an embodiment of the present invention is shown;

[0022] Figure 2 Shows Figure 1 The connection diagram when the middle selection module uses NMOS tube;

[0023] Figure 3 Shows Figure 2 The connection diagram of the switch module with the gating module when the switch module is a PMOS tube;

[0024] Figure 4 Shows Figure 2 The connection diagram of the switch module with the gating module when the switch module is an NMOS tube;

[0025] Figure 5 Shows Figure 1 The connection diagram of the storage unit in FIG. 1 is a diagram showing a connection diagram of the storage unit in FIG. 1 using a single transistor structure;

[0026] Figure 6 Shows Figure 1 The connection diagram of the storage unit in FIG. 1 is a diagram showing a connection diagram of the storage unit in FIG. 1 using a dual transistor structure;

[0027] Figure 7A schematic flow chart of a method for suppressing bit line disturbance provided by an embodiment of the present invention is shown.

[0028] Icons: 10 - memory; 101 - switch module; 201 - storage unit; 202 - selection module; 2011 - storage transistor; 2012 - selection transistor. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0031] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0032] Please refer to Figure 1 , is a schematic diagram of a structure of a memory 10 provided in an embodiment of the present invention. The memory 10 includes a plurality of bit lines (BL0 to BLn, where n can be 2 k , such as 4, 8, 16, 32, 64, etc.) and a bit line interference suppression circuit, the bit line interference suppression circuit includes a plurality of switch modules 101, the switch modules 101 correspond to the bit lines in the memory 10 one by one, one end of the switch module 101 is electrically connected to the corresponding bit line, and the other end of the switch module 101 is grounded; the switch module 101 is turned on when the corresponding bit line is not selected, and is turned off when the corresponding bit line is selected.

[0033] For example, when the bit line BL1 needs to be selected, the switch module 101 corresponding to the bit line BL1 can be controlled to be disconnected, and the switch modules 101 corresponding to other bit lines (BL0, BL2~BLn) can be controlled to be turned on. In this way, even if the voltage on the bit line BL1 is coupled to the unselected bit lines that are close (such as the adjacent bit lines BL0 and BL2), the voltage can quickly flow to the ground through the switch modules 101 corresponding to the bit lines BL0 and BL2 without interfering with the unselected bit lines BL0 and BL2, thereby improving the reliability of the memory 10.

[0034] It can be seen that the bit line interference suppression circuit provided by the embodiment of the present invention includes a plurality of switch modules, the switch modules correspond to the bit lines in the memory one by one, one end of the switch module is electrically connected to the corresponding bit line, and the other end of the switch module is grounded; the switch module is turned on when the corresponding bit line is not selected, and is turned off when the corresponding bit line is selected. Since the switch module is turned on when the corresponding bit line is not selected, the unselected bit line is equivalent to being directly grounded, so even if the voltage on the selected bit line at a relatively close distance is coupled to the unselected bit line, the voltage can quickly flow to the ground through the switch module without causing interference to the unselected bit line, thereby improving the reliability of the memory.

[0035] In one embodiment, please continue to refer to Figure 1 A gating module 202 is correspondingly arranged on each bit line, and the switch module 101 corresponding to each bit line and the gating module 202 are mutually exclusive and conductive.

[0036] In this embodiment, each bit line of the memory 10 is connected to a corresponding gating module 202, and the gating module 202 is used to control whether the corresponding bit line is selected. When the gating module 202 is turned on, the bit line corresponding to the gating module 202 is selected; when the gating module 202 is turned off, the bit line corresponding to the gating module 202 is not selected.

[0037] The switch module 101 and the gating module 202 are mutually exclusive, which can be understood as that at the same time, one of the switch module 101 and the gating module 202 is in the on state and the other is in the off state. Therefore, by controlling the switch module 101 and the gating module 202 corresponding to each bit line to be mutually exclusive, it can be achieved that the switch module 101 is turned on when the corresponding bit line is not selected, and is turned off when the corresponding bit line is selected.

[0038] In one implementation, the gating module 202 may be an NMOS transistor, and one end of the switch module 101 is electrically connected to the source of the gating module 202 on the corresponding bit line.

[0039] like Figure 2As shown, the gating modules 202 on the bit lines BL0-BLn are NMOS tubes BLT0-BLTn respectively, and the sources of the NMOS tubes BLT0-BLTn are electrically connected to the corresponding bit lines. When the bit line is selected, the corresponding gating module 202 is in the on state, and the voltage on the drain of the gating module 202 is transmitted to the bit line. The switch module 101 corresponding to the bit line is in the off state, and will not affect the voltage on the selected bit line; when the bit line is not selected, the corresponding gating module 202 is in the off state, and the corresponding switch module 101 is in the on state, which is equivalent to the unselected bit line being directly grounded. Therefore, even if the voltage on the nearby selected bit line is coupled to the unselected bit line, it can be conducted away by the ground, effectively avoiding the generation of interference.

[0040] In this embodiment, in order to realize that the switch module 101 and the gating module 202 corresponding to each bit line are mutually exclusive, the switch module 101 may be a PMOS tube or an NMOS tube.

[0041] In one embodiment, Figure 3 As shown, the switch module 101 is a PMOS tube, the gate of the switch module 101 is electrically connected to the gate of the gate module 202 to receive the same control signal, the source of the switch module 101 is grounded, and the drain of the switch module 101 is electrically connected to the source of the gate module 202.

[0042] In this embodiment, since the switch module 101 is a PMOS tube, the gate module 202 is an NMOS tube, and the gate of the switch module 101 is connected to the gate of the gate module 202, the switch module 101 and the gate module 202 can be mutually exclusive under the control of the same control signal.

[0043] For example, for the bit line BL1 that needs to be selected, a high voltage control signal (such as +V) can be applied to the gate of the gating module 202 corresponding to the bit line BL1. Since the gate of the switch module 101 is connected to the gate of the gating module 202, the gate of the switch module 101 corresponding to the bit line BL1 will also receive the high voltage control signal. The gating module 202 is turned on under the action of the high voltage control signal, and the switch module 101 is turned off under the action of the high voltage control signal. For the bit lines BL0, BL2~BLn that do not need to be selected, a high voltage control signal (such as +V) can be applied to the bit lines BL0, BL2~BLn. A low voltage control signal (such as -V) is applied to the gate of the selection module 202 corresponding to Ln. At this time, the gate of the switch module 101 corresponding to the bit lines BL0, BL2~BLn will also receive the low voltage control signal. The selection module 202 is disconnected under the action of the low voltage control signal, and the switch module 101 is turned on under the action of the low voltage control signal. The bit lines BL0, BL2~BLn are equivalent to being directly grounded. Even if the voltage on the bit line BL1 is coupled to the adjacent bit lines BL0, BL2, it can be conducted away by the corresponding switch module 101, thereby effectively avoiding the generation of interference.

[0044] In another embodiment, if Figure 4 As shown, the switch module 101 is an NMOS tube, the gate of the switch module 101 and the gate of the gate module 202 receive different control signals respectively, the source of the switch module 101 is grounded, and the drain of the switch module 101 is electrically connected to the source of the gate module 202.

[0045] In this embodiment, since the switch module 101 and the gate module 202 are both NMOS transistors, different control signals need to be applied to the gate of the switch module 101 and the gate of the gate module 202 respectively to achieve mutual exclusive conduction.

[0046] For example, for the bit line BL1 that needs to be selected, a high voltage control signal (such as +V) can be applied to the gate of the gating module 202 corresponding to the bit line BL1, and a low voltage control signal (such as -V or 0V) can be applied to the gate of the switch module 101 corresponding to the bit line BL1. The gating module 202 is turned on by the high voltage control signal, and the switch module 101 is turned off by the low voltage control signal. For the bit lines BL0, BL2 to BLn that do not need to be selected, the gates of the gating modules 202 corresponding to the bit lines BL0, BL2 to BLn are turned on by the low voltage control signal. A low voltage control signal (such as -V or 0V) is applied, and a high voltage control signal (such as +V) is applied to the gate of the switch module 101 corresponding to the bit lines BL0, BL2~BLn. The selection module 202 is disconnected under the action of the low voltage control signal, and the switch module 101 is turned on under the action of the high voltage control signal. The bit lines BL0, BL2~BLn are equivalent to being directly grounded. Even if the voltage on the bit line BL1 is coupled to the adjacent bit lines BL0, BL2, it can be conducted away through the corresponding switch module 101 to the ground, effectively avoiding the generation of interference.

[0047] In one embodiment, please continue to refer to Figure 1 The memory 10 also includes a plurality of word lines (WL0 to WLm, where m can be 2 k , such as 4, 8, 16, 32, 64, etc.) and a plurality of memory cells 201 arranged in an array, the memory cells 201 in the same row are electrically connected to the same word line, and the memory cells 201 in the same column are electrically connected to the same bit line.

[0048] In this embodiment, the memory cell 201 in the memory 10 may adopt a single transistor (1T) structure or a double transistor (2T) structure.

[0049] When the memory cell 201 adopts a single transistor structure, please refer to Figure 5 Each memory cell 201 includes a floating gate transistor, the control gate of the floating gate transistor is electrically connected to the corresponding word line, the drain of the floating gate transistor is electrically connected to the corresponding bit line, and the source of the floating gate transistor is electrically connected to the corresponding source line (SL0-SLm). The sources of the floating gate transistors in the same row are all connected to the same source line, and all the source lines are connected to a fixed voltage reference point VSS (for example, it can be the ground terminal of the power supply).

[0050] When the memory cell 201 adopts a dual transistor structure, please refer to Figure 6Each memory cell 201 includes a memory transistor 2011 and a selection transistor 2012. The drain of the memory transistor 2011 is electrically connected to the source of the selection transistor 2012. The drain of the selection transistor 2012 is electrically connected to the corresponding bit line. The control gate of the memory transistor 2011 is electrically connected to the corresponding word line. The gate of the selection transistor 2012 is electrically connected to the corresponding selection line (ML0-ML m). The source of the memory transistor 2011 is electrically connected to the corresponding source line (SL0-SLm). The gates of the selection transistors 2012 in the same row are all connected to the same selection line. The sources of the memory transistors 2011 in the same row are all connected to the same source line. All source lines are connected to a fixed voltage reference point VSS.

[0051] Please refer to Figure 7 , is a flow chart of a bit line interference suppression method provided by an embodiment of the present invention, the bit line interference suppression method can be executed by a controller to suppress the interference between bit lines in the above-mentioned memory 10. Figure 7 As shown, the bit line disturbance suppression method includes:

[0052] Step S701 , for any target bit line to be selected, control the gating module 202 on the target bit line to be turned on and the switch module 101 corresponding to the target bit line to be turned off.

[0053] Step S702 , controlling the selection modules 202 on the bit lines other than the target bit line in the memory 10 to be turned off and the switch modules 101 corresponding to the other bit lines to be turned on.

[0054] In this embodiment, when a write operation needs to be performed on a target memory cell, the bit line corresponding to the target memory cell is the target bit line to be selected, and it is necessary to control the gating module 202 on the target bit line to be turned on and the switch module 101 corresponding to the target bit line to be turned off, and control the gating modules 202 on other bit lines in the memory 10 except the target bit line to be turned off and the switch modules 101 corresponding to other bit lines to be turned on. Since the gating module 202 on the target bit line is turned on, the high voltage required for the write operation is transmitted to the target memory cell through the gating module 202, and a high voltage is also applied to the word line corresponding to the target memory cell. The target memory cell will generate hot electrons under the influence of the high voltage on the bit line, and these hot electrons are injected into the Floating Gate (FG) under the action of the longitudinal electric field generated by the high voltage on the word line, thereby changing the threshold voltage of the target memory cell and completing the write operation. In the process of performing a write operation on the target memory cell, since the switch module 101 on the bit lines other than the target bit line (the unselected bit lines) is in the on state, which is equivalent to the unselected bit lines being directly grounded, even if the voltage on the target bit line is coupled to the nearby unselected bit lines, it can be conducted away by the ground, effectively suppressing the generation of write interference. For example, the target memory cell is C11, the corresponding bit line is BL1, and the corresponding word line is WL1. When performing a write operation on the target memory cell C11, even if the voltage on the bit line BL1 is coupled to the adjacent unselected bit lines BL1 and BL2, it will not cause write interference to the memory cells C10 and C12 that share the word line WL1 with the target memory cell C11.

[0055] In summary, the bit line interference suppression circuit, method and memory provided by the embodiments of the present invention include a plurality of switch modules, the switch modules correspond to the bit lines in the memory one by one, one end of the switch module is electrically connected to the corresponding bit line, and the other end of the switch module is grounded; the switch module is turned on when the corresponding bit line is not selected, and is turned off when the corresponding bit line is selected. Since the switch module is turned on when the corresponding bit line is not selected, the unselected bit line is equivalent to being directly grounded, so even if the voltage on the selected bit line at a relatively close distance is coupled to the unselected bit line, the voltage can quickly flow to the ground through the switch module, so as not to cause interference to the unselected bit line, thereby improving the reliability of the memory.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A bit line disturbance suppression circuit, characterized in that: Applied to a memory, the bit line interference suppression circuit includes a plurality of switch modules, each of which corresponds to a bit line in the memory one by one, one end of each switch module is electrically connected to the corresponding bit line, and the other end of each switch module is grounded; the switch module is turned on when the corresponding bit line is not selected, and is turned off when the corresponding bit line is selected.

2. The bit line disturbance suppression circuit according to claim 1, characterized in that: A gating module is correspondingly arranged on each of the bit lines, and the switch module corresponding to each of the bit lines is mutually exclusive and conductive with the gating module.

3. The bit line disturbance suppression circuit according to claim 2, characterized in that: The gating module is an NMOS tube, and one end of the switch module is electrically connected to the source of the gating module on the corresponding bit line.

4. The bit line disturbance suppression circuit according to claim 3, characterized in that: The switch module is a PMOS tube, the gate of the switch module is electrically connected to the gate of the gating module to receive the same control signal, the source of the switch module is grounded, and the drain of the switch module is electrically connected to the source of the gating module.

5. The bit line disturbance suppression circuit according to claim 3, characterized in that: The switch module is an NMOS tube, the gate of the switch module and the gate of the gating module receive different control signals respectively, the source of the switch module is grounded, and the drain of the switch module is electrically connected to the source of the gating module.

6. A memory, characterized in that: The memory comprises a plurality of bit lines and the bit line disturbance suppression circuit according to any one of claims 1 to 5.

7. The memory according to claim 6, characterized in that: The memory also includes a plurality of word lines and a plurality of storage cells arranged in an array, the storage cells in the same row are electrically connected to the same word line, and the storage cells in the same column are electrically connected to the same bit line.

8. The memory according to claim 7, characterized in that: Each of the memory cells includes a floating gate transistor, a control gate of the floating gate transistor is electrically connected to the corresponding word line, a drain of the floating gate transistor is electrically connected to the corresponding bit line, and a source of the floating gate transistor is electrically connected to the corresponding source line.

9. The memory according to claim 7, characterized in that: Each of the memory cells includes a selection transistor and a storage transistor, the drain of the storage transistor is electrically connected to the source of the selection transistor, the drain of the selection transistor is electrically connected to the corresponding bit line, the control gate of the storage transistor is electrically connected to the corresponding word line, the gate of the selection transistor is electrically connected to the corresponding selection line, and the source of the storage transistor is electrically connected to the corresponding source line.

10. A method for suppressing bit line disturbance, characterized in that: The method for suppressing interference between bit lines in the memory according to any one of claims 6 to 9 comprises: For any target bit line to be selected, controlling the gating module on the target bit line to be turned on and the switch module corresponding to the target bit line to be turned off; The gating modules on the other bit lines in the memory except the target bit line are controlled to be disconnected and the switch modules corresponding to the other bit lines are controlled to be turned on.

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