Code word information decoding method and device and storage medium

Abstract

The invention relates to the technical field of memorizers, and discloses a decoding method and device of code word information and a storage medium, and relates to the technical field of memorizers, and the decoding method comprises the steps that when the code word information is read, the number of error bits in the code word information is determined; if the number of the error bits is greater than the error correctable number, re-reading the codeword information, and performing a flipping operation on the codeword information according to a re-reading result; and performing hard decoding on the flipping result based on an iterative algorithm to obtain a corresponding decoding result. The invention aims to improve the decoding capability.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a decoding method, device and storage medium for codeword information. Background Art

[0002] NAND Flash (Not AND Flash) is a very important non-volatile memory, which is widely used in various portable electronic devices. Although NAND Flash has the advantages of high density and low cost, it is prone to various errors during data storage.

[0003] In order to improve the reliability of NAND Flash, ECC (Error Correction Code) technology is usually used to detect and correct errors generated during the storage process. Common algorithms include BCH (Bose Chaudhuri Hocquenghem). BCH code is a linear cyclic code that can locate and correct error bits by calculating adjoint polynomials and applying specific algorithms, thereby restoring the original information.

[0004] However, for a specific BCH code, the number of correctable errors is determined during design. Once the number of errors that actually occur exceeds this threshold, the decoding performance will be severely affected.

[0005] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0006] The main purpose of this application is to provide a decoding method, device and storage medium for codeword information, aiming to solve the technical problem of insufficient decoding capability.

[0007] To achieve the above purpose, the present application proposes a method for decoding codeword information, the method comprising:

[0008] When the code word information is read, determining the number of error bits in the code word information;

[0009] If the number of error bits is greater than the number of correctable errors, the codeword information is re-read, and the codeword information is flipped according to the re-reading result;

[0010] The flip result is hard-decoded based on the iterative algorithm to obtain the corresponding decoding result.

[0011] In one embodiment, when the code word information is read, the step of determining the number of error bits in the code word information includes:

[0012] When the code word information is read, a division operation is performed on the code word information based on the generating polynomial to obtain a corresponding adjoint polynomial;

[0013] The number of erroneous bits is determined based on the syndrome coefficients of the syndrome polynomial.

[0014] In one embodiment, the steps of re-reading the code word information and performing a flipping operation on the code word information according to the re-reading result include:

[0015] Adjust the voltage according to the preset adjustment amount and collect the re-reading results at each voltage;

[0016] Performing XOR calculation on all re-read results, and determining the bit to be flipped in the codeword information according to the calculation result;

[0017] Flip the bit to be flipped.

[0018] In one embodiment, the step of performing a flipping operation on the bit to be flipped includes:

[0019] Detecting the decoding record of the hierarchical structure where the codeword information is located;

[0020] If the decoding record is empty, all bits to be flipped are flipped;

[0021] If the decoding record is not empty, the bits to be flipped are screened according to the average number of error bits in the decoding record, and a flip operation is performed on the screened bits to be flipped.

[0022] In one embodiment, the step of screening the bits to be flipped includes:

[0023] Determine the correlation coefficient between the bit to be flipped and the historical error bit in the decoding record;

[0024] All the bits to be flipped are sorted according to the correlation coefficient to generate a sequence, and the sequence is screened according to the average.

[0025] In one embodiment, before the step of sorting all the bits to be flipped according to the correlation coefficient to generate a sequence and screening the sequence according to the average, the step further includes:

[0026] Determine the failure mode of the bit to be flipped according to the failure mode of the historical error bit that matches the bit to be flipped;

[0027] The correlation coefficients are weighted according to the severity of the failure mode.

[0028] In one embodiment, when the code word information is read, after the step of determining the number of error bits in the code word information, the method further includes:

[0029] If the number of erroneous bits is less than or equal to the number of correctable errors, the codeword information is decoded based on an iterative algorithm to obtain a corresponding decoding result.

[0030] In one embodiment, the step of hard decoding the flip result based on the iterative algorithm to obtain the corresponding decoding result includes:

[0031] If the number of error bits in the flip result is less than or equal to the number of correctable errors, the flip result is hard-decoded based on the iterative algorithm to obtain the corresponding decoding result;

[0032] After the step of hard decoding the flip result based on the iterative algorithm to obtain the corresponding decoding result, the method further includes:

[0033] If the number of error bits in the flip result is greater than the number of correctable errors, the flip result is decoded based on a low-density parity check algorithm to obtain a corresponding decoding result.

[0034] In addition, to achieve the above-mentioned purpose, the present application also proposes a decoding device for codeword information, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the codeword information decoding method as described above.

[0035] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the decoding method of the codeword information as described above are implemented.

[0036] One or more technical solutions proposed in this application have at least the following technical effects:

[0037] The present application provides a decoding method for codeword information. When the codeword information is read, the number of error bits therein is first determined. If it is greater than the correctable number, the codeword information will be reread and flipped. This strategy aims to capture and correct errors that may be introduced by instantaneous interference during the reading process, which can effectively reduce the number of error bits and significantly improve the reliability of the codeword information. After completing the above operations, an iterative algorithm will be used for hard decoding to obtain the final decoding result. This stage focuses on using the hard decoding algorithm to deeply analyze the pre-processed codeword information to obtain high-quality decoding results. In general, this solution combines the advantages of soft decoding and hard decoding to form a set of collaborative decoding processes. In particular, when facing a high error rate storage environment, soft decoding technology is preferred. With its optimization capability, the quality of codeword information is initially improved to reduce the processing burden of hard decoding, so that hard decoding can play a good error correction performance, and ultimately ensure that the processing capacity of the entire decoding process is maximized, achieving a good balance between error correction capability and hardware resource overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0040] Figure 1 A schematic diagram of a flow chart provided for the first embodiment of the method for decoding codeword information of the present application;

[0041] Figure 2 A schematic diagram of a flow chart provided for the second embodiment of the method for decoding codeword information of the present application;

[0042] Figure 3 A flowchart of a third embodiment of a method for decoding codeword information of the present application is provided;

[0043] Figure 4 A schematic diagram of the device structure of the hardware operating environment involved in the method for decoding codeword information in the embodiment of the present application.

[0044] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0045] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0046] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0047] The main solution of the embodiment of the present application is: when the code word information is read, the number of error bits in the code word information is determined; if the number of error bits is greater than the number of correctable errors, the code word information is re-read, and the code word information is flipped according to the re-reading result; the flipping result is hard-decoded based on the iterative algorithm to obtain the corresponding decoding result.

[0048] NAND Flash is a very important non-volatile memory, which is widely used in solid-state drives, USB (Universal Serial Bus) flash drives, SD cards (Secure Digital Cards), embedded systems and other devices. Although NAND Flash has the advantages of high density and low cost, it is prone to various errors during data storage, including but not limited to:

[0049] 1. Physical damage: NAND Flash storage cells will gradually degrade during repeated erasing and writing, resulting in reduced reliability of the cells and eventually causing errors.

[0050] 2. Read disturbance: During the reading process, the charge state of adjacent cells may be disturbed, resulting in read errors.

[0051] 3. Charge leakage: When storing data for a long time, the charge in the storage cell may gradually leak out, resulting in data errors.

[0052] 4. Programming interference: When writing data, the programming voltage may affect adjacent cells and cause programming errors.

[0053] 5. Process error: logical error introduced during the production of semiconductors, etc.

[0054] In addition, with the continuous advancement of manufacturing technology, Nandflash has adopted multi-layer cell manufacturing to increase storage density and page size, which has now increased to 8KB. Although this change provides a significant increase in storage capacity, it also increases the bit error rate.

[0055] In order to improve the reliability of NAND Flash, ECC technology is usually used to detect and correct errors generated during the storage process. Traditional algorithms such as CRC (Cyclic Redundancy Check), CRC check and Hamming code are rarely used due to their low error correction capabilities. LDPC (Low density parity check) and BCH are currently popular ECC algorithms.

[0056] Among them, the encoding and decoding circuits of BCH codes are relatively simple, requiring fewer hardware resources, and are suitable for resource-constrained application scenarios. However, for a specific BCH code, the number of correctable errors has been determined during the design. Once the number of errors that actually occur exceeds this threshold, the decoding performance will be seriously affected. In other words, the error correction capability of BCH codes is limited, and they can usually only correct a small number of bit errors, making it difficult to cope with storage environments with high error rates.

[0057] Among them, LDPC code is a low-density parity-check code, which can be divided into many different types such as LP (Low Power), HP (High Performance), HT (High Throughput), etc. LDPC code has a strong error correction capability and can correct a large number of bit errors, which is suitable for storage media with high error rates. However, the encoding and decoding process of LDPC code is relatively complex, and the required hardware resources and computing power are high, which poses a great challenge to the area cost and power consumption of the storage controller.

[0058] In practical applications, how to strike a balance between error correction capability and hardware overhead is the main challenge facing NAND Flash storage systems. In almost all ECC algorithms, the area and power consumption of the decoding module are often greater than those of the encoding module. Therefore, this solution mainly optimizes the decoding module and optimizes the decoding capability based on the BCH algorithm decoding module with smaller area overhead.

[0059] It should be noted that the execution subject of this solution can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or a decoding device for codeword information that can realize the above functions, etc. The following embodiments are described below taking the decoding device for codeword information as an example.

[0060] Based on this, the embodiment of the present application provides a method for decoding codeword information, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the method for decoding codeword information of the present application.

[0061] In this embodiment, the method for decoding codeword information includes steps S10 to S30:

[0062] Step S10: when the code word information is read, the number of error bits in the code word information is determined.

[0063] It should be noted that in communication or data storage systems, data is usually transmitted or stored in the form of codewords. Codeword information refers to the data block processed by the coding algorithm, and the system can read the codeword information from the communication channel or storage medium.

[0064] After reading the codeword information, the system will use some kind of error detection mechanism to check the number of error bits in the codeword information. Among them, error bits refer to bits that do not match the original data due to various reasons such as physical damage, read interference, charge leakage, etc. during data transmission or storage. These error bits will make it impossible to correctly identify or understand the original data. The number of error bits refers to the total number of bits in the codeword information that do not match the original data. This number is one of the important indicators for evaluating the quality of data transmission or storage.

[0065] Optionally, if there is sufficient historical data and error records, the error pattern can be analyzed by machine learning or statistical methods, and the distribution law of the bits can be analyzed to infer the bits in the codeword information where errors may occur.

[0066] Alternatively, the original codeword information is divided into multiple groups using a grouping method, and then redundant information, such as parity bits or other types of check bits, is added to each group. The redundant bits of each group can reflect the integrity of the data in that group. In this way, during the decoding process, data and redundant bits can be extracted from each group and checked group by group, and then the number of error bits can be calculated based on the check results of each group. For example, if it is found that the checks of group 1, group 2, and group 5 fail, this indicates that there are errors in three independent data groups, which also implies the existence of at least three error bits.

[0067] Step S20: if the number of error bits is greater than the number of correctable errors, the code word information is re-read, and the code word information is flipped according to the re-reading result.

[0068] In this solution, a combination of soft decoding and hard decoding is used. Among them, hard decoding refers to the use of direct algorithms to identify and correct errors, such as BCH codes. In contrast, soft decoding pays more attention to the confidence of the bit, that is, the possibility of each bit being judged as 0 or 1.

[0069] It should be noted that the number of correctable errors is a quantitative indicator of hard decoding capability, which defines the maximum threshold of error bits that the system can automatically identify and correct. For example, a BCH code is designed with a correctable error number of 3. This means that the BCH code can correct up to 3 bit errors. If 2 bit errors occur, the decoder of the BCH code will be able to successfully correct these errors and recover the original data; if 4 bit errors occur, the decoder of the BCH code may not be able to correctly recover the data because the number of correctable errors is exceeded, resulting in decoding failure or data errors.

[0070] Based on the above principle, when the number of detected error bits exceeds this threshold, the system will not be able to fully recover the data through its built-in error correction mechanism. Therefore, when the number of detected error bits is less than or equal to the number of correctable errors, within the processing capacity of hard decoding, you can directly enter the hard decoding stage. When the number of error bits is greater than the number of correctable errors, you need to reduce the number of error bits before entering the hard decoding stage.

[0071] In this solution, it is considered that during the reading process, the charge state of the adjacent cells may be disturbed, resulting in temporary reading errors. For such situations, since they are temporary, a re-reading method can be used to obtain a more accurate reading result. For example, the codeword information can be re-read directly according to the original voltage, or the voltage can be adjusted first and then re-read at the new voltage, which can improve the reading accuracy.

[0072] Next, all the reading results are collected, and the codeword information read for the first time in S10 may be included in the statistics.

[0073] This information is compared to analyze whether the bits have changed. For those bits that have changed significantly, the system will perform a flip operation, that is, change the value of certain bits in the codeword information from 0 to 1, or from 1 to 0, to restore the correctness of the data.

[0074] For example, the codeword information read in step S10 is 1010001, and the re-read result in step S20 is 1011011. After bit-by-bit comparison, the 4th and 6th bits from left to right change, so the 4th and 6th bits of the codeword information need to be flipped, and the flip result is 1011011.

[0075] The number of re-reading and flipping may be preset to a fixed value, such as 3 times.

[0076] After completing these operations, the correctness of the codeword information can be verified again. If the number of error bits is less than or equal to the number of correctable errors, it means that the error has been reduced to an acceptable range, and you can jump directly to the hard decoding stage. If the number of error bits is greater than the number of correctable errors, it means that the error is still serious after soft decoding processing. At this time, the LDPC low-density parity check algorithm with stronger error correction capability can be used for decoding.

[0077] Step S30, hard decoding the flip result based on an iterative algorithm to obtain a corresponding decoding result.

[0078] In this solution, the BM (Berlekamp-Massey) iterative algorithm in the BCH algorithm can be used for hard decoding. The BCH decoding process mainly includes three steps: calculating the adjoint polynomial, calculating the error polynomial, and error location and correction.

[0079] The first step is to calculate the adjoint polynomial:

[0080] According to the preset codeword length n and error correction capability t, a binary polynomial G(x) is first generated, called the generating polynomial. The flip result is converted into a polynomial R(x), which is usually expressed as R(x) = r 0 +r 1 x1 +r 2 x 2 +…+r n x n At this point, we can use polynomial division to divide R(x) by G(x). The remainder S(x) is the adjoint polynomial, S(x) = S 0 +S 1 x 1 +S 2 x 2 +…+S n x n .

[0081] The second step is to calculate the error polynomial:

[0082] First, define the initial structure of the error polynomial E(x), E(x) = e 1 x P1 +e 2 x p2 +…+e n x pn , where P 1 ,P 2 ,…,P n is the location where the error occurred, e n is the error mark for the corresponding position.

[0083] Then, the coefficients of the adjoint polynomial S(x) are associated with the structure of the error polynomial to construct the corresponding linear equation coefficients. The coefficients of each term reflect the error and position information. For example, for the adjoint polynomial S(x)=S 0 +S 1 x 1 +S 2 x 2 +…+S n x n , a set of linear equations can be derived based on the form of the error polynomial.

[0084] Next, the coefficients of the adjoint polynomial are substituted into the resulting linear equations to form a system of equations. This system of equations is solved by Gaussian elimination or other linear algebra techniques to obtain the indices of the error locations and the corresponding signs. Once the indices and signs of the error locations are determined, they can be plugged into the predefined error polynomial form to obtain the final error polynomial E(x).

[0085] The third step is to locate the error and correct it:

[0086] The roots of the known error polynomial E(x) correspond to the actual error occurrence positions, which are usually expressed in exponential form and need to be converted into specific bit positions.

[0087] Once the error location polynomial E(x) is known, its roots can be found using the Chien search method. This usually involves testing E(α i )=0 for all possible values ​​of i, where α is the primitive element.

[0088] For each error position found, a corresponding error correction operation is performed, usually by inverting the corresponding bit, or performing more complex correction actions according to the specific coding and modulation strategy, and finally obtaining a decoding result.

[0089] This embodiment provides a decoding method for codeword information. When the codeword information is read, the number of error bits therein is first determined. If it is greater than the correctable number, the codeword information will be reread and flipped. This strategy aims to capture and correct errors that may be introduced by instantaneous interference during the reading process, which can effectively reduce the number of error bits and significantly improve the reliability of the codeword information. After completing the above operations, an iterative algorithm will be used for hard decoding to obtain the final decoding result. This stage focuses on using the hard decoding algorithm to deeply analyze the pre-processed codeword information to obtain high-quality decoding results. In general, this solution combines the advantages of soft decoding and hard decoding to form a set of collaborative decoding processes. In particular, when facing a high error rate storage environment, soft decoding technology is preferred. With its optimization capability, the quality of codeword information is initially improved to reduce the processing burden of hard decoding, so that hard decoding can play a good error correction performance, and ultimately ensure that the processing capacity of the entire decoding process is maximized, achieving a good balance between error correction capability and hardware resource overhead.

[0090] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can refer to the above introduction, and will not be repeated later. Figure 2 Step S10 may include steps A10 to A20:

[0091] Step A10: When the code word information is read, a division operation is performed on the code word information based on the generator polynomial to obtain a corresponding adjoint polynomial.

[0092] Step A20, determining the number of error bits according to the syndrome coefficients of the syndrome polynomial.

[0093] In this embodiment, the number of error bits may be determined by directly referring to the adjoint polynomial in the first step of the iterative algorithm.

[0094] After reading the encoded codeword information, the codeword information is first divided by a known generating polynomial. The key to this step is that the generating polynomial is designed based on the preset codeword length n and the error correction capability t, and it contains key information about the codeword structure and error correction capability. Through polynomial division, a remainder can be obtained, which is called the adjoint polynomial. The adjoint polynomial is a direct reflection of the specific relationship between the codeword information and the generating polynomial, and it contains important information about the position of the error bit in the codeword.

[0095] After obtaining the companion polynomial, the next step is to determine the number of error bits based on its coefficients, i.e., the companion coefficients. The companion coefficients are the components of the companion polynomial, and the value of each coefficient corresponds to the error of a certain bit in the codeword. Usually, a non-zero companion coefficient indicates that there is an error at the corresponding bit position. Therefore, by counting the number of non-zero coefficients in the companion coefficients, the number of error bits can be preliminarily inferred.

[0096] Specifically, it is known that the first step of calculating the adjoint polynomial is as follows:

[0097] According to the preset codeword length n and error correction capability t, a binary polynomial G(x) is first generated, called the generating polynomial. The codeword information is converted into a polynomial R(x), which is usually expressed as R(x) = r 0 +r 1 x 1 +r 2 x 2 +…+r n x n At this point, we can use polynomial division to divide R(x) by G(x). The remainder S(x) is the adjoint polynomial, S(x) = S 0 +S 1 x 1 +S 2 x 2 +…+S n x n .

[0098] Based on the companion polynomial S(x), determine the companion coefficient S=(S 0 ,S 0 ,…,S n ).

[0099] The value of each syndrome coefficient may indicate an error condition of the corresponding bit. Generally speaking, a non-zero syndrome coefficient indicates that an error exists at the corresponding bit position.

[0100] By counting the number k of non-zero coefficients in the syndrome coefficient S, it can be inferred that errors have occurred in bits at k positions.

[0101] Exemplarily, the companion polynomial is S=(0, 1, 2, 3), which has three non-zero coefficients, and the number of error bits is three.

[0102] This embodiment provides a method for decoding codeword information, which directly uses algebraic structures to obtain adjoint polynomials by dividing the codeword information with the generator polynomial. The adjoint coefficients of the adjoint polynomial directly reflect the errors in the codeword. This scheme is based on rigorous mathematical derivation and proof, and can accurately indicate the existence of errors. Unlike machine learning, redundant information verification, etc., this scheme directly relies on algebraic characteristics, does not require additional training steps, and does not require additional redundant information. It directly uses the codeword itself and the generator polynomial for error detection, so it is more efficient and reliable. Moreover, since this scheme has already executed the first step of hard decoding in step S10, the second and third steps of hard decoding can be directly executed based on the ready-made adjoint polynomials in step S30. Such a design not only optimizes the decoding process, but also significantly saves computing resources and achieves the goal of efficient decoding.

[0103] Based on the first embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those in the first embodiment can be referred to the above description, and will not be described in detail later. Figure 3 Step S20 may include steps B10 to B30:

[0104] Step B10, adjusting the voltage according to a preset adjustment amount, and collecting the codeword information reading results under each voltage.

[0105] Step B20, performing XOR calculation on all read results, and determining the bit to be flipped according to the calculation result.

[0106] In this scheme, dynamic voltage is used to perform multiple reads.

[0107] The voltage is adjusted according to the preset adjustment amount. At each different voltage level, the system will collect the corresponding re-reading results. All re-reading results are collected, and the codeword information read for the first time in S10 can also be counted.

[0108] XOR calculation is performed on all read results. XOR calculation is a bit operation. A result of 0 indicates that the bit value is the same under different voltages, while a result of 1 indicates that the bit value has changed, which indicates that the unit where the bit is located may be affected by the adjacent unit. For example, when the adjacent unit is written, the bit value of this unit may change from 0 to 1.

[0109] Furthermore, the bit positions where the calculation results are 1 are screened out, and the corresponding bits are found in the codeword information, which are set as the bits to be flipped, and then the flipping operation is performed on all the bits to be flipped, thereby restoring the correctness of the data.

[0110] It is understandable that by re-reading the data at different voltages and using XOR calculations to detect changes in bit values, the system can more accurately identify bits that are interfered with by adjacent cells or are unstable. This refined error detection mechanism helps reduce bit error rates and improve the overall accuracy of data.

[0111] For example, a preset adjustment amount is set, such as adjusting by 0.1V each time. Then, starting from an initial voltage, such as 2.5V, the voltage is gradually increased according to the preset adjustment amount, and the codeword information in the storage unit is re-read after each increase. In this process, multiple reading results are obtained:

[0112] 2.5V: 10101010

[0113] 2.6V: 10101110

[0114] 2.7V: 10101010

[0115] Next, perform XOR calculation on all read results:

[0116] 10101010⊕10101110⊕10101010=00000100

[0117] The result of the XOR calculation shows that a bit value changes under different voltage levels, that is, changes from 0 to 1 and then back to 0, so the bit is set as the bit to be flipped.

[0118] Step B30, performing a flip operation on the bit to be flipped.

[0119] When performing the flipping operation on the to-be-flipped bit, you can choose to flip all or part of it according to the actual situation:

[0120] According to the hierarchical structure of the storage system, such as page, block, region, etc., a data structure is designed in advance to store decoding records of each level, including detailed information of error bits encountered when performing decoding operations.

[0121] When reading codeword information, the decoding record corresponding to the hierarchical structure where the current codeword information is located is detected.

[0122] If the decoded record is empty, this indicates that no errors have been detected at this level before, and you can choose to flip all the bits to be flipped.

[0123] If the decoding record is not empty, the average number of error bits needs to be obtained from it and used as a screening basis. As for the screening method, random screening can be used, or certain screening conditions can be set to achieve more accurate screening.

[0124] For example, there are currently 10 bits to be flipped, and the average number of error bits in the decoding record is 6, then 6 bits can be randomly selected from the 10 bits to be flipped for subsequent flipping operations.

[0125] Exemplarily, the historical error bit information in the hierarchical structure is recorded in detail in the known decoding record. First, relevant features such as bit position information, bit value, state of surrounding bits and context information need to be extracted for the bits to be flipped and the historical error bits respectively. Subsequently, a correlation analysis method, such as the Pearson correlation coefficient or the Spearman rank correlation coefficient, can be used to calculate the correlation coefficient between each bit to be flipped and the historical error bit. According to the calculated correlation coefficient, a sorting sequence is generated for all bits to be flipped. In this sequence, bits with higher correlation coefficients have higher priority because they have a stronger correlation with the historical error bits. From the sorted bit sequence, a corresponding number of bits are selected for flipping operation according to a set average. For example, the first 6 bits to be flipped in the sorting sequence can be selected for flipping.

[0126] In addition, when sorting, the degree of impact of different failure modes on bit values ​​can also be considered. For example, physical damage usually leads to permanent loss of data, while read disturbance may only be temporary. Therefore, it is necessary to prioritize bits that are prone to major failures. Through a weighted approach, it can be ensured that bits with higher risks are prioritized over bits with lower risks.

[0127] Specifically, different failure modes are pre-set during the design phase, including but not limited to physical damage, read disturbance, charge leakage, programming disturbance, process error, etc. Then, these failure modes are classified according to severity based on evaluation criteria such as impact range, misalignment frequency, and repair difficulty. The results can be divided into different levels such as severe, moderate, and mild. In addition, corresponding weighting strategies are set for different severity levels.

[0128] In this way, in the actual application stage, for a bit to be flipped, the historical error bit information with the highest correlation coefficient can be matched, and then the failure mode of this historical error bit information can be found in the decoding record as the failure mode of the bit to be flipped. Then, the severity of the failure mode is determined, and the corresponding weighting strategy is adopted to perform weighted processing on the correlation coefficient of the bit to be flipped.

[0129] For example, bit A to be flipped is physically damaged and its degree is a serious fault, so its correlation coefficient needs to be increased by 10%. Bit B to be flipped is read disturbance and its degree is a mild fault, so its correlation coefficient needs to be reduced by 20%.

[0130] At this point, all the bits to be flipped can be sorted according to the weighted correlation coefficients, thereby performing effective screening.

[0131] This scheme allows flexible selection of full or partial flipping in the flipping operation according to the error detection situation. By selecting the flipping bits based on the average number of error bits, only some bits can be flipped instead of blindly flipping all the bits to be flipped. This optimization strategy based on historical data can reduce unnecessary flipping and improve decoding efficiency. Among them, the screening method based on data correlation can identify bits that have a strong correlation with historical error bits, and can accurately select the bits to be flipped, reduce the risk of false flipping, and thus improve the accuracy of data recovery.

[0132] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the decoding method of the codeword information of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0133] The present application provides a device for decoding codeword information, the device for decoding codeword information comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the method for decoding codeword information in the first embodiment above.

[0134] Reference below Figure 4 , which shows a schematic diagram of a structure of a decoding device for codeword information suitable for implementing the embodiment of the present application. The decoding device for codeword information in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The decoding device for codeword information shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0135] like Figure 4As shown, the decoding device of the codeword information may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In the RAM 1004, various programs and data required for the operation of the decoding device of the codeword information are also stored. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1003 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1009. The communication device 1009 may allow the decoding device of the codeword information to communicate wirelessly or wired with other devices to exchange data. Although the figure shows a decoding device of the codeword information with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have alternatively.

[0136] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0137] The decoding device of the codeword information provided by the present application adopts the decoding method of the codeword information in the above embodiment, which can solve the technical problem of insufficient decoding ability. Compared with the prior art, the beneficial effects of the decoding device of the codeword information provided by the present application are the same as the beneficial effects of the decoding method of the codeword information provided by the above embodiment, and other technical features in the decoding device of the codeword information are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0138] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0139] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0140] The present application provides a computer-readable storage medium having a computer program stored thereon, and the computer-readable program instructions are used to execute the decoding method of the codeword information in the above embodiment.

[0141] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0142] The computer-readable storage medium may be included in the decoding device for codeword information; or may exist independently without being assembled into the decoding device for codeword information.

[0143] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by a decoding device for codeword information, the decoding device for codeword information: when reading the codeword information, determines the number of error bits in the codeword information; if the number of error bits is greater than the number of correctable errors, re-reads the codeword information and performs a flip operation on the codeword information according to the re-reading result; and hard-decodes the flipping result based on an iterative algorithm to obtain a corresponding decoding result.

[0144] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0145] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0146] The modules involved in the embodiments of the present application may be implemented by software or hardware, wherein the name of the module does not limit the unit itself in some cases.

[0147] The readable storage medium provided by the present application is a computer-readable storage medium, which stores a computer program for executing the decoding method of the above-mentioned codeword information, and can solve the technical problem of insufficient decoding ability. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the decoding method of the codeword information provided by the above-mentioned embodiment, and will not be repeated here.

[0148] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A method for decoding codeword information, characterized in that: The method comprises: When the code word information is read, determining the number of error bits in the code word information; If the number of the error bits is greater than the correctable error number, the code word information is re-read, and the code word information is flipped according to the re-reading result; The flip result is hard-decoded based on the iterative algorithm to obtain the corresponding decoding result.

2. The method according to claim 1, characterized in that When the code word information is read, the step of determining the number of error bits in the code word information comprises: When the code word information is read, a division operation is performed on the code word information based on the generator polynomial to obtain a corresponding adjoint polynomial; The number of error bits is determined according to the syndrome coefficients of the syndrome polynomial.

3. The method according to claim 1, characterized in that The step of re-reading the code word information and flipping the code word information according to the re-reading result includes: Adjust the voltage according to the preset adjustment amount and collect the re-reading results at each voltage; Performing an XOR calculation on all the re-read results, and determining the bit to be flipped in the codeword information according to the calculation result; Perform a flip operation on the bit to be flipped.

4. The method according to claim 3, characterized in that The step of performing a flipping operation on the bit to be flipped comprises: Detecting a decoding record of a hierarchical structure where the codeword information is located; If the decoding record is empty, performing a flip operation on all the bits to be flipped; If the decoding record is not empty, the bits to be flipped are screened according to the average number of error bits in the decoding record, and a flipping operation is performed on the screened bits to be flipped.

5. The method according to claim 4, characterized in that The step of screening the bits to be flipped comprises: Determine a correlation coefficient between the bit to be flipped and a historical error bit in the decoding record; All the bits to be flipped are sorted according to the correlation coefficient to generate a sequence, and the sequence is screened according to the average.

6. The method according to claim 5, characterized in that Before the step of sorting all the bits to be flipped according to the correlation coefficient to generate a sequence and screening the sequence according to the average, the step further includes: Determining the failure mode of the bit to be flipped according to the failure mode of the historical error bit matching the bit to be flipped; The correlation coefficient is weighted according to the severity of the failure mode.

7. The method according to claim 1, characterized in that After the step of determining the number of error bits in the code word information when the code word information is read, the method further includes: If the number of the erroneous bits is less than or equal to the number of correctable errors, the codeword information is decoded based on an iterative algorithm to obtain a corresponding decoding result.

8. The method according to claim 1, characterized in that The step of hard decoding the flip result based on the iterative algorithm to obtain the corresponding decoding result includes: If the number of error bits in the flip result is less than or equal to the correctable error number, hard decoding the flip result based on an iterative algorithm to obtain a corresponding decoding result; After the step of hard decoding the flip result based on the iterative algorithm to obtain the corresponding decoding result, the method further includes: If the number of error bits in the flip result is greater than the number of correctable errors, the flip result is decoded based on a low-density parity check algorithm to obtain a corresponding decoding result.

9. A decoding device for codeword information, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the method for decoding codeword information according to any one of claims 1 to 8.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the method for decoding codeword information according to any one of claims 1 to 8 are implemented.

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