A hub and system with synchronous downlink data transmission and PD fast charging

Abstract

The present application provides a hub with synchronous downlink data transmission and PD fast charging, including a housing, an output port, an access port and a charging port. The charging port consists of a first port and a second port, which are used to connect a functional power supply device and a power input device, respectively. This design enables the hub to support data transmission and power fast charging functions at the same time. The control chip is responsible for identifying and controlling the working status of each circuit. The first control circuit, the second control circuit and the third control circuit are respectively connected to the first port, the second port and the access port to form a complex control loop. The hub is enabled to flexibly adjust the working status of the internal circuit according to the access status of the external device. Integrating data transmission and PD fast charging functions in the same hub meets the user's demand for a multi-functional hub. By designing the first port and the second port, the hub can support multiple types of power input devices, thereby increasing its scope of application.

Description

Technical Field

[0001] The present application relates to a field, and in particular to a hub and system with synchronous downlink data transmission and PD fast charging. Background Art

[0002] With the popularity of electronic devices and the diversification of their functions, users have a growing demand for charging efficiency and data exchange. Especially in mobile office and daily life, devices that can simultaneously meet the needs of fast charging and efficient data transmission have become the new favorites of the market. The USB Type C port has gradually become the standard interface for many high-end electronic devices due to its reversible plug-in convenience and powerful data transmission capabilities. At the same time, the introduction of USB Power Delivery (PD) fast charging technology has greatly shortened the charging time of the device and improved the user experience.

[0003] However, in the existing technical solutions, if a traditional charger is used for charging, although some high-end chargers already support the USB PD fast charging function, which can greatly shorten the charging time, they are often limited to a single charging function and do not have the ability to transmit data. This means that users cannot simultaneously back up, synchronize, or exchange data with other devices during the charging process, which limits the multitasking capabilities of the device. On the other hand, if a USB hub is used to achieve data transmission, although it can effectively expand the data interface and improve data transmission efficiency, most hubs do not support fast charging functions, especially USB PD fast charging, which results in users having to sacrifice charging speed while pursuing efficient data transmission. This is undoubtedly a significant defect for users who rely on fast charging to maintain device endurance.

[0004] Therefore, it is necessary to provide a hub and system whose downstream port of a fast charging circuit can not only transmit USB data, but also perform fast charging through the downstream at the same time. Summary of the invention

[0005] In view of this, it is necessary to provide a hub and system whose downstream port of a fast charging circuit can not only transmit USB data but also perform fast charging through the downstream at the same time, so as to solve the above problems.

[0006] The embodiment of the present application provides a hub with synchronous transmission of downlink data and PD fast charging, comprising: a housing and an output port and an access port arranged on the housing, wherein the output port is connected to the access port, and further comprising:

[0007] a charging port, provided on the housing and connected to the output port, wherein the charging port comprises: a first port and a second port connected to the first port, the first port is externally connected to a functional power supply device, and the second port is used to connect to a power input device;

[0008] A control chip is disposed on a circuit board in the housing and is connected to the output port, the access port and the charging port respectively;

[0009] A control circuit is provided on a circuit board in the housing and connected to the control chip, and the control circuit board includes a first control circuit, a second control circuit and a third control circuit, the first control circuit is connected to the first port, the second control circuit is connected to the second port, and the third control circuit is connected to the access port, wherein the first control circuit and the third control circuit are connected to form a first node, and the first node is connected to the second control circuit;

[0010] Among them, when only a functional power supply device is connected to the first port, the control chip identifies and controls the first control circuit and the third control circuit to be turned on, so that the output port establishes a communication connection with the access port; when the power input device is connected to the second port and the functional power supply device is connected to the first port, the control chip identifies and controls the first control circuit and the third control circuit to be blocked, and turns on the second control circuit, so that the output port establishes a communication connection with the access port and outputs power to the output port.

[0011] In at least one embodiment of the present application, it also includes:

[0012] The step-down chip establishes a protocol communication connection with the control chip. When the power input device is connected to the second port, the control chip identifies the external device connected to the output port and controls the step-down chip to output the first power so as to transmit the first power to the output port.

[0013] In at least one embodiment of the present application, the output port includes:

[0014] The function port is respectively connected to the first port, the second port and the access port, and the function port is used for the control chip to control the first power supply to be output to the function port when the power input device is connected to the second port.

[0015] In at least one embodiment of the present application, the first control circuit includes:

[0016] A first output node connected to the control chip;

[0017] A second output node connected to the first port;

[0018] a first switch connected to the first output node;

[0019] a second switch, connecting the first switch, the second output node and the first node respectively;

[0020] When a functional power supply device is connected to the first port, the control chip controls the first output node to output a high level, the first switch and the second switch are turned on, and the first port outputs power to the first node via the second output node.

[0021] In at least one embodiment of the present application, the second control circuit includes:

[0022] A third output node connected to the second port;

[0023] a fourth output node connected to the third output node;

[0024] a blocking circuit, connected to the third output node, the fourth output node and the first node, and configured to block the first node from outputting power to the fourth output node when the second control circuit is turned on;

[0025] a third switch, connecting the third output node and the fourth output node;

[0026] a fourth switch connected to the third output node;

[0027] When a power input device is connected to the second port, the third output node outputs a high level to turn on the third switch and the fourth switch, the blocking circuit is turned off, and the second port outputs power through the third output node to the fourth output node.

[0028] In at least one embodiment of the present application, the third control circuit includes:

[0029] A fifth output node connected to the control chip;

[0030] a sixth output node, connected to the access port;

[0031] a fifth switch connected to the fifth output node;

[0032] a sixth switch, connecting the fifth switch, the fifth output node and the first node respectively;

[0033] When the access port is connected to the first device, the control chip controls the fifth output node to output a high level, and the fifth switch and the sixth switch are turned on, so that the access port is connected to the first node.

[0034] In at least one embodiment of the present application, the blocking circuit includes:

[0035] a seventh switch connected to the third output node;

[0036] a first blocking switch group, connected to the seventh switch, the first blocking switch group comprising: an eighth switch and a ninth switch connected to the eighth switch, the seventh switch being connected between the eighth switch and the ninth switch;

[0037] a second blocking switch group, respectively connecting the first blocking switch group, the first node and the fourth output node, the second blocking switch group comprising: a tenth switch and an eleventh switch connected to the tenth switch, the tenth switch being connected to the eighth switch and the first node, and the eleventh switch being connected to the ninth switch and the fourth output node;

[0038] When the power input device is connected to the second port, the seventh switch is turned on to turn off the first blocking switch group and the second blocking switch group to cut off the connection between the first node and the second control circuit.

[0039] In at least one embodiment of the present application, the output port further includes:

[0040] A plurality of connection ports, each of the connection ports being connected to the control chip;

[0041] The plurality of connection ports include: a first downstream end, a second downstream end, and a third downstream end;

[0042] The transmission speed of the first downstream end is greater than the transmission speed of the second downstream end, and the transmission speed of the second downstream end is greater than the transmission speed of the third downstream end.

[0043] In at least one embodiment of the present application, the hub further includes:

[0044] A plurality of indication signals, each of the indication signals is connected to a corresponding functional port and a connecting port, and is connected to the control chip.

[0045] The present application provides a hub system with synchronous downlink data transmission and PD fast charging, including any one of the hubs with synchronous downlink data transmission and PD fast charging.

[0046] The above-mentioned hub with synchronous downlink data transmission and PD fast charging is designed to include a housing, an output port, an access port and a charging port. The charging port consists of a first port and a second port, which are used to connect a functional power supply device and a power input device, respectively. This design enables the hub to support data transmission and power fast charging functions at the same time. As the core of the hub, the control chip is responsible for identifying and controlling the working status of each circuit. The first control circuit, the second control circuit and the third control circuit are respectively connected to the first port, the second port and the access port to form a complex control loop. This design enables the hub to flexibly adjust the working status of the internal circuit according to the access status of the external device. Integrating data transmission and PD fast charging functions in the same hub meets the user's demand for a multi-functional hub. By designing the first port and the second port, the hub can support various types of power input devices, thereby increasing its scope of application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 This is a structural diagram of a hub with synchronous downlink data transmission and PD fast charging in an embodiment of the present application.

[0048] Figure 2 is a circuit diagram of the first control loop and the third control loop in the embodiment of the present application.

[0049] Figure 3 FIG. 4 is a circuit diagram of a second control loop of an embodiment.

[0050] Figure 4 This is the structural block diagram of the control chip and control loop.

[0051] Main component symbols

[0052] 100. A hub with synchronous transmission of downstream data and PD fast charging; 10. Shell; 20. Output port; 21. Function port; 22. Connection port; 221. First downstream end; 222. Second downstream end; 223. Third downstream end; 30. Access port; 40. Charging port; 41. First port; 42. Second port; 50. Control chip; 60. Control loop; 61. First control circuit; 611. First output node; 612. Second output node; 62. Second control circuit; 621. Third output node; 622. Fourth output node; 623. Blocking circuit; 6231. First blocking switch group; 6232. Second blocking switch group; 63. Third control circuit; 631. Fifth output node; 632. Sixth output node; 64. First node; 70. Step-down chip; 80. Indication signal;

[0053] Q15, first switch; Q13, second switch; Q7, third switch; Q10, fourth switch; Q14, fifth switch; Q12, sixth switch; Q11, seventh switch; Q9, eighth switch; Q8, ninth switch; Q5, tenth switch; Q6, eleventh switch. DETAILED DESCRIPTION

[0054] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0055] It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a central component at the same time. When a component is considered to be "located on" another component, it may be directly located on the other component or there may be a central component at the same time. The terms "top", "bottom", "upper", "lower", "left", "right", "front", "back", and similar expressions used herein are for illustrative purposes only.

[0056] The embodiment of the present application provides a hub with synchronous transmission of downlink data and PD fast charging, comprising: a housing and an output port and an access port arranged on the housing, wherein the output port is connected to the access port, and further comprising:

[0057] a charging port, provided on the housing and connected to the output port, wherein the charging port comprises: a first port and a second port connected to the first port, the first port is externally connected to a functional power supply device, and the second port is used to connect to a power input device;

[0058] A control chip is disposed on a circuit board in the housing and is connected to the output port, the access port and the charging port respectively;

[0059] A control circuit is provided on a circuit board in the housing and connected to the control chip, and the control circuit board includes a first control circuit, a second control circuit and a third control circuit, the first control circuit is connected to the first port, the second control circuit is connected to the second port, and the third control circuit is connected to the access port, wherein the first control circuit and the third control circuit are connected to form a first node, and the first node is connected to the second control circuit;

[0060] Among them, when only a functional power supply device is connected to the first port, the control chip identifies and controls the first control circuit and the third control circuit to be turned on, so that the output port establishes a communication connection with the access port; when the power input device is connected to the second port and the functional power supply device is connected to the first port, the control chip identifies and controls the first control circuit and the third control circuit to be blocked, and turns on the second control circuit, so that the output port establishes a communication connection with the access port and outputs power to the output port.

[0061] The above-mentioned hub with synchronous downlink data transmission and PD fast charging is designed to include a housing, an output port, an access port and a charging port. The charging port consists of a first port and a second port, which are used to connect a functional power supply device and a power input device, respectively. This design enables the hub to support data transmission and power fast charging functions at the same time. As the core of the hub, the control chip is responsible for identifying and controlling the working status of each circuit. The first control circuit, the second control circuit and the third control circuit are respectively connected to the first port, the second port and the access port to form a complex control loop. This design enables the hub to flexibly adjust the working status of the internal circuit according to the access status of the external device. Integrating data transmission and PD fast charging functions in the same hub meets the user's demand for a multi-functional hub. By designing the first port and the second port, the hub can support various types of power input devices, thereby increasing its scope of application.

[0062] In conjunction with the accompanying drawings Figure 1-Figure 4 , some embodiments of the present application are described in detail. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0063] The present application provides a hub 100 with synchronous transmission of downlink data and PD fast charging, comprising: a housing 10 and an output port 20 and an access port 30 provided on the housing 10, wherein the output port 20 is connected to the access port 30, and further comprising:

[0064] A charging port 40 is provided on the housing 10 and connected to the output port 20, wherein the charging port 40 comprises: a first port 41 and a second port 42 connected to the first port 41, the first port 41 is connected to an external functional power supply device, and the second port 42 is used to connect a power input device;

[0065] A control chip 50 is disposed on a circuit board in the housing 10 and is respectively connected to the output port 20, the access port 30 and the charging port 40;

[0066] A control circuit 60 is provided on a circuit board in the housing 10 and connected to the control chip 50, and the control circuit board includes a first control circuit 61, a second control circuit 62 and a third control circuit 63, wherein the first control circuit 61 is connected to the first port 41, the second control circuit 62 is connected to the second port 42, and the third control circuit 63 is connected to the access port 30, wherein the first control circuit 61 and the third control circuit 63 are connected to form a first node 64, and the first node 64 is connected to the second control circuit 62;

[0067] Among them, when only a functional power supply device is connected to the first port 41, the control chip 50 identifies and controls the first control circuit 61 and the third control circuit 63 to be turned on, so that the output port 20 establishes a communication connection with the access port 30; when the power input device is connected to the second port 42 and the functional power supply device is connected to the first port 41, the control chip 50 identifies and controls the first control circuit 61 and the third control circuit 63 to be blocked, and turns on the second control circuit 62, so that the output port 20 establishes a communication connection with the access port 30 and outputs power to the output port 20.

[0068] Specifically, the housing 10 is used to protect the internal circuit structure from external influences. The output port 20 and the access port 30 are arranged on the housing 10. The output port 20 is a downstream port for supplying power to external devices and transmitting data. The access port 30 is a UFP USB Type C Plug port for connecting to an upstream device (such as a computer) for data transmission and charging. When an upstream device such as a mobile phone, tablet or computer with Power Delivery function is connected to the access port 30, the hub immediately communicates with the upstream device so that the upstream device can automatically recognize the product.

[0069] The first port 41 is a USB Type C PD100W In input port, which is used to connect a power supply device that supports PD fast charging, and a power adapter with Power Delivery function connected to the input port USB Type C PD100W In. The second port 42 is a DC In input port, which is used for a power supply input device connected via DC In, that is, a DC power adapter.

[0070] The control chip 50 is arranged on the circuit board inside the housing 10, monitors and identifies whether there is a device connected to the output downstream port, and controls the connection or blocking of each circuit in turn according to the connection of the charging port 40 and the identified device, so that the output port 20 can perform data transmission and fast charging.

[0071] After the access port 30, the first port 41 or the second port 42 is connected to a device, it can provide power supply for the built-in circuit mainboard of the present application. After this power supply is loaded to each port and subjected to voltage processing, the main power supply voltage provided to the circuit mainboard is 5V.

[0072] When the first port 41 and the second port 42 are connected to the device at the same time, the control chip 50 preferentially selects the second port 42 as the main power energy source, disconnects the first control circuit 61 and the third control circuit 63 in the control loop 60, connects the second control circuit 62, and supplies power energy to the power conversion unit of the second port 42. The power conversion unit can convert the input power into power suitable for this product and the downstream port, which serves as the power supply for this product and the downstream port of this product.

[0073] In a specific embodiment, it also includes: a step-down chip 70, which establishes a protocol communication connection with the control chip 50. When the power input device is connected to the second port 42, the control chip 50 identifies the external device connected to the output port 20, and controls the step-down chip 70 to output the first power so as to transmit the first power to the output port 20.

[0074] Specifically, the buck chip 70 is connected to the control chip 50 through the I2C bus and performs data transmission. It serves as a communication bridge between the control chip 50 and the buck chip 70 to achieve fast and reliable data transmission, including control instructions and status feedback. The buck chip 70 can reduce the input high voltage (such as the voltage input from the DC power adapter) to a low voltage suitable for external devices. In the application embodiment, the buck chip 70 is TMI3455 and the control chip 50 is RTS5481.

[0075] The control chip 50RTS5481 uses its two-wire communication protocol I2C RTS5481_SDA and RTS5481_SCL to establish a connection with the DC / DC buck chip 70TMI3455 two-wire communication protocol I2C SDA_TMI3455 and SCL_TMI3455 and perform I2C protocol communication. The control chip 50RTS5481 adjusts and controls TMI3455 in real time to output the first power supply to the output port 20 according to the PD protocol to meet the power supply requirements of the external device. The first power supply is a voltage and current suitable for the output port 20. Provide PD fast charging service to the Device connected to this output port 20 and having the PowerDelivery function.

[0076] In summary, the user connects the DC power adapter to the second port 42 to provide power to the system. The control chip 50 identifies the type of the external device or the required voltage through the internal control unit and the external detection circuit. Based on the identification result, the control chip 50 sends an instruction to adjust the output voltage to the buck chip 70 through the I2C bus. After receiving the instruction, the buck chip 70 adjusts its output voltage to a level suitable for the external device. The adjusted voltage is transmitted to the external device through the output port 20 to complete the power supply process.

[0077] In a specific embodiment, the output port 20 includes: a functional port 21, which is respectively connected to the first port 41, the second port 42 and the access port 30, and the functional port 21 is used for controlling the first power supply to be output to the functional port 21 by the control chip 50 when the power input device is connected to the second port 42.

[0081] Specifically, the functional port 21 is a port in the output port 20 that can provide power and data transmission functions to the connected device, can support forward and reverse insertion, provides a bidirectional data transmission rate of up to 10Gbps, supports the power transmission protocol, and can dynamically adjust the output voltage and current according to the needs of the connected device to achieve efficient charging.

[0083] In a specific embodiment, the first control circuit 61 includes: a first output node 611 connected to the control chip 50; a second output node 612 connected to the first port 41; a first switch Q15 connected to the first output node 611; and a second switch Q13 respectively connecting the first switch Q15, the second output node 612 and the first node 64.

[0084] When a functional power supply device is connected to the first port 41 , the control chip 50 controls the first output node 611 to output a high level, the first switch Q15 and the second switch Q13 are turned on, and the first port 41 outputs power through the second output node 612 to the first node 64 .

[0085] Specifically, the first output node 611 is used as a node between the control chip 50 and the first control circuit 61, and is used to identify the connected device at the control chip 50 and receive the control signal sent by the control chip 50, which is usually a high level or low level signal to indicate whether the power output is allowed. The second output node 612 is a power input node, which is used to output the power of the functional power device on the first port 41, that is, the PD power adapter to the first control circuit 61. In the embodiment of the present application, the first switch Q15 and the second switch Q13 are a MOS tube switch, wherein the first switch Q15 is an NMOS tube, and its gate is connected to the first output node 611, so that when the first output node 611 outputs a high level, the first switch Q15 is turned on. The second switch Q13 is a P-channel MOSFET tube.

[0086] Further, after the control chip 50RTS5481 recognizes that the PD power adapter is connected to the first port 41, it communicates with the PD power adapter to negotiate and confirm the PD output voltage and current parameters that can be provided, and generates these voltage and current parameters on the second output node 612. The control chip 50RTS5481 controls its GPIO to output a high level on the first output node 611, turning on the first switch Q15, and the drain of the first switch Q15 outputs a low level to control the conduction of the second switch Q13. Thus, the voltage and current output by the PD power adapter are generated on the first node 64, and the electric energy of the PD power adapter is officially output to the circuit.

[0087] When the control chip 50RTS5481 does not recognize that the PD power adapter is connected to the first port 41, the control chip 50 outputs a low level, thereby blocking the voltage and current on the first node 64, and preventing the voltage and current of the first node 64 from flowing back to the second output node 612 of the PD power adapter.

[0088] In a specific embodiment, the second control circuit 62 includes: a third output node 621 connected to the second port 42;

[0089] The fourth output node 622 is connected to the third output node 621; the blocking circuit 623 is connected to the third output node 621, the fourth output node 622 and the first node 64, and is used to block the first node 64 from outputting power to the fourth output node 622 when the second control circuit 62 is turned on; the third switch Q7 is connected to the third output node 621 and the fourth output node 622; the fourth switch Q10 is connected to the third output node 621.

[0090] When the power input device is connected to the second port 42, the third output node 621 outputs a high level to turn on the third switch Q7 and the fourth switch Q10, and the blocking circuit 623 is turned off, and the second port 42 outputs power through the third output node 621 to the fourth output node 622.

[0091] Specifically, the third output node 621 is a key point for signal transmission and power distribution, which is directly connected to the second port 42 and connected to the DC power adapter. The third switch Q7 and the fourth switch Q10 are MOS tube switches, wherein the fourth switch Q10 is an NMOS tube, and its gate is connected to the third output node 621, so that when the third output node 621 outputs a high level, the fourth switch Q10 is turned on. The third switch Q7 is a P-channel MOSFET tube.

[0092] Further, when the control chip 50 recognizes that the DC power adapter is connected to the second port 42, a high-level signal is generated on the fourth switch Q10, so that the fourth switch Q10 is turned on and the voltage of the drain of the fourth switch Q10 is clamped to 0, so that the third switch Q7 is turned on, and the DC power adapter is effectively connected to the circuit, and a voltage and current are generated on the fourth output node 622, and the electric energy is output to the circuit to provide the main power supply of the system motherboard with a voltage of 5V. In addition, when connected to the second port 42, the output high-level signal turns off the blocking circuit 623, blocks the voltage and current generated on the first node 64 from the PD power adapter or the upstream device, thereby preventing the voltage generated on the first node 64 from the PD power adapter or the upstream device from generating a voltage difference with the voltage generated on the fourth output node 622, thereby burning out the internal components and circuits, and causing the product to fail.

[0093] Furthermore, after the DC power adapter is connected, the voltage output from the DC power adapter is generated on the third output node 621 and given to the DC / DC buck chip 70TMI3455. The control chip 50 uses its two-wire communication protocol I2CRTS5481_SDA and RTS5481_SCL to establish a connection with the two-wire communication protocol I2C SDA_TMI3455 and SCL_TMI3455 of the buck chip 70 and perform I2C protocol communication. The control chip 50 adjusts and controls the buck chip 70 in real time to output the appropriate voltage and current to the function port according to the PD protocol.

[0094] 21. Give the connection to this functional port

[0095] Devices with Power Delivery function on 21 can provide PD fast charging service.

[0096] In a specific embodiment, the third control circuit 63 includes: a fifth output node 631, connected to the control chip 50; a sixth output node 632, connected to the access port 30; a fifth switch Q14, connected to the fifth output node 631; and a sixth switch Q12, respectively connecting the fifth switch Q14, the fifth output node 631 and the first node 64.

[0097] When the access port 30 is connected to the first device, the control chip 50 controls the fifth output node 631 to output a high level, and the fifth switch Q14 and the sixth switch Q12 are turned on, so that the access port 30 is connected to the first node 64 .

[0098] Specifically, the fifth output node 631 is used as a node between the control chip 50 and the third control circuit 63, and is used to identify the connected device at the control chip 50 and receive the control signal sent by the control chip 50, which is usually a high level or low level signal to indicate whether the power output is allowed. The sixth output node 632 is a power input node, which is used to output the power of the upstream device on the access port 30 to the second control circuit 62. In the embodiment of the present application, the fifth switch Q14 and the sixth switch Q12 are a MOS tube switch, wherein the fifth switch Q14 is an NMOS tube, and its gate is connected to the fifth output node 631, so that when the fifth output node 631 outputs a high level, the fifth switch Q14 is turned on. The sixth switch Q12 is a P-channel MOSFET tube.

[0099] Furthermore, after the control chip 50RTS5481 recognizes that an upstream device such as a mobile phone, tablet or computer with the Power Delivery function is inserted into the access port 30, it communicates with the upstream device to negotiate and confirm acceptable PD input voltage and current parameters, and generates these voltage and current parameters on the sixth output node 632. The control chip 50 controls its GPIO pin to output a high level on the fifth output node 631, turning on the fifth switch Q14, and the drain of the fifth switch Q14 outputs a low level to control the conduction of the sixth switch Q12. Thus, the upstream device is officially connected to the circuit.

[0100] Furthermore, after the main control chip 50 negotiates the voltage and current parameters of PD charging with the connected PD power adapter and the upstream device, the control chip 50 controls its GPIO pins to output high levels at the fifth output node 631 and the first output node 611, respectively, so that the fifth switch Q14 and the first switch Q15 are turned on, and the drains of the fifth switch Q14 and the first switch Q15 are output low levels to control the conduction of the sixth switch Q12 and the second switch Q13. Thus, the power of the PD power adapter at the second output node 612 is output to the sixth output node 632 of the upstream device through the sixth switch Q12 and the second switch Q13, so that the PD power adapter can charge the PD of the upstream device.

[0101] In a specific embodiment, the blocking circuit 623 includes: a seventh switch Q11, connected to the third output node 621; a first blocking switch group 6231, connected to the seventh switch Q11, the first blocking switch group 6231 includes: an eighth switch Q9 and a ninth switch Q8 connected to the eighth switch Q9, the seventh switch Q11 is connected between the eighth switch Q9 and the ninth switch Q8; a second blocking switch group 6232, respectively connecting the first blocking switch group 6231, the first node 64 and the fourth output node 622, the second blocking switch group 6232 includes: a tenth switch Q5 and an eleventh switch Q6 connected to the tenth switch Q5, the tenth switch Q5 is connected to the eighth switch Q9 and the first node 64, the eleventh switch Q6 and the ninth switch Q8 are connected to the fourth output node 622.

[0102] When the power input device is connected to the second port 42, the seventh switch Q11 is turned on to turn off the first blocking switch group 6231 and the second blocking switch group 6232, so as to cut off the connection between the first node 64 and the second control circuit 62. 623, blocking circuit 623; Q11, seventh switch Q11; 6231, first blocking switch group 6231; Q9, eighth switch Q9; Q8, ninth switch Q8; 6232, second blocking switch group 6232; Q5, tenth switch Q5; Q6, eleventh switch Q6;

[0103] Specifically, the seventh switch Q11, the eighth switch Q9 and the ninth switch Q8 are all MOS switches. The tenth switch Q5 and the eleventh switch Q6 are MOSFET tubes. The gate of the seventh switch Q11 is connected to the third output node 621, so that when the third output node 621 outputs a high level, the seventh switch Q11 is turned on.

[0104] Furthermore, after the DC power adapter is connected to the second port 42, a high level is generated at the drain of the seventh switch Q11, turning on the seventh switch Q11 and clamping the voltage of the drain of the seventh switch Q11 to 0, forcing the eighth switch Q9 and the ninth switch Q8 to be turned off, thereby turning off the tenth switch Q5 and the eleventh switch Q6, blocking the voltage and current generated by the PD power adapter or the upstream device at the first node 64. This prevents the voltage generated by the PD power adapter or the upstream device at the first node 64 from being generated by the voltage generated by the DC power adapter at the fourth output node 622, which will generate a huge current due to the voltage difference between the two nodes, thereby burning out the internal devices and circuits, causing the product to fail.

[0105] In a specific embodiment, the output port 20 further includes: a plurality of connection ports 22, each of which is connected to the control chip 50; the plurality of connection ports 22 include: a first downstream end 221, a second downstream end 222, and a third downstream end 223, wherein the transmission speed of the first downstream end 221 is greater than the transmission speed of the second downstream end 222, and the transmission speed of the second downstream end 222 is greater than the transmission speed of the third downstream end 223.

[0106] Specifically, multiple connection ports 22 can be connected to downstream devices and support bidirectional data transmission. In the embodiment of the present application, the number of the first downstream ports 221 is 2, and supports bidirectional data transmission at a speed of USB3.2 Gen210Gbps10Gbps; the number of the second downstream ports 222 is 3, and supports bidirectional data transmission at a speed of USB3.2 Gen15Gbps; the number of the third downstream ports 223 is 1, and only supports bidirectional data transmission at a speed of USB2.0480Mbps.

[0107] In a specific embodiment, the hub further includes: a plurality of indication signals 80, each of which corresponds to a connection to one of the functional ports.

[0108] 21 and a connecting port 22 , and connected to the control chip 50 .

[0109] Specifically, the indication signal 80 is an LED indicator light, and the control chip 50 can monitor and identify the multiple connection ports 22 and the functional ports.

[0110] 21, ensure that each port has an independent indicator light to indicate the status, and achieve one-to-one accurate mapping. If a device is connected to a downstream port, the control chip 50 will light up the LED indicator light on the corresponding downstream port, otherwise it will be turned off. The indicator light display can be updated in real time according to the port status, which improves the response speed and accuracy of the system.

[0111] The present application provides a system 100 with synchronous downlink data transmission and PD fast charging hub, including a system with synchronous downlink data transmission and PD fast charging hub as described in any one of the items.

[0112] The specific implementation methods are described above and will not be described in detail here.

[0113] By this, a hub 100 with synchronous transmission of downlink data and PD fast charging is provided above. The hub includes a housing 10, an output port 20, an access port 30 and a charging port 40 by design. The charging port 40 is composed of a first port 41 and a second port 42, which are used to connect functional power devices and power input devices respectively. This design enables the hub to support data transmission and power fast charging functions at the same time. The control chip 50, as the core of the hub, is responsible for identifying and controlling the working status of each circuit. The first control circuit 61, the second control circuit 62 and the third control circuit 63 are respectively connected to the first port 41, the second port 42 and the access port 30 to form a complex control loop 60. This design enables the hub to flexibly adjust the working status of the internal circuit according to the access status of the external device. Integrating data transmission and PD fast charging functions in the same hub meets the user's demand for a multi-functional hub. By designing the first port 41 and the second port 42, the hub can support various types of power input devices, thereby increasing its scope of application.

[0114] The above is only an implementation method of the present application. It should be pointed out that a person skilled in the art can make improvements without departing from the inventive concept of the present application, but these improvements are within the scope of protection of the present application.

Claims

1. A hub with synchronous downlink data transmission and PD fast charging, comprising: A housing and an output port and an access port provided on the housing, wherein the output port is connected to the access port, characterized in that it further comprises: a charging port, provided on the housing and connected to the output port, wherein the charging port comprises: a first port and a second port connected to the first port, the first port is externally connected to a functional power supply device, and the second port is used to connect to a power input device; A control chip is disposed on a circuit board in the housing and is connected to the output port, the access port and the charging port respectively; A control circuit is provided on a circuit board in the housing and connected to the control chip, and the control circuit board includes a first control circuit, a second control circuit and a third control circuit, the first control circuit is connected to the first port, the second control circuit is connected to the second port, and the third control circuit is connected to the access port, wherein the first control circuit and the third control circuit are connected to form a first node, and the first node is connected to the second control circuit; Among them, when only a functional power supply device is connected to the first port, the control chip identifies and controls the first control circuit and the third control circuit to be turned on, so that the output port establishes a communication connection with the access port; when the power input device is connected to the second port and the functional power supply device is connected to the first port, the control chip identifies and controls the first control circuit and the third control circuit to be blocked, and turns on the second control circuit, so that the output port establishes a communication connection with the access port and outputs power to the output port.

2. A hub with synchronous downlink data transmission and PD fast charging according to claim 1, characterized in that: Also includes: The step-down chip establishes a protocol communication connection with the control chip. When the power input device is connected to the second port, the control chip identifies the external device connected to the output port and controls the step-down chip to output the first power so as to transmit the first power to the output port.

3. A hub with synchronous downlink data transmission and PD fast charging according to claim 2, characterized in that: The output port comprises: A functional port is respectively connected to the first port, the second port and the access port, and the functional port is used for the control chip to control the first power supply to be output to the functional port when a power input device is connected to the second port.

4. The hub with synchronous downlink data transmission and PD fast charging according to claim 1, characterized in that: The first control circuit comprises: A first output node connected to the control chip; A second output node connected to the first port; a first switch connected to the first output node; a second switch, connecting the first switch, the second output node and the first node respectively; When a functional power supply device is connected to the first port, the control chip controls the first output node to output a high level, the first switch and the second switch are turned on, and the first port outputs power to the first node via the second output node.

5. The hub with synchronous downlink data transmission and PD fast charging according to claim 1, characterized in that: The second control circuit comprises: A third output node connected to the second port; a fourth output node connected to the third output node; a blocking circuit, connected to the third output node, the fourth output node and the first node, and configured to block the first node from outputting power to the fourth output node when the second control circuit is turned on; a third switch, connecting the third output node and the fourth output node; a fourth switch connected to the third output node; When a power input device is connected to the second port, the third output node outputs a high level to turn on the third switch and the fourth switch, the blocking circuit is turned off, and the second port outputs power through the third output node to the fourth output node.

6. The hub with synchronous downlink data transmission and PD fast charging according to claim 1, characterized in that: The third control circuit comprises: A fifth output node connected to the control chip; a sixth output node, connected to the access port; a fifth switch connected to the fifth output node; a sixth switch, connecting the fifth switch, the fifth output node and the first node respectively; When the access port is connected to the first device, the control chip controls the fifth output node to output a high level, and the fifth switch and the sixth switch are turned on, so that the access port is connected to the first node.

7. The hub with synchronous downlink data transmission and PD fast charging according to claim 5, characterized in that: The blocking circuit comprises: a seventh switch connected to the third output node; a first blocking switch group, connected to the seventh switch, the first blocking switch group comprising: an eighth switch and a ninth switch connected to the eighth switch, the seventh switch being connected between the eighth switch and the ninth switch; a second blocking switch group, respectively connecting the first blocking switch group, the first node and the fourth output node, the second blocking switch group comprising: a tenth switch and an eleventh switch connected to the tenth switch, the tenth switch being connected to the eighth switch and the first node, and the eleventh switch being connected to the ninth switch and the fourth output node; When the power input device is connected to the second port, the seventh switch is turned on to turn off the first blocking switch group and the second blocking switch group to cut off the connection between the first node and the second control circuit.

8. The hub with synchronous downlink data transmission and PD fast charging according to claim 1, characterized in that: The output port also includes: A plurality of connection ports, each of the connection ports being connected to the control chip; The plurality of connection ports include: a first downstream end, a second downstream end, and a third downstream end; The transmission speed of the first downstream end is greater than the transmission speed of the second downstream end, and the transmission speed of the second downstream end is greater than the transmission speed of the third downstream end.

9. The hub with synchronous downlink data transmission and PD fast charging according to claim 3, characterized in that: The hub also includes: A plurality of indication signals, each of the indication signals is connected to a corresponding functional port and a connecting port, and is connected to the control chip.

10. A hub system with synchronous downlink data transmission and PD fast charging, characterized in that: It includes a hub with synchronous downlink data transmission and PD fast charging as described in any one of claims 1-9.

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