Clock synchronization circuit

Abstract

The invention relates to a clock synchronization circuit. An apparatus includes a communication interface, a command processing circuit (524), a clock synchronization circuit (522), and a controllable clock source (520). The command processing circuit (524) has a command input, a reference frequency output, and a reference phase output. The command input is coupled to the communication interface. The clock synchronization circuit (522) has a reference frequency input, a reference phase input, and a frequency control output. The reference frequency output is coupled to the reference frequency input, and the reference phase input is coupled to the reference phase output. The clock synchronization circuit (522) includes a frequency synchronization circuit (526) and a phase synchronization circuit (528). The controllable clock source (520) has a frequency control input and a clock output. The frequency control input is coupled to the frequency control output.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 588,012, filed on October 5, 2023, entitled “Clock Synchronization Using Frequency and Phase Correction,” which is hereby incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to circuits and, more particularly, to clock synchronization circuits. Background Art

[0004] Many circuits include oscillators to provide clock signals. In a system including multiple oscillators, the clock signals generated by the oscillators may have mismatches in phase and / or frequency, which may affect the operation of the system. Summary of the invention

[0005] In one example, an apparatus includes a clock source, a counter, a command generation circuit, and a communication interface. The clock source has a clock output. The counter has a counter clock input and a count output. The clock output is coupled to the counter clock input. The command generation circuit has a frequency input, a phase input, and a command output. The frequency input is coupled to the clock output, and the phase input is coupled to the count output. The communication interface is coupled to the command output.

[0006] In another example, an apparatus includes a communication interface, a command processing circuit, a clock synchronization circuit, and a controllable clock source. The command processing circuit has a command input, a reference frequency output, and a reference phase output. The command input is coupled to the communication interface. The clock synchronization circuit has a reference frequency input, a reference phase input, and a frequency control output. The reference frequency output is coupled to the reference frequency input, and the reference phase input is coupled to the reference phase output. The clock synchronization circuit includes a frequency synchronization circuit and a phase synchronization circuit. The controllable clock source has a frequency control input and a clock output. The frequency control input is coupled to the frequency control output.

[0007] In another example, an integrated circuit includes a communication interface, a controllable clock source, a counter, a command generation circuit, a command processing circuit, and a clock synchronization circuit. The controllable clock source has a frequency control input and a clock output. The counter has a clock input and a count output. The clock input is coupled to the clock output. The command generation circuit has a frequency input, a phase input, and a command output. The frequency input is coupled to the clock output, the phase input is coupled to the count output, and the command output is coupled to the communication interface. The command processing circuit has a command input, a reference phase output, and a reference frequency output. The command input is coupled to the communication interface. The clock synchronization circuit has a reference phase input, a reference frequency input, and a frequency control output. The reference phase input is coupled to the reference phase output. The reference frequency output is coupled to the reference frequency input. The frequency control output is coupled to the frequency control input. The clock synchronization circuit includes a frequency synchronization circuit and a phase synchronization circuit.

[0008] In another example, a system includes a device under test (DUT) monitoring device, a first measurement device, and a second measurement device. The DUT monitoring device includes a stimulus generation circuit, an impedance spectroscopy circuit, and a current sensing circuit. The stimulus generation circuit has a stimulus output. The impedance spectroscopy circuit has a first spectroscopy input, a second spectroscopy input, and an impedance spectroscopy input. The current sensing circuit has a current sensing output. The first measurement device includes a synchronization command processing circuit, a clock synchronization circuit, a controllable clock source, a first sampling circuit, and a first processing circuit. The synchronization command processing circuit has a command input. The clock synchronization circuit is coupled to the synchronization command processing circuit. The clock synchronization circuit has a frequency control output. The controllable clock source has a frequency control input and a first clock output. The frequency control input is coupled to the frequency control output. The first sampling circuit has a DUT input, a first sample output, and a first clock input. The first clock input is coupled to the first clock output. The first sampling circuit is configured to receive a voltage measurement signal at the DUT input and provide a sample of the voltage measurement signal at the first sample output. The first processing circuit has a first processing input and a first processing output. The first processing input is coupled to the first sample output. The first processing output is coupled to the first spectral method input. The first processing circuit is configured to provide a first signal representing a spectral component of the voltage measurement signal at the first processing output. The second measurement device includes a reference clock source, a counter, a synchronization command generation circuit, a second sampling circuit, and a second processing circuit. The reference clock source has a reference clock output. The counter has a second clock input and a count output. The second clock input is coupled to the reference clock output. The synchronization command generation circuit has a frequency input, a phase input, and a command output. The frequency input is coupled to the reference clock output, the phase input is coupled to the count output, and the command output is coupled to the command input. The second sampling circuit has a current sensing input, a second sample output, and a third clock input. The third clock input is coupled to the reference clock output, and the current sensing input is coupled to the current sensing output. The second sampling circuit is configured to receive the current measurement signal at the current sensing input and provide a sample of the current measurement signal at the second sample output. The second processing circuit has a second processing input and a second processing output. The second processing input is coupled to the second sample output, and the second processing output is coupled to the second spectral method input. The second processing circuit is configured to provide a second signal representing a spectral component of the current measurement signal at the second processing output.

[0009] In another example, a method includes generating a reference clock signal by a first device, and providing a reference count value by the first device based on counting cycles of the reference clock signal. The method also includes providing a divided clock signal by the first device based on dividing the reference clock signal, providing a first command including the divided clock signal by the first device, and providing a second command including the reference count value by the first device. The method further includes receiving the first command and the second command by a second device, and generating a target clock signal by the second device. The method further includes determining a target count value based on the target clock signal by the second device, and adjusting a frequency and a phase of the target clock signal by the second device based on the divided clock signal and a difference between the reference count value and the target count value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of an example system for monitoring the status of a device under test (DUT).

[0011] Figure 2 and 3 is a block diagram of a system including devices coupled to each other for communicating commands.

[0012] Figure 4 is a timing diagram showing example timing of reference and target clocks in the system.

[0013] Figure 5 is a block diagram of an example system that provides clock synchronization via command transmission.

[0014] Figure 6 is a block diagram of example circuitry for a target device providing clock synchronization based on commands received from a reference device.

[0015] Figure 7 is a block diagram of an example integrated circuit that includes battery monitoring circuitry and circuitry for clock synchronization via a communications interface.

[0016] Figure 8 is a flow chart of an example method of performing clock synchronization via a communication interface.

[0017] Fig. 9 is a flow chart of an example method of generating a synchronization command in a reference device.

[0018] Fig.10 is a flow chart of an example method of phase synchronization in a target device.

[0019] Fig.11 is a timing diagram showing frequency synchronous communication and phase synchronous communication between a reference device and a target device.

[0020] Fig. 12A ,12B and 12C is applicable to Figure 5 Schematic diagram of frequency synchronization commands and phase synchronization commands for a system.

[0021] Fig.13 is a graphical representation of example synchronization timing errors with and without randomization of frequency synchronization commands.

[0022] Fig.14 is a graphical representation of example synchronization timing errors with and without a phase synchronization command.

[0023] Fig.15 is a flow chart of an example method of clock synchronization using frequency synchronization and phase synchronization. DETAILED DESCRIPTION

[0024] Figure 1 1 is a block diagram of an example system 100 for monitoring the state of a DUT. A DUT may be a target device analyzed in the frequency domain using a spectroscopy method such as impedance spectroscopy. Examples of a DUT may include a charge storage device (e.g., a battery, a capacitor, a supercapacitor, etc.), a motor, a sensor, etc. Figure 1 In the example shown, the system 100 includes a battery pack 102 as a DUT. The battery pack 102 contains a plurality of batteries connected in series, such as battery 104. The battery pack 102 can power a vehicle (e.g., an electric or hybrid vehicle), a power tool, or other battery-powered device. In other examples, the system 100 can include other types of DUTs.

[0025] In addition to the battery pack 102, the system 100 also includes a voltage measurement circuit 106, a current measurement circuit 108, a controller 110, an excitation current source 112, a load 114, and a sense resistor 116. The excitation current source 112, the load 114, and the sense resistor 116 are coupled in series between the positive terminal of the battery pack 102 and the negative terminal of the battery pack 102. The excitation current source 112 generates an excitation current for measuring the impedance of the battery 104. The current measurement circuit 108 and / or the voltage measurement circuit 106 are coupled to the controller 110 (e.g., via a serial communication bus). The controller 110 provides control information to the voltage measurement circuit 106 and the current measurement circuit 108, and retrieves status information from the voltage measurement circuit 106 and the current measurement circuit 108. The voltage measurement circuit 106 may also be coupled to the current measurement circuit 108 via a data interface 134. The data interface 134 may be a serial bus that provides information exchange between the current measurement circuit 108 and the voltage measurement circuit 106.

[0026] The voltage measurement circuit 106 includes a clock oscillator 118, a frequency divider 120, an analog-to-digital converter (ADC) 122, and a discrete frequency transform (DFT) circuit 124. The clock oscillator 118 generates a clock signal, which is divided by the frequency divider 120 to generate a conversion clock, which sets the acquisition timing of the ADC 122. The ADC 122 samples the voltage of the battery 104, while the excitation current source 112 generates an excitation current. The ADC 122 provides a voltage measurement value representing the voltage sample to the DFT circuit 124, and the DFT circuit 124 transforms the voltage measurement value into a signal composed of Figure 1 V i (k) represents the frequency domain.

[0027] The current measurement circuit 108 includes a clock oscillator 126, a frequency divider 128, an analog-to-digital converter (ADC) 130, and a discrete frequency transform (DFT) circuit 132. The clock oscillator 126 generates a clock signal, which is divided by the frequency divider 128 to generate a conversion clock, which sets the acquisition timing of the ADC 130. The ADC 130 samples the voltage across the sense resistor 116, which represents the current flowing through the sense resistor 116 and the battery pack 102, while the excitation current source 112 generates the excitation current. The ADC 130 provides a measurement value representing the current sample to the DFT circuit 132, and the DFT circuit 132 transforms the current measurement value into a signal represented by Figure 1 I(k) in the representation is the frequency domain.

[0028] The voltage measurement circuit 106 provides a voltage measurement to the impedance calculation circuit 136, and the current measurement circuit 108 provides a current measurement to the impedance calculation circuit. The impedance calculation circuit 136 can divide the voltage measurement by the current measurement at a selected frequency to provide an impedance spectroscopy analysis of the battery 104 at the selected frequency. Information related to the state of the battery 104 can be determined based on the impedance spectroscopy analysis of the battery 104. For example, the internal temperature of the battery 104 can be determined based on the measured impedance spectroscopy analysis of the battery 104.

[0029] The accuracy of the impedance measurement results provided by the system 100 is affected by the timing of the voltage and current sampling performed by the voltage measurement circuit 106 and the current measurement circuit 108. The difference in the sampling time of the voltage by the voltage measurement circuit 106 relative to the sampling time of the current by the current measurement circuit 108 may introduce a misalignment in the sampling time of the voltage (by the voltage measurement circuit 106) and the sampling time of the current (by the current measurement circuit 108). The misalignment may result in a mismatch between the voltage samples and the current samples, which may reduce the accuracy of the impedance value and reduce the accuracy of the battery state information derived from the impedance value. The sampling of the voltage measurement circuit 106 and the current measurement circuit 108 can be synchronized for accurate post-processing of the data and generating time-aligned control commands. However, synchronization may be challenging because the voltage measurement circuit 106 and the current measurement circuit 108 have different clocks to determine the timing of the local data measurements, where the clocks are based on the clock oscillator 118 and the clock oscillator 126. The frequencies of the clock oscillator 118 and the clock oscillator 126 vary independently with temperature and other factors. Due to temperature variations between devices and over time, calibration of clock oscillator 118 and clock oscillator 126 may not be sufficient to ensure the same clock source frequency during device operation. As a result, voltage measurement circuit 106 and current measurement circuit 108 may not be properly synchronized or may operate asynchronously at different clock frequencies, which may result in time misalignment between measurements, thereby potentially introducing errors in the impedance measurement results.

[0030] In the system 100, the sampling of voltage and current by the clock oscillator 118 and the clock oscillator 126 and the voltage measurement circuit 106 and the current measurement circuit 108 can be synchronized to improve the accuracy of the impedance value. In the system 100, the clock oscillator 118 of the voltage measurement circuit 106 can be synchronized with the clock oscillator 126 of the current measurement circuit 108 by transmitting synchronization information via the data interface 134. The synchronization information can include frequency information and phase information provided by the current measurement circuit 108 and transmitted to the voltage measurement circuit 106 via the data interface 134. The voltage measurement circuit 106 can apply the frequency information and phase information to adjust the frequency and phase of the clock signal generated by the clock oscillator 118 to match the frequency and phase of the clock signal generated by the clock oscillator 126 within an acceptable timing error (e.g., less than 3 microseconds), and synchronize the sampling performed by the ADC 122 with the sampling performed by the ADC 130.

[0031] In the example of system 100 , the devices for sampling voltage and current may be connected in various topologies such as a ring topology and a bus topology. Figure 2System 200 is shown, comprising devices 202, 204, 206, 208, and 210 connected in a ring topology. In the ring topology of system 200, commands are transmitted serially from one device to another through intermediate devices. Figure 3 System 300 is shown, which includes devices 302, 304, 306, 308, and 310 connected in a bus topology. In the bus topology of system 300, commands can be transmitted from one reference device to all target devices in parallel. Examples of system 100 can be implemented using a bus topology or a ring topology.

[0032] Figure 4 is a timing diagram illustrating example timing of reference clocks and target clocks in system 100. Figure 4 In FIG. 1 , the reference clock is labeled as Ref. Clock and the target clock is labeled as Device i Clock. Clock oscillator 126 provides the reference clock and clock oscillator 118 provides the target clock. Considering the frequency f of the reference clock at time sample n ref and the frequency f of the i-th target device (eg, the voltage measurement circuit 106) i (n), the rising transition of each clock is defined as t ref (n) and t i (n), such as Figure 4 The target device clock frequency includes cycle-by-cycle frequency variation based on temperature variation and includes clock jitter t jitter The time error between the clocks is defined as:

[0033] t err_i (n) = t ref (n)-t i (n) (1)

[0034] In system 100, clock oscillator 118 and clock oscillator 126 are synchronized to minimize the sum of the squared time errors of the i-th target device during the measurement duration, defined as Where N is the number of clock cycles over which the duration is measured.

[0035] Figure 5is a block diagram of an example system 500 that provides clock synchronization via command transmission. System 500 is an example of system 100. System 500 includes a reference device 502, and target devices 504, 506, and 508 coupled to reference device 502 via a communication interface. Examples of system 500 may include any number of target devices coupled to reference device 502. Target device 506 and target device 508 may include circuitry similar to that described with reference to target device 504. The synchronization operations described with respect to target device 504 also apply to target device 506 and target device 508.

[0036] The reference device 502 provides frequency information and phase information to the target device 504 to synchronize the clock generated by the target device 504 with the clock generated by the reference device 502 by, for example, reducing the phase and / or frequency mismatch between the clocks. The reference device 502 includes a reference clock source 510, a clock burst generator 512, a phase counter 514, a communication unit 516, and a control unit 518. The reference clock source 510 generates a reference clock for timing operations of the reference device 502. The output of the reference clock source 510 (at which the reference clock is provided) is coupled to an input of the clock burst generator 512 and an input of the phase counter 514. Each reference device 502 may include an application specific integrated circuit (ASIC) or a programmable logic circuit, a programmable controller, etc., which is configured (e.g., by instructions) to control the operation of various components of the device. For example, the control unit 518 of the reference device 502 may be a programmable controller.

[0037] The clock burst generator 512 generates cyclic bursts of a reference clock or a divided version of the reference clock for use in synchronizing the target device 504. For example, the clock burst generator 512 may include a divider circuit that divides the reference clock by an integer value to produce a lower frequency reference clock burst that is provided to the communication unit 516. The output of the clock burst generator 512, at which the reference clock bursts are provided, is coupled to the input of the communication unit 516.

[0038] Phase counter 514 counts cycles of the reference clock within a selected phase determination time interval. The output of phase counter 514 is coupled to an input of communication unit 516. Phase counter 514 provides a count of reference clock cycles at an output as a reference clock phase count.

[0039] The communication unit 516 receives the reference clock burst from the clock burst generator 512 and receives the reference clock phase count from the phase counter 514. The communication unit 516 includes a command generation circuit that generates a synchronization command based on the reference clock burst and the reference clock phase count. The communication unit 516 can periodically transmit a synchronization command including the reference clock burst and / or the reference clock phase count to the target device 504 to adjust the frequency and phase of the target clock generated by the target device 504. For example, the communication unit 516 can broadcast a first command including the reference clock burst to the target devices 504, 506, and 508, and broadcast a second command including the reference clock phase count to the target devices 504, 506, and 508. In some examples, the communication unit 516 can transmit a command including the reference clock burst and the reference clock phase count to the target device 504. The control unit 518 is coupled to the clock burst generator 512, the phase counter 514, and the communication unit 516 to control the generation of the reference clock burst, the reference clock phase count, and the synchronization command.

[0040] The target device 504 receives the synchronization command transmitted by the reference device 502, and applies the reference clock burst and the reference clock phase count to synchronize the target clock generated by the target device 504 with the reference clock generated by the reference device 502. The target device 504 includes a control unit 523, a communication unit 524, a clock synchronization circuit 522, and a target oscillator 520. The input of the communication unit 524 is coupled to the output of the communication unit 516 via the data interface 134, and the output of the communication unit 524 is coupled to the clock synchronization circuit 522. The communication unit 524 receives the synchronization command transmitted by the reference device 502. The communication unit 524 includes a command processing circuit that extracts the reference clock burst and the reference clock count from the synchronization command and provides the reference clock burst and the reference clock phase count to the clock synchronization circuit 522. Each target device, including the target device 504, may include an application specific integrated circuit (ASIC) or a programmable logic circuit, a programmable controller, etc., which is configured (e.g., by instructions) to control the operation of various components of the device. For example, the control unit 523 may be a programmable controller.

[0041] The clock synchronization circuit 522 includes a frequency synchronization circuit 526 and a phase synchronization circuit 528. The output of the clock synchronization circuit 522 is coupled to the input of the target oscillator 520, and the input of the clock synchronization circuit 522 is coupled to the output of the target oscillator 520. The clock synchronization circuit 522 controls the target clock ( Figure 5The frequency and phase of the target oscillator 520 are shown as "synchronized clock" in FIG. 1 . The frequency synchronization circuit 526 provides a frequency control signal to the target oscillator 520 to adjust the frequency of the target clock based on the comparison of the frequency of the target clock with the frequency of the reference clock burst. The phase synchronization circuit 528 provides a phase control signal ( Figure 6 Marked as ΔD freq ) to adjust the phase of the target clock based on a comparison of the reference clock phase count and the target clock phase count. The target clock phase count is a count of target clock cycles in a phase determination time interval. The clock synchronization circuit 522 can provide a frequency control signal and a phase control signal sequentially or concurrently. In some examples, various functions of the phase synchronization circuit 528 can be implemented using a programmable controller, a programmable logic circuit, an ASIC, etc. For example, the phase counter 618 and the phase comparator 620 can be circuits or implemented by a programmable controller executing software instructions.

[0042] In some examples, the reference device 502 may be part of or include a measurement device (e.g., voltage measurement circuit 106, current measurement circuit 108, etc.), and the target device 506 / 508 may be part of or include another measurement device (e.g., voltage measurement circuit 106, current measurement circuit 108, etc.), and clock synchronization operations may be performed to reduce sampling time / frequency mismatch between voltage and current. In some examples, the reference device 502 / target device 506 / 508 does not have a sampling circuit (e.g., ADC 122 / 130). For example, the reference device 502 / target device 506 / 508 may be Figure 1 The clock synchronization operation may be performed to reduce a time / frequency mismatch between, for example, the excitation current provided by the excitation current source 112 and the sampling of the current and voltage of the battery 104 in response to the excitation current.

[0043] Figure 66 is a block diagram of an example circuit system 600 for providing target clock synchronization for a target device 504 based on a command received from a reference device 502. The circuit system 600 includes a phase synchronization circuit 528 and a phase-locked loop circuit 602. The phase-locked loop circuit 602 includes a target oscillator 520 and a frequency synchronization circuit 526. The frequency synchronization circuit 526 includes a frequency divider 604, a phase detector 606, a charge pump 608, and a loop filter 610. The frequency divider 604 has an input coupled to an output of the target oscillator 520. The frequency divider 604 divides a target clock generated by the target oscillator 520 by a divisor to generate a divided target clock for comparison with a reference clock burst. The output of the frequency divider 604 is coupled to a first detector input of the phase detector 606. A second detector input of the phase detector 606 is coupled to the communication unit 524 for receiving a reference clock burst transmitted by the reference device 502.

[0044] Phase detector 606 compares the reference clock burst with the divided target clock and provides an error signal representing the frequency difference between the divided target clock and the reference clock burst. Phase detector 606 generates the error signal periodically, for example, when a command containing a reference clock burst is received. Charge pump 608 has an input coupled to the detector output of phase detector 606. Phase detector 606 can pull or sink current based on the error signal received from phase detector 606. Loop filter 610 averages the error signal (as represented by the charge pump output signal) to control the frequency of target oscillator 520. The output signal of frequency synchronization circuit 526 is provided by loop filter 610 to a first input of summing circuit 612. A second input of summing circuit 612 is coupled to phase synchronization circuit 528. The output of summing circuit 612 is coupled to an input of target oscillator 520 to control the frequency and phase of the target clock.

[0045] The phase synchronization circuit 528 includes a phase counter 618 and a phase comparator 620. The phase counter 618 has an input coupled to the output of the target oscillator 520. The phase counter 618 counts the cycles of the target clock in the phase determination time interval to generate a target clock phase count. The output of the phase counter 618 is coupled to a first input of the phase comparator 620. The second input of the phase comparator 620 is coupled to the communication unit 524 for receiving the reference clock phase count transmitted by the reference device 502. The phase comparator 620 compares the target clock phase count with the reference clock phase count and generates a difference signal representing the difference between the target clock phase count and the reference clock phase count. The comparator output of the phase comparator 620 is coupled to the second input of the summing circuit 612 to adjust the phase of the target clock.

[0046] Figure 7is a block diagram of an example integrated circuit 700 including battery monitoring circuitry and circuitry for clock synchronization. Integrated circuit 700 can be configured to act as a reference device that transmits a clock synchronization command, or as a target device that receives a clock synchronization command and synchronizes a target clock with a reference clock based on the received synchronization command. Integrated circuit 700 includes clock burst generator 512, phase counter 514, clock synchronization circuit 522, communication interface 702, controllable clock source 704, mode control circuit 706, DFT circuit 708, and sampling circuit 710.

[0047] Sampling circuit 710 may include an ADC (eg, Figure 1 ADC 122 or 130 shown). The sampling clock input of the sampling circuit 710 is coupled to the clock output of the controllable clock source 704. The sensing terminal of the sampling circuit 710 can be coupled to the battery 104 to sense a voltage signal, or coupled to the sensing resistor 116 to sense a current signal, such as Figure 1 shown.

[0048] DFT circuit 708 is a signal processing circuit and may be Figure 1 1. An example of DFT circuit 124 or DFT circuit 132 is shown. The input of DFT circuit 708 is coupled to the output of sampling circuit 710. DFT circuit 708 transforms the time domain digital measurement value received from sampling circuit 710 into a frequency domain measurement value. The output of DFT circuit 708 is coupled to communication interface 702 for transmitting the frequency domain measurement value to an external circuit, which can calculate the impedance based on the frequency domain measurement value. In some examples, DFT circuit 708 can be a digital signal processor (DSP). In some examples, DFT circuit 708 can be part of an ASIC, programmable logic circuit, etc. configured to perform the transformation operation. Communication interface 702 can be used as Figure 5 The communication unit 516 or the communication unit 524 is shown. If the integrated circuit 700 is configured to function as a reference device, the communication interface 702 functions as the communication unit 516. If the integrated circuit 700 is configured to function as a target device, the communication interface 702 functions as the communication unit 524.

[0049] The controllable clock source 704 can be used as Figure 5 The reference clock source 510 or the target oscillator 520 is shown. If the integrated circuit 700 is configured as a reference device, the controllable clock source 704 is used as the reference clock source 510. If the integrated circuit 700 is configured as a target device, the controllable clock source 704 is used as the target oscillator 520.

[0050] If the integrated circuit 700 is used as a target device, the mode control circuit 706 provides a frequency / phase control signal to the controllable clock source 704. The mode control circuit 706 has a mode control input for receiving a mode control signal, which specifies whether the integrated circuit 700 is used as a reference device or as a target device. For example, a first state of the mode control signal can specify that the integrated circuit 700 is to be used as a reference device, and a second state of the mode control signal can specify that the integrated circuit 700 is to be used as a target device. The mode control signal can be provided from a control register (not shown) of the integrated circuit 700. The mode control circuit 706 has a frequency control input coupled to the output of the clock synchronization circuit 522 and an output coupled to the input of the controllable clock source 704. The mode control circuit 706 can also control the operation of various components of the integrated circuit 700, such as the clock burst generator 512, the phase counter 514, the clock synchronization circuit 522, the communication interface 702, the DFT circuit 708, and the sampling circuit 710. In some examples, the mode control circuit 706 can be a programmable controller.

[0051] If the integrated circuit 700 is used as a reference device, the mode control circuit 706 can provide a steady-state signal to the controllable clock source 704. If the integrated circuit 700 is used as a reference device, the mode control circuit 706 can also enable the communication interface 702 to function as a communication unit 516, and can control the clock burst generator 512 and the phase counter 514 to initiate the generation of reference clock bursts and reference clock phase counts. If the integrated circuit 700 is used as a target device, the mode control circuit 706 can enable the communication interface 702 to function as a communication unit 524, and enable the operation of the clock synchronization circuit 522.

[0052] Figure 8 800 is a flow chart of an example method 800 for clock synchronization via a communication interface. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some embodiments may only perform some of the actions shown. The operations of method 800 may be performed by an embodiment of system 500. For example, the operations of blocks 802 to 808 may be performed by reference device 502, and the operations of blocks 810 to 818 may be performed by target device 504.

[0053] In block 802, reference clock source 510 generates a reference clock. In block 810, target oscillator 520 generates a target clock.

[0054] In block 804, the phase counter 514 counts cycles of the reference clock in the phase determination time interval. In block 812, the phase counter of the phase synchronization circuit 528 counts cycles of the target clock in the phase determination time interval.

[0055] In block 806, the reference device 502 (e.g., a command generation circuit of the reference device 502) generates a synchronization command including reference clock frequency information and / or reference clock phase information. For example, the reference device 502 may generate a reference clock burst including reference clock frequency information, and generate a command including the reference clock burst. The reference device 502 may also generate a command including a count of cycles of the reference clock during a phase determination time interval (reference clock phase count), wherein the count of cycles is the reference clock phase information.

[0056] In block 808 , the reference device 502 transmits a synchronization command to the target device.

[0057] In block 814 , the target device 504 receives the synchronization command transmitted by the reference device 502 .

[0058] In block 816, the target device 504 (e.g., command processing circuitry of the target device 504) extracts reference clock frequency information and / or reference clock phase information from the synchronization command. For example, the target device 504 may identify the synchronization command as including a reference clock burst and provide the reference clock burst to the frequency synchronization circuit 526. Similarly, the target device 504 may identify the synchronization command as including a reference clock phase count and provide the reference clock phase count to the phase synchronization circuit 528.

[0059] In block 818 , the target device 504 synchronizes the target clock with the reference clock based on the reference clock frequency information and / or the reference clock phase information provided by the reference device 502 .

[0060] Fig. 9 900 is a flow chart of an example method 900 for generating synchronization commands in reference device 502. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some embodiments may only perform some of the actions shown.

[0061] In block 902 , the reference device 502 (eg, the control unit 518 of the reference device 502 ) initializes a frequency synchronization time value and a phase synchronization time value.

[0062] In block 904, the reference device 502 (eg, the control unit 518) determines whether it is currently time to provide phase synchronization to the target device 504. The determination is based on the time since the last phase synchronization time t p Whether the phase synchronization time interval t has passed phase If the current time (t) is synchronized with the last phase t p The difference between them is less than t phase, the control unit 518 determines that it is not time to provide phase synchronization to the target device 504 , and the method 900 continues to block 910 . Otherwise, if it is time to provide phase synchronization information to the target device 504 , the method 900 continues to block 906 .

[0063] In block 906, the reference device 502 (eg, the control unit 518) updates the latest time t p , so that the next time of phase synchronization can be determined.

[0064] In block 908, the reference device 502 (e.g., the control unit 518) generates a phase synchronization command and transmits the phase synchronization command to the target device 504. The generation of the phase synchronization command may include the control unit 518 retrieving the reference clock phase count from the phase counter 514 and providing the reference clock phase count to the communication unit 516, which may then insert the reference phase count into the phase synchronization command and transmit the phase synchronization command. The method 900 continues to block 904.

[0065] In block 910, the reference device 502 (eg, the control unit 518) determines whether it is currently time to provide frequency synchronization to the target device 504. The determination is based on the time since the last frequency synchronization time t f Whether the frequency synchronization time interval t has passed since freq If the current time (t) is synchronized with the last frequency t f The difference between them is less than t freq , the control unit 518 determines that it is not time to provide frequency synchronization to the target device 504, and the method 900 continues to block 904. Otherwise, if it is time to provide frequency synchronization information to the target device 504, the method 900 continues to block 912.

[0066] In block 912, the reference device 502 (eg, the control unit 518) updates the latest time t f , so that the next time for frequency synchronization can be determined.

[0067] In block 914, the reference device 502 (e.g., the control unit 518) generates a frequency synchronization command and transmits the frequency synchronization command to the target device 504. The generation of the frequency synchronization command may include the control unit 518 causing the clock burst generator 512 to generate a reference clock burst and provide the reference clock burst to the communication unit 516, which may then insert the reference clock burst into the frequency synchronization command and transmit the frequency synchronization command. The method 900 continues to block 904.

[0068] Fig.101 is a flow chart of an example method 1000 of phase synchronization in a target device 504. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some implementations may perform only some of the actions shown.

[0069] In system 500, temperature changes between frequency synchronization command transmissions may cause higher frequency errors, which results in cumulative phase errors that increase quadratically over time. To reduce the impact of temperature changes, target device 504 may periodically perform phase synchronization between frequency synchronization commands via phase synchronization circuit 528. Phase synchronization circuit 528 may provide a periodic frequency change ΔD based on the phase difference between the reference clock and the target clock. freq The phase control signal of the two clocks is used to reduce the phase error between the two clocks and minimize the time error. The clock phase is captured in each device by a phase counter, which is reset at the beginning of the measurement and incremented at each clock cycle. phase At the reference device 502, the phase counter N ref The target device 504 samples the phase counter N and transmits this value to the target device 504 in the phase synchronization command. When the target device 504 receives the phase synchronization command, the target device sets its phase counter N i Sampling is performed and the value of its phase counter is compared with the reference phase counter by a digital comparator (phase comparator 620).

[0070] In block 1002, the target device 504 (eg, the control unit 523) determines whether a phase synchronization command has been received from the reference device 502. If a phase synchronization command has not been received, the method 1000 continues to block 1002. If a phase synchronization command has been received, the method 1000 continues to block 1004.

[0071] In block 1004, the target device 504 (eg, the control unit 523) extracts the reference clock phase count N from the phase synchronization command. ref , and provides the reference clock phase count to the phase synchronization circuit 528. The phase synchronization circuit 528 also retrieves the target clock phase count value N from the target phase counter of the target device 504. i , and subtract the target clock phase count from the reference clock phase count to generate a phase difference value (ΔN).

[0072] The reference phase counter and the target phase counter can have N values limit The operations of blocks 1006 through 1012 correct for such counter wraparound. In block 1006, the target device 504 (eg, phase synchronization circuit 528) determines whether the phase difference value is greater than or equal to one-half Nlimit If the phase difference is less than half of N limit , then method 1000 continues to box 1010, otherwise method 1000 continues to box 1008.

[0073] In block 1008, the target device 504 (eg, the phase synchronization circuit 528) sets N limit The phase difference value is subtracted to generate an adjusted phase difference value (ΔN').

[0074] In block 1010, the target device 504 (eg, the phase synchronization circuit 528) determines whether the phase difference value is less than or equal to one-half of -N limit If the phase difference is greater than half of -N limit , then method 1000 continues to box 1012, otherwise method 1000 continues to box 1011.

[0075] In block 1011, the target device 504 (eg, the phase synchronization circuit 528) sets N limit The phase difference value is added to generate an adjusted phase difference value (ΔN').

[0076] In block 1012 , the target device 504 (eg, the phase synchronization circuit 528 ) sets the adjusted phase difference value (ΔN′) equal to the phase difference value (ΔN).

[0077] In block 1014, the target device 504 (e.g., the phase synchronization circuit 528) provides a phase control signal including a frequency update value as:

[0078] ΔD freq =round(ΔN′·G psync ) (2)

[0079] Among them G psync is the gain value used to control the step in the frequency update based on the update rate, the frequency resolution of the oscillator, and the phase counter resolution.

[0080] Fig.11 is a timing diagram illustrating frequency synchronous communication and phase synchronous communication between the reference device 502 and the target device 504 . Fig.11 It is shown that in the reference device 502, the frequency synchronization command is sent at intervals t freq The trigger and phase synchronization commands are set at intervals of t phase The triggering, transmission of frequency synchronization command and phase synchronization command and reference phase counter state. In the target device 504, Fig.11 The frequency synchronization command and the phase synchronization command based on the comparison of the reference phase count and the target phase count, the target phase counter state and ΔD are shown. freq of reception.

[0081] exist Fig.11 In the example, the clock synchronization sequence may be initiated by the control unit 518 in the reference device 502, so that at t freq Next, the control unit 518 triggers frequency synchronization at t phase The reference device 502 responds to the frequency synchronization trigger from the control unit 518 by generating and sending a frequency synchronization command containing multiple reference clock cycles (reference clock burst). The first phase synchronization trigger 1102 generates a counter reset command (reset count command—used to reset the phase counter), and then generates and transmits a phase synchronization command containing the reference clock phase count. Fig.11 In the example shown, phase synchronization commands 1104 and 1106 include phase counts of 13 and 27, respectively. Target device 504 delays data interface t comm After receiving the phase synchronization command, the data interface delay is the delay between the clocks after synchronization. This data interface delay is a deterministic delay that can be determined and compensated in data post-processing. The corresponding target device phase counts after receiving the phase synchronization command are 14 and 27 respectively. This phase counter difference after the phase synchronization command 1104 is 1, which indicates the phase and time error between the reference clock and the device clock. Therefore, the target device frequency ΔD is required freq The phase and time errors are reduced by the change of the reference device clock. Once the phase counter value matches, no further change of the target device oscillator frequency is required. This condition means that the phase and time errors between the reference device clock and the target device clock are minimal, and clock synchronization has been achieved between the reference device clock and the target device clock.

[0082] Fig. 12A , 12B 12C are diagrams of example frequency synchronization commands and phase synchronization commands sent by reference device 502 to target device 504. Fig. 12A Command 1202 is an example frequency synchronization command. Fig. 12B Command 1204 is an example phase synchronization command. Fig. 12CCommand 1206 is an example frequency / phase synchronization command. Each command begins with a preamble used for synchronization between the transmitting communication unit and the receiving communication unit in the reference device and the target device, respectively. The next part of the command is a header that may contain an identifier of the command type, followed by a payload containing the required information to be transmitted. The payload contents depend on the type of synchronization command. In command 1202, the payload contains a reference clock burst for a frequency synchronization command. In command 1204, the payload contains a reference phase count for a phase synchronization command. In command 1206, the payload contains a reference clock burst followed by a reference phase count for frequency and phase synchronization in a single synchronization command. Finally, the command ends with a command stop field that identifies the end of the synchronization command.

[0083] In each of commands 1202 and 1206, the reference clock burst may be represented by a predetermined set of bits that toggle between logic ones and logic zeros, where the bit width (in time) indicates the frequency of the reference clock burst. Additionally, in each of commands 1204 and 1206, the reference phase clock count may be represented by a binary number having a predetermined set of bits. A command parser (e.g., a portion of communication unit 524 / communication interface 702) may parse the command based on the command type indicated in the header to extract a set of bits representing the reference clock burst and / or a set of bits representing the reference phase count.

[0084] Fig.13 is a diagram of example variations in synchronization timing error with and without randomization of frequency synchronization commands. Frequency synchronization using transmission and reception of frequency synchronization commands as described herein can reduce the frequency difference between the target clock and the reference clock at certain update intervals, which reduces synchronization timing error. However, using a fixed time interval between frequency synchronization commands may result in a gain difference at a particular gain value G. psync The phase synchronization under the condition of 100 ms is unstable. The periodic repetition of the frequency synchronization command may lead to the accumulation of phase error, which causes the synchronization time error to continue to increase over time.

[0085] In some examples of system 500, reference device 502 may randomize the frequency synchronization update interval by, for example, randomizing the time offset of the update interval (the time between transmissions of frequency synchronization commands) by up to 10% of the update period. Fig.13 The synchronization time error t err Relative to gain G psync Without frequency synchronization, stable performance is shown over a wide gain range up to 2.5. Larger gain values ​​above 2.5 result in larger variations in the oscillator frequency, leading to unstable performance. However, due to the large frequency difference between the reference and target devices, not having frequency synchronization can result in t errOn the other hand, using frequency synchronization without randomization may result in unstable performance for most gain values. Frequency synchronization based on randomized update intervals can make the performance more stable for most gain values ​​while providing lower t compared to the baseline case without frequency synchronization. err .

[0086] Fig.14 is a graphical representation of example synchronization timing errors with and without a phase synchronization command. Fig.14 Figure 5 shows the clock time error between the proposed clock synchronization method (frequency and phase synchronization), phase synchronization only, and no synchronization case of system 500 The diagram shows is very large and increases quadratically without any synchronization. Phase synchronization will The error is reduced to less than 8 μs, but the error increases over time due to frequency drift, which cannot be compensated by phase synchronization alone. Finally, the best results are achieved by using frequency synchronization in addition to phase synchronization as implemented in system 500. This approach limits frequency drift and can maintain value is less than 3μs and prevent it from increasing over time.

[0087] Fig.15 is a block diagram of an example processor platform 1500 including a processor configured to execute machine-readable instructions to implement Figure 5-10 For example, processor platform 1500 may be a processor circuit system that can be used to represent the logic / functionality depicted in the example of FIG. Figure 5 The reference device 502 and the target devices 504, 506 and 508 and Figure 7 A part of the integrated circuit 700 or including them.

[0088] The processor platform 1500 of the illustrated example may include a processor circuit system 1512. The processor circuit system 1512 of the illustrated example includes hardware. For example, the processor circuit system 1512 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), and / or microcontrollers from any desired series or manufacturer. The processor circuit system 1512 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In some examples, the processor circuit system 1512 may implement control units 518, 523, phase synchronization circuits 528, mode control circuits 706, DFT circuits 708, and the like.

[0089] The processor circuit system 1512 of the illustrated example may include a local memory 1513 (e.g., cache memory, registers, etc.). The processor circuit system 1512 of the illustrated example communicates with a computer-readable storage device such as a main memory including a volatile memory 1514 and a non-volatile memory 1516 via a bus 1518. The volatile memory 1514 may be composed of, for example, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 1516 may be implemented by a programmable read-only memory, a flash memory, and / or any other desired type of non-volatile memory device. Access to the main memory 1514, 1516 of the illustrated example may be controlled by a memory controller 1517.

[0090] The processor platform 1500 of the illustrated example also includes an interface circuit system 1520. The interface circuit system 1520 can be implemented by hardware that complies with any type of interface standard, such as an (I2C) interface, a serial peripheral interface (SPI), an Ethernet interface, a universal serial bus (USB) interface, Interface circuitry 1520 may include communication units 516 and 524 or may be a part thereof.

[0091] In the example shown, one or more input ADCs 1522 are connected to bus 1518. ADC 1522 may convert analog signals into digital signals for processing by processor circuitry 1512. ADC 1522 may represent sampling circuit 710.

[0092] One or more output devices 1524 may be connected to the interface circuitry 1020 of the illustrated example. The output devices 1524 may include circuitry such as driver circuits.

[0093] The machine-readable instructions 1532 may be stored in the volatile memory 1514 and / or the non-volatile memory 1516. When executed by the processor circuitry 1512, the machine-readable instructions 1532 cause the processor platform 1500 to perform any or all of the functionality assigned to the reference device 502, the target devices 504, 506, and 508, the integrated circuit 700, and the methods 800, 900, and 1000 described herein.

[0094] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0095] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0096] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0097] The circuits described herein may be reconfigured to include additional components or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the impedance amount represented by the resistors shown. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0098] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0099] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A device comprising: a clock source having a clock output; a counter having a counter clock input and a count output, the clock output being coupled to the counter clock input; a command generation circuit having a frequency input, a phase input, and a command output, the frequency input being coupled to the clock output and the phase input being coupled to the count output; as well as A communication interface is coupled to the command output.

2. The device of claim 1, further comprising a frequency divider coupled between the clock source and the frequency input.

3. The apparatus of claim 1 , wherein the command generation circuit is configured to: receiving a clock signal at the frequency input; receiving a count value at the phase input; transmitting, via the communication interface, at the command output, a first command including the clock signal; and After the transmission of the first command, a second command including the count value is transmitted at the command output via the communication interface. 4 . The device of claim 3 , wherein the command generation circuit is configured to transmit a plurality of second commands between consecutive first commands. The device of claim 3 , wherein the second command comprises a reset count command. The device of claim 3 , wherein the second command includes the clock signal, or the first command includes the count value.

7. The device of claim 3, wherein the command generation circuit is configured to transmit the first command and the second command at random intervals.

8. The apparatus of claim 1 , wherein the communication interface, the clock source, the counter, and the command generation circuit are part of an integrated circuit, and the integrated circuit further comprises: a sampling circuit having a sense input, a sample output, and a sampling clock input coupled to the clock output, the sampling circuit being configured to receive a measurement signal at the sense input and to provide a sample of the measurement signal at the sample output; as well as A signal processing circuit has a processing input coupled to the sample output and a processing output, the signal processing circuit being configured to provide a signal representative of a spectral component of the measurement signal at the processing output. 9 . The device of claim 8 , wherein the measurement signal comprises at least one of: a current signal through a device under test (DUT), or a voltage signal across the DUT.

10. The apparatus of claim 9, wherein the DUT is a battery.

11. An apparatus comprising: Communication interface; a command processing circuit having a command input, a reference frequency output, and a reference phase output, the command input being coupled to the communication interface; a clock synchronization circuit having a reference frequency input, a reference phase input, and a frequency control output, the reference frequency output being coupled to the reference frequency input, and the reference phase input being coupled to the reference phase output, the clock synchronization circuit comprising a frequency synchronization circuit and a phase synchronization circuit; as well as A controllable clock source has a frequency control input and a clock output, the frequency control input being coupled to the frequency control output.

12. The device of claim 11, wherein the command processing circuit is configured to: receiving a first command including a reference clock signal; receiving a second command including a reference count value; providing the reference clock signal at the reference frequency output; and providing the reference count value at the reference phase output; and The phase synchronization circuit comprises: a counter having a counter clock input and a count output, the counter clock input being coupled to the clock output; as well as a phase comparator having a first input coupled to the count output, a second input coupled to the reference phase input, and a comparator output coupled to the frequency control output, the phase comparator being configured to generate a first frequency control signal based on a comparison between the reference count value and a target count value; and The frequency synchronization circuit comprises: a phase detector having a first detector input and a second detector input and a detector output, the first detector input being coupled to the reference frequency input and the second detector input being coupled to the clock output; as well as a charge pump and a loop filter coupled between the detector output and the frequency control output; and Wherein the frequency synchronization circuit is configured to provide a second frequency control signal based on a phase difference between the reference clock signal and a target clock signal at the clock output.

13. The device of claim 12, further comprising a frequency divider coupled between the clock output and the second detector input.

14. The device of claim 12, further comprising a processing circuit coupled between the comparator output, the detector output, and the frequency control output, the processing circuit configured to provide a third frequency control signal based on the first frequency control signal and the second frequency control signal.

15. The apparatus of claim 11, wherein the communication interface, the command processing circuit, and the clock synchronization circuit are part of an integrated circuit, and the integrated circuit further comprises: a sampling circuit having a sense input, a sample output, and a sampling clock input coupled to the clock output, the sampling circuit being configured to receive a measurement signal at the sense input and to provide a sample of the measurement signal at the sample output; as well as A processing circuit has a processing input coupled to the sample output and a processing output, the processing input being configured to provide a signal at the processing output representative of a spectral component of the measurement signal. 16 . The device of claim 15 , wherein the measurement signal comprises at least one of: a current signal through a device under test (DUT), or a voltage signal across the DUT.

17. The apparatus of claim 16, wherein the DUT is a battery.

18. An integrated circuit comprising: Communication interface; a controllable clock source having a frequency control input and a clock output; a counter having a clock input and a count output, the clock input being coupled to the clock output; a command generation circuit having a frequency input, a phase input, and a command output, the frequency input being coupled to the clock output, the phase input being coupled to the count output, and the command output being coupled to the communication interface; a command processing circuit having a command input, a reference phase output, and a reference frequency output, the command input being coupled to the communication interface; as well as A clock synchronization circuit having a reference phase input, a reference frequency input and a frequency control output, wherein the reference phase input is coupled to the reference phase output, the reference frequency output is coupled to the reference frequency input, and the frequency control output is coupled to the frequency control input, wherein the clock synchronization circuit includes a frequency synchronization circuit and a phase synchronization circuit.

19. The integrated circuit of claim 18, further comprising a mode control circuit having a mode control input, the mode control circuit being configured to: In response to the mode control input having a first state, causing the command generation circuit to: receiving a clock signal at the frequency input; receiving a count value at the phase input; transmitting, via the communication interface, at the command output, a first command comprising the clock signal; and transmitting, via the communication interface, at the command output, a second command including the count value; and In response to the mode control input having a second state: causing the command processing circuit to receive a first command including a reference clock signal and to provide the reference clock signal at the reference frequency output; causing the command processing circuit to receive a second command including a reference count value and to provide the reference count value at the reference phase output; causing the clock synchronization circuit to provide a frequency control signal at the frequency control output based on the reference count value and the reference clock signal; and The controllable clock source is caused to provide a clock signal at a second clock output based on the frequency control signal.

20. The integrated circuit of claim 19, further comprising: a sampling circuit having a sense input, a sample output, and a sampling clock input coupled to the clock output, the sampling circuit being configured to receive a measurement signal at the sense input and to provide a sample of the measurement signal at the sample output; as well as A signal processing circuit has a processing input coupled to the sample output and a processing output, the signal processing circuit being configured to provide a signal representative of a spectral component of the measurement signal at the processing output.

21. The integrated circuit of claim 20, wherein the measurement signal comprises at least one of: a current signal through a device under test (DUT), or a voltage signal across the DUT.

22. The integrated circuit of claim 21, wherein the DUT is a battery.

23. A system comprising: A device under test (DUT) monitoring device, comprising: a stimulus generating circuit having a stimulus output; an impedance spectroscopy circuit having a first spectroscopy input, a second spectroscopy input, and an impedance spectroscopy input; a current sensing circuit having a current sensing output; A first measuring device comprising: a synchronous command processing circuit having a command input; a clock synchronization circuit coupled to the synchronization command processing circuit, the clock synchronization circuit having a frequency control output; a controllable clock source having a frequency control input and a first clock output, the frequency control input being coupled to the frequency control output; a first sampling circuit having a DUT input, a first sample output, and a first clock input, the first clock input being coupled to the first clock output, and the first sampling circuit being configured to receive a voltage measurement signal at the DUT input and to provide a sample of the voltage measurement signal at the first sample output; as well as a first processing circuit having a first processing input and a first processing output, the first processing input being coupled to the first sample output, the first processing output being coupled to the first spectral input, and the first processing circuit being configured to provide at the first processing output a first signal representative of spectral components of the voltage measurement signal; as well as A second measuring device comprising: a reference clock source having a reference clock output; a counter having a second clock input and a count output, the second clock input being coupled to the reference clock output; a synchronous command generation circuit having a frequency input, a phase input, and a command output, the frequency input being coupled to the reference clock output, the phase input being coupled to the count output, and the command output being coupled to the command input; a second sampling circuit having a current sensing input, a second sample output, and a third clock input, the third clock input being coupled to the reference clock output, the current sensing input being coupled to the current sensing output, and the second sampling circuit being configured to receive a current measurement signal at the current sensing input and to provide a sample of the current measurement signal at the second sample output; as well as a second processing circuit having a second processing input coupled to the second sample output and a second processing output coupled to the second spectral input, and configured to provide a second signal representative of spectral components of the current measurement signal at the second processing output.

24. The system of claim 23, wherein the DUT is a battery.

25. A method comprising: generating a reference clock signal by a first device; providing, by the first device, a reference count value based on counting cycles of the reference clock signal; providing, by the first device, a divided clock signal based on dividing the reference clock signal; providing, by the first device, a first command including the divided clock signal; providing, by the first device, a second command including the reference count value; receiving the first command by the second device; receiving, by the second device, the second command; generating a target clock signal by the second device; determining, by the second device, a target count value based on the target clock signal; as well as The frequency and phase of the target clock signal are adjusted by the second device based on the divided clock signal and a difference between the reference count value and the target count value.

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