A signal processing method, system, device, medium and product

Abstract

The present application provides a signal processing method, system, device, medium and product, which relates to the field of communication technologies, and includes: obtaining a digital signal to be processed, performing delay adjustment to obtain a signal after delay adjustment; if a first preset condition is satisfied, outputting the signal after delay adjustment; if the first preset condition is not satisfied and a second preset condition is not satisfied either, performing aliasing distortion compensation on it, obtaining and outputting; if the signal after delay adjustment does not satisfy the first preset condition but satisfies the second preset condition, continuing to perform at least one delay adjustment on it until the currently adjusted signal after delay satisfies the first preset condition, or when the number of times of delay adjustment reaches a first preset threshold, outputting the currently adjusted signal after delay. Thus, through multi-level conditional judgment and dynamic adjustment, digital signals can be effectively processed and optimized, ensuring that the output signals meet the expected standards in terms of quality and performance, and can improve the effect of digital predistortion and reduce the power consumption of hardware.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of communication technologies, and in particular, to a signal processing method, system, device, medium, and product. Background Art

[0002] Looking at the existing multi-phase digital pre-distortion (DPD) technologies, the industry and academia face some common challenges and limitations when designing and implementing solutions. The industry usually chooses to retain only the multi-phase module in order to reduce hardware complexity and power consumption, ignoring the necessity of the aliasing distortion compensation part. This choice can reduce the system complexity and cost in the short term, but may lead to a decline in signal quality. Especially in high-frequency and high-power applications, aliasing distortion may significantly affect the overall performance of the system.

[0003] On the other hand, there is a choice to retain both the multi-phase module and the aliasing distortion compensation in order to find a balance between performance and complexity. However, such a design often increases the system cost and power consumption, especially when dealing with high-bandwidth signals. At this time, the contradiction between the consumption of hardware resources and the performance improvement becomes more prominent, especially in the field of mobile communication, where the requirements for energy efficiency and processing power are increasing day by day.

[0004] In academia, research mainly focuses on reducing the number of filters through multi-phase interpolation technology to reduce implementation complexity. Although this method optimizes the system design to a certain extent, it often ignores the in-depth analysis of hardware computing power. With the rapid development of mobile communication technologies, especially the advent of 5G and future 6G networks, users' demands for data throughput and signal processing capabilities are constantly increasing, and traditional design methods cannot meet the needs of future flexible loading of multiple computing powers.

[0005] In summary, in current wireless communication technologies, especially for applications facing next-generation base stations, with the increasing demands for large bandwidth, high transmission rate, and low latency, the existing linearization pre-correction processing technologies face significant challenges. Although the existing technologies can meet the basic linear pre-distortion processing effects to a certain extent, there are obvious deficiencies in the balance between processing accuracy and computing power requirements. Summary of the Invention

[0006] Embodiments of the present application provide a signal processing method, system, device, medium, and product to solve the technical problem that although the existing linearization pre-correction processing technologies can meet the basic linear pre-distortion processing effects to a certain extent, there are obvious deficiencies in the balance between processing accuracy and computing power requirements.

[0007] To solve the above technical problem, the present application is implemented as follows:

[0008] In a first aspect, an embodiment of the present application provides a signal processing method, which is applied to a signal processing system. The method includes:

[0009] The signal processing system acquires a digital signal to be processed and performs delay adjustment on the digital signal to be processed to obtain a signal after delay adjustment;

[0010] If the signal after delay adjustment meets a first preset condition, the signal processing system outputs the signal after delay adjustment;

[0011] If the signal after delay adjustment does not meet the first preset condition and does not meet a second preset condition, the signal processing system performs aliasing distortion compensation on the signal after delay adjustment to obtain and output a signal after aliasing distortion compensation;

[0012] If the signal after delay adjustment does not meet the first preset condition but meets the second preset condition, at least one more delay adjustment is continued on the signal after delay adjustment until the currently adjusted signal meets the first preset condition or the number of delay adjustments reaches a first preset threshold, and then the currently adjusted signal is output;

[0013] Wherein, the first preset condition is that the sum of the mean square error between the currently adjusted signal and a preset target signal and the reciprocal of the signal-to-noise ratio of the currently adjusted signal is less than a second preset threshold;

[0014] The second preset condition is that the signal-to-noise ratio of the signal after delay adjustment is greater than a third preset threshold.

[0015] Optionally, performing delay adjustment on the digital signal to be processed to obtain a signal after delay adjustment includes:

[0016] The signal processing system divides the digital signal to be processed into P parallel sub-digital signals; P is a positive integer and is the number of polyphase branches that the signal processing system can support;

[0017] The signal processing system performs delay adjustment on the P parallel sub-digital signals respectively and then combines them to obtain the signal after delay adjustment.

[0018] Optionally, performing aliasing distortion compensation on the signal after delay adjustment to obtain and output a signal after aliasing distortion compensation includes:

[0019] The signal processing system configures the order of a preset filter according to the aliasing distortion degree of the signal after delay adjustment;

[0020] The aliasing distortion of the delay-adjusted signal is compensated by the filter to obtain an aliasing distortion-compensated signal; the aliasing distortion-compensated signal is output.

[0021] Optionally, the signal processing system configures the order of a preset filter according to the aliasing distortion degree of the delay-adjusted signal. Compensating the aliasing distortion of the delay-adjusted signal by the filter to obtain an aliasing distortion-compensated signal includes:

[0022] The signal processing system calculates the signal-to-noise ratio of the delay-adjusted signal;

[0023] The signal processing system performs normalization processing on the signal-to-noise ratio to obtain a normalized signal-to-noise ratio;

[0024] The signal processing system determines the target order of the filter according to the normalized signal-to-noise ratio and the maximum order of the preset filter, and adjusts the current order of the filter to the target order;

[0025] The signal processing system compensates the aliasing distortion of the delay-adjusted signal based on the filter to obtain an aliasing distortion-compensated signal;

[0026] Wherein, the higher the aliasing distortion degree, the larger the target order of the filter, and the lower the aliasing distortion degree, the smaller the target order of the filter.

[0027] Optionally, continue to perform at least one delay adjustment on the delay-adjusted signal until the currently delay-adjusted signal meets the first preset condition, or when the number of delay adjustments reaches a preset threshold, outputting the currently delay-adjusted signal includes:

[0028] The signal processing system divides the delay-adjusted signal into P - N parallel sub-digital signals; and after respectively performing delay adjustment on the P - N parallel sub-digital signals and then combining them, it is judged whether the currently delay-adjusted signal meets the first preset condition. If not, the currently delay-adjusted signal is divided into P - (N + 1) parallel sub-digital signals, and after respectively performing delay adjustment on the P - (N + 1) parallel sub-digital signals and then combining them, and so on, where N ∈ [1, P - 3], N is a positive integer, the value of N is 1 when performing delay adjustment again, and each time the delay adjustment increases by 1 until the currently delay-adjusted signal meets the first preset condition, or until the value of N is equal to P - 3, outputting the currently delay-adjusted signal, where when the value of N is equal to P - 3, the number of delay adjustments reaches the first preset threshold.

[0029] Second aspect, an embodiment of the present application provides a signal processing system, and the signal processing system includes:

[0030] A multiphase DPD module, a delay adjustment module, and a computing power scheduling optimization module;

[0031] The multiphase DPD module is configured to obtain a digital signal to be processed; and send the digital signal to be processed to the delay adjustment module;

[0032] The delay adjustment module is connected to the multiphase DPD module and is configured to receive the digital signal to be processed, perform delay adjustment on the digital signal to be processed to obtain a delay-adjusted signal; and send the delay-adjusted signal to the computing power scheduling optimization module;

[0033] The computing power scheduling optimization module is connected to the multiphase DPD module and is configured to receive the delay-adjusted signal, and when the delay-adjusted signal meets a first preset condition, output the delay-adjusted signal;

[0034] When the delay-adjusted signal does not meet the first preset condition and does not meet the second preset condition, perform aliasing distortion compensation on the delay-adjusted signal to obtain and output an aliasing distortion-compensated signal;

[0035] When the delay-adjusted signal does not meet the first preset condition but meets the second preset condition, return the delay-adjusted signal to the multiphase DPD module;

[0036] The multiphase DPD module is configured to send the delay-adjusted signal to the delay adjustment module;

[0037] The delay adjustment module is configured to continue to perform at least one delay adjustment on the delay-adjusted signal until the computing power scheduling optimization module determines that the currently delay-adjusted signal meets the first preset condition, or when the number of delay adjustments reaches a first preset threshold, the computing power scheduling optimization module outputs the currently delay-adjusted signal;

[0038] Wherein, the first preset condition is that the sum of the mean square error between the currently delay-adjusted signal and a preset target signal and the reciprocal of the signal-to-noise ratio of the currently delay-adjusted signal is less than a second preset threshold;

[0039] The second preset condition is that the signal-to-noise ratio of the delay-adjusted signal is greater than a third preset threshold.

[0040] Optionally, the polyphase DPD module is further configured to divide the digital signal to be processed into P parallel sub-digital signals; and send the P parallel sub-digital signals to the delay adjustment module, where P is a positive integer and is the number of polyphase branches supported by the signal processing system;

[0041] The delay adjustment module is configured to receive the P parallel sub-digital signals, perform delay adjustment on the P parallel sub-digital signals respectively, and then combine them to obtain the delay-adjusted signal.

[0042] Optionally, the computing power scheduling optimization module includes: a judgment switching module and an aliasing distortion compensation module;

[0043] The judgment switching module is connected to the delay adjustment module and the aliasing distortion compensation module, and is configured to receive the delay-adjusted signal, and when the delay-adjusted signal does not meet the first preset condition and does not meet the second preset condition, input the delay-adjusted signal to the aliasing distortion compensation module;

[0044] The aliasing distortion compensation module is configured to configure the order of a preset filter according to the aliasing distortion degree of the delay-adjusted signal;

[0045] Perform aliasing distortion compensation on the delay-adjusted signal through the filter to obtain an aliasing distortion-compensated signal; output the aliasing distortion-compensated signal.

[0046] Optionally, the aliasing distortion compensation module is further configured to calculate the signal-to-noise ratio of the delay-adjusted signal;

[0047] Perform normalization processing on the signal-to-noise ratio to obtain a normalized signal-to-noise ratio;

[0048] Determine the target order of the filter according to the normalized signal-to-noise ratio and the maximum order of the preset filter, and adjust the current order of the filter to the target order;

[0049] Perform aliasing distortion compensation on the delay-adjusted signal based on the filter to obtain an aliasing distortion-compensated signal;

[0050] Wherein, the higher the aliasing distortion degree, the larger the target order of the filter, and the lower the aliasing distortion degree, the smaller the target order of the filter.

[0051] Optionally, the polyphase DPD module is connected to the judgment switching module, and is further configured to receive the delay-adjusted signal returned by the judgment switching module when the judgment switching module determines that the delay-adjusted signal does not meet the first preset condition but meets the second preset condition;

[0052] Divide the signal after the delay adjustment into P - N parallel sub - digital signals; send the P - N parallel sub - digital signals to the delay adjustment module;

[0053] The delay adjustment module is configured to receive the P - N parallel sub - digital signals, perform delay adjustment on each of the P - N parallel sub - digital signals again and then merge them; and send the currently delay - adjusted signal to the judgment and switching module;

[0054] The judgment and switching module is configured to judge whether the currently delay - adjusted signal meets the first preset condition. If not, send the currently delay - adjusted signal to the multi - phase DPD module again;

[0055] The multi - phase DPD module is configured to divide the currently delay - adjusted signal into P - (N + 1) parallel sub - digital signals and send them to the delay adjustment module;

[0056] The delay adjustment module is configured to perform delay adjustment on each of the P - (N + 1) parallel sub - digital signals again and then merge them, and so on, where N ∈ [1, P - 3], N is a positive integer, the value of N is 1 when performing the delay adjustment again, and each time the delay adjustment increases by 1 until the judgment and switching module determines that the currently delay - adjusted signal meets the first preset condition, or until the value of N is equal to P - 3. The judgment and switching module outputs the currently delay - adjusted signal. When the value of N is equal to P - 3, the number of times of delay adjustment reaches the first preset threshold.

[0057] In a third aspect, an embodiment of the present application provides a network device, including: a processor, a memory, and a program stored on the memory and executable on the processor. When the program is executed by the processor, the steps of a signal processing method as described in the first aspect are implemented.

[0058] In a fourth aspect, an embodiment of the present application provides a computer - readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of a signal processing method as described in the first aspect are implemented.

[0059] In a fifth aspect, an embodiment of the present application provides a computer program product, including computer instructions. When the computer instructions are executed by a processor, the steps of a signal processing method as described in the first aspect are implemented.

[0060] In the embodiments of the present application, through multi-level conditional judgment and dynamic adjustment, digital signals can be effectively processed and optimized, ensuring that the finally output signals meet the expected standards in terms of quality and performance, improving the effect of digital predistortion, and reducing the cost and power consumption of hardware. Description of the Drawings

[0061] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present application. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0062] Figure 1 is a flowchart of a signal processing method provided by an embodiment of the present application;

[0063] Figure 2 is a flowchart of a signal processing method provided by an embodiment of the present application;

[0064] Figure 3 is a block diagram of the structure of a signal processing system provided by an embodiment of the present application;

[0065] Figure 4 is a block diagram of the structure of a signal processing system provided by an embodiment of the present application;

[0066] Figure 5 is a schematic diagram of the principle of aliasing cancellation realized by a dual-phase DPD module through delay adjustment provided by an embodiment of the present application;

[0067] Figure 6 is a block diagram of the structure of a network device provided by an embodiment of the present application. Detailed Embodiments

[0068] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0069] Figure 1 shows a signal processing method provided by an embodiment of the present application. The method is applied to a signal processing system and includes:

[0070] Step S101, the signal processing system acquires a digital signal to be processed and performs delay adjustment on the digital signal to be processed to obtain a signal after delay adjustment;

[0071] In step S101, the digital signal to be processed is subjected to delay adjustment to obtain the signal after delay adjustment, including: the signal processing system divides the digital signal to be processed into P parallel sub-digital signals; P is a positive integer and is the number of polyphase branches that the signal processing system can support; the signal processing system performs delay adjustment on the P parallel sub-digital signals respectively and then combines them to obtain the signal after delay adjustment.

[0072] Step S102: If the signal after delay adjustment meets the first preset condition, the signal processing system outputs the signal after delay adjustment;

[0073] Step S103: If the signal after delay adjustment does not meet the first preset condition and does not meet the second preset condition either, the signal processing system performs aliasing distortion compensation on the signal after delay adjustment to obtain and output the signal after aliasing distortion compensation;

[0074] In step S103, performing aliasing distortion compensation on the signal after delay adjustment to obtain and output the signal after aliasing distortion compensation includes: the signal processing system configures the order of a preset filter according to the aliasing distortion degree of the signal after delay adjustment; performs aliasing distortion compensation on the signal after delay adjustment through the filter to obtain the signal after aliasing distortion compensation; and outputs the signal after aliasing distortion compensation.

[0075] Step S104: If the signal after delay adjustment does not meet the first preset condition but meets the second preset condition, continue to perform at least one delay adjustment on the signal after delay adjustment until the currently adjusted signal meets the first preset condition or the number of delay adjustments reaches the first preset threshold, and then output the currently adjusted signal;

[0076] In step S104, continuing to perform at least one delay adjustment on the signal after delay adjustment until the currently adjusted signal meets the first preset condition or the number of delay adjustments reaches the preset threshold and then outputting the currently adjusted signal includes: the signal processing system divides the signal after delay adjustment into P - N parallel sub-digital signals; and performs delay adjustment on the P - N parallel sub-digital signals respectively again and then combines them, and determines whether the currently adjusted signal meets the first preset condition. If not, divides the currently adjusted signal into P - (N + 1) parallel sub-digital signals, and performs delay adjustment on the P - (N + 1) parallel sub-digital signals respectively again and then combines them, and so on, where N ∈ [1, P - 3], N is a positive integer, the value of N is 1 when performing delay adjustment again, and each time the delay adjustment increases by 1 until the currently adjusted signal meets the first preset condition, or until the value of N is equal to P - 3, and then outputs the currently adjusted signal. Among them, when the value of N is equal to P - 3, the number of delay adjustments reaches the first preset threshold.

[0077] It should be noted that the first preset condition is that the sum of the mean square error between the current delay-adjusted signal and the preset target signal and the reciprocal of the signal-to-noise ratio of the current delay-adjusted signal is less than the second preset threshold; the second preset condition is that the signal-to-noise ratio of the delay-adjusted signal is greater than the third preset threshold.

[0078] In a possible implementation, as Figure 2 shown, the signal processing system configures the order of a preset filter according to the aliasing distortion degree of the delay-adjusted signal, and compensates for the aliasing distortion of the delay-adjusted signal through the filter, and the obtained signal after aliasing distortion compensation includes:

[0079] Step S201, the signal processing system calculates the signal-to-noise ratio of the delay-adjusted signal;

[0080] Step S202, the signal processing system performs normalization processing on the signal-to-noise ratio to obtain the normalized signal-to-noise ratio;

[0081] Step S203, the signal processing system determines the target order of the filter according to the normalized signal-to-noise ratio and the maximum order of the preset filter, and adjusts the current order of the filter to the target order;

[0082] Step S204, the signal processing system performs aliasing distortion compensation on the delay-adjusted signal based on the filter to obtain the signal after aliasing distortion compensation;

[0083] Among them, the higher the aliasing distortion degree, the larger the target order of the filter, and the lower the aliasing distortion degree, the smaller the target order of the filter.

[0084] Through multi-level conditional judgment and dynamic adjustment, digital signals can be effectively processed and optimized, ensuring that the finally output signal meets the expected standards in terms of quality and performance, and can improve the effect of digital predistortion and reduce the cost and power consumption of hardware.

[0085] Figure 3 Fig. shows a signal processing system 30 according to an embodiment of the present application. The signal processing system 30 includes:

[0086] A multi-phase DPD module 301, a delay adjustment module 302, and a computing power scheduling and optimization module 303;

[0087] The multi-phase DPD module 301 is configured to obtain a digital signal to be processed; and send the digital signal to be processed to the delay adjustment module 302;

[0088] The delay adjustment module 302, connected to the multi-phase DPD module 301, is configured to receive the digital signal to be processed, perform delay adjustment on the digital signal to be processed to obtain a delayed and adjusted signal, and send the delayed and adjusted signal to the computing power scheduling optimization module 303;

[0089] The computing power scheduling optimization module 303, connected to the multi-phase DPD module 301, is configured to receive the delayed and adjusted signal, and output the delayed and adjusted signal when the delayed and adjusted signal meets the first preset condition;

[0090] When the delayed and adjusted signal does not meet the first preset condition and does not meet the second preset condition, perform aliasing distortion compensation on the delayed and adjusted signal to obtain and output the aliasing distortion compensated signal;

[0091] When the delayed and adjusted signal does not meet the first preset condition but meets the second preset condition, return the delayed and adjusted signal to the multi-phase DPD module 301;

[0092] The multi-phase DPD module 301 is configured to send the delayed and adjusted signal to the delay adjustment module 302;

[0093] The delay adjustment module 302 is configured to continue to perform at least one delay adjustment on the delayed and adjusted signal until the computing power scheduling optimization module 303 determines that the currently delayed and adjusted signal meets the first preset condition, or when the number of delay adjustments reaches the first preset threshold, the computing power scheduling optimization module 303 outputs the currently delayed and adjusted signal;

[0094] Wherein, the first preset condition is that the sum of the mean square error between the currently delayed and adjusted signal and the preset target signal and the reciprocal of the signal-to-noise ratio of the currently delayed and adjusted signal is less than the second preset threshold;

[0095] The second preset condition is that the signal-to-noise ratio of the delayed and adjusted signal is greater than the third preset threshold.

[0096] In a possible implementation, the multi-phase DPD module 301 is further configured to divide the digital signal to be processed into P parallel sub-digital signals, and send the P parallel sub-digital signals to the delay adjustment module 302, where P is a positive integer and is the number of multi-phase branches that the signal processing system 30 can support;

[0097] The delay adjustment module 302 is configured to receive the P parallel sub-digital signals, perform delay adjustment on the P parallel sub-digital signals respectively and then combine them to obtain a delayed and adjusted signal.

[0098] In a possible implementation, the computing power scheduling optimization module 303 includes: a judgment switching module and an aliasing distortion compensation module;

[0099] A judgment switching module, connected to the delay adjustment module 302 and also connected to the aliasing distortion compensation module, is configured to receive the signal after delay adjustment and input the signal after delay adjustment to the aliasing distortion compensation module when the signal after delay adjustment does not meet the first preset condition and does not meet the second preset condition;

[0100] The aliasing distortion compensation module is configured to configure the order of a preset filter according to the aliasing distortion degree of the signal after delay adjustment;

[0101] Perform aliasing distortion compensation on the signal after delay adjustment through the filter to obtain the signal after aliasing distortion compensation; output the signal after aliasing distortion compensation.

[0102] In a possible implementation manner, the aliasing distortion compensation module is further configured to calculate the signal-to-noise ratio of the signal after delay adjustment; perform normalization processing on the signal-to-noise ratio to obtain the normalized signal-to-noise ratio; determine the target order of the filter according to the normalized signal-to-noise ratio and the maximum order of the preset filter, and adjust the current order of the filter to the target order; perform aliasing distortion compensation on the signal after delay adjustment based on the filter to obtain the signal after aliasing distortion compensation; wherein, the higher the aliasing distortion degree, the larger the target order of the filter, and the lower the aliasing distortion degree, the smaller the target order of the filter.

[0103] In a possible implementation, the polyphase DPD module 301 is connected to the judgment and switching module. It is further configured to receive the signal after delay adjustment returned by the judgment and switching module when the judgment and switching module determines that the signal after delay adjustment does not meet the first preset condition but meets the second preset condition; divide the signal after delay adjustment into P - N parallel sub-digital signals; send the P - N parallel sub-digital signals to the delay adjustment module 302; the delay adjustment module 302 is configured to receive the P - N parallel sub-digital signals, perform delay adjustment on each of the P - N parallel sub-digital signals again and then merge them; and send the current signal after delay adjustment to the judgment and switching module; the judgment and switching module is configured to determine whether the current signal after delay adjustment meets the first preset condition. If not, it sends the current signal after delay adjustment to the polyphase DPD module 301 again; the polyphase DPD module 301 is configured to divide the current signal after delay adjustment into P - (N + 1) parallel sub-digital signals and send them to the delay adjustment module 302; the delay adjustment module 302 is configured to perform delay adjustment on each of the P - (N + 1) parallel sub-digital signals again and then merge them, and so on, where N ∈ [1, P - 3], N is a positive integer, the value of N is 1 when performing delay adjustment again, and each time the delay adjustment increases by 1 until the judgment and switching module determines that the current signal after delay adjustment meets the first preset condition, or until the value of N is equal to P - 3, and the judgment and switching module outputs the current signal after delay adjustment. When the value of N is equal to P - 3, the number of times of delay adjustment reaches the first preset threshold.

[0104] It should be noted that the problem to be solved by the embodiments of the present application is the computing power balance problem for high-precision digital pre-distortion processing, realizing the optimization of the system computing power while ensuring the linear pre-distortion processing effect. Through the novel delay adjustment module and computing power scheduling optimization module, the algorithm execution efficiency is further improved, the application efficiency of the hardware computing power is increased, and the flexible loading of the computing power module is realized.

[0105] Figure 4 Fig. shows a signal processing system according to an embodiment of the present application, as Figure 4 shown, the signal processing system mainly consists of a polyphase DPD module, a delay adjustment module, and a computing power scheduling optimization module, and the computing power scheduling optimization module can be further divided into a judgment and switching module and an aliasing distortion compensation module.

[0106] Now, several main modules will be introduced separately:

[0107] Multi-phase DPD Module: The basic idea of multi-phase is to divide the incoming data samples into multiple parallel signal processing chains. This module uses this idea to divide the input broadband digital signal x(n) into p parallel narrowband signals [x1(n), x2(n) … xp(n)] for digital pre-distortion processing to achieve the purpose of reducing the sampling rate. The downsampling rate is determined by P.

[0108] As Figure 4 shown, this module receives the signal S1 transmitted from the computing power scheduling optimization module and determines whether to adjust the sampling rate according to S1. If S1 = 1, it is considered that the signal processing system has serious aliasing and the number of signal branches should be reduced to increase the sampling rate. At this time, calculate p = q - L * S1, where the initial value of L is set to 0, and each time it is judged that S1 = 1 during the loop, the value of L is incremented by 1, that is, L = L + 1; q is the maximum number of multi-phase branches that the system can support, and p = q during the first processing; the lowest threshold value of the P value is designed to be 2. If it is calculated that q - L * S1 < 2, then assign P = 2.

[0109] If S1 = 0, the computing power scheduling optimization module determines that the output meets the system requirements. At this time, the size of P is fixed and subsequent work is carried out at a stable sampling rate.

[0110] Since partial aliasing distortion will occur in the signals during the low-sampling parallel processing, the p parallel signals are input into the delay adjustment module to separate the aliasing distortion from the desired signal.

[0111] Delay Adjustment Module:

[0112] This module dynamically adjusts the delays of the p parallel signals [x1(n), x2(n) … xp(n)] transmitted from the multi-phase DPD module to obtain the signals [y1(n - Δ1), y2(n - Δ2) … yp(n - Δp)], linearly adds the signals after adjusting the delays to obtain the signal y(n), and outputs it to the computing power scheduling optimization module for processing, where Δ is only related to p.

[0113] This module uses a variable tap delay filter (Delay Adjustment Filter, DAF) to achieve dynamic adjustment of signal delays. The variable tap delay filter has the advantages of high real-time performance, being able to process in parallel, and fine delay control. By setting the filter taps, it is possible to ensure appropriate group delay and a relatively flat amplitude response within the linearization bandwidth. Using the variable tap delay filter, signals with different delays can be generated in different branches according to the signal characteristics to prepare for subsequent aliasing cancellation, while precisely adjusting the group delay and reducing additional distortion. The specific implementation is as follows:

[0114] Taking the dual-phase DPD as an example, the realization of aliasing cancellation by delay adjustment is introduced. There is an additional group delay in the parallel signal components. The impact of the group delay is inverted by using a delay adjustment filter. A linear combination of the desired component and the aliased component is obtained in the upper branch. In the lower branch, the aliased component will have a 180° phase shift after adjustment. Therefore, after adjusting the group delay, the signal can be directly output to the parallel signal summation output module. After the parallel signals are added, the aliasing distortion will be cancelled, and the desired signal component will be obtained, as Figure 5 shown.

[0115] The obtained parallel desired signal components

y1(n-Δ1), y2(n-Δ2)…yp(n-Δp)

[0116] Since the coefficients of the filter do not change with the characteristics of the input signal of the Power Amplifier (PA), but are only related to the downsampling rate (coefficient P), the polyphase DPD module and the delay adjustment module can operate offline, and the sampling rate and the dynamic delay adjustment coefficient can be determined in advance according to the system performance requirements. In actual implementation, P and Δ can be regarded as constants. Under specific signal bandwidth and system performance requirements, the design of the downsampling rate P and the dynamic delay adjustment Δ can achieve a balance between system performance and complexity, thus reducing the overall computational complexity and design cost.

[0117] Computing power scheduling optimization module:

[0118] This module monitors the output y(n) of the delay adjustment module in real time and decides whether to continue the aliasing distortion compensation process and whether to adjust the downsampling rate according to the set judgment criteria. The design concept of this module is based on the precise control of system stability and the optimal allocation of computing power resources. By dynamically adjusting the allocation of computing power resources, the best digital predistortion effect can be achieved.

[0119] This module is divided into two parts: an aliasing distortion compensation module and a switching judgment module.

[0120] Switching judgment module: In the design of this module, a designable threshold is introduced to judge whether the system needs to adjust the downsampling rate and perform aliasing distortion compensation.

[0121] This module receives the output y(n) of the delay adjustment module. Based on the mean square error between y(n) and the ideal output t(n), as well as the signal-to-noise ratio of y(n), it obtains signal S1 and outputs it to the multi-phase DPD module. It determines whether the system needs further sampling adjustment. If not, it outputs signal y(n). If sampling adjustment is required, it further calculates signals S2 and S3 and outputs them to the aliasing distortion compensation module. It decides whether aliasing distortion compensation is needed according to S2. If aliasing distortion compensation is required, it configures the filter order according to the magnitude of signal S3. The specific implementation is as follows:

[0122] Calculate the mean square error between y(n) and t(n) to verify whether the output y(n) of the delay adjustment module can ensure that signal information is not lost. The calculation method is as follows:

[0123] ,

[0124] The smaller the mean square error, the closer y(n) is to the ideal output.

[0125] Calculate the signal-to-noise ratio of y(n) to verify whether the delay adjustment module has achieved precise cancellation of aliasing. The calculation method is as follows:

[0126] ,

[0127] Where Ps is the useful signal power and Pn is the noise power. In practical applications, it is desired that the MSE be as small as possible and the SNR be as large as possible. Therefore, the judgment for designing the delay adjustment module is switched to T1 = MSE + 1 / SNR. If T1 < m, it is considered that the output y(n) of the delay adjustment module meets the system output requirements, and S1 is assigned a value of 0, that is, the signal sampling rate and the delay state Δ are fixed. S2 is assigned a value of 0, that is, no further aliasing distortion compensation is required, avoiding unnecessary computational overhead, thus saving a large amount of computing power resources and directly outputting the signal y(n). m represents a designable threshold, which can be flexibly designed according to the actual capabilities of the circuit and the requirements of the application scenario. If T1 > m, it is considered that the output y(n) of the delay adjustment module does not meet the system output requirements, and S1 is assigned a value of 1, that is, the polyphase DPD module and the delay adjustment module need to be further adjusted. At this time, the signal-to-noise ratio SNR calculated from the output y(n) of the delay adjustment module is compared with the minimum acceptable signal-to-noise ratio SNRmin of the system. If SNR > SNRmin, it is considered that no anti-aliasing processing is required, and S2 is assigned a value of 0. At this time, the system does not output the signal and continues to perform sampling rate and delay adjustment. If SNR < SNRmin, S2 is assigned a value of 1, and the signal y(n) is transmitted to the aliasing distortion compensation module for processing, triggering the calculation of S3, which is used to determine the order of the filter in the aliasing distortion compensation module. The order of the filter in the aliasing distortion compensation module is determined by the noise level of y(n). If the signal-to-noise ratio of y(n) is close to the minimum acceptable signal-to-noise ratio of the system at this time, the order of the filter in the aliasing distortion compensation is reduced. If the signal-to-noise ratio at this time is significantly different from the minimum acceptable signal-to-noise ratio of the system, the order of the filter in the aliasing distortion compensation is increased to perform fine-grained anti-aliasing filtering. The specific implementation method is as follows: Normalize the signal-to-noise ratio calculated from the output y(n) of the delay adjustment module: , where SNRmin is the minimum acceptable signal-to-noise ratio of the system, and S3 = round(T2 × P), where round represents rounding to an integer and P represents the maximum order of the filter in the aliasing distortion compensation module. Although the design of this module consumes a certain amount of computing power resources, it can, to a certain extent, reduce the unnecessary computational burden while ensuring the accuracy of the output result and saving the overall computing resources.

[0128] Aliasing distortion compensation module: This module adopts a design with configurable filter order. It configures the filter order according to the degree of aliasing distortion in the system. This design can avoid unnecessary computational overhead, thus saving a large amount of computing power resources. According to the signals S2 and S3 transmitted from the switching judgment sub-module, anti-aliasing filtering is performed on y(n) and the signal z(n) is output. The specific implementation is as follows: This module uses a variable-order filter for anti-aliasing filtering, and monitors the signal S2 transmitted from the switching judgment sub-module in real time. If S2 = 0, this module does not work. If S2 = 1, it receives the signal S3 and y(n) transmitted from the switching judgment sub-module, configures the order of the filter according to the magnitude of S3, performs anti-aliasing filtering on the signal y(n), and outputs the signal z(n) after processing. The design of this module mainly enables flexible invocation of the anti-aliasing filter module according to the actual requirements of the system, rather than forcing anti-aliasing filtering in all cases, and can flexibly configure the filter order according to system requirements. This design can not only reduce unnecessary computational burden, but also help reduce the power consumption and cost of the hardware. For the released computing power resources, they can be invested in other key DFE (Decision Feedback Equalization) processes, thereby further improving the overall performance and computing power utilization rate of the system.

[0129] Generally speaking, the design of the computing power scheduling optimization module fully considers the stability of the system and the optimal allocation of computing power resources. Through real-time monitoring and dynamic adjustment, it not only helps improve the effect of digital pre-distortion, but also can reduce the cost and power consumption of the hardware. This is of great significance for improving the overall performance and reliability of the system.

[0130] Embodiments of this application provide a network device 60, as Figure 6 shown. The network device 60 includes: a processor 601, a memory 602, and a program stored on the memory 602 and executable on the processor 601. When the program is executed by the processor 601, it implements the steps of the signal processing method as shown in the above embodiments.

[0131] Embodiments of this application also provide a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, it implements the steps of the signal processing method as shown in the above embodiments and can achieve the same technical effects. To avoid repetition, it will not be elaborated here. Among them, the computer-readable storage medium is, for example, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disc, etc.

[0132] The embodiments of the present application also provide a computer program product, including computer instructions. When the computer instructions are executed by a processor, the steps of the above signal processing method are implemented, and the same technical effects can be achieved. To avoid repetition, details are not described here again.

[0133] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including such element.

[0134] Through the description of the above embodiments, those skilled in the art can clearly understand that the above embodiment method can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc), and includes several instructions for causing a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present application.

[0135] The embodiments of the present application have been described above with reference to the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

Claims

1. A signal processing method, characterized in that, The method is applied to a signal processing system, and the method includes: The signal processing system acquires a digital signal to be processed and performs delay adjustment on the digital signal to be processed to obtain a signal after delay adjustment; If the signal after delay adjustment meets a first preset condition, the signal processing system outputs the signal after delay adjustment; If the signal after delay adjustment does not meet the first preset condition and does not meet a second preset condition, the signal processing system performs aliasing distortion compensation on the signal after delay adjustment to obtain and output a signal after aliasing distortion compensation; If the signal after delay adjustment does not meet the first preset condition but meets the second preset condition, then at least one more delay adjustment is continued on the signal after delay adjustment until the currently adjusted signal meets the first preset condition or the number of delay adjustments reaches a first preset threshold, and the currently adjusted signal is output; Wherein, the first preset condition is that the sum of the mean square error between the currently adjusted signal and a preset target signal and the reciprocal of the signal-to-noise ratio of the currently adjusted signal is less than a second preset threshold; The second preset condition is that the signal-to-noise ratio of the signal after delay adjustment is greater than a third preset threshold.

2. The method according to claim 1, wherein, The performing delay adjustment on the digital signal to be processed to obtain a signal after delay adjustment includes: The signal processing system divides the digital signal to be processed into P parallel sub-digital signals; P is a positive integer and is the number of polyphase branches that the signal processing system can support; The signal processing system performs delay adjustment on the P parallel sub-digital signals respectively and then combines them to obtain the signal after delay adjustment.

3. The method according to claim 1, wherein The performing aliasing distortion compensation on the signal after delay adjustment to obtain and output a signal after aliasing distortion compensation includes: The signal processing system configures the order of a preset filter according to the aliasing distortion degree of the signal after delay adjustment; Performing aliasing distortion compensation on the signal after delay adjustment through the filter to obtain a signal after aliasing distortion compensation; and outputting the signal after aliasing distortion compensation.

4. The method according to claim 3, characterized in that The signal processing system configures the order of a preset filter according to the aliasing distortion degree of the signal after delay adjustment, and performs aliasing distortion compensation on the signal after delay adjustment through the filter to obtain a signal after aliasing distortion compensation includes: The signal processing system calculates the signal-to-noise ratio of the signal after delay adjustment; The signal processing system performs normalization processing on the signal-to-noise ratio to obtain a normalized signal-to-noise ratio; The signal processing system determines the target order of the filter according to the normalized signal-to-noise ratio and the maximum order of the preset filter, and adjusts the current order of the filter to the target order; The signal processing system performs aliasing distortion compensation on the signal after delay adjustment based on the filter to obtain a signal after aliasing distortion compensation; Wherein, the higher the aliasing distortion degree, the larger the target order of the filter, and the lower the aliasing distortion degree, the smaller the target order of the filter.

5. The method according to claim 2, wherein Continuously perform at least one delay adjustment on the signal after the delay adjustment until the signal after the current delay adjustment meets the first preset condition, or when the number of delay adjustments reaches the preset threshold, outputting the signal after the current delay adjustment includes: The signal processing system divides the signal after the delay adjustment into P - N parallel sub-digital signals; and performs delay adjustment on the P - N parallel sub-digital signals respectively and then combines them, and determines whether the signal after the current delay adjustment meets the first preset condition. If not, it divides the signal after the current delay adjustment into P - (N + 1) parallel sub-digital signals, and performs delay adjustment on the P - (N + 1) parallel sub-digital signals respectively and then combines them, and so on, where N ∈ [1, P - 3], N is a positive integer, the value of N is 1 when performing the delay adjustment again, and each time the delay adjustment increases by 1 until the signal after the current delay adjustment meets the first preset condition, or until the value of N is equal to P - 3, and outputs the signal after the current delay adjustment. Wherein, when the value of N is equal to P - 3, the number of delay adjustments reaches the first preset threshold.

6. A signal processing system, characterized in that, The signal processing system includes: A multi-phase digital pre-distortion DPD module, a delay adjustment module, and a computing power scheduling optimization module; The multi-phase DPD module is used to obtain the digital signal to be processed; and send the digital signal to be processed to the delay adjustment module; The delay adjustment module, connected to the multi-phase DPD module, is used to receive the digital signal to be processed, perform delay adjustment on the digital signal to be processed to obtain the signal after the delay adjustment; and send the signal after the delay adjustment to the computing power scheduling optimization module; The computing power scheduling optimization module, connected to the multi-phase DPD module, is used to receive the signal after the delay adjustment, and output the signal after the delay adjustment when the signal after the delay adjustment meets the first preset condition; When the signal after the delay adjustment does not meet the first preset condition and does not meet the second preset condition, perform aliasing distortion compensation on the signal after the delay adjustment to obtain and output the signal after the aliasing distortion compensation; When the signal after the delay adjustment does not meet the first preset condition but meets the second preset condition, return the signal after the delay adjustment to the multi-phase DPD module; The multi-phase DPD module is used to send the signal after the delay adjustment to the delay adjustment module; The delay adjustment module is used to continuously perform at least one delay adjustment on the signal after the delay adjustment until the computing power scheduling optimization module determines that the signal after the current delay adjustment meets the first preset condition, or when the number of delay adjustments reaches the first preset threshold, the computing power scheduling optimization module outputs the signal after the current delay adjustment; Wherein, the first preset condition is that the sum of the mean square error between the signal after the current delay adjustment and the preset target signal and the reciprocal of the signal-to-noise ratio of the signal after the current delay adjustment is less than the second preset threshold; The second preset condition is that the signal-to-noise ratio of the signal after the delay adjustment is greater than the third preset threshold.

7. The system according to claim 6, wherein: The polyphase DPD module is further configured to divide the digital signal to be processed into P parallel sub-digital signals; and send the P parallel sub-digital signals to the delay adjustment module, where P is a positive integer and is the number of polyphase branches that the signal processing system can support; The delay adjustment module is configured to receive the P parallel sub-digital signals, perform delay adjustment on each of the P parallel sub-digital signals respectively and then merge them to obtain the delay-adjusted signal.

8. The system according to claim 7, wherein: The computing power scheduling optimization module includes: a judgment switching module and an aliasing distortion compensation module; The judgment switching module is connected to the delay adjustment module and is also connected to the aliasing distortion compensation module, and is configured to receive the delay-adjusted signal, and when the delay-adjusted signal does not meet the first preset condition and does not meet the second preset condition, input the delay-adjusted signal to the aliasing distortion compensation module; The aliasing distortion compensation module is configured to configure the order of a preset filter according to the aliasing distortion degree of the delay-adjusted signal; Perform aliasing distortion compensation on the delay-adjusted signal through the filter to obtain an aliasing distortion-compensated signal; output the aliasing distortion-compensated signal.

9. The system according to claim 8, wherein: The aliasing distortion compensation module is further configured to calculate the signal-to-noise ratio of the delay-adjusted signal; Perform normalization processing on the signal-to-noise ratio to obtain a normalized signal-to-noise ratio; Determine the target order of the filter according to the normalized signal-to-noise ratio and the maximum order of the preset filter, and adjust the current order of the filter to the target order; Perform aliasing distortion compensation on the delay-adjusted signal based on the filter to obtain an aliasing distortion-compensated signal; Wherein, the higher the aliasing distortion degree, the larger the target order of the filter, and the lower the aliasing distortion degree, the smaller the target order of the filter.

10. The system according to claim 8, wherein: The polyphase DPD module is connected to the judgment switching module, and is further configured to receive the delay-adjusted signal returned by the judgment switching module when the judgment switching module determines that the delay-adjusted signal does not meet the first preset condition but meets the second preset condition; Divide the delay-adjusted signal into P-N parallel sub-digital signals; send the P-N parallel sub-digital signals to the delay adjustment module; The delay adjustment module is configured to receive the P-N parallel sub-digital signals, perform delay adjustment on each of the P-N parallel sub-digital signals respectively again and then merge them; and send the currently delay-adjusted signal to the judgment switching module; The judgment switching module is configured to judge whether the currently delay-adjusted signal meets the first preset condition, and if not, send the currently delay-adjusted signal to the polyphase DPD module again; The multi-phase DPD module is used to divide the currently delay-adjusted signal into P-(N+1) parallel sub-digital signals and send them to the delay adjustment module; The delay adjustment module is used to respectively perform delay adjustment on the P-(N+1) parallel sub-digital signals again and then merge them, and so on, where N∈[1, P-3], N is a positive integer, the value of N is 1 when performing delay adjustment again, and each delay adjustment increases by 1 until the judgment switching module determines that the currently delay-adjusted signal meets the first preset condition, or until the value of N is equal to P-3. The judgment switching module outputs the currently delay-adjusted signal. Wherein, when the value of N is equal to P-3, the number of times of delay adjustment reaches the first preset threshold.

11. A network device, characterized in that, Comprising: A processor, a memory, and a program stored on the memory and executable on the processor. When the program is executed by the processor, the steps of a signal processing method as described in any one of claims 1 to 5 are implemented.

12. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium. When the computer program is executed by the processor, the steps of a signal processing method as described in any one of claims 1 to 5 are implemented.

13. A computer program product, characterized in that, Comprising computer instructions. When the computer instructions are executed by the processor, the steps of a signal processing method as described in any one of claims 1 to 5 are implemented.

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