A HDMI receiver digital signal processing method and apparatus

Abstract

A digital signal processing method for an HDMI receiver provided by the present invention multiplexes each of the received three chrominance channel data into 8 registers of a register unit for 8-level caching. Each register caches 10-bit data and combines it with the chrominance channel data input by the 9th clock to output a 90-bit data sequence. The output 90-bit data sequence is detected. When 8 consecutive special character sequences are detected, a 10-bit special character sequence detection unit flag signal is generated and assigned according to the detection result. According to the generated special character sequence detection unit flag signal, the output value of the register unit is selected, and 8 special characters are continuously output as the starting point data for bit alignment. The three chrominance channel data after alignment processing are output after clock synchronization. The present invention also provides a digital signal processing device for an HDMI receiver.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and particularly relates to a method and device for processing digital signals at an HDMI receiving end. Background Art

[0002] High-Definition Multimedia Interface (HDMI), a digital video transmission standard based on Transition Minimized Differential Signaling (TMDS) encoding, uses three TMDS data channels and one TMDS clock channel to achieve high-speed data transmission. In an HDMI transmission system, the receiver can start working at any moment relative to the transmitter, which means that the receiver may start receiving data from any position in the transmitted data stream. Therefore, if the existing SerDes PHY IP (physical layer IP core of a serializer / deserializer) is directly docked with the TMDS data channels of the receiver, in the absence of bit alignment, the received data may be disordered and the original information cannot be accurately restored, thus failing to meet the user's usage requirements. At the same time, the aligned data also needs to be further synchronized in channels so that the processed video data can meet the usage requirements.

[0003] To solve the above problems, it is necessary to introduce a bit alignment unit and a channel synchronization unit. The main responsibility of the bit alignment unit is to identify the first data bit transmitted by the transmitter within each independent data channel to ensure that the receiver can correctly interpret the entire data frame. The channel synchronization unit is dedicated to dealing with the possible data skew problems between multiple data channels, that is, the inconsistent arrival times of data due to differences in physical lengths between different channels or other factors.

[0004] Therefore, it is necessary to improve the existing HDMI receiving end by adding a bit synchronization function and a channel synchronization function to the existing HDMI receiving end so that the received data will not be disordered. Summary of the Invention

[0005] The present invention provides a method for processing digital signals at an HDMI receiving end, which makes the data at the receiving end not disordered by adding a bit alignment function and a channel synchronization function at the receiving end.

[0006] The present invention also provides a device for processing digital signals at an HDMI receiving end, which makes the data at the receiving end not disordered by adding a bit alignment device and a channel synchronization device at the receiving end.

[0007] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or some or all of the above purposes or other purposes, a method for processing digital signals at the HDMI receiving end provided by a technical solution of the present invention multiplexes each of the three received chrominance channel data into 8 registers of a register unit for 8-level caching. Each register caches 10-bit data and combines it with the chrominance channel data input by the 9th clock to output a 90-bit data sequence; detects the output 90-bit data sequence, and when 8 consecutive special character sequences are detected, generates a 10-bit special character sequence detection unit flag signal and assigns a value according to the detection result; according to the generated special character sequence detection unit flag signal, selects the output value of the register unit and continuously outputs 8 special characters as the starting data for bit alignment; the three chrominance channel data after alignment processing are output after clock synchronization.

[0009] Generate 8 groups of data from the 90-bit data sequence output by the register unit with 10-bit data as a group; sequentially select one data value from the highest bit of the data sequence backward as the starting data for the 8 groups of data to generate 10 different groups of 8 groups of data; sequentially detect the generated 10 groups of 8 groups of data and determine whether there is a continuous 8 special character sequence.

[0010] If each 10-bit data in any one of the 8 groups of data is equal to the special character sequence, generate a special character sequence detection unit flag signal and assign 1 to the corresponding bit.

[0011] If each 10-bit data value in any one of the 8 groups of data is equal to any one of the special character sequences data_k1, data_k2, data_k3, or data_k4, generate a special character sequence detection unit flag signal and assign 1 to the corresponding bit.

[0012] According to the generation order of the 10 groups of 8 groups of data, sequentially detect each group of 8 groups of data in order, and assign a value to the special character sequence detection unit flag signal according to the detection order and the detection result. The detection result of each group of 8 groups of data corresponds to one assignment result of the 10-bit special character sequence detection unit flag signal; if any one of the 8 groups of data is equal to the special character sequence, the value of the corresponding bit of the special character sequence detection unit flag signal is 1.

[0013] Detect the generated special character sequence detection unit flag signal, and when the value of the special character sequence detection unit flag signal is not 0, generate a signal flag detection unit flag signal and set it to 0, and no longer perform special character sequence detection.

[0014] Based on the generated special character sequence detection unit flag signal, select the output value of the register unit, including selecting a number from 0 to 9 according to the special character sequence detection unit flag signal value, and selecting and outputting 10 consecutive bits of data from the 89th to 71st bits of the output value of the register unit.

[0015] The 3-channel chrominance channel data after alignment processing is subjected to clock synchronization processing, including writing the received 3-channel chrominance channel data into 3 storage devices respectively through the write address; counting the interval time of the special character sequence in the received 3-channel chrominance channel data, and generating a synchronization signal or an error signal according to the statistical result to indicate whether to perform data synchronization; when the synchronization signal is received, perform clock synchronization processing on the 3-channel chrominance channel data so that the data meets the synchronization requirements in terms of time.

[0016] Count the interval time of the special character sequence in the received 3-channel chrominance channel data, including setting 3 counters and setting the maximum count value of the counters. During the counting period, find the special character sequence in each data channel through the counters and output the count value. When the count value does not reach the maximum count value, perform a logical "AND" operation with the count value of the counter within the range from 0 to the maximum count value and output the counter flag signal; perform a logical "AND" operation on the counter flag signals generated by the 3 channels to generate an intermediate synchronization signal, and output the rising edge signal of the intermediate synchronization signal as the synchronization signal; otherwise, generate an error signal.

[0017] An HDMI receiver digital signal processing device provided by another technical solution of the present invention includes a bit alignment unit and a channel synchronization unit; the bit alignment unit includes a data register unit for receiving chrominance channel data, and the register unit multiplexes each of the received 3-channel chrominance channel data with 8 registers for 8-level caching. Each register caches 10 bits of data and combines it with the chrominance channel data input by the 9th clock to output a 90-bit data sequence; a special character sequence detection unit detects the data sequence, and when 8 consecutive special character sequences are detected, generates a special character sequence detection unit flag signal; a channel data selection unit generates a channel data selection unit flag signal according to the input special character sequence detection unit flag signal and inputs it to the chrominance channel data output unit; the chrominance channel data output unit selects the output value of the register unit according to the channel data selection unit flag signal and continuously outputs a target number of special characters as the bit alignment start point data; the chrominance channel data after completing the data alignment processing enters the channel synchronization unit and is output after clock synchronization.

[0018] When the signal flag detection unit flag signal output by the signal flag detection unit is 1, the special character sequence detection unit detects the special character sequence in the data sequence output by the register unit; the signal flag detection unit receives the special character sequence detection unit flag signal output by the special character sequence detection unit, and when the value of the special character sequence detection unit flag signal is not 0, generates a signal flag detection unit flag signal and sets it to 0.

[0019] The 90-bit data sequence output by the register unit is grouped into 8 groups with 10-bit data in each group; starting from the highest bit of the data sequence, one data value is sequentially selected backward as the start data of the 8 groups of data to generate 10 different groups of 8 groups of data; the generated 10 groups of 8 groups of data are sequentially detected, and it is judged whether there is a continuous sequence of 8 special characters; if each 10-bit data in any one of the 8 groups of data is equal to the special character sequence, a special character sequence detection unit flag signal is generated and the corresponding bit is assigned a value of 1.

[0020] According to the generation order of the 10 groups of 8 groups of data, each group of 8 groups of data is sequentially detected in order, and based on the detection order and the detection result, the special character sequence detection unit flag signal is assigned. The detection result of each group of 8 groups of data corresponds to the assignment result of one bit of the 10-bit special character sequence detection unit flag signal; if any one of the 8 groups of data is equal to the special character sequence, the value of the corresponding bit of the special character sequence detection unit flag signal is 1.

[0021] The channel data selection unit selects a number from 0 to 9 as the channel data selection unit flag signal according to the value of the special character sequence detection unit flag signal; the chrominance channel data output unit selects and outputs 10 consecutive bits of data from the 89th to 71st bits of the output value of the register unit according to the channel data selection unit flag signal.

[0022] The channel synchronization unit includes a data receiving unit, and the data receiving unit is provided with 3 storage devices for writing chrominance channel data; the data detection unit receives the 3-way chrominance channel data stored in the data receiving unit, calculates the mutual interval time of the special character sequences among the 3-way chrominance channel data, and generates a synchronization signal or an error signal; after receiving the synchronization signal, the data synchronization unit synchronizes the 3-way chrominance channel data stored in the data receiving unit under the clock signal.

[0023] The data detection unit includes three counters, sets the maximum count value of the counters, each counter receives a chrominance channel data respectively, and finds out the special character sequence in the three data channels through the counters within the counting period, and outputs the count value; a first logic judgment module, which is used to judge whether the count values of the three counters reach the maximum count value, and outputs a judgment signal when the maximum count value is reached; three first logic "AND" circuits, when the count value does not reach the maximum count value, perform a logic operation on the count value within the range of 0 to the maximum count value and the count value of the counter, and output a counter flag signal; a second logic "AND" circuit, which performs a logic operation on the three generated counter flag signals to generate an intermediate synchronization signal; a second logic judgment module, which outputs the high potential signal of the generated intermediate synchronization signal as a synchronization signal; a third logic "AND" circuit, which performs a logic operation on the low potential signal in the intermediate synchronization signal output by the second logic judgment module and the judgment signal, and outputs an error signal.

[0024] Compared with the prior art, the beneficial effects of the present invention mainly include: the present invention realizes the alignment and synchronization of multi-channel chrominance data by setting the bit alignment function and the channel synchronization function, reducing the risk of data disorder.

[0025] In order to make the above and other objects, features and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0027] Figure 1 Schematic diagram of the HDMI receiver digital signal processing device of the present invention.

[0028] Figure 2 Schematic diagram of the bit alignment unit structure of the present invention.

[0029] Figure 3 Schematic diagram of traversing the special character sequence of the present invention.

[0030] Figure 4 Schematic diagram of the channel synchronization unit structure of the present invention.

[0031] Figure 5 Schematic diagram of the data detection unit of the present invention.

[0032] Figure 6This is the data processing flow chart of the HDMI receiver end of the present invention. Specific embodiments

[0033] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0034] Embodiment 1

[0035] Embodiment 1 provides a method for processing digital signals at the HDMI receiver end. Each of the three received chrominance channel data is multiplexed with 8 registers of a register unit for 8-level buffering. Each register buffers 10-bit data, and the chrominance channel data input at the 9th clock is combined to form a 90-bit data sequence for output; the output 90-bit data sequence is detected. When 8 consecutive special character sequences are detected, a 10-bit special character sequence detection unit flag signal is generated and assigned according to the detection result; according to the generated special character sequence detection unit flag signal, the output value of the register unit is selected, and 8 special characters are continuously output as the starting point data for bit alignment; the three chrominance channel data after alignment processing are output after clock synchronization.

[0036] The following specifically explains the solution of Embodiment 1 of the present invention with reference to the drawings. See Figure 6 , a method for processing digital signals at the HDMI receiver end in Embodiment 1, includes the following steps:

[0037] Step S1: Bit alignment step, perform bit alignment operations on the three received chrominance channel data, specifically including:

[0038] Step S1-1: Through multiplexing 8 registers for 8-level buffering of the 3 chrominance channel data output by the physical layer IP core of the received serial deserializer. Each chrominance channel data corresponds to one component of a pixel point. The three chrominance channels jointly transmit a pixel point. Each chrominance channel data corresponds to 10-bit data. A pixel point is composed of 30-bit data. Each data is respectively combined with the chrominance channel data input at the 9th clock to form a 90-bit data sequence, and the register unit outputs a 90-bit data sequence;

[0039] The chrominance channel data of the 9th clock input here refers to: when the data in each chrominance channel undergoes bit alignment operation, the register caches 80 bits of data, and then combines it with the data of the 9th input of this channel. The digital video transmission standard HDMI (High-Definition Multimedia Interface) has three TMDS data channels and one TMDS clock channel. The TMDS clock channel provides a clock signal, and when the three TMDS data channels transmit data, they follow the clock signal for transmission.

[0040] Step S1-2: Receive a 90-bit data sequence and perform special character sequence detection. The specific detection method is to divide the 90-bit data sequence data_seq into 8 groups of data with each group being 10 bits. Then, starting from the highest bit of the data, select one bit of data in turn as the starting data of the 8 groups of data, generating 10 types of 8 groups of data. Traverse these 10 types of 8 groups of data in turn to determine whether 8 special character sequences can be continuously detected. When 8 special character sequences are continuously detected, generate a 10-bit special character sequence detection unit flag signal key_flag, and at the same time assign values to the corresponding bits of key_flag according to the detection results. The specific assignment process is referred to Figure 3 for description:

[0041] Figure 3 A total of 10 types of 8 groups of data are generated. These 10 types of 8 groups of data are obtained by combining 8 groups of consecutive data with each group being 10 bits from the 90-bit data sequence with each bit as the step value. During detection, it is also detected in the order of generation of the 10 types of 8 groups of data. For example Figure 3, first, the 8 groups of data generated in stage 1 are detected. Specifically, it is detected whether data_seq[89:80], data_seq[79:70], data_seq[69:60], data_seq[59:50], data_seq[49:40], data_seq[39:30], data_seq[29:20], and data_seq[19:10] are simultaneously equal to any one of the special character sequences data_k1, data_k2, data_k3, and data_k4. Here, the special character sequences data_k1, data_k2, data_k3, and data_k4 are control characters based on the TMDS coding technology in the HDMI protocol, and each special character sequence corresponds to a fixed 10-bit binary sequence. Each group of the 8 groups of data generated in step S1-2 has 10-bit data. Therefore, 10-bit data is used as a group for comparison, which is convenient for comparison. If they are equal, a special character sequence detection unit flag signal key_flag is generated and the highest bit of key_flag is set to 1. Otherwise, it is set to 0 and the detection in stage 2 is started. The detection in stage 2 is the same as that in stage 1. If there is also a special character sequence number in stage 2, the second highest bit of key_flag is set to 1. Otherwise, it is set to 0, and the detection in stage 3 is started. The above detection method is repeated until all 8 groups of data are detected, and then the finally assigned 10-bit special character sequence detection unit flag signal key_flag is obtained.

[0042] Step S1-3: Receive the special character sequence detection unit flag signal key_flag output by step S1-2 and perform detection. When the flag signal key_flag is not 0, a signal flag detection unit flag signal key_detect is generated and set to 0. When a sequence similar to the 8 special character sequences appears subsequently, it is determined as chrominance channel data, and the special character sequence detection link is no longer executed.

[0043] Step S1-4: According to the generated special character sequence detection unit flag signal key_flag, select the output value of the register unit, including selecting a number from 0 to 9 according to the value of the special character sequence detection unit flag signal, and selecting and outputting 10 consecutive bits of data from the 89-71st bits of the output value of the register unit. For example: when the generated value is 0, output [89:80]; when the generated value is 1, output [88:79], and so on. When the generated value is 9, output [80:71].

[0044] Step S1-5: Based on the register value output in Step S1-4, continuously output 8 special characters as the bit alignment starting point data. When the value generated in Step S1-4 remains unchanged, sequentially output the video or data island cycle data. When the value generated in Step S1-4 changes, do not transmit the video or data island cycle data, thus achieving the output after data alignment.

[0045] Step S2: For the three chrominance channel data with completed data bit alignment received, output them after clock synchronization, specifically including:

[0046] Step S2-1: Write the received 3-channel chrominance channel data into 3 storage devices respectively through the write address.

[0047] Step S2-2: Statistically analyze the interval time of the special character sequence in the received 3-channel chrominance channel data, and generate a synchronization signal or an error signal according to the statistical result, specifically including:

[0048] Step S2-21: Set 3 counters, and set the maximum count value of the counters, for example, set it to 15. During the counting cycle, find the special character sequence in each data channel through the counters, and output the count values cnt_clk0, cnt_clk1, cnt_clk2;

[0049] Step S2-22: When the count value does not reach the maximum count value, perform a logical "AND" operation within the range from 0 to the maximum count value (for example, within 0-15) with the count value of the counter, and output 3 counter flag signals cnt_clk0_r, cnt_clk1_r, cnt_clk2_r;

[0050] Step S2-23: Perform a logical "AND" operation on the 3 counter flag signals generated by the 3 channels to generate an intermediate synchronization signal data_out_ep;

[0051] Step S2-24: Use a logical judgment module to output the rising edge signal of the intermediate synchronization signal as the synchronization signal ep_en;

[0052] Step S2-3: When receiving the data synchronization signal ep_en, perform clock synchronization processing on the 3-channel chrominance channel data to make the data meet the synchronization requirements in terms of time.

[0053] Among them, the generated synchronization signal is used to indicate that within the maximum interval time range, the special character sequences of the three data channels can all be transmitted. Therefore, within the maximum interval time range, the three signals can be synchronized through the clock. When generating the error signal error_flag, it indicates that the special character sequences of the three data channels are too far apart from each other within the maximum interval time range, and at this time, it is meaningless to use the clock for synchronization.

[0054] Embodiment 2

[0055] Embodiment 2 provides an HDMI receiver digital signal processing device, including a bit alignment unit and a channel synchronization unit; the bit alignment unit includes a data register unit for receiving chrominance channel data, and the register unit multiplexes each of the received 3-channel chrominance channel data using 8 registers for 8-level caching. Each register caches 10-bit data and combines it with the chrominance channel data input at the 9th clock to output a 90-bit data sequence; a special character sequence detection unit detects the data sequence and generates a special character sequence detection unit flag signal when 8 consecutive special character sequences are detected; a channel data selection unit generates a channel data selection unit flag signal based on the input special character sequence detection unit flag signal and inputs it to the chrominance channel data output unit; the chrominance channel data output unit selects the output value of the register unit according to the channel data selection unit flag signal and continuously outputs a target number of special characters as bit alignment start data; the chrominance channel data after completing data alignment processing enters the channel synchronization unit and is output after clock synchronization.

[0056] The following combines the drawings to make a detailed description of the HDMI receiver digital signal processing device in this embodiment 2. See Figures 1 - 5 , the HDMI receiver digital signal processing device of the present invention includes a bit alignment unit and a channel synchronization unit. The specific structure of the bit alignment unit is as Figure 2 shown, including a data register unit, a special character sequence detection unit, a channel data selection unit, a chrominance channel data output unit, and a signal flag detection unit. The data register unit receives each of the 3-channel chrominance channel data respectively. The data register unit has multiple registers, and each register receives 10-bit chrominance channel data. The multiple registers in the data register unit perform multi-level caching on the received chrominance channel data and combine it with the chrominance channel data input at the 9th clock to output a 90-bit data sequence to the special character sequence detection unit for detection. The special character sequence detection unit detects whether there are 8 consecutive special character sequences in the data sequence when the signal flag detection unit flag signal key_detect output by the signal flag detection unit is 1, and outputs a special character sequence detection unit flag signal key_flag when there are 8 consecutive special character sequences. At the same time, assign values to the corresponding bits of key_flag according to the detection result. The specific assignment process refers to Figure 3 .

[0057] As an implementation manner, the process of the special character sequence detection unit for detecting special characters in the data sequence and assigning values can refer to step S1-2 in Embodiment 1 above, which will not be elaborated here.

[0058] The signal flag detection unit is further configured to receive the special character sequence detection unit flag signal key_flag output by the special character sequence detection unit, and when key_flag is not 0, generate the signal flag detection unit flag signal key_detect and set it to 0, and no longer execute the special character sequence detection link. After the signal flag detection unit is reset, key_detect is first set to 1, and the special character sequence detection is executed by default. When the special character sequence detection unit flag signal key_flag is not 0, key_detect is set to 0, indicating that the special code pattern sequence has been found. Subsequently, there is no need to detect the special character sequence again. Even if a sequence identical to the special character sequence appears, the special character sequence detection link is no longer executed, unless restarted.

[0059] The channel data selection unit receives the special character sequence detection unit flag signal key_flag output by the special character sequence detection unit and outputs the channel data selection unit flag signal data_pos. Specifically, according to the special character sequence detection unit flag signal key_flag, a number from 0 to 9 is selected and generated as the channel data selection unit flag signal data_pos.

[0060] The channel data selection unit flag signal data_pos is input to the chrominance channel data output unit. The chrominance channel data output unit selects the output value of the register unit according to the channel data selection unit flag signal data_pos. Specifically, 10 consecutive bits of data in the 89-71st bits of the output value of the output register unit are selected and output. For example: when the generated value is 0, [89:80] is output; when the generated value is 1, [88:79] is output, and so on. When the generated value is 9, [80:71] is output. At the same time, the chrominance channel data output unit continuously outputs a target number of special characters as the bit alignment start point data, thereby completing the bit alignment of the data.

[0061] See Figure 4 , the channel synchronization unit includes a data receiving unit, a data detecting unit, and a data synchronization unit. The data receiving unit is provided with 3 storage devices RAM1, RAM2, and RAM3, which are respectively used for writing 3 channels of aligned data ( Figure 4Taking the 10-bit data of each channel as an example for illustration); the data detection unit receives the three-channel chrominance channel data data0_en, data1_en, and data2_en stored in the data receiving unit, and calculates the mutual interval time of the special character sequences among the three-channel chrominance channel data, generating a synchronization signal or an error signal; after receiving the synchronization signal, the data synchronization unit synchronizes the three-channel chrominance channel data stored in the data receiving unit under the unit clock signal.

[0062] See Figure 5 , the data detection unit includes three counters, sets the maximum count value of the counters, and each counter receives one-channel chrominance channel data respectively. During the counting period, the special character sequences in the three data channels are found through the counters, and the count values cnt_clk0, cnt_clk1, and cnt_clk2 are output. The first logic judgment module ( Figure 5 the logic judgment 1 in Figure 5 ), is used to judge whether the count values of the three counters reach the maximum count value, and when the maximum count value is reached, a judgment signal (value is 0) is output. When the count values of the three counters do not reach the maximum count value ( Figure 5 the output value of the logic judgment 1 in

[0063] is 1), and logical operations are respectively performed with the count values of the counters within the range from 0 to the maximum count value through a logical "AND" circuit ( Figure 5 the logical AND 0, logical AND 1, and logical AND 2 in Figure 5 ), and three counter flag signals cnt_clk0_r, cnt_clk1_r, and cnt_clk2_r are output; Figure 5 the logical judgment 1 in Figure 5 ), and an error signal is output. It indicates that the special character sequences in the three data channels are too far apart from each other within the maximum interval time and cannot be synchronized.

[0064] After being detected by the data detection unit, the output synchronization signal and error signal are input into the data synchronization unit and synchronized by the clock clk_sync in the data synchronization unit.

[0065] The above has introduced in detail a method and device for digital signal processing at the HDMI receiving end provided by the present invention. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for processing digital signals at an HDMI receiving end, characterized in that: Each of the 3 chromaticity channel data received is cached in 8 levels using 8 registers of the register unit, each register caches 10 bits of data, and is combined with the chromaticity channel data input by the 9th clock into a 90-bit data sequence for output; Detect the output 90-bit data sequence, and when 8 consecutive special character sequences are detected, generate a 10-bit special character sequence detection unit flag signal and assign a value according to the detection result; The 90-bit data sequence output by the register unit is used as a group of 10 bits to generate 8 groups of data; starting from the highest bit of the data sequence, one bit of data value is selected backward in sequence as the start data of the 8 groups of data to generate 10 different 8 groups of data; the 10 generated 8 groups of data are detected in sequence to determine whether there is a continuous sequence of 8 special characters; According to the generated special character sequence detection unit flag signal, select the output value of the register unit, and continuously output 8 special characters as the starting point data of the bit alignment; The 3-channel chroma channel data is aligned and output after clock synchronization.

2. The HDMI receiving end digital signal processing method according to claim 1, characterized in that: If each of the 10-bit data in any of the 8 groups of data is equal to the special character sequence, a special character sequence detection unit flag signal is generated and the corresponding bit is assigned a value of 1; The special character sequence is a control character based on the TMDS encoding technology in the HDMI protocol, and each special character sequence corresponds to a fixed 10-bit binary sequence.

3. A method for processing digital signals at an HDMI receiving end according to claim 2, characterized in that: According to the generation order of 10 kinds of 8 groups of data, each kind of 8 groups of data is detected in sequence, and according to the detection order and the detection result, the special character sequence detection unit flag signal is assigned a value, and each kind of 8 groups of data detection result corresponds to a one-bit assignment result of the 10-bit special character sequence detection unit flag signal; If any of the 8 groups of data is equal to the special character sequence, the special character sequence detection unit flag signal value of the corresponding position is 1.

4. The method for processing digital signals at an HDMI receiving end according to claim 1, wherein: The generated special character sequence detection unit flag signal is detected, and when the special character sequence detection unit flag signal value is not 0, a signal flag detection unit flag signal is generated and set to 0, and no special character sequence detection is performed.

5. The method for processing digital signals at an HDMI receiving end according to claim 1, wherein: According to the generated special character sequence detection unit flag signal, the output value of the register unit is selected, including selecting to generate a number from 0-9 according to the special character sequence detection unit flag signal value, and selecting continuous 10 bits of data from the 89th to 71st bits of the output value of the register unit.

6. The HDMI receiving end digital signal processing method according to claim 1, characterized in that: The aligned 3-channel chromaticity channel data are processed using clock synchronization, including writing the received 3-channel chromaticity channel data into 3 storage devices respectively through write addresses; Count the interval time of the special character sequence in the received 3-channel chrominance channel data, and generate a synchronization signal or an error signal according to the statistical result to indicate whether to perform data synchronization; After receiving the synchronization signal, the clock synchronization processing is performed on the 3-channel chrominance channel data so that the data meets the synchronization requirements in time.

7. A method for processing digital signals at an HDMI receiving end according to claim 6, characterized in that: The time interval of the special character sequence in the received 3-channel chrominance channel data is counted, including setting 3 counters and setting the maximum count value of the counters, finding the special character sequence in each data channel through the counters within the counting cycle, outputting the count value, and performing a logical "AND" operation with the count value of the counter within the range of 0 to the maximum count value when the count value does not reach the maximum count value, and outputting a counter flag signal; Perform a logic "AND" operation on the counter flag signals generated by the three channels to generate an intermediate synchronization signal, and output the rising edge signal of the intermediate synchronization signal as the synchronization signal; Otherwise an error signal is generated.

8. A HDMI receiving end digital signal processing device, characterized in that: including a bit alignment unit and a channel synchronization unit; The bit alignment unit includes a data register unit for receiving chroma channel data, wherein the register unit multiplexes each of the 3 chroma channel data received into 8 registers for 8-level cache, each register caches 10 bits of data, and combines the data with the chroma channel data input by the 9th clock into a 90-bit data sequence for output; A special character sequence detection unit detects the data sequence and generates a special character sequence detection unit flag signal when eight special character sequences are detected continuously; The 90-bit data sequence output by the register unit is used as a group of 10 bits to generate 8 groups of data; starting from the highest bit of the data sequence, one bit of data value is selected backward in sequence as the start data of the 8 groups of data to generate 10 different 8 groups of data; the 10 generated 8 groups of data are detected in sequence to determine whether there is a continuous sequence of 8 special characters; The channel data selection unit generates a channel data selection unit flag signal according to the input special character sequence detection unit flag signal and inputs the signal to the chrominance channel data output unit; The chroma channel data output unit selects the register unit output value according to the channel data selection unit flag signal, and continuously outputs a target number of special characters as bit alignment starting point data; The chrominance channel data that has completed the data alignment process enters the channel synchronization unit and is output after being synchronized with the clock.

9. The HDMI receiving end digital signal processing device according to claim 8, characterized in that: The special character sequence detection unit detects the special character sequence in the data sequence output by the register unit when the signal flag detection unit flag signal output by the signal flag detection unit is 1; The signal flag detection unit receives the special character sequence detection unit flag signal output by the special character sequence detection unit, and generates a signal flag detection unit flag signal and sets it to 0 when the value of the special character sequence detection unit flag signal is not 0.

10. The HDMI receiving end digital signal processing device according to claim 8, characterized in that: If each of the 10-bit data in any of the 8 groups of data is equal to the special character sequence, a special character sequence detection unit flag signal is generated and the corresponding bit is assigned a value of 1; The special character sequence is a control character based on the TMDS encoding technology in the HDMI protocol, and each special character sequence corresponds to a fixed 10-bit binary sequence.

11. The HDMI receiving end digital signal processing device according to claim 10, characterized in that: According to the generation order of 10 kinds of 8 groups of data, each kind of 8 groups of data is detected in sequence, and according to the detection order and the detection result, the special character sequence detection unit flag signal is assigned a value, and each kind of 8 groups of data detection result corresponds to a one-bit assignment result of the 10-bit special character sequence detection unit flag signal; If any of the 8 groups of data is equal to the special character sequence, the special character sequence detection unit flag signal value of the corresponding position is 1.

12. The HDMI receiving end digital signal processing device according to claim 8, characterized in that: The channel data selection unit selects a number from 0 to 9 as the channel data selection unit flag signal according to the special character sequence detection unit flag signal value; The chrominance channel data output unit selects continuous 10 bits of data from bits 89 to 71 of the output value of the output register unit according to the channel data selection unit flag signal.

13. The HDMI receiving end digital signal processing device according to claim 8, characterized in that: The channel synchronization unit includes a data receiving unit, and the data receiving unit is provided with three storage devices for writing chrominance channel data; The data detection unit receives the 3-channel chromaticity channel data stored in the data receiving unit, calculates the time intervals between the special character sequences between the 3-channel chromaticity channel data, and generates a synchronization signal or an error signal; After receiving the synchronization signal, the data synchronization unit synchronously processes the three chromaticity channel data stored in the data receiving unit under the clock signal.

14. The HDMI receiving end digital signal processing device according to claim 13, characterized in that: The data detection unit includes three counters, the maximum count value of the counters is set, each counter receives one channel of chrominance channel data respectively, finds out the special character sequence in the three data channels through the counter within the counting cycle, and outputs the count value; The first logic judgment module is used to judge whether the count values ​​of the three counters have reached the maximum count value, and output a judgment signal when the maximum count value is reached; 3 first logic "AND" circuits, when the count value does not reach the maximum count value, perform a logic operation on the count value within the range of 0 to the maximum count value and the count value of the counter, and output a counter flag signal; a second logic "AND" circuit, performing a logic operation on the three generated counter flag signals to generate an intermediate synchronization signal; A second logic judgment module outputs the generated high potential signal of the intermediate synchronization signal as a synchronization signal; A third logic “AND” circuit performs a logic operation on the low potential signal in the intermediate synchronization signal output by the second logic judgment module and the judgment signal, and outputs an error signal.

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