Audio SOC chip, audio subsystem interface module thereof and electronic equipment

Abstract

The invention relates to an audio SOC chip, an audio subsystem interface module thereof, and electronic equipment, and the audio subsystem interface module comprises a plurality of downlink path units which are used for carrying out the downlink processing of at least one path of digital audio data obtained from an application processor chip and / or a digital signal processing chip through a peripheral bus interface module, the audio data is output through the audio data transmission interface module; the plurality of uplink path units are used for performing uplink processing on at least one path of digital audio data input through the audio data transmission interface module and outputting the processed data to the application processor chip and / or the digital signal processing chip through the peripheral bus interface module; and the plurality of loopback path units are used for converging the at least one path of digital audio data input through the audio data transmission interface module and the digital audio data obtained by performing downlink processing through any downlink path unit in the plurality of downlink path units, and outputting the digital audio data through the audio data transmission interface module, so that the power consumption of a chip is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of audio SOC chips, and in particular, to an audio SOC chip, an audio subsystem interface module thereof, and an electronic device. Background Art

[0002] With the multi-functionalization of intelligent devices such as mobile phones and smart watches, they need to interact efficiently with various peripherals such as Bluetooth headsets and microphones to support functions such as high-definition audio playback, voice assistant response, and noise cancellation. The addition of these functions has led to an increased demand for the internal resources of audio SOC (System on Chip) chips, especially the AP (Application Processor) and DSP (Digital Signal Processing) chips.

[0003] As the core processor chips, the AP and DSP are responsible for processing complex computing tasks, but their frequent use will cause a significant increase in the power consumption of the chip. Therefore, how to reduce the power consumption of the audio SOC chip has become an urgent problem to be solved at present. Summary of the Invention

[0004] The present disclosure provides an audio subsystem interface module used in an audio SOC chip. Through the audio subsystem interface module, complex sound effect processing, sampling rate processing, routing processing, and other large computing logics can be implemented in the form of hardware, thereby reducing the power consumption of the audio SOC chip. The technical solution of the present disclosure is as follows:

[0005] In a first aspect embodiment of the present disclosure, an audio subsystem interface module in an audio SOC chip is proposed. The audio subsystem interface module is connected between a peripheral bus interface module and an audio data transmission interface module. The peripheral bus interface module is also connected to an application processor chip and a digital signal processing chip. The audio subsystem interface module includes:

[0006] A plurality of downlink path units, configured to perform downlink processing on at least one path of digital audio data obtained from the application processor chip and / or the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module;

[0007] A plurality of uplink path units, configured to perform uplink processing on at least one path of digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing through the peripheral bus interface module to the application processor chip and / or the digital signal processing chip;

[0008] Multiple loopback path units are configured to converge at least one digital audio data input through the audio data transmission interface module and the digital audio data obtained after downlink processing through any one of the multiple downlink path units, and output the converged digital audio data through the audio data transmission interface module.

[0009] In one embodiment of the present disclosure, the multiple downlink path units include:

[0010] A first downlink path, which includes a first data buffer AP-FIFO, a first frequency control module AP-FC0, a first sample rate conversion module AP-SRC, a second frequency control module AP-FC1, a first convergence point, a first sound effect processing module DA0-SE0, a third frequency control module DA0-FC2, a second sound effect processing module DA-SE1, a first synchronous first-in first-out data buffer SFIFO-DA0, and a second convergence point connected in sequence; wherein, the input end of the first data buffer AP-FIFO is connected to the first output end of the peripheral bus interface module, the output end of the second convergence point is connected to the first input end of the audio data transmission interface module, and the first downlink path is configured to perform downlink processing on the first digital audio data obtained from the application processor chip through the peripheral bus interface module, and output the digital audio data obtained after downlink processing through the audio data transmission interface module;

[0011] A second downlink path, which includes a second data buffer DA0-FIFO, a fourth frequency control module DA0-FC0, a second sample rate conversion module DA0-SRC, a fifth frequency control module DA0-FC1, the first convergence point, the first sound effect processing module DA0-SE0, the third frequency control module DA0-FC2, the second sound effect processing module DA-SE1, the first synchronous first-in first-out data buffer SFIFO-DA0, and the second convergence point connected in sequence; wherein, the input end of the second data buffer DA0-FIFO is connected to the second output end of the peripheral bus interface module, and the second downlink path is configured to perform downlink processing on the second digital audio data obtained from the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after downlink processing through the audio data transmission interface module;

[0012] The third downlink path, the third downlink path includes a third data buffer DA1-FIFO, a sixth frequency control module DA1-FC0, a third sample rate conversion module DA1-SRC0, a seventh frequency control module DA1-FC1, a third audio processing module DA1-SE0, an eighth frequency control module DA1-FC2, the second audio processing module DA-SE1, a second synchronous first-in first-out data buffer SFIFO-DA1, a third convergence point, a fourth sample rate conversion module DA1-SRC1, and a third synchronous first-in first-out data buffer SFIFO-DA1-SRC1. The input end of the third data buffer DA1-FIFO is connected to the third output end of the peripheral bus interface module. The output end of the third synchronous first-in first-out data buffer SFIFO-DA1-SRC1 is connected to the second input end of the audio data transmission interface module. The third downlink path is used to perform downlink processing on the third digital audio data obtained from the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module.

[0013] In an embodiment of the present disclosure, the multiple uplink path units include:

[0014] The first uplink path, the first uplink path includes a fifth sample rate conversion module AD1-SRC0, a fourth audio processing module AD1-SE, a fifth audio processing module AD0-SE, a multiplexer AP-MUX, and a second frequency control module AP-FC1, a first sample rate conversion module AP-SRC, a first frequency control module AP-FC0, and a first data buffer AP-FIFO connected in sequence to the output end of the multiplexer AP-MUX. Among them, the fifth sample rate conversion module AD1-SRC0 and the fourth audio processing module AD1-SE are connected in series and then connected to the first input end of the multiplexer AP-MUX. The fifth audio processing module AD0-SE is connected to the second input end of the multiplexer AP-MUX. The input end of the fifth sample rate conversion module AD1-SRC0 is connected to the first output end of the audio data transmission interface module. The input end of the fifth audio processing module AD0-SE is connected to the second output end of the audio data transmission interface module. The first uplink path is used to perform uplink processing on the fourth digital audio data and the fifth digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing to the application processor chip through the peripheral bus interface module;

[0015] The second upstream path, which includes a fourth audio effect processing module AD0-SE, a sixth sampling rate conversion module AD0-SRC, and a fourth data buffer AD0-FIFO connected in sequence. The second upstream path is used to perform upstream processing on the fourth digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the upstream processing to the digital signal processing chip through the peripheral bus interface module;

[0016] The third upstream path, which includes the fifth sampling rate conversion module AD1-SRC0, the fifth audio effect processing module AD1-SE, the seventh sampling rate conversion module AD1-SRC1, and the fifth data buffer AD1-FIFO connected in sequence. The third upstream path is used to perform upstream processing on the fifth digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the upstream processing to the digital signal processing chip through the peripheral bus interface module.

[0017] In an embodiment of the present disclosure, the multiple loop path units include:

[0018] The first loop path, which includes the fifth sampling rate conversion module AD1-SRC0, the loop path module ST, the fourth synchronous first-in-first-out data buffer SFIFO-ST-DA0, and the second downstream path. Among them, the first input end of the loop path module ST is connected to the first output end of the audio data transmission interface module through the fifth sampling rate conversion module AD1-SRC0, the second input end of the loop path module ST is connected to the second output end of the audio data transmission interface module, the first output end of the loop path module ST is connected to the second convergence point through the fourth synchronous first-in-first-out data buffer SFIFO-ST-DA0. The first loop path is used to converge the fourth digital audio data and the fifth digital audio data input through the audio data transmission interface module with the digital audio data obtained after the downstream processing through the second downstream path unit, and output the digital audio data obtained after the convergence processing through the audio data transmission interface module;

[0019] The second loop path, the second loop path includes the fifth sampling rate conversion module AD1-SRC0, the loop path module ST, the fifth synchronous first-in first-out data buffer SFIFO-ST-DA1, and the third downlink path; wherein, the second output end of the loop path module ST is connected to the third convergence point through the fifth synchronous first-in first-out data buffer SFIFO-ST-DA1, and the second loop path is used to converge the fourth digital audio data and the fifth digital audio data input through the audio data transmission interface module with the digital audio data obtained after downlink processing through the third downlink path unit, and output the converged digital audio data through the audio data transmission interface module.

[0020] In an embodiment of the present disclosure, the second downlink path is open, the first downlink path is closed, the third downlink path is closed, the first audio effect processing module DA0-SE0 is closed, and the second audio effect processing module DA-SE1 is closed. The backpressure logic on the audio subsystem interface module includes the following steps:

[0021] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as the backpressure signal to backpressure the fourth frequency control module DA0-FC0 to control the output speed of the fourth frequency control module DA0-FC0.

[0022] The fourth frequency control module DA0-FC0 generates a speed control signal to control the speed at which the first digital audio data output from the digital signal processing chip through the peripheral bus interface module flows into the second data buffer DA0-FIFO.

[0023] In an embodiment of the present disclosure, the second downlink path is open, the third downlink path is closed, the first downlink path is open, the first audio effect processing module DA0-SE0 is open, and the second audio effect processing module DA-SE1 is closed. The backpressure logic on the audio subsystem interface module includes the following steps:

[0024] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as the backpressure signal to backpressure the first synchronous first-in first-out data buffer SFIFO-DA0 to control the output speed of the first synchronous first-in first-out data buffer SFIFO-DA0.

[0025] Use the almost full signal of the first synchronous first-in first-out data buffer SFIFO-DA0 as the backpressure signal to backpressure the third frequency control module DA0-FC2 to control the output speed of the third frequency control module DA0-FC2.

[0026] The third frequency control module DA0-FC2 generates a speed control signal to synchronously backpressure the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, so as to control the output speeds of the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1;

[0027] The fifth frequency control module DA0-FC1 generates a speed control signal to backpressure the fourth frequency control module DA0-FC0, so as to control the output speed of the fourth frequency control module DA0-FC0, and the second frequency control module AP-FC1 generates a speed control signal to backpressure the first frequency control module AP-FC0, so as to control the output speed of the first frequency control module AP-FC0;

[0028] The fourth frequency control module DA0-FC0 and the first frequency control module AP-FC0 generate corresponding speed control signals to correspondingly control the speeds at which the first digital audio data output from the application processor chip flows into the first data buffer AP-FIFO and the second digital audio data output from the digital signal processing chip flows into the second data buffer DA0-FIFO through the peripheral bus interface module.

[0029] In an embodiment of the present disclosure, the second downlink path is open, the third downlink path is closed, the first downlink path is open, the first audio effect processing module DA0-SE0 is open, and the second audio effect processing module DA-SE1 is open. The backpressure logic on the audio subsystem interface module includes the following steps:

[0030] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to synchronously backpressure the first synchronous first-in-first-out data buffer SFIFO-DA0 and the second synchronous first-in-first-out data buffer SFIFO-DA1, so as to correspondingly control the output speeds of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the second synchronous first-in-first-out data buffer SFIFO-DA1;

[0031] Use the almost full signal of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the almost full signal of the second synchronous first-in-first-out data buffer SFIFO-DA1 as backpressure signals to backpressure the third frequency control module DA0-FC2, so as to control the output speed of the third frequency control module DA0-FC2;

[0032] The third frequency control module DA0-FC2 generates a speed control signal to backpressure the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, so as to control the output speeds of the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1;

[0033] The fifth frequency control module DA0-FC1 generates a speed control signal to backpressure the fourth frequency control module DA0-FC0, so as to control the output of the fourth frequency control module DA0-FC0, and the second frequency control module AP-FC1 generates a speed control signal to backpressure the first frequency control module AP-FC0, so as to control the output speed of the first frequency control module AP-FC0;

[0034] The fourth frequency control module DA0-FC0 and the first frequency control module AP-FC0 respectively generate corresponding speed control signals to respectively control the speed at which the first digital audio data output from the application processor chip flows into the first data buffer AP-FIFO and the speed at which the second digital audio data output from the digital signal processing chip flows into the second data buffer DA0-FIFO through the peripheral bus interface module.

[0035] In an embodiment of the present disclosure, when the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is closed, the second audio effect processing module DA-SE1 is closed, and the fourth sampling rate conversion module DA1-SRC1 is closed, the backpressure logic on the audio subsystem interface module includes the following steps:

[0036] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0;

[0037] The sixth frequency control module DA1-FC0 generates a speed control signal to control the speed at which the third digital audio data output from the digital signal processing chip flows into the third data buffer DA1-FIFO through the peripheral bus interface module.

[0038] In an embodiment of the present disclosure, when the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is closed, the second audio effect processing module DA-SE1 is closed, and the fourth sampling rate conversion module DA1-SRC1 is open, the backpressure logic on the audio subsystem interface module includes the following steps:

[0039] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, so as to control the output speed of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1;

[0040] Use the almost-full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 as a backpressure signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0;

[0041] The sixth frequency control module DA1-FC0 generates a speed control signal to control the speed at which the third digital audio data output from the digital signal processing chip flows into the third data buffer DA1-FIFO through the peripheral bus interface module.

[0042] In an embodiment of the present disclosure, when the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is open, the second audio effect processing module DA-SE1 is closed, and the fourth sampling rate conversion module DA1-SRC1 is open, the backpressure logic on the audio subsystem interface module includes the following steps:

[0043] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, so as to control the output speed of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1;

[0044] Use the almost-full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 as a backpressure signal to backpressure the second synchronous first-in-first-out data buffer SFIFO-DA1, so as to control the output speed of the second synchronous first-in-first-out data buffer SFIFO-DA1;

[0045] Use the almost-full signal of the second synchronous first-in-first-out data buffer SFIFO-DA1 as a backpressure signal to backpressure the eighth frequency control module DA1-FC2, so as to control the output speed of the eighth frequency control module DA1-FC2;

[0046] The eighth frequency control module DA1-FC2 generates a speed control signal to backpressure the seventh frequency control module DA1-FC1, so as to control the output speed of the seventh frequency control module DA1-FC1;

[0047] The seventh frequency control module DA1-FC1 generates a speed control signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0;

[0048] The sixth frequency control module DA1-FC0 generates a speed control signal to backpressure the third data buffer DA1-FIFO, so as to control the speed at which the third digital audio data output from the digital signal processing chip flows into the third data buffer DA1-FIFO through the peripheral bus interface module.

[0049] In an embodiment of the present disclosure, when the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is open, the second audio effect processing module DA-SE1 is open, and the fourth sampling rate conversion module DA1-SRC1 is open, the backpressure logic on the audio subsystem interface module includes the following steps:

[0050] Using the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the first synchronous first-in first-out data buffer SFIFO-DA0 and the third synchronous first-in first-out data buffer SFIFO-DA1-SRC1, so as to control the output speeds of the first synchronous first-in first-out data buffer SFIFO-DA0 and the third synchronous first-in first-out data buffer SFIFO-DA1-SRC1;

[0051] Using the almost full signal of the third synchronous first-in first-out data buffer SFIFO-DA1_SRC1 as a backpressure signal to backpressure the second synchronous first-in first-out data buffer SFIFO-DA1, so as to control the output speed of the second synchronous first-in first-out data buffer SFIFO-DA1;

[0052] Using the almost full signals of the first synchronous first-in first-out data buffer SFIFO-DA0 and the second synchronous first-in first-out data buffer SFIFO-DA1 to jointly backpressure the eighth frequency control module DA1-FC2, so as to control the output speed of the eighth frequency control module DA1-FC2;

[0053] The eighth frequency control module DA1-FC2 generates a speed control signal to backpressure the seventh frequency control module DA1-FC1, so as to control the output speed of the seventh frequency control module DA1-FC1;

[0054] The seventh frequency control module DA1-FC1 generates a speed control signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0;

[0055] The sixth frequency control module DA1-FC0 generates a speed control signal to backpressure the third data buffer DA1-FIFO, so as to control the speed at which the third-channel digital audio data output from the digital signal processing chip flows into the third data buffer DA1-FIFO through the peripheral bus interface module.

[0056] In an embodiment of the present disclosure, all modules on the second downlink path and the third downlink path are turned on, and the backpressure logic on the audio subsystem interface module includes the following steps:

[0057] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the first synchronous first-in-first-out data buffer SFIFO-DA0 and the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, so as to control the output speed of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1;

[0058] Use the almost full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1_SRC1 as a backpressure signal to backpressure the second synchronous first-in-first-out data buffer SFIFO-DA1, so as to control the output speed of the second synchronous first-in-first-out data buffer SFIFO-DA1;

[0059] Use the almost full signals of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the second synchronous first-in-first-out data buffer SFIFO-DA1 to backpressure the third frequency control module DA0-FC2 and the eighth frequency control module DA1-FC2, so as to jointly control the output speeds of the third frequency control module DA0-FC2 and the eighth frequency control module DA1-FC2;

[0060] The third frequency control module DA0-FC2 generates a speed control signal to backpressure the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, so as to control the output speeds of the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, and the eighth frequency control module DA1-FC2 generates a speed control signal to backpressure the seventh frequency control module DA1-FC1, so as to control the output speed of the seventh frequency control module DA1-FC1;

[0061] The fifth frequency control module DA0-FC1 generates a speed control signal to reverse bias the fourth frequency control module DA0-FC0, so as to control the output speed of the fourth frequency control module DA0-FC0; the seventh frequency control module DA1-FC1 generates a speed control signal to reverse bias the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0; the second frequency control module AP-FC1 generates a speed control signal to reverse bias the first frequency control module AP-FC0, so as to control the output speed of the first frequency control module AP-FC0.

[0062] The fourth frequency control module DA0-FC0 generates a speed control signal to control the speed at which the second path of digital audio data output from the digital signal processing chip flows into the second data buffer DA0-FIFO through the peripheral bus interface module; the sixth frequency control module DA1-FC0 generates a speed control signal to control the speed at which the third path of digital audio data output from the digital signal processing chip flows into the third data buffer DA1-FIFO through the peripheral bus interface module; the first frequency control module AP-FC0 generates a speed control signal to control the speed at which the first path of digital audio data output from the application processor chip flows into the first data buffer AP-FIFO through the peripheral bus interface module.

[0063] In an embodiment of the present disclosure, the first data buffer AP-FIFO, the second data buffer DA0_FIFO, the third data buffer DA1_FIFO, the fourth data buffer AD0_FIFO, and the fifth data buffer AD1_FIFO all include:

[0064] A static random access memory SRAM and an asynchronous first-in-first-out data buffer AFIFO. The input end of the static random access memory SRAM is connected to the peripheral bus interface module, and the output end of the static random access memory SRAM is connected to the input end of the asynchronous first-in-first-out data buffer AFIFO.

[0065] An embodiment of the second aspect of the present disclosure provides an audio SOC chip, including: an application processor chip, a digital signal processing chip, a peripheral bus interface module, an audio subsystem interface module, and an audio data transmission interface module; wherein,

[0066] The application processor chip and the digital signal processing chip are connected to the peripheral bus interface module, and the peripheral bus interface module is further connected to the audio data transmission interface module through the audio subsystem interface module.

[0067] An embodiment of the third aspect of the present disclosure provides an electronic device, which includes the audio SOC chip as described above.

[0068] The technical solutions provided by the embodiments of the present disclosure at least bring the following beneficial effects:

[0069] Through the embodiments of the present disclosure, an audio subsystem interface module is connected between the peripheral bus interface module and the audio data transmission interface module. The peripheral bus interface module is also connected to the application processor chip and the digital signal processing chip. The audio subsystem interface module includes: a plurality of downlink path units, a plurality of uplink paths, and a plurality of loopback paths. Among them, the plurality of downlink path units are used to perform downlink processing on at least one digital audio data obtained from the application processor chip and / or the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module; the plurality of uplink path units are used to perform uplink processing on at least one digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing through the peripheral bus interface module to the application processor chip and / or the digital signal processing chip; the plurality of loopback path units are used to perform aggregation processing on at least one digital audio data input through the audio data transmission interface module and the digital audio data obtained after the downlink processing by any one of the plurality of downlink path units, and output the digital audio data obtained after the aggregation processing through the audio data transmission interface module. Thus, through the audio subsystem interface module, the present disclosure can implement complex sound effect processing, sampling rate processing, routing processing and other large operation logics in the form of hardware, thereby reducing the power consumption of the audio SOC chip.

[0070] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The accompanying drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, and do not constitute an improper limitation to the present disclosure.

[0072] Figure 1 is a schematic diagram of the audio subsystem interface module in the audio SOC chip according to an embodiment of the present disclosure;

[0073] Figure 2 is a schematic diagram of the data flow direction of the first downlink path in the audio subsystem interface module according to an embodiment of the present disclosure;

[0074] Figure 3 is a schematic diagram of the data flow direction of the second downlink path in the audio subsystem interface module according to an embodiment of the present disclosure;

[0075] Figure 4It is a schematic diagram of the data flow direction of the third downstream path in the audio subsystem interface module according to an embodiment of the present disclosure;

[0076] Figure 5 It is a schematic diagram of the data flow direction of the first upstream path in the audio subsystem interface module according to an embodiment of the present disclosure;

[0077] Figure 6 It is a schematic diagram of the data flow direction of the second upstream path in the audio subsystem interface module according to an embodiment of the present disclosure;

[0078] Figure 7 It is a schematic diagram of the data flow direction of the third upstream path in the audio subsystem interface module according to an embodiment of the present disclosure;

[0079] Figure 8 It is a schematic diagram of the data flow direction of the first loopback path in the audio subsystem interface module according to an embodiment of the present disclosure;

[0080] Figure 9 It is a schematic diagram of the data flow direction of the second loopback path in the audio subsystem interface module according to an embodiment of the present disclosure;

[0081] Figure 10 It is a schematic diagram of the data flow direction in the first application scenario and the second application scenario of the audio subsystem interface module according to an embodiment of the present disclosure;

[0082] Figure 11 It is a schematic diagram of the data flow direction in the third application scenario of the audio subsystem interface module according to an embodiment of the present disclosure;

[0083] Figures 12 - 15 It is a schematic diagram of the data flow characteristics of the audio subsystem interface module according to an embodiment of the present disclosure;

[0084] Figures 16 - 24 It is a schematic diagram of the speed control of the data flow of the audio subsystem interface module according to an embodiment of the present disclosure;

[0085] Figure 25 It is a schematic diagram of the first data buffer to the fifth data buffer according to an embodiment of the present disclosure. Detailed implementation manners

[0086] In order to enable those of ordinary skill in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0087] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the present disclosure are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0088] The audio SOC chip, its audio subsystem interface module and electronic device according to the embodiments of the present disclosure will be described below with reference to the drawings.

[0089] Figure 1 It is a schematic diagram of the audio subsystem interface module AUDIF in the audio SOC chip according to the embodiments of the present disclosure.

[0090] It should be noted that as Figure 1 shown, the audio subsystem interface module AUDIF in the audio SOC chip according to the embodiments of the present disclosure is connected between the peripheral bus interface module and the audio data transmission interface module. The peripheral bus interface module is also connected to the application processor chip AP and the digital signal processing chip DSP. Among them, the peripheral bus interface module can be APB (Advanced Peripheral Bus), and the audio data transmission interface module can be I2S (Inter-IC Sound). The audio data transmission interface module can transmit analog audio signals to and from the peripherals.

[0091] As Figure 1 shown, the audio subsystem interface module AUDIF in the audio SOC chip according to the embodiments of the present disclosure includes: a plurality of downlink path units, a plurality of uplink path units and a plurality of loopback path units.

[0092] Among them, multiple downlink path units are used to perform downlink processing on at least one path of digital audio data obtained from the application processor chip AP and / or the digital signal processing chip DSP through the peripheral bus interface module APB, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module I2S. Multiple uplink path units are used to perform uplink processing on at least one path of digital audio data input through the audio data transmission interface module I2S, and output the digital audio data obtained after the uplink processing to the application processor chip AP and / or the digital signal processing chip DSP through the peripheral bus interface module APB. Multiple loopback path units are used to converge at least one path of digital audio data input through the audio data transmission interface module I2S with the digital audio data obtained after performing downlink processing by any one of the multiple downlink path units, and output the digital audio data obtained after the convergence processing through the audio data transmission interface module I2S.

[0093] In an embodiment of the present disclosure, the multiple downlink path units include: a first downlink path (also referred to as an AP downlink path), a second downlink path (also referred to as a DA0 downlink path), and a third downlink path (also referred to as a DA1 downlink path).

[0094] As Figure 2 shown, the first downlink path includes a first data buffer AP-FIFO, a first frequency control module AP-FC0, a first sample rate conversion module AP-SRC, a second frequency control module AP-FC1, a first convergence point, a first sound effect processing module DA0-SE0, a third frequency control module DA0-FC2, a second sound effect processing module DA-SE1, a first synchronous first-in first-out data buffer SFIFO-DA0, and a second convergence point connected in sequence; wherein, the input end of the first data buffer AP-FIFO is connected to the first output end of the peripheral bus interface module APB, and the output end of the second convergence point is connected to the first input end of the audio data transmission interface module I2S. The first downlink path is used to perform downlink processing on the first path of digital audio data obtained from the application processor chip AP through the peripheral bus interface module APB, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module I2S.

[0095] As Figure 3As shown in the figure, the second downlink path includes a second data buffer DA0-FIFO, a fourth frequency control module DA0-FC0, a second sample rate conversion module DA0-SRC, a fifth frequency control module DA0-FC1, a first convergence point, a first audio processing module DA0-SE0, a third frequency control module DA0-FC2, a second audio processing module DA-SE1, a first synchronous first-in first-out data buffer SFIFO-DA0 (the position of the dashed box marked 1 in the figure), and a second convergence point. The input end of the second data buffer DA0-FIFO is connected to the second output end of the peripheral bus interface module APB. The second downlink path is used to perform downlink processing on the second digital audio data obtained from the digital signal processing chip DSP through the peripheral bus interface module APB, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module I2S.

[0096] As Figure 4 shown in the figure, the third downlink path includes a third data buffer DA1-FIFO, a sixth frequency control module DA1-FC0, a third sample rate conversion module DA1-SRC0, a seventh frequency control module DA1-FC1, a third audio processing module DA1-SE0, an eighth frequency control module DA1-FC2, a second audio processing module DA-SE1, a second synchronous first-in first-out data buffer SFIFO-DA1 (the position of the dashed box marked 2 in the figure), a third convergence point, a fourth sample rate conversion module DA1-SRC1, and a third synchronous first-in first-out data buffer SFIFO-DA1-SRC1 (the position of the dashed box marked 5 in the figure). The input end of the third data buffer DA1-FIFO is connected to the third output end of the peripheral bus interface module APB. The output end of the third synchronous first-in first-out data buffer SFIFO-DA1-SRC1 is connected to the second input end of the audio data transmission interface module I2S. The third downlink path is used to perform downlink processing on the third digital audio data obtained from the digital signal processing chip DSP through the peripheral bus interface module APB, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module I2S.

[0097] In an embodiment of the present disclosure, multiple uplink path units include: a first uplink path (also referred to as an AP uplink path), a second uplink path (also referred to as an AD0 uplink path), and a third uplink path (also referred to as an AD1 uplink path).

[0098] As Figure 5As shown, the first upstream path includes a fifth sampling rate conversion module AD1-SRC0, a fourth audio effect processing module AD1-SE, a fifth audio effect processing module AD0-SE, a multiplexer AP-MUX, and a second frequency control module AP-FC1, a first sampling rate conversion module AP-SRC, a first frequency control module AP-FC0, and a first data buffer AP-FIFO that are sequentially connected to the output end of the multiplexer AP-MUX. Among them, the fifth sampling rate conversion module AD1-SRC0 and the fourth audio effect processing module AD1-SE are connected in series and then connected to the first input end of the multiplexer AP-MUX. The fifth audio effect processing module AD0-SE is connected to the second input end of the multiplexer AP-MUX. The input end of the fifth sampling rate conversion module AD1-SRC0 is connected to the first output end of the audio data transmission interface module I2S. The input end of the fifth audio effect processing module AD0-SE is connected to the second output end of the audio data transmission interface module I2S. The first upstream path is used to perform upstream processing on the fourth digital audio data and the fifth digital audio data input through the audio data transmission interface module I2S, and output the digital audio data obtained after the upstream processing to the application processor chip AP through the peripheral bus interface module APB.

[0099] As Figure 6 shown, the second upstream path includes a fourth audio effect processing module AD0-SE, a sixth sampling rate conversion module AD0-SRC, and a fourth data buffer AD0-FIFO that are sequentially connected. The second upstream path is used to perform upstream processing on the fourth digital audio data input through the audio data transmission interface module I2S, and output the digital audio data obtained after the upstream processing to the digital signal processing chip DSP through the peripheral bus interface module APB.

[0100] As Figure 7 shown, the third upstream path includes a fifth sampling rate conversion module AD1-SRC0, a fifth audio effect processing module AD1-SE, a seventh sampling rate conversion module AD1-SRC1, and a fifth data buffer AD1-FIFO that are sequentially connected. The third upstream path is used to perform upstream processing on the fifth digital audio data input through the audio data transmission interface module I2S, and output the digital audio data obtained after the upstream processing to the digital signal processing chip DSP through the peripheral bus interface module APB.

[0101] In an embodiment of the present disclosure, multiple loop path units include: a first loop path (also referred to as the ST-DA0 path) and a second loop path (also referred to as the ST-DA1 path).

[0102] As Figure 8As shown in the figure, the first loop path includes a fifth sampling rate conversion module AD1-SRC0, a loop path module ST, a fourth synchronous first-in first-out data buffer SFIFO-ST-DA0 (the position of the dotted box marked with 3 in the figure), and a second downlink path. Among them, the first input end of the loop path module ST is connected to the first output end of the audio data transmission interface module I2S through the fifth sampling rate conversion module AD1-SRC0, the second input end of the loop path module ST is connected to the second output end of the audio data transmission interface module I2S, the first output end of the loop path module ST is connected to the second convergence point through the fourth synchronous first-in first-out data buffer SFIFO-ST-DA0. The first loop path is used to perform data selection and processing on the fourth digital audio data and the fifth digital audio data input through the audio data transmission interface module I2S, perform convergence processing with the digital audio data obtained after downlink processing through the second downlink path unit, and output the digital audio data obtained after convergence processing through the audio data transmission interface module I2S.

[0103] As Figure 9 As shown in the figure, the second loop path includes a fifth sampling rate conversion module AD1-SRC0, a loop path module ST, a fifth synchronous first-in first-out data buffer SFIFO-ST-DA1 (the position of the dotted box marked with 4 in the figure), and a third downlink path. Among them, the second output end of the loop path module ST is connected to the third convergence point through the fifth synchronous first-in first-out data buffer SFIFO-ST-DA1. The second loop path is used to perform data selection and processing on the fourth digital audio data and the fifth digital audio data input through the audio data transmission interface module (I2S), perform convergence processing with the digital audio data obtained after downlink processing through the third downlink path unit, and output the digital audio data obtained after convergence processing through the audio data transmission interface module (I2S).

[0104] For ease of understanding, the following lists three common application scenarios as examples to describe the data flow.

[0105] The first application scenario: playing music.

[0106] As Figure 10 As shown in the figure, the sound source data is sent into the digital signal processing chip DSP. After preliminary processing by the digital signal processing chip DSP, it is sent into the second downlink path of the audio subsystem interface module AUDIF through the peripheral bus interface module APB (it should be noted that it can also be sent into the third downlink path, and the selection of the downlink path is configured by software). After that, after sampling rate conversion and sound effect module processing by the second downlink path, the digital audio signal is converted into an analog audio signal through the audio data transmission interface module I2S and is heard by the user.

[0107] The second application scenario: receiving a text message during music playback.

[0108] As Figure 10 shown, the music playback process is as described above. When a text message is received, the application processor chip AP immediately generates a digital audio signal corresponding to the text message prompt tone. The digital audio signal corresponding to the text message prompt tone is sent into the first downstream path of the application processor chip through the peripheral bus interface module APB, and after simple processing, it is immediately sent to the second downstream path to converge with the digital audio signal corresponding to music playback. Then, the digital audio signal corresponding to music playback and the digital audio signal corresponding to the text message prompt tone are mixed, and finally, through the audio data transmission interface module I2S, it is digitally converted into an analog audio signal and heard by the user.

[0109] The third application scenario: making a call.

[0110] As Figure 11 shown, the voice of the other party is received from the mobile phone modem module, and the corresponding digital audio signal is sent into the digital signal processing chip DSP. After preliminary processing by the digital signal processing chip DSP, it is then sent into the third downstream path of the audio subsystem interface module AUDIF through the peripheral bus interface module APB (it should be noted that it can also be sent into the second downstream path, and the selection of the downstream path is configured by software). It is processed by each sound effect module on the third downstream path, and finally sent into the audio data transmission interface module I2S. The audio data transmission interface module I2S is digitally converted into an analog sound signal and heard by the user.

[0111] The analog signal corresponding to the user's own voice is digitally converted into a digital signal through the audio data transmission interface module I2S, and then sent into the third upstream path (it should be noted that it can also be sent into the second upstream path, and the selection of the upstream path is configured by software). After that, it is processed by each sound effect module on the third upstream path, and then the data is sent into the digital signal processing chip DSP through the peripheral bus interface module APB for processing, and finally sent out through the mobile phone modem module to be received by the other party's mobile phone.

[0112] If making a call with the mobile phone in hand, assuming the mobile phone is held against the right ear to answer, since the right ear is covered, the voice of one's own speech is clearer in the left ear and less clear in the right ear. At this time, the data corresponding to the voice of one's own speech is received by the third upstream path, selected and processed through the second loopback path, then mixed with the voice of the other party in the third downstream path, and finally sent into the audio data transmission interface module I2S. Through the audio data transmission interface module I2S, it is digitally converted into an analog mixed signal and heard by the user, improving the listening experience.

[0113] Next, combined with Figures 12 - 15 introduce the data flow characteristics of the audio subsystem interface module AUDIF.

[0114] As Figure 12 shown, from the application processor chip AP and / or the digital signal processing chip DSP to the audio subsystem interface module AUDIF, and then to the peripherals, there are a total of 3 clock domain conversions involving pclk, audif core clk, and I2S clk, and at the same time include sample rate conversion (the SRC module can support mutual conversion of multiple frequency sample rates, such as converting 44.1K to 48K), and various data path routing aggregations.

[0115] The data stream has a zero-padding mechanism: there is a specific "padding number" requirement at the audio multiplexing aggregation point. For two paths A / B from the same clock domain, after the data arrives on path A, if there is no data on path B, then zero is padded, and then it is aggregated with the data on path A and sent to the subsequent module after processing.

[0116] As Figure 13 shown, at the three aggregation points, namely the first aggregation point, the second aggregation point, and the third aggregation point, there is a "zero-padding" mechanism. The second audio effect processing module DA-SE1 also has a "zero-padding" mechanism.

[0117] For example: in the architecture Figure 13 , at the first aggregation point, assuming that when a valid signal arrives, there is no data in the first data buffer AP-FIFO of the first downstream path, and there is already data in the second data buffer DA0-FIFO of the second downstream path, then the first downstream path automatically pads a zero data, aggregates it with the data of the second downstream path for processing, and then sends it to the subsequent first audio effect processing module DA0-SE0.

[0118] The data stream has a "data loss" mechanism: there is a "data loss" requirement at the audio multiplexing aggregation point. For two paths C / D from different clock domains, that is, after the data arrives on path C, if there is no data on path D (the main path), then the data that has arrived on path C will be "discarded", and the aggregation with path C will start after the data arrives on path D. It should be noted that the "data loss" mechanism is unique to the loopback path.

[0119] For example, in the architecture Figure 14 , assuming that the second downstream path is the main path and the first loopback path is the slave path. Since there are fewer modules in the first loopback path, the time to reach the aggregation point is short. While the time for the second downstream path to reach the aggregation point is relatively long. At this time, the valid signal on the main path has not arrived yet, but the valid signal on the first loopback path has arrived several beats and buffered a lot of data. These data will be discarded before the valid signal on the main path arrives, until the data and valid signal on the main path arrive and are aggregated with the latest data from the slave path for processing.

[0120] The data stream has a multi-channel synchronization mechanism: Under the premise of the requirement of "complementing numbers + discarding numbers" at the convergence point, the second audio processing module DA-SE1 also requires multi-channel data synchronization and convergence, and it cannot complement too many or too few numbers. Therefore, the requirements for data stream control in the entire link are extremely high.

[0121] Such as the architecture Figure 15 In:

[0122] In the main paths (such as the second downlink path and the third downlink path), most of the links are independent of each other. In the case where the slave paths (such as the first downlink path, the first loopback path, and the second loopback path) converge, it is necessary to ensure that the "complementing numbers + discarding numbers" mechanism works properly.

[0123] However, for the second audio processing module DA-SE1, it is required that the two main paths of the second downlink path and the third downlink path converge synchronously here, and the data in the second downlink path and the third downlink path are taken together for logic operations, and no misalignment should occur.

[0124] At the same time, the second audio processing module DA-SE1 also has a mechanism for complementing "0". Suppose there is data and a valid signal in the second downlink path, but there is no data and valid signal in the third downlink path. At this time, when the second audio processing module DA-SE1 works, if it detects the valid signal in the second downlink path and verifies that there is no valid signal in the third downlink path, it will complement the data in the third downlink path with "0" and regard the valid signal in the second downlink path as the valid signal in the third downlink path.

[0125] Next, in combination with Figures 16 - 24 The speed control principle of the data stream will be introduced.

[0126] The principle of data stream speed control is as follows: By configuring relevant counting registers, the first valid signal is correctly started; by configuring relevant counting registers, the input and output rates of the sampling rate conversion module SRC are reasonably controlled; the data flow rate across clock domains is ensured to be normal; by configuring relevant counting registers, the input speed of the multi-channel synchronization module is reasonably controlled.

[0127] The waveform diagram of the speed control module is as Figure 16 shown: When the FIFO is non-empty for the first time, it will generate a time delay first and then start reading. The purpose is to wait for other FIFOs to be non-empty, and when reading, data can be read from multiple FIFOs together to facilitate alignment; after starting to read the FIFO, a read enable signal is generated at the set time interval to control the data reading rate; the backpressure of the subsequent FIFO is received. When there is backpressure, the read enable is not output, and after the backpressure ends, the enable is output according to the counting state; at the convergence point of the two paths of data, when there is no data in one of the paths, data can still be actively transmitted to the subsequent stage at a certain rate and will not be blocked by the other path.

[0128] In an embodiment of the present disclosure, such asFigure 17 As shown, the second downlink path is open, the first downlink path is closed, the third downlink path is closed, the first audio processing module DA0-SE0 is closed, and the second audio processing module DA-SE1 is closed. The backpressure logic on the audio subsystem interface module AUDIF includes the following steps:

[0129] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module I2S as the backpressure signal to backpressure the fourth frequency control module DA0-FC0 to control the output speed of the fourth frequency control module DA0-FC0;

[0130] The fourth frequency control module DA0-FC0 generates a speed control signal to control the speed at which the first digital audio data output from the digital signal processing chip DSP through the peripheral bus interface module APB flows into the second data buffer DA0-FIFO.

[0131] In summary, use one-level backpressure and one-level speed control to separately control the data streams in three clock domains.

[0132] In an embodiment of the present disclosure, as Figure 18 shown, the second downlink path is open, the third downlink path is closed, the first downlink path is open, the first audio processing module DA0-SE0 is open, and the second audio processing module DA-SE1 is closed. The backpressure logic on the audio subsystem interface module AUDIF includes the following steps:

[0133] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module I2S as the backpressure signal to backpressure the first synchronous first-in-first-out data buffer SFIFO-DA0 to control the output speed of the first synchronous first-in-first-out data buffer SFIFO-DA0;

[0134] Use the almost full signal of the first synchronous first-in-first-out data buffer SFIFO-DA0 as the backpressure signal to backpressure the third frequency control module DA0-FC2 to control the output speed of the third frequency control module DA0-FC2;

[0135] The third frequency control module DA0-FC2 generates a speed control signal to synchronously backpressure the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1 to control the output speeds of the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1;

[0136] The fifth frequency control module DA0-FC1 generates a speed control signal to backpressure the fourth frequency control module DA0-FC0 to control the output speed of the fourth frequency control module DA0-FC0, and the second frequency control module AP-FC1 generates a speed control signal to backpressure the first frequency control module AP-FC0 to control the output speed of the first frequency control module AP-FC0;

[0137] The fourth frequency control module DA0-FC0 and the first frequency control module AP-FC0 generate corresponding speed control signals to correspondingly control the speed at which the first digital audio data output from the application processor chip AP flows into the first data buffer AP-FIFO through the peripheral bus interface module APB and the speed at which the second digital audio data output from the digital signal processing chip DSP flows into the second data buffer DA0-FIFO.

[0138] In summary, four-level backpressure and three-level speed control are used to separately control the data streams in three clock domains.

[0139] In an embodiment of the present disclosure, as Figure 19 shown, the second downlink path is open, the third downlink path is closed, the first downlink path is open, the first audio effect processing module DA0-SE0 is open, and the second audio effect processing module DA-SE1 is open. The backpressure logic on the audio subsystem interface module AUDIF includes the following steps:

[0140] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as the backpressure signal to synchronously backpressure the first synchronous first-in-first-out data buffer SFIFO-DA0 and the second synchronous first-in-first-out data buffer SFIFO-DA1 to correspondingly control the output speeds of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the second synchronous first-in-first-out data buffer SFIFO-DA1;

[0141] Use the almost full signal of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the almost full signal of the second synchronous first-in-first-out data buffer SFIFO-DA1 as backpressure signals to backpressure the third frequency control module DA0-FC2 to control the output speed of the third frequency control module DA0-FC2;

[0142] The third frequency control module DA0-FC2 generates a speed control signal to backpressure the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1 to control the output speeds of the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1;

[0143] The fifth frequency control module DA0-FC1 generates a speed control signal to backpressure the fourth frequency control module DA0-FC0 to control the output of the fourth frequency control module DA0-FC0, and the second frequency control module AP-FC1 generates a speed control signal to backpressure the first frequency control module AP-FC0 to control the output speed of the first frequency control module AP-FC0;

[0144] The fourth frequency control module DA0-FC0 and the first frequency control module AP-FC0 respectively generate corresponding speed control signals to respectively control the speed at which the first digital audio data output from the application processor chip AP flows into the first data buffer AP-FIFO through the peripheral bus interface module APB and the speed at which the second digital audio data output from the digital signal processing chip DSP flows into the second data buffer DA0-FIFO.

[0145] In summary, using four-level backpressure and three-level speed control, the first synchronous first-in first-out data buffer SFIFO-DA0 and the second synchronous first-in first-out data buffer SFIFO-DA1 simultaneously control the third frequency control module DA0-FC2 to separately control the data streams in three clock domains.

[0146] In an embodiment of the present disclosure, as Figure 20 shown, when the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is closed, the second audio effect processing module DA-SE1 is closed, and the fourth sampling rate conversion module DA1-SRC1 is closed, the backpressure logic on the audio subsystem interface module AUDIF includes the following steps:

[0147] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module I2S as a backpressure signal to backpressure the sixth frequency control module DA1-FC0 to control the output speed of the sixth frequency control module DA1-FC0;

[0148] The sixth frequency control module DA1-FC0 generates a speed control signal to control the speed at which the third digital audio data output from the digital signal processing chip DSP flows into the third data buffer DA1-FIFO through the peripheral bus interface module APB.

[0149] In summary, using one-level backpressure and one-level speed control, separately control the data streams in three clock domains.

[0150] In an embodiment of the present disclosure, as Figure 21 shown, when the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is closed, the second audio effect processing module DA-SE1 is closed, and the fourth sampling rate conversion module DA1-SRC1 is open, the backpressure logic on the audio subsystem interface module AUDIF includes the following steps:

[0151] Take the full signal of the data buffer I2S-FIFO in the audio data transmission interface module I2S as the backpressure signal to backpressure the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, so as to control the output speed of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1;

[0152] Take the almost full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 as the backpressure signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0;

[0153] The sixth frequency control module DA1-FC0 generates a speed control signal to control the speed at which the third digital audio data output from the digital signal processing chip DSP through the peripheral bus interface module APB flows into the third data buffer DA1-FIFO.

[0154] To sum up, since the third downstream path has one more fourth sample rate conversion module DA1-SRC1 and one third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 than the second downstream path, when the fourth sample rate conversion module DA1-SRC1 is turned on, it is necessary to separate the I2S clock domain and the core clk clock domain where the fourth sample rate conversion module DA1-SRC1 is located through a first-level backpressure, and use a second-level backpressure and a first-level speed control to separately control the data streams of the three clock domains.

[0155] In an embodiment of the present disclosure, as Figure 22 shown, when the third downstream path is turned on, the second downstream path is turned off, the third audio effect processing module DA1-SE0 is turned on, the second audio effect processing module DA-SE1 is turned off, and the fourth sample rate conversion module DA1-SRC1 is turned on, the backpressure logic on the audio subsystem interface module AUDIF includes the following steps:

[0156] Take the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as the backpressure signal to backpressure the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, so as to control the output speed of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1;

[0157] Take the almost full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 as the backpressure signal to backpressure the second synchronous first-in-first-out data buffer SFIFO-DA1, so as to control the output speed of the second synchronous first-in-first-out data buffer SFIFO-DA1;

[0158] Use the almost-full signal of the second synchronous first-in first-out data buffer SFIFO-DA1 as a backpressure signal to backpressure the eighth frequency control module DA1-FC2, so as to control the output speed of the eighth frequency control module DA1-FC2;

[0159] The eighth frequency control module DA1-FC2 generates a speed control signal to backpressure the seventh frequency control module DA1-FC1, so as to control the output speed of the seventh frequency control module DA1-FC1;

[0160] The seventh frequency control module DA1-FC1 generates a speed control signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0;

[0161] The sixth frequency control module DA1-FC0 generates a speed control signal to backpressure the third data buffer DA1-FIFO, so as to control the speed at which the third digital audio data output from the digital signal processing chip (DSP) through the peripheral bus interface module (APB) flows into the third data buffer DA1-FIFO.

[0162] To summarize, use five-level backpressure and three-level speed control to separately control the data streams in three clock domains.

[0163] In an embodiment of the present disclosure, as Figure 23 shown, the third downlink path is opened, the second downlink path is closed, the third audio effect processing module DA1-SE0 is opened, the second audio effect processing module DA-SE1 is opened, and the fourth sampling rate conversion module DA1-SRC1 is opened. The backpressure logic on the audio subsystem interface module AUDIF includes the following steps:

[0164] Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the first synchronous first-in first-out data buffer SFIFO-DA0 and the third synchronous first-in first-out data buffer SFIFO-DA1-SRC1, so as to control the output speeds of the first synchronous first-in first-out data buffer SFIFO-DA0 and the third synchronous first-in first-out data buffer SFIFO-DA1-SRC1;

[0165] Use the almost-full signal of the third synchronous first-in first-out data buffer SFIFO-DA1_SRC1 as a backpressure signal to backpressure the second synchronous first-in first-out data buffer SFIFO-DA1, so as to control the output speed of the second synchronous first-in first-out data buffer SFIFO-DA1;

[0166] The almost-full signal of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the almost-full signal of the second synchronous first-in-first-out data buffer SFIFO-DA1 jointly backpressure the eighth frequency control module DA1-FC2 to control the output speed of the eighth frequency control module DA1-FC2;

[0167] The eighth frequency control module DA1-FC2 generates a speed control signal to backpressure the seventh frequency control module DA1-FC1 to control the output speed of the seventh frequency control module DA1-FC1;

[0168] The seventh frequency control module DA1-FC1 generates a speed control signal to backpressure the sixth frequency control module DA1-FC0 to control the output speed of the sixth frequency control module DA1-FC0;

[0169] The sixth frequency control module DA1-FC0 generates a speed control signal to backpressure the third data buffer DA1-FIFO to control the speed at which the third digital audio data output from the digital signal processing chip DSP through the peripheral bus interface module APB flows into the third data buffer DA1-FIFO.

[0170] In summary, using five-level backpressure and three-level speed control, the first synchronous first-in-first-out data buffer SFIFO-DA0 and the second synchronous first-in-first-out data buffer SFIFO-DA1 jointly control the eighth frequency control module DA1-FC2 to separately control the data streams in three clock domains.

[0171] In an embodiment of the present disclosure, as Figure 24 shown, all the modules on the second downlink path and the third downlink path are turned on, and the backpressure logic on the audio subsystem interface module AUDIF includes the following steps:

[0172] Taking the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as the backpressure signal to backpressure the first synchronous first-in-first-out data buffer SFIFO-DA0 and the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 to control the output speeds of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1;

[0173] Taking the almost-full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1_SRC1 as the backpressure signal to backpressure the second synchronous first-in-first-out data buffer SFIFO-DA1 to control the output speed of the second synchronous first-in-first-out data buffer SFIFO-DA1;

[0174] The almost-full signals of the first synchronous first-in first-out data buffer SFIFO-DA0 and the second synchronous first-in first-out data buffer SFIFO-DA1 are used to backpressure the third frequency control module DA0-FC2 and the eighth frequency control module DA1-FC2, so as to jointly control the output speeds of the third frequency control module DA0-FC2 and the eighth frequency control module DA1-FC2;

[0175] The third frequency control module DA0-FC2 generates a speed control signal to backpressure the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, so as to control the output speeds of the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, and the eighth frequency control module DA1-FC2 generates a speed control signal to backpressure the seventh frequency control module DA1-FC1, so as to control the output speed of the seventh frequency control module DA1-FC1;

[0176] The fifth frequency control module DA0-FC1 generates a speed control signal to backpressure the fourth frequency control module DA0-FC0, so as to control the output speed of the fourth frequency control module DA0-FC0; the seventh frequency control module DA1-FC1 generates a speed control signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0; the second frequency control module AP-FC1 generates a speed control signal to backpressure the first frequency control module AP-FC0, so as to control the output speed of the first frequency control module AP-FC0;

[0177] The fourth frequency control module DA0-FC0 generates a speed control signal to control the speed at which the second path of digital audio data output from the digital signal processing chip DSP flows into the second data buffer DA0-FIFO through the peripheral bus interface module APB; the sixth frequency control module DA1-FC0 generates a speed control signal to control the speed at which the third path of digital audio data output from the digital signal processing chip DSP flows into the third data buffer DA1-FIFO through the peripheral bus interface module APB; the first frequency control module AP-FC0 generates a speed control signal to control the speed at which the first path of digital audio data output from the application processor chip AP flows into the first data buffer AP-FIFO through the peripheral bus interface module APB.

[0178] In summary, by using five-level backpressure and three-level speed control, the backpressure logics when the second downlink path and the third downlink path are separately opened are combined. The first synchronous first-in first-out data buffer SFIFO-DA0 and the second synchronous first-in first-out data buffer SFIFO-DA1 jointly control the third frequency control module DA0-FC2 and the eighth frequency control module DA1-FC2, and separately control the data flows in three clock domains.

[0179] It can be seen from this that the present disclosure processes data streams through forward data flow rate control, reverse key node backpressure, reasonable configuration of AFIFO / SFIFO, and necessary software constraints. Among them, the forward rate control module controls the data flow rate at key nodes of different links by configuring the corresponding register values related to counting. For the data stream across clock domains in the downstream path, the backpressure signal is taken from the subsequent module and sent to the previous key node to assist in controlling the data flow rate. At the same time, multiple sets of backpressure logics are designed for different scenarios to reduce unnecessary backpressure levels and corresponding logics, and reduce power consumption. AFIFO / SFIFO is reasonably configured at different nodes. When designing data interaction in multiple clock domains, necessary software constraints need to be added.

[0180] In the present disclosure, the data of the application processor chip AP and the digital signal processing chip DSP are interacted through the peripheral bus interface module APB and the audio subsystem interface module AUDIF. Since it is the data interaction between pclk and audif core clk and the data is multi-bit data, an asynchronous first-in-first-out data buffer AFIFO is required for data caching.

[0181] According to the design requirements, the required depth of the asynchronous first-in-first-out data buffer AFIFO is relatively large (such as exceeding 200). Therefore, directly using the asynchronous first-in-first-out data buffer AFIFO will cause a significant increase in area. Therefore, the asynchronous first-in-first-out data buffer AFIFO here is split into a combination of a SRAM with the same large depth and an asynchronous first-in-first-out data buffer AFIFO with a very small depth. The static random access memory SRAM directly interacts with the APB to be responsible for caching data, and the AFIFO is responsible for transmitting multi-bit data across clock domains. At the same time, considering the different flow directions of the upstream and downstream data streams, the actual solution is as Figure 25 shown.

[0182] Subsequently, through synthesis, it is found that when the depth of the AFIFO is very large, performing the above splitting can reduce the total area by about 30%, and the power consumption is also correspondingly reduced.

[0183] In the present disclosure, the design ideas of the first synchronous first-in-first-out data buffer SFIFO-DA0, the second synchronous first-in-first-out data buffer SFIFO-DA1, the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, the fourth synchronous first-in-first-out data buffer SFIFO-ST-DA0, and the fifth synchronous first-in-first-out data buffer SFIFO-ST-DA1 are as follows:

[0184] There is an SFIFO at the intersection of the second downlink path, the third downlink path, the first loop path, and the second loop path. Since the first loop path and the second loop path have a "data loss" mechanism, part of the data on the first loop path and the second loop path must be cached into the SFIFO and wait for the data of the second downlink path and the third downlink path to converge. For the second downlink path and the third downlink path, because the previous stage is the multi-channel synchronization module DA-SE1, the data of the second downlink path and the third downlink path needs to be synchronized before being sent to the subsequent stage.

[0185] The third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 set at the subsequent stage of DA1-SRC1 in the third downlink channel. Since the sampling rate conversion module SRC is responsible for the sampling rate change and the input and output data frequencies must be stable, if the output of the fourth sampling rate conversion module DA1-SRC1 is directly sent to the subsequent stage, it will be affected by the backpressure logic of the subsequent stage, resulting in unstable output frequency, and then unstable input frequency, leading to errors in the output of the fourth sampling rate conversion module DA1-SRC1. Therefore, the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 is used to separate the output of the fourth sampling rate conversion module DA1-SRC1 and avoid being affected by the backpressure signals generated by multi-channel convergence, multi-channel synchronization, and subsequent stages across clock domains.

[0186] It should be noted that since the stage after SRC in the second uplink path and the third uplink path is a FIFO combination, which can implement the function of SFIFO, there is no need to set up an SFIFO separately.

[0187] The software constraint logic principle of the audio SOC chip of the present disclosure is that it is necessary to ensure that when the audio data transmission interface module I2S inputs or outputs data, the audio subsystem interface module AUDIF is already in a normal working state. Therefore:

[0188] Reset sequence: The audio data transmission interface module I2S is reset first, and the audio subsystem interface module AUDIF is reset later.

[0189] De-reset sequence: The audio subsystem interface module AUDIF is de-reset first, and the audio data transmission interface module I2S is de-reset later.

[0190] In the present disclosure, if the loop path is opened, there will be a scenario where the data from I2SA passes through the loop path, converges with the downlink path data, and is sent to I2SB. At this time, it is required that I2SA / B must have the same clock source to prevent the accumulation of frequency differences from causing errors in convergence. If the loop path is opened, there must be data arriving at the convergence point on the downlink path. Otherwise, it is necessary to ensure that the "zero filling" mechanism works properly to avoid the ST path being in a "data loss" state all the time.

[0191] When the second audio effect processing module DA-SE1 is turned on, if the data of the two branches of the second downlink path and the third downlink path ultimately go to different I2S, it is required that all corresponding I2S must have the same clock source to prevent the accumulation of frequency differences from causing synchronization failure.

[0192] When the second audio effect processing module DA-SE1 is turned on, it must be ensured that the data of the two branches of the second downlink path and the third downlink path can be normally sent out from the I2S. Otherwise, any abnormal data transmission of one branch leading to abnormal backpressure will affect the data flow of the other branch, and further cause synchronization errors in the second audio effect processing module DA-SE1.

[0193] In summary, through the embodiments of the present disclosure, an audio subsystem interface module is connected between the peripheral bus interface module and the audio data transmission interface module. The peripheral bus interface module is also connected to the application processor chip and the digital signal processing chip. The audio subsystem interface module includes: a plurality of downlink path units, a plurality of uplink paths, and a plurality of loopback paths. Among them, the plurality of downlink path units are used to perform downlink processing on at least one digital audio data obtained from the application processor chip and / or the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module; the plurality of uplink path units are used to perform uplink processing on at least one digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing through the peripheral bus interface module to the application processor chip and / or the digital signal processing chip; the plurality of loopback path units are used to converge at least one digital audio data input through the audio data transmission interface module with the digital audio data obtained after the downlink processing by any one of the plurality of downlink path units, and output the digital audio data obtained after the convergence processing through the audio data transmission interface module. Thus, through the audio subsystem interface module of the present disclosure, complex audio effect processing, sample rate processing, routing processing and other large computing logics can be implemented in the form of hardware, thereby reducing the power consumption of the audio SOC chip.

[0194] Based on the above embodiments, the present disclosure also proposes an audio SOC chip.

[0195] The audio SOC chip of the embodiments of the present disclosure includes: an application processor chip AP, a digital signal processing chip DSP, a peripheral bus interface module APB, an audio subsystem interface module, and an audio data transmission interface module I2S; wherein, the application processor chip AP and the digital signal processing chip DSP are connected to the peripheral bus interface module APB, and the peripheral bus interface module APB is also connected to the audio data transmission interface module I2S through the audio subsystem interface module.

[0196] Based on the above embodiments, the present disclosure also provides an electronic device.

[0197] The electronic device according to the embodiments of the present disclosure includes the audio SOC chip as described above.

[0198] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0199] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0200] Any process or method description in a flowchart or described in other ways herein may be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0201] The logic and / or steps represented in the flowchart or otherwise described herein can, for example, be considered a definable sequence list of executable instructions for implementing logical functions, and can be embodied specifically in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or otherwise processing as appropriate, and then storing it in a computer memory.

[0202] It should be understood that various parts of the present disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0203] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0204] In addition, each functional unit in various embodiments of the present disclosure may be integrated into one processing module, may exist separately as individual physical units, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0205] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. An audio subsystem interface module in an audio SOC chip, characterized in that The audio subsystem interface module is connected between the peripheral bus interface module and the audio data transmission interface module. The peripheral bus interface module is also connected to the application processor chip and the digital signal processing chip. The audio subsystem interface module includes: Multiple downlink path units, configured to perform downlink processing on at least one path of digital audio data obtained from the application processor chip and / or the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module; Multiple uplink path units, configured to perform uplink processing on at least one path of digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing to the application processor chip and / or the digital signal processing chip through the peripheral bus interface module; Multiple loopback path units, configured to perform aggregation processing on at least one path of digital audio data input through the audio data transmission interface module and the digital audio data obtained after the downlink processing by any one of the multiple downlink path units, and output the digital audio data obtained after the aggregation processing through the audio data transmission interface module.

2. The audio subsystem interface module in the audio SOC chip according to claim 1, characterized in that The multiple downlink path units include: A first downlink path, which includes a first data buffer AP-FIFO, a first frequency control module AP-FC0, a first sample rate conversion module AP-SRC, a second frequency control module AP-FC1, a first convergence point, a first audio effect processing module DA0-SE0, a third frequency control module DA0-FC2, a second audio effect processing module DA-SE1, a first synchronous first-in first-out data buffer SFIFO-DA0, and a second convergence point, which are connected in sequence. The input end of the first data buffer AP-FIFO is connected to the first output end of the peripheral bus interface module, and the output end of the second convergence point is connected to the first input end of the audio data transmission interface module. The first downlink path is configured to perform downlink processing on the first path of digital audio data obtained from the application processor chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module; The second downlink path, which includes a second data buffer DA0-FIFO, a fourth frequency control module DA0-FC0, a second sample rate conversion module DA0-SRC, a fifth frequency control module DA0-FC1, the first convergence point, the first audio processing module DA0-SE0, the third frequency control module DA0-FC2, the second audio processing module DA-SE1, the first synchronous first-in first-out data buffer SFIFO-DA0, and the second convergence point, which are connected in sequence; wherein, the input end of the second data buffer DA0-FIFO is connected to the second output end of the peripheral bus interface module, and the second downlink path is used for performing downlink processing on the second digital audio data obtained from the digital signal processing chip through the peripheral bus interface module, and outputting the digital audio data obtained after the downlink processing through the audio data transmission interface module; The third downlink path, which includes a third data buffer DA1-FIFO, a sixth frequency control module DA1-FC0, a third sample rate conversion module DA1-SRC0, a seventh frequency control module DA1-FC1, a third audio processing module DA1-SE0, an eighth frequency control module DA1-FC2, the second audio processing module DA-SE1, a second synchronous first-in first-out data buffer SFIFO-DA1, a third convergence point, a fourth sample rate conversion module DA1-SRC1, and a third synchronous first-in first-out data buffer SFIFO-DA1-SRC1. The input end of the third data buffer DA1-FIFO is connected to the third output end of the peripheral bus interface module, and the output end of the third synchronous first-in first-out data buffer SFIFO-DA1-SRC1 is connected to the second input end of the audio data transmission interface module. The third downlink path is used for performing downlink processing on the third digital audio data obtained from the digital signal processing chip through the peripheral bus interface module, and outputting the digital audio data obtained after the downlink processing through the audio data transmission interface module.

3. The audio subsystem interface module in the audio SOC chip according to claim 1, characterized in that, The multiple uplink path units include: The first upstream path, the first upstream path includes a fifth sampling rate conversion module AD1-SRC0, a fourth audio effect processing module AD1-SE, a fifth audio effect processing module AD0-SE, a multiplexer AP-MUX, and a second frequency control module AP-FC1, a first sampling rate conversion module AP-SRC, a first frequency control module AP-FC0, and a first data buffer AP-FIFO that are sequentially connected to the output end of the multiplexer AP-MUX. Among them, the fifth sampling rate conversion module AD1-SRC0 and the fourth audio effect processing module AD1-SE are connected in series and then connected to the first input end of the multiplexer AP-MUX, the fifth audio effect processing module AD0-SE is connected to the second input end of the multiplexer AP-MUX, the input end of the fifth sampling rate conversion module AD1-SRC0 is connected to the first output end of the audio data transmission interface module, the input end of the fifth audio effect processing module AD0-SE is connected to the second output end of the audio data transmission interface module. The first upstream path is used to perform upstream processing on the fourth digital audio data and the fifth digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the upstream processing to the application processor chip through the peripheral bus interface module; The second upstream path, the second upstream path includes a fourth audio effect processing module AD0-SE, a sixth sampling rate conversion module AD0-SRC, and a fourth data buffer AD0-FIFO that are sequentially connected. The second upstream path is used to perform upstream processing on the fourth digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the upstream processing to the digital signal processing chip through the peripheral bus interface module; The third upstream path, the third upstream path includes the fifth sampling rate conversion module AD1-SRC0, a fifth audio effect processing module AD1-SE, a seventh sampling rate conversion module AD1-SRC1, and a fifth data buffer AD1-FIFO that are sequentially connected. The third upstream path is used to perform upstream processing on the fifth digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the upstream processing to the digital signal processing chip through the peripheral bus interface module.

4. The audio subsystem interface module in the audio SOC chip according to claim 1, wherein The multiple loop path units include: The first loop path, the first loop path includes a fifth sampling rate conversion module AD1-SRC0, a loop path module ST, a fourth synchronous first-in first-out data buffer SFIFO-ST-DA0, and a second downlink path; wherein, a first input end of the loop path module ST is connected to a first output end of the audio data transmission interface module through the fifth sampling rate conversion module AD1-SRC0, a second input end of the loop path module ST is connected to a second output end of the audio data transmission interface module, a first output end of the loop path module ST is connected to a second convergence point through the fourth synchronous first-in first-out data buffer SFIFO-ST-DA0, the first loop path is used for aggregating the fourth digital audio data and the fifth digital audio data input through the audio data transmission interface module with the digital audio data obtained after downlink processing through a second downlink path unit, and outputting the aggregated digital audio data through the audio data transmission interface module; The second loop path, the second loop path includes the fifth sampling rate conversion module AD1-SRC0, the loop path module ST, a fifth synchronous first-in first-out data buffer SFIFO-ST-DA1, and a third downlink path; wherein, a second output end of the loop path module ST is connected to a third convergence point through the fifth synchronous first-in first-out data buffer SFIFO-ST-DA1, the second loop path is used for aggregating the fourth digital audio data and the fifth digital audio data input through the audio data transmission interface module with the digital audio data obtained after downlink processing through a third downlink path unit, and outputting the aggregated digital audio data through the audio data transmission interface module.

5. The audio subsystem interface module in the audio SOC chip according to claim 2, wherein The second downlink path is turned on, the first downlink path is turned off, the third downlink path is turned off, the first audio effect processing module DA0-SE0 is turned off, and the second audio effect processing module DA-SE1 is turned off. The backpressure logic on the audio subsystem interface module includes the following steps: Using the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the fourth frequency control module DA0-FC0 to control the output speed of the fourth frequency control module DA0-FC0; The fourth frequency control module DA0-FC0 generates a speed control signal to control the speed at which the first digital audio data output from the digital signal processing chip through the peripheral bus interface module flows into the second data buffer DA0-FIFO.

6. The audio subsystem interface module in the audio SOC chip according to claim 2, wherein The second downlink path is turned on, the third downlink path is turned off, the first downlink path is turned on, the first audio effect processing module DA0-SE0 is turned on, and the second audio effect processing module DA-SE1 is turned off. The backpressure logic on the audio subsystem interface module includes the following steps: Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the first synchronous first-in-first-out data buffer SFIFO-DA0, so as to control the output speed of the first synchronous first-in-first-out data buffer SFIFO-DA0; Use the almost-full signal of the first synchronous first-in-first-out data buffer SFIFO-DA0 as a backpressure signal to backpressure the third frequency control module DA0-FC2, so as to control the output speed of the third frequency control module DA0-FC2; The third frequency control module DA0-FC2 generates a speed control signal to synchronously backpressure the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, so as to control the output speeds of the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1; The fifth frequency control module DA0-FC1 generates a speed control signal to backpressure the fourth frequency control module DA0-FC0, so as to control the output speed of the fourth frequency control module DA0-FC0, and the second frequency control module AP-FC1 generates a speed control signal to backpressure the first frequency control module AP-FC0, so as to control the output speed of the first frequency control module AP-FC0; The fourth frequency control module DA0-FC0 and the first frequency control module AP-FC0 generate corresponding speed control signals to correspondingly control the speed at which the first digital audio data output from the application processor chip flows into the first data buffer AP-FIFO through the peripheral bus interface module and the speed at which the second digital audio data output from the digital signal processing chip flows into the second data buffer DA0-FIFO; 7. The audio subsystem interface module in the audio SOC chip according to claim 2, characterized in that, The second downlink path is open, the third downlink path is closed, the first downlink path is open, the first audio effect processing module DA0-SE0 is open, and the second audio effect processing module DA-SE1 is open. The backpressure logic on the audio subsystem interface module includes the following steps: Use the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to synchronously backpressure the first synchronous first-in-first-out data buffer SFIFO-DA0 and the second synchronous first-in-first-out data buffer SFIFO-DA1, so as to correspondingly control the output speeds of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the second synchronous first-in-first-out data buffer SFIFO-DA1; Use the almost-full signal of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the almost-full signal of the second synchronous first-in-first-out data buffer SFIFO-DA1 as backpressure signals to backpressure the third frequency control module DA0-FC2, so as to control the output speed of the third frequency control module DA0-FC2; The third frequency control module DA0-FC2 generates a speed control signal to backpressure the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, so as to control the output speeds of the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1; The fifth frequency control module DA0-FC1 generates a speed control signal to backpressure the fourth frequency control module DA0-FC0, so as to control the output of the fourth frequency control module DA0-FC0, and the second frequency control module AP-FC1 generates a speed control signal to backpressure the first frequency control module AP-FC0, so as to control the output speed of the first frequency control module AP-FC0; The fourth frequency control module DA0-FC0 and the first frequency control module AP-FC0 respectively generate corresponding speed control signals to respectively control the speed at which the first digital audio data output from the application processor chip flows into the first data buffer AP-FIFO and the speed at which the second digital audio data output from the digital signal processing chip flows into the second data buffer DA0-FIFO through the peripheral bus interface module.

8. The audio subsystem interface module in the audio SOC chip according to claim 2, characterized in that, When the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is closed, the second audio effect processing module DA-SE1 is closed, and the fourth sample rate conversion module DA1-SRC1 is closed, the backpressure logic on the audio subsystem interface module includes the following steps: Using the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0; The sixth frequency control module DA1-FC0 generates a speed control signal to control the speed at which the third digital audio data output from the digital signal processing chip flows into the third data buffer DA1-FIFO through the peripheral bus interface module.

9. The audio subsystem interface module in the audio SOC chip according to claim 2, characterized in that, When the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is closed, the second audio effect processing module DA-SE1 is closed, and the fourth sample rate conversion module DA1-SRC1 is open, the backpressure logic on the audio subsystem interface module includes the following steps: Using the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, so as to control the output speed of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1; Using the almost full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 as a backpressure signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0; The sixth frequency control module DA1-FC0 generates a speed control signal to control the speed at which the third digital audio data output from the digital signal processing chip through the peripheral bus interface module flows into the third data buffer DA1-FIFO.

10. The audio subsystem interface module in the audio SOC chip according to claim 2, characterized in that, When the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is open, the second audio effect processing module DA-SE1 is closed, and the fourth sampling rate conversion module DA1-SRC1 is open, the backpressure logic on the audio subsystem interface module includes the following steps: Using the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, so as to control the output speed of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1; Using the almost-full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 as a backpressure signal to backpressure the second synchronous first-in-first-out data buffer SFIFO-DA1, so as to control the output speed of the second synchronous first-in-first-out data buffer SFIFO-DA1; Using the almost-full signal of the second synchronous first-in-first-out data buffer SFIFO-DA1 as a backpressure signal to backpressure the eighth frequency control module DA1-FC2, so as to control the output speed of the eighth frequency control module DA1-FC2; The eighth frequency control module DA1-FC2 generates a speed control signal to backpressure the seventh frequency control module DA1-FC1, so as to control the output speed of the seventh frequency control module DA1-FC1; The seventh frequency control module DA1-FC1 generates a speed control signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0; The sixth frequency control module DA1-FC0 generates a speed control signal to backpressure the third data buffer DA1-FIFO, so as to control the speed at which the third digital audio data output from the digital signal processing chip through the peripheral bus interface module flows into the third data buffer DA1-FIFO.

11. The audio subsystem interface module in the audio SOC chip according to claim 2, characterized in that, When the third downlink path is open, the second downlink path is closed, the third audio effect processing module DA1-SE0 is open, the second audio effect processing module DA-SE1 is open, and the fourth sampling rate conversion module DA1-SRC1 is open, the backpressure logic on the audio subsystem interface module includes the following steps: Using the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the first synchronous first-in-first-out data buffer SFIFO-DA0 and the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, so as to control the output speeds of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1; Take the almost-full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1_SRC1 as a backpressure signal to backpressure the second synchronous first-in-first-out data buffer SFIFO-DA1, so as to control the output speed of the second synchronous first-in-first-out data buffer SFIFO-DA1; Take the almost-full signal of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the almost-full signal of the second synchronous first-in-first-out data buffer SFIFO-DA1 to jointly backpressure the eighth frequency control module DA1-FC2, so as to control the output speed of the eighth frequency control module DA1-FC2; The eighth frequency control module DA1-FC2 generates a speed control signal to backpressure the seventh frequency control module DA1-FC1, so as to control the output speed of the seventh frequency control module DA1-FC1; The seventh frequency control module DA1-FC1 generates a speed control signal to backpressure the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0; The sixth frequency control module DA1-FC0 generates a speed control signal to backpressure the third data buffer DA1-FIFO, so as to control the speed at which the third digital audio data output from the digital signal processing chip flows into the third data buffer DA1-FIFO through the peripheral bus interface module.

12. The audio subsystem interface module in the audio SOC chip according to claim 2, wherein All modules on the second downlink path and the third downlink path are turned on. The backpressure logic on the audio subsystem interface module includes the following steps: Take the full signal of the data buffer I2S-FIFO in the audio data transmission interface module as a backpressure signal to backpressure the first synchronous first-in-first-out data buffer SFIFO-DA0 and the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1, so as to control the output speeds of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the third synchronous first-in-first-out data buffer SFIFO-DA1-SRC1; Take the almost-full signal of the third synchronous first-in-first-out data buffer SFIFO-DA1_SRC1 as a backpressure signal to backpressure the second synchronous first-in-first-out data buffer SFIFO-DA1, so as to control the output speed of the second synchronous first-in-first-out data buffer SFIFO-DA1; Take the almost-full signals of the first synchronous first-in-first-out data buffer SFIFO-DA0 and the second synchronous first-in-first-out data buffer SFIFO-DA1 to backpressure the third frequency control module DA0-FC2 and the eighth frequency control module DA1-FC2, so as to jointly control the output speeds of the third frequency control module DA0-FC2 and the eighth frequency control module DA1-FC2; The third frequency control module DA0-FC2 generates a speed control signal to counteract the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, so as to control the output speeds of the fifth frequency control module DA0-FC1 and the second frequency control module AP-FC1, and the eighth frequency control module DA1-FC2 generates a speed control signal to counteract the seventh frequency control module DA1-FC1, so as to control the output speed of the seventh frequency control module DA1-FC1; The fifth frequency control module DA0-FC1 generates a speed control signal to counteract the fourth frequency control module DA0-FC0, so as to control the output speed of the fourth frequency control module DA0-FC0; the seventh frequency control module DA1-FC1 generates a speed control signal to counteract the sixth frequency control module DA1-FC0, so as to control the output speed of the sixth frequency control module DA1-FC0; the second frequency control module AP-FC1 generates a speed control signal to counteract the first frequency control module AP-FC0, so as to control the output speed of the first frequency control module AP-FC0; The fourth frequency control module DA0-FC0 generates a speed control signal to control the speed at which the second digital audio data output from the digital signal processing chip flows into the second data buffer DA0-FIFO through the peripheral bus interface module; the sixth frequency control module DA1-FC0 generates a speed control signal to control the speed at which the third digital audio data output from the digital signal processing chip flows into the third data buffer DA1-FIFO through the peripheral bus interface module; the first frequency control module AP-FC0 generates a speed control signal to control the speed at which the first digital audio data output from the application processor chip flows into the first data buffer AP-FIFO through the peripheral bus interface module.

13. The audio subsystem interface module in the audio SOC chip according to any one of claims 2-12, characterized in that, The first data buffer AP-FIFO, the second data buffer DA0_FIFO, the third data buffer DA1_FIFO, the fourth data buffer AD0_FIFO, and the fifth data buffer AD1_FIFO all include: A static random access memory SRAM and an asynchronous first-in-first-out data buffer AFIFO. The input end of the static random access memory SRAM is connected to the peripheral bus interface module, and the output end of the static random access memory SRAM is connected to the input end of the asynchronous first-in-first-out data buffer AFIFO.

14. An audio SOC chip, characterized in that, Including: An application processor chip, a digital signal processing chip, a peripheral bus interface module, an audio subsystem interface module, and an audio data transmission interface module; wherein, The application processor chip and the digital signal processing chip are connected to the peripheral bus interface module, and the peripheral bus interface module is further connected to the audio data transmission interface module through the audio subsystem interface module.

15. An electronic device, characterized in that, Including: The audio SOC chip as described in claim 14.

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