Semiconductor structure, memory and method of manufacturing the same, electronic device

Abstract

Embodiments of the present application provide a semiconductor structure, a memory and a manufacturing method thereof, and an electronic device. The present application relates to the technical field of semiconductor. The semiconductor structure comprises a semiconductor layer, a gate insulating layer and a gate. The semiconductor layer comprises a source region, a first channel region and a drain region, the first channel region is arranged between the source region and the drain region, the gate is located at least one side of the first channel region, and the gate insulating layer is located between the first channel region and the gate; along the extension direction of the first channel region, one end of the gate insulating layer forms isolation between the gate and at least part of the source region, and / or the other end of the gate insulating layer forms isolation between the gate and at least part of the drain region. Embodiments of the present application increase the length of the effective channel region, can inhibit the short channel effect, and reduce the on-state current.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a memory and its manufacturing method, and an electronic device. Background Technology

[0002] Currently, memory technology is developing towards increasing integration and reducing device size. To improve integration capabilities and reduce cell area, allowing for the fabrication of more memory cells within the same chip area, the size of memory devices needs to be continuously miniaturized with technological advancements. However, this miniaturization of memory introduces several challenges. Summary of the Invention

[0003] This application addresses the shortcomings of existing methods by proposing a semiconductor structure, memory, manufacturing method thereof, and electronic device to solve the technical problem of existing memory having a short-channel effect that leads to a large off-state current.

[0004] In a first aspect, embodiments of this application provide a semiconductor structure, including:

[0005] A semiconductor layer, the semiconductor layer including a source region, a first channel region and a drain region, wherein the first channel region is disposed between the source region and the drain region;

[0006] A gate insulating layer and a gate, the gate being located on at least one side of the first channel region, the gate insulating layer being located between the first channel region and the gate; along the extension direction of the first channel region, one end of the gate insulating layer forms isolation between the gate and at least a portion of the source region, and / or the other end of the gate insulating layer forms isolation between the gate and at least a portion of the drain region.

[0007] Secondly, embodiments of this application provide a memory, including: a memory structure comprising an array of mutually insulated structures, the memory structure comprising a plurality of semiconductor structures as described in the first aspect, the plurality of semiconductor structures being stacked and insulated along a first direction perpendicular to the substrate and arranged in an array in a plane parallel to the substrate;

[0008] The gate of the semiconductor structure is located on at least one side of the first channel region, and the gate insulating layer is located between the first channel region and the gate. One end of the gate insulating layer forms isolation between the gate and at least a portion of the source region, and / or the other end of the gate insulating layer forms isolation between the gate and at least a portion of the drain region.

[0009] Thirdly, embodiments of this application provide an electronic device, including: the memory described in the second aspect.

[0010] Fourthly, embodiments of this application provide a method for manufacturing a memory, comprising:

[0011] An initial storage structure is fabricated on one side of a substrate by an array of multiple phase-insulating layers. The initial storage structure includes semiconductor layers spaced apart along a first direction perpendicular to the substrate, and a first insulating layer disposed on both sides of the semiconductor layers along a third direction parallel to the substrate and between the two ends of two adjacent semiconductor layers.

[0012] A gate insulating layer and a gate are sequentially disposed on the outer periphery of a first channel region of the semiconductor layer, such that one end of the gate insulating layer forms isolation between the gate and at least a portion of the source region of the semiconductor layer, and / or the other end of the gate insulating layer forms isolation between the gate and at least a portion of the drain region of the semiconductor layer.

[0013] The beneficial technical effects of the technical solutions provided in this application include:

[0014] One end of the gate insulating layer forms isolation between the gate and at least a portion of the source region, and / or the other end of the gate insulating layer forms isolation between the gate and at least a portion of the drain region. This enhances the capacitance of the source region covered by the gate insulating layer, and / or enhances the capacitance at the gate and the drain region covered by the gate insulating layer, when a voltage is applied. This enhanced capacitance allows for adjustment of the actual effective channel region length. Increasing the effective channel region length suppresses short-channel effects and helps reduce off-state current.

[0015] Moreover, when manufacturing this semiconductor structure, the two ends of the gate insulating layer are directly extended to part of the source region and part of the drain region to form isolation, without the need to manufacture an additional isolation layer or add an additional manufacturing process, which helps to save manufacturing time and cost.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 This is a schematic cross-sectional view of the film layer of the first semiconductor structure provided in the embodiments of this application;

[0019] Figure 2 This is a schematic cross-sectional view of the film layer of the second semiconductor structure provided in the embodiments of this application;

[0020] Figure 3This is a schematic cross-sectional view of the film layer of the first semiconductor structure provided in the embodiments of this application under the condition of applying voltage;

[0021] Figure 4 This is a schematic cross-sectional view of the film layer of the second semiconductor structure provided in the embodiments of this application under the condition of applying voltage;

[0022] Figure 5 A schematic cross-sectional view of the film layer of the first type of memory provided in the embodiments of this application;

[0023] Figure 6 A top view of the film layer of the first type of memory provided in the embodiments of this application;

[0024] Figure 7 A top view of the film layer of the second type of memory provided in the embodiments of this application;

[0025] Figure 8 for Figure 7 Schematic diagram of the cross section at point AA;

[0026] Figure 9 A schematic flowchart illustrating a method for manufacturing a memory according to an embodiment of this application;

[0027] Figures 10 to 21 A schematic diagram of the film layers obtained in each step of the manufacturing method of the first memory provided in the embodiments of this application;

[0028] Figures 22 to 45 A schematic diagram of the film layers obtained in each step of the manufacturing method of the second memory provided in the embodiments of this application.

[0029] Explanation of reference numerals in the attached figures:

[0030] 1-Semiconductor layer; 11-Source region; 111-First depletion region; 12-First channel region; 13-Drain region; 131-Second depletion region; 14-Second channel region;

[0031] 21 - Gate insulating layer; 22 - Gate;

[0032] 3-Dielectric layer;

[0033] 4-Memory structure; 41-Word line; 42-Bit line; 43-First dielectric layer; 44-First electrode;

[0034] 5 - Initial storage structure; 50 - Initial storage structure region; 51 - First insulating layer; 511 - First sub-insulating layer; 512 - Second sub-insulating layer;

[0035] 61 - Second insulating layer; 62 - Third insulating layer;

[0036] 71 - Initial sacrificial layer; 72 - First intermediate sacrificial layer; 721 - Second intermediate sacrificial layer; 73 - Sacrificial layer; 74 - Trench; 75 - Groove;

[0037] 81 - Initial semiconductor layer; 811 - Intermediate semiconductor layer; 82 - First intermediate semiconductor layer; 83 - Second intermediate semiconductor layer;

[0038] 91-First groove; 92-Second groove; 93-Initial bit line; 94-Third groove; 95-First isolation layer; 96-Second isolation layer; 97-First groove; 98-Initial word line; 99-Fourth groove; 991-Third isolation layer;

[0039] 10-Substrate. Detailed Implementation

[0040] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0041] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the word “comprising” as used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term “and / or” as used herein refers to at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0043] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0044] This application provides a semiconductor structure, the schematic diagram of which is shown below. Figure 1 and Figure 2 As shown, it includes: semiconductor layer 1, gate insulating layer 21 and gate 22.

[0045] The semiconductor layer 1 includes a source region 11, a first channel region 12 and a drain region 13, with the first channel region 12 disposed between the source region 11 and the drain region 13.

[0046] The gate 22 is located on at least one side of the first channel region 12, and the gate insulating layer 21 is located between the first channel region 12 and the gate 22; along the extending direction of the first channel region 12, one end of the gate insulating layer 21 forms an isolation between the gate 22 and at least a portion of the source region 11, and / or the other end of the gate insulating layer 21 forms an isolation between the gate 22 and at least a portion of the drain region 13.

[0047] In this embodiment, the gate insulating layer 21 is used to isolate the gate 22 from the first channel region 12. (See reference...) Figure 1 In this application, the two ends of the gate insulating layer 21 extend to a portion of the source region 11 and a portion of the drain region 13, wherein the portion of the source region 11 and the portion of the drain region 13 are both regions close to the first channel region 12.

[0048] Because one end of the gate insulating layer 21 forms isolation between the gate 22 and at least a portion of the source region 11, and / or the other end of the gate insulating layer 21 forms isolation between the gate 22 and at least a portion of the drain region 13, the capacitance of the gate 22 and the portion of the source region 11 covered by the gate insulating layer 21 can be enhanced when a voltage is applied, and / or the capacitance of the gate 22 and the portion of the drain region 13 covered by the gate insulating layer 21 can be enhanced. Therefore, the length of the actual effective channel region can be controlled by the enhanced capacitance. Increasing the length of the effective channel region can suppress the short-channel effect and help reduce the off-state current.

[0049] Moreover, when manufacturing this semiconductor structure, the gate insulating layer 21 is directly extended to a portion of the source region 11 and a portion of the drain region 13 to form isolation, without the need to additionally manufacture an isolation layer on the periphery of the portion of the source region 11 and the portion of the drain region 13, and without the need for additional manufacturing processes, which helps to save manufacturing time and costs.

[0050] Optionally, the relative permittivity of the gate insulating layer 21 is greater than that of silicon dioxide.

[0051] In this embodiment, the relative permittivity of the gate insulating layer 21 is greater than that of silicon dioxide. This makes the capacitance formed by the gate 22, the gate insulating layer 21, and the semiconductor layer 1 greater than the capacitance formed by the gate 22, the silicon dioxide dielectric layer, and the semiconductor layer 1. This is beneficial for enhancing the capacitance formed by the source region 11 covered by the gate insulating layer 21 and the gate 22, as well as for enhancing the capacitance formed by the drain region 13 covered by the gate insulating layer 21 and the gate 22. This, in turn, helps to increase the length of the effective channel region, suppresses the short-channel effect, and helps to reduce the off-state current.

[0052] Specifically, the relative permittivity of the gate insulating layer 21 is greater than 3.9.

[0053] Optionally, the source region 11, the first channel region 12, and the drain region 13 are of the same doped dielectric type.

[0054] In this embodiment, when the doping media types of the source region 11, the first channel region 12, and the drain region 13 are the same, the semiconductor structure is a junctionless transistor.

[0055] When the semiconductor structure is a junctionless transistor, when a negative voltage is applied to the gate 22, the gate 22, the gate insulating layer 21, and the semiconductor layer 1 can form a capacitor structure. In this case, the gate 22 can deplete the electrons in the source region 11 covered by the extended gate insulating layer 21 and the electrons in the drain region 13 covered by the extended gate insulating layer 21. (Reference) Figure 3 and Figure 4 A first depletion region 111 is formed in the source region 11 covering one end of the gate insulating layer 21, and a second depletion region 131 is formed in the drain region 13 covering the other end of the gate insulating layer 21. The first depletion region 111, the first channel region 12, and the second depletion region 131 can form a second channel region 14. Since the second channel region 14 is the actual effective channel region, the length of the second channel region 14 is increased relative to the length of the first channel region 12, which helps to alleviate the short-channel effect, thereby reducing the off-state current and improving the performance and reliability of the semiconductor structure.

[0056] When the semiconductor structure is a junctionless transistor, applying a positive voltage to the gate 22 allows the gate 22, gate insulating layer 21, and semiconductor layer 1 to form a capacitor structure. This results in greater electron accumulation in the source region 11 covered by one end of the gate insulating layer 21, and also in greater electron accumulation in the drain region 13 covered by the other end of the gate insulating layer 21. This helps reduce parasitic resistance, increase turn-on current, and improve the performance and reliability of the semiconductor structure.

[0057] Of course, the doping media types of the source region 11, the first channel region 12, and the drain region 13 can be different, i.e., the semiconductor structure is a junction-type transistor. Since the gate insulating layer 21 extends to part of the drain region 13, a lightly doped N-region is added to the drain region 13, which reduces the electric field of the drain region 13 and the maximum field strength deviates from the gate 22. This can increase the length of the effective channel, reduce the off-state current, and thus help reduce the hot carrier effect and punch-through effect.

[0058] It should be noted that the semiconductor structure is disposed on the side of the dielectric layer 3 away from the substrate 10. The dielectric layer 3 can prevent the gate 22 from direct contact with the substrate 10 and protect the gate 22 from being short-circuited.

[0059] Optionally, such as Figure 1As shown, the gate insulating layer 21 and the gate 22 are sequentially disposed around the outer periphery of the first channel region 12; along the extending direction of the first channel region 12, the gate insulating layer 21 extends to a portion of the source region 11 and a portion of the drain region 13.

[0060] In this embodiment, one end of the gate insulating layer 21 forms isolation between the gate 22 and at least a portion of the source region 11, and the other end forms isolation between the gate 22 and at least a portion of the drain region 13. The gate insulating layer 21 is disposed between the gate 22 and the first channel region 12, and the gate 22 surrounds the outer periphery of the first channel region 12, which can enhance the control of the gate 22 over the first channel region 12 and is beneficial to improving the performance of the semiconductor structure.

[0061] Optionally, refer to Figure 2 The gate 22 is disposed around the outer periphery of the first channel region 12, and the gate insulating layer 21 is disposed between the gate 22 and the first channel region 12 and is disposed around the outer periphery of the gate 22. The orthogonal projection of the gate 22 on the substrate 10 coincides with the orthogonal projection of the first channel region 12 on the substrate 10.

[0062] In this embodiment, the gate 22 surrounds the outer periphery of the first channel region 12, and the gate insulating layer 21 is disposed on the outer periphery of the gate 22, which can further protect the gate 22.

[0063] The orthographic projection of the gate 22 on the substrate 10 coincides with the orthographic projection of the first channel region 12 on the substrate 10. Since the gate insulating layer 21 is disposed on the outer periphery of the gate 22, part of the gate insulating layer 21 will cover part of the source region 11 and the drain region 13.

[0064] Optionally, the thickness of the first channel region 12 in the direction perpendicular to the substrate 10 is not less than 10 nanometers and less than 20 nanometers. Specifically, the thickness of the first channel region 12 is 15 nanometers.

[0065] Based on the same inventive concept, this application provides a memory, the structural schematic diagram of which is shown below. Figures 1 to 8 As shown, the memory includes a memory structure 4 arranged in an array that is insulated from each other. The memory structure 4 includes a plurality of semiconductor structures provided in the above embodiments. The plurality of semiconductor structures are stacked and insulated along a first direction perpendicular to the substrate 10 and arranged in an array in a plane parallel to the substrate 10.

[0066] The gate 22 of the semiconductor structure is located on at least one side of the first channel region 12, and the gate insulating layer 21 is located between the first channel region 12 and the gate 22. One end of the gate insulating layer 21 forms an isolation between the gate 22 and at least a portion of the source region 11, and / or the other end of the gate insulating layer 21 forms an isolation between the gate 22 and at least a portion of the drain region 13.

[0067] In this embodiment, the semiconductor structure of the memory can be a junctionless transistor. When a voltage is applied to the word line 41, and the voltage is negative, the word line 41, the gate insulating layer 21, and the semiconductor layer 1 can form a capacitor structure. Therefore, the word line 41 can deplete the electrons in the source region 11 covered by one end of the gate insulating layer 21 and the electrons in the drain region 13 covered by the other end of the gate insulating layer 21. (See reference...) Figures 5 to 8 The fact that at least a portion of the source region 11 and at least a portion of the source region 13, covered by the gate insulating layer 21, together with the first channel region 12, form an effective channel region helps to increase the effective channel region, alleviate the short-channel effect, and thus reduce the off-state current. When the voltage is positive, the source region 11 covered at one end of the gate insulating layer 21 can accumulate more electrons, and the drain region 13 covered at the other end of the gate insulating layer 21 can accumulate more electrons, which helps to reduce parasitic resistance, increase turn-on current, and improve the performance and reliability of the memory.

[0068] One feasible approach is to refer to Figure 6 Along a second direction parallel to the substrate 10, the memory structure 4 includes multiple rows of semiconductor structures, with the gates 22 of each semiconductor structure in the same row connected to form a word line 41.

[0069] In this embodiment, the word line 41 extends along the second direction and includes the gate 22 of each semiconductor structure located in the same column and the connection line connecting any two adjacent gates 22 of the semiconductor structure.

[0070] Optionally, refer to Figure 5 and Figure 6 A bit line 42 is provided between two adjacent semiconductor structures along a third direction that is parallel to the substrate 10 and perpendicular to the second direction. The bit line 42 extends along a first direction perpendicular to the substrate 10 and is connected to the drain region 13 of the adjacent semiconductor structure.

[0071] In this embodiment, along a third direction, a bit line 42 is provided between the drain region 13 of a semiconductor layer 1 of one semiconductor structure and the drain region 13 of a semiconductor layer 1 of another semiconductor structure located in the same row. The fact that two adjacent semiconductor structures in the same row share a single bit line 42 reduces the size of the memory and improves the integration density of the memory.

[0072] Optionally, the memory further includes a first dielectric layer 43 and a first electrode 44, which are sequentially disposed on the outer periphery of at least a portion of the source region 11 away from the first channel region 12.

[0073] In this embodiment, a portion of the source region 11 of the semiconductor layer 1, the first dielectric layer 43, and the first electrode 44 constitute a storage capacitor structure. Directly utilizing the source region 11 of the semiconductor layer 1 as an electrode plate of the storage capacitor structure can help improve integration.

[0074] In another feasible approach, the gates 22 of each semiconductor structure located in the same vertical column are connected along the first direction to form a word line 41.

[0075] In this embodiment, as Figure 7 and Figure 8 As shown, line 41 extends along the first direction.

[0076] Optionally, along a second direction parallel to the substrate 10, the memory structure includes multiple rows of semiconductor structures, and a bit line 42 is provided on one side of the drain region 13 of the semiconductor structures in the same row, the bit line 42 extending along the second direction.

[0077] In this embodiment, reference Figure 7 and Figure 8 Bit line 42 extends along the second direction and is connected to one end of the drain region 13 of the semiconductor structure in the same column for transmitting signals.

[0078] Based on the same inventive concept, this application provides an electronic device that includes the memory provided in the above embodiments.

[0079] In this embodiment, since the electronic device uses any of the memory provided in the foregoing embodiments, the principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0080] Optionally, the electronic device may include a smartphone, computer, tablet, artificial intelligence, wearable device, or smart mobile terminal.

[0081] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the memory provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.

[0082] Based on the same inventive concept, this application provides a method for manufacturing a memory, the flowchart of which is shown below. Figure 9 As shown, the method includes the following steps S1 to S2.

[0083] S1: An initial storage structure 5 consisting of multiple phase-insulated arrays is fabricated on one side of a substrate 10. The initial storage structure 5 includes semiconductor layers 1 spaced apart along a first direction perpendicular to the substrate 10, and a first insulating layer 51 disposed on both sides of the semiconductor layers 1 along a third direction parallel to the substrate 10 and between the two ends of two adjacent semiconductor layers 1.

[0084] S2: A gate insulating layer 21 and a gate 22 are sequentially disposed on the outer periphery of the first channel region 12 of the semiconductor layer 1, such that one end of the gate insulating layer 21 forms an isolation between the gate 22 and at least a portion of the source region 11 of the semiconductor layer 1, and / or the other end of the gate insulating layer 21 forms an isolation between the gate 22 and at least a portion of the drain region 13 of the semiconductor layer 1.

[0085] In this embodiment, the gate insulating layer 21 covers a portion of the source region 11 at one end and a portion of the drain region 13 at the other end. This enhances the capacitance between the source region 11 and the gate 22 covered by the gate insulating layer 21, as well as the capacitance between the drain region 13 and the gate 22, when a voltage is applied. This enhanced capacitance allows for adjustment of the actual effective channel length. Increasing the effective channel length suppresses short-channel effects and reduces off-state current. By extending the gate insulating layer 21 to a portion of the source region 11 and a portion of the drain region 13 to form isolation, no additional isolation layer or manufacturing process is required, saving manufacturing time and costs.

[0086] In one feasible embodiment, step S1 includes:

[0087] An alternating initial sacrificial layer 71 and an initial semiconductor layer 81 are fabricated on one side of the substrate 10.

[0088] The initial sacrificial layer 71 and the initial semiconductor layer 81 are patterned to form an array of initial memory structure regions 50, resulting in trenches 74 between adjacent memory structure regions 20, and intermediate sacrificial layer 72 and semiconductor layer 1 in memory structure region 50.

[0089] Laterally etch the intermediate sacrificial layer 72 along a third direction to obtain the sacrificial layer 73, such that the side of the sacrificial layer 73 along the third direction forms a groove 75 with the ends of the two adjacent semiconductor layers 1.

[0090] A first insulating layer 51 is manufactured within the groove 74 and the recess 75.

[0091] Remove the sacrificial layer 73 to obtain the initial storage structure 5.

[0092] In this embodiment, Figure 10This is a schematic cross-sectional view of a film obtained after fabricating an alternating initial sacrificial layer 71 and an initial semiconductor layer 81 on one side of a substrate 10. Figure 10 Multiple alternating initial sacrificial layers 71 and initial semiconductor layers 81 can be fabricated, with the specific number set according to actual needs. The initial sacrificial layer 71 is made of superlattice silicon germanide, and the initial semiconductor layer 81 is made of single-crystal silicon. Superlattice silicon germanide is easier to remove in subsequent manufacturing processes.

[0093] Figure 11 This is a schematic diagram of another film layer cross-section obtained after fabricating an alternating initial sacrificial layer 71 and an initial semiconductor layer 81 on one side of a substrate 10. Figure 11 The diagram shows three initial sacrificial layers 71 and three initial semiconductor layers 81 arranged alternately along a first direction. This application uses... Figure 11 We will take one example to introduce a method for manufacturing a memory.

[0094] Figure 12 To pattern the initial sacrificial layer 71 and the initial semiconductor layer 81 to form an arrayed initial memory structure region 50, a trench 74 is obtained between adjacent memory structure regions 20, and a cross-sectional view of the film layer is obtained after obtaining the intermediate sacrificial layer 72 and the semiconductor layer 1 in the memory structure region 50. Figure 12 It is known that the initial memory structure regions 50 are isolated from each other, which can prevent short circuits in the semiconductor layer 1. Specifically, the initial memory structure regions 50 of the array arrangement can be obtained by etching the initial sacrificial layer 71 and the initial semiconductor layer 81.

[0095] Figure 13 A schematic cross-sectional view of the film layer after lateral etching of the intermediate sacrificial layer 72 along a third direction to obtain sacrificial layer 73, such that the side of sacrificial layer 73 along the third direction forms a groove 75 with the ends of the two adjacent semiconductor layers 1. Figure 13 It can be seen that the intermediate sacrificial layer 72 is etched laterally along the third direction, and the two ends of the intermediate sacrificial layer 72 are etched away to form the groove 75.

[0096] Figure 14 A schematic cross-sectional view of the film obtained after manufacturing the first insulating layer 51 in the trench 74 and the recess 75 and removing the sacrificial layer 73. Figure 15 A top view of the film obtained after fabricating the first insulating layer 51 within trenches 74 and recesses 75 and removing the sacrificial layer 73. (Reference) Figure 14 The fabrication of a first insulating layer 51 within trenches 74 and recesses 75 facilitates the isolation of adjacent memory structures to prevent short circuits and provides support for the semiconductor layers 1 of adjacent layers.

[0097] Optionally, after removing the sacrificial layer 73, the process further includes: creating a third insulating layer 62 in the area of ​​the sacrificial layer 73.

[0098] In this embodiment, Figure 16 A schematic cross-sectional view of the film obtained after fabricating the third insulating layer 62 in the region of the sacrificial layer 73; Figure 17 A top view of the film obtained after the third insulating layer 62 is manufactured in the area of ​​the sacrificial layer 73.

[0099] Optionally, in step S2, fabricating a gate insulating layer 21 and a gate 22 sequentially disposed on the outer periphery of the first channel region 12 of the semiconductor layer 1 includes:

[0100] A gate insulating layer 21 is fabricated surrounding the first channel region 12 of the semiconductor layer 1.

[0101] A word line 41 is fabricated around the outer periphery of the gate insulating layer 21 and extending along a second direction, and a second insulating layer 61 is fabricated between two adjacent word lines 41. The second direction is parallel to the substrate 10 and perpendicular to the third direction. The word line 41 includes the gate 22 of each semiconductor structure in the same column.

[0102] In this embodiment, before fabricating the gate insulating layer 21, the third insulating layer 62 needs to be patterned to obtain the area for fabricating the gate insulating layer 21, the gate 22, and the second insulating layer 61. (See reference...) Figure 18 and Figure 19 A gate insulating layer 21 is disposed around the outer periphery of the first channel region 12.

[0103] Figure 18 A schematic cross-sectional view of the film obtained after manufacturing word lines 41 that surround the outer periphery of the gate insulating layer 21 and extend along the second direction, and a second insulating layer 61 between two adjacent word lines 41. Figure 19 A top view of the film layers obtained after fabricating word lines 41 surrounding the outer periphery of the gate insulating layer 21 and extending along the second direction, and a second insulating layer 61 between adjacent word lines 41. (See reference) Figure 18 and Figure 19 The second insulating layer 61 can isolate the word lines 41 of the two adjacent layers to prevent short circuits between the word lines 41.

[0104] Optionally, in step S2, after fabricating the gate insulating layer 21 and the gate 22 sequentially surrounding the first channel region 12 of the semiconductor layer 1, the method further includes:

[0105] A first dielectric layer 43 and a first electrode 44 are sequentially fabricated on the outer periphery of at least a portion of the source region 11 of the semiconductor layer 1 away from the first channel region 12.

[0106] A bit line 42 is formed between the drain region 13 of a semiconductor layer 1 of one semiconductor structure located in the same row along the second direction and the drain region 13 of a semiconductor layer 1 of another semiconductor structure, such that the bit line 42 extends along the first direction.

[0107] In this embodiment, Figure 20 A schematic cross-sectional view of the film obtained after sequentially fabricating a first dielectric layer 43 and a first electrode 44 on the outer periphery of at least a portion of the source region 11 of the semiconductor layer 1 away from the first channel region 12. Figure 21 This is a top view schematic diagram of the film obtained after sequentially fabricating a first dielectric layer 43 and a first electrode 44 on the outer periphery of at least a portion of the source region 11 of semiconductor layer 1 away from the first channel region 12. Figure 20 and Figure 21 It can be seen that a portion of the source region 11 of the semiconductor layer 1, the first dielectric layer 43, and the first electrode 44 constitute a storage capacitor structure. Directly using the source region 11 of the semiconductor layer 1 as an electrode plate of the storage capacitor structure can help improve integration.

[0108] Figure 5 A schematic diagram of the film cross-section obtained by extending the bit line 42 along the first direction between the drain region 13 of a semiconductor layer 1 of one semiconductor structure located in the same row along the second direction and the drain region 13 of a semiconductor layer 1 of another semiconductor structure. Figure 6 A top view schematic diagram of the film layer obtained by fabricating a bit line 42 between the drain region 13 of a semiconductor layer 1 of one semiconductor structure located in the same row along the second direction and the drain region 13 of another semiconductor layer 1 of the same semiconductor structure, such that the bit line 42 extends along the first direction. (Reference) Figure 5 Along with 6, two adjacent semiconductor structures located in the same row share a bit line 42, which can reduce the size of the memory and improve the integration density of the memory.

[0109] In another feasible approach, step S1 includes:

[0110] An alternating initial sacrificial layer 71 and an initial semiconductor layer 81 are fabricated on one side of the substrate 10.

[0111] The initial sacrificial layer 71 and the initial semiconductor layer 81 are patterned to form an array of initial memory structure regions 50, resulting in trenches 74 between adjacent memory structure regions 20, and a first intermediate sacrificial layer 72 and an intermediate semiconductor layer 811 in the memory structure region 50.

[0112] In this embodiment, Figure 22To pattern the initial sacrificial layer 71 and the initial semiconductor layer 81 to form an array of initial memory structure regions 50, a trench 74 is obtained between adjacent memory structure regions 20, and a cross-sectional schematic diagram is obtained after obtaining the first intermediate sacrificial layer 72 and the intermediate semiconductor layer 811 in the memory structure region 50.

[0113] Optionally, after patterning the initial sacrificial layer 71 and the initial semiconductor layer 81 to form an array of initial memory structure regions 50, obtaining trenches 74 between adjacent memory structure regions 20, and obtaining the first intermediate sacrificial layer 72 and the intermediate semiconductor layer 811 in the memory structure region 50, the manufacturing method further includes;

[0114] The intermediate semiconductor layer 811 is patterned to obtain a first intermediate semiconductor layer 82. The first intermediate semiconductor layer 82 includes a plurality of horizontal portions arranged at intervals along a second direction and extending along a third direction, and vertical portions connecting the plurality of horizontal portions.

[0115] A first sub-insulating layer 511 is manufactured between the trench 74 and any two adjacent horizontal sections in the same column.

[0116] By removing the vertical portion and the intermediate region of the first intermediate sacrificial layer 72 corresponding to the vertical portion, a second intermediate semiconductor layer 83 formed by the first intermediate semiconductor layer 82, a second intermediate sacrificial layer 721 formed by the first intermediate sacrificial layer 72, and a first trench 91 extending along the second direction are obtained, such that the width of the remaining vertical portion along the third direction is the width of the bit line.

[0117] The remaining vertical portion and part of the horizontal portion connected to the vertical portion are removed to obtain semiconductor layer 1 and second trench 92.

[0118] The initial bit line 93 is manufactured within the second trench 92.

[0119] The initial bit line 93 is patterned to obtain the third groove 94 and the bit line 42 formed by the initial bit line 93, and the third groove 94 is positioned in the same position as the first groove 91.

[0120] The first isolation layer 95 is manufactured within the third trench 94.

[0121] The second intermediate sacrificial layer 721 is laterally etched along a third direction to obtain a sacrificial layer 73, such that the side of the sacrificial layer 73 along the third direction forms a groove 75 with the ends of the two adjacent semiconductor layers 1.

[0122] A second sub-insulating layer 512 is manufactured within the groove 75, forming a first insulating layer 51 comprising a first sub-insulating layer 511 and a second sub-insulating layer 512.

[0123] Remove the sacrificial layer 73 to obtain a blank area, and create a second isolation layer 96 within the blank area.

[0124] The second isolation layer 96 is patterned to obtain a first groove 97, such that the first groove 97 extends along a first direction, and the first groove 97 includes a region between two adjacent first channel regions 12 located in the same vertical column.

[0125] In this embodiment, Figure 23 A top view of the first sub-insulating layer 511 obtained after the trench 74 is manufactured between any two adjacent horizontal sections in the same column; Figure 24 for Figure 23 Schematic diagram of the cross section at point AA. Figure 25 A top view diagram obtained by removing the middle area of ​​the vertical part and obtaining the first groove 91 extending along the second direction; Figure 26 for Figure 25 Schematic diagram of the cross section at point AA. Figure 27 A top view diagram obtained after removing the remaining vertical portion and part of the horizontal portion connected to the vertical portion to obtain the second intermediate semiconductor layer 83, semiconductor layer 1, and second trench 92; Figure 28 for Figure 27 Schematic diagram of the cross section at point AA. Figure 29 A top view diagram obtained after the initial bit line 93 is manufactured in the second trench 92; Figure 30 for Figure 29 Schematic diagram of the cross section at point AA. Figure 31 To pattern the initial bit line 93, a third groove 94 and a bit line 42 formed by the initial bit line 93 are obtained, and the third groove 94 is positioned the same as the first groove 91, resulting in a top view schematic diagram. Figure 32 for Figure 31 Schematic diagram of the cross section at point AA. Figure 33 A top view diagram obtained after the first isolation layer 95 is manufactured in the third trench 94; Figure 34 for Figure 33 Schematic diagram of the cross section at point AA. Figure 35 A cross-sectional view is obtained by laterally etching the second intermediate sacrificial layer 721 along a third direction to obtain a sacrificial layer 73, such that the side of the sacrificial layer 73 along the third direction forms a groove 75 with the ends of the two adjacent semiconductor layers 1. Figure 36 A cross-sectional view obtained after forming a first insulating layer 51 including a first sub-insulating layer 511 and a second sub-insulating layer 512 in order to manufacture a second sub-insulating layer 512 in the groove 75. Figure 37 A schematic cross-sectional view of the blank area obtained after removing the sacrificial layer 73. Figure 38 This is a top-view diagram obtained after creating the second isolation layer 96 in the blank area. Figure 39 for Figure 38Schematic diagram of the cross section at point AA. Figure 40 To pattern the second isolation layer 96, a first groove 97 is obtained, such that the first groove 97 extends along a first direction, and the first groove 97 includes the area between two adjacent first channel regions 12 located in the same vertical column, as shown in the top view. Figure 41 for Figure 40 Schematic diagram of the cross-section at point AA. Figure 40 and Figure 41 As shown, the width of the first groove 91 along the third direction is greater than the width of the first channel area 12, which is beneficial to make the width of the character lines manufactured subsequently equal to the width of the first channel area 12.

[0126] Optionally, in step S2, fabricating a gate insulating layer 21 and a gate 22 sequentially disposed on the outer periphery of the first channel region 12 of the semiconductor layer 1 includes:

[0127] Along the first direction, a gate insulating layer 21 is conformally formed on the outer periphery of each first channel region 12 located in the same vertical column and in the first groove 97 between two adjacent first channel regions 12.

[0128] The word line 41 is manufactured such that it fills the first groove 97 between two adjacent first channel regions 12 in the same vertical column. The word line 41 includes gates 22 located in the same vertical column and extends along a first direction.

[0129] In this embodiment, the gate insulating layer 21 covers the outer periphery of each first channel region 12 and also covers the groove wall of the first groove 91 between two adjacent first channel regions 12. Figure 42 This is a top view schematic diagram obtained after conformally fabricating a gate insulating layer 21 around the outer periphery of each first channel region 12 located in the same vertical column and in the first groove 97 between two adjacent first channel regions 12 along the first direction. Figure 43 for Figure 42 Schematic diagram of the cross section at point AA.

[0130] Figure 7 A top view of the character line 41 after it is extended along the first direction, so that the character line 41 fills the first groove 97 between two adjacent first channel areas 12 in the same vertical column. Figure 8 for Figure 7 Schematic diagram of the cross section at point AA.

[0131] Optionally, after conformally fabricating the gate insulating layer 21 along the first direction on the outer periphery of each first channel region 12 located in the same vertical column and in the first groove 97 between two adjacent first channel regions 12, and before fabricating the word line 41, the process further includes:

[0132] An initial word line 98 is fabricated covering the gate insulating layer 21 such that the initial word line 98 fills the first groove 97.

[0133] The initial character line 98 is patterned to obtain character lines 41 extending along the first direction and a fourth groove 99 between two adjacent character lines 41.

[0134] The third isolation layer 991 is filled into the fourth trench 99.

[0135] In this embodiment, the fourth groove 99 isolates two adjacent word lines 41. Figure 44 A top view of the initial word line 98 obtained after filling the first groove 97 to create the initial word line 98 covering the gate insulating layer 21. Figure 45 To pattern the initial character line 98, a top view diagram is obtained by obtaining the character line 41 extending along the first direction and the fourth groove 99 between two adjacent character lines 41.

[0136] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0137] 1. In the embodiments of this application, one end of the gate insulating layer forms isolation between the gate and at least a portion of the source region, and / or the other end of the gate insulating layer forms isolation between the gate and at least a portion of the drain region. This can enhance the capacitance of the source region covered by the gate insulating layer, and / or enhance the capacitance at the gate and the drain region covered by the gate insulating layer, when a voltage is applied. Therefore, the length of the actual effective channel region can be controlled by the enhanced capacitance. Increasing the length of the effective channel region can suppress the short-channel effect and help reduce the off-state current.

[0138] 2. In the embodiments of this application, when manufacturing the semiconductor structure, the two ends of the gate insulating layer are directly extended to a portion of the source region and a portion of the drain region to form isolation. There is no need to manufacture an additional isolation layer or add an additional manufacturing process, which helps to save manufacturing time and cost.

[0139] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0140] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0141] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0142] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0143] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0144] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application, the steps in each process can be executed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages may be executed at the same time or at different times. In scenarios where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application does not limit this.

[0145] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor layer, the semiconductor layer including a source region, a first channel region and a drain region, wherein the first channel region is disposed between the source region and the drain region; A gate insulating layer and a gate, the gate being located on at least one side of the first channel region, the gate insulating layer being located between the first channel region and the gate; along the extension direction of the first channel region, one end of the gate insulating layer forms isolation between the gate and at least a portion of the source region, and / or the other end of the gate insulating layer forms isolation between the gate and at least a portion of the drain region; The gate is disposed around the outer periphery of the first channel region, the gate insulating layer is disposed around the outer periphery of the gate, a portion of the gate insulating layer is disposed between the gate and the first channel region, and the orthographic projection of the gate on the substrate coincides with the orthographic projection of the first channel region on the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The source region, the first channel region, and the drain region are all of the same doped dielectric type.

3. A memory, characterized in that, The storage structure includes an array of mutually insulated structures, the storage structure comprising a plurality of semiconductor structures as described in any one of claims 1-2, the plurality of semiconductor structures being stacked and insulated along a first direction perpendicular to the substrate and arranged in an array in a plane parallel to the substrate; The semiconductor structure includes a semiconductor layer, a gate insulating layer, and a gate. The semiconductor layer includes a source region, a first channel region, and a drain region. The first channel region is disposed between the source region and the drain region. The gate of the semiconductor structure is located on at least one side of the first channel region, and the gate insulating layer is located between the first channel region and the gate. Along the extension direction of the first channel region, one end of the gate insulating layer forms isolation between the gate and at least a portion of the source region, and / or the other end of the gate insulating layer forms isolation between the gate and at least a portion of the drain region.

4. The memory according to claim 3, characterized in that, Along a second direction parallel to the substrate, the memory structure includes multiple rows of semiconductor structures, with the gates of each semiconductor structure in the same row connected to form a word line.

5. The memory according to claim 4, characterized in that, A bit line is provided between two adjacent semiconductor structures along a third direction parallel to the substrate and perpendicular to the second direction. The bit line extends along a first direction perpendicular to the substrate and is connected to the drain region of the adjacent semiconductor structure.

6. The memory according to claim 4 or 5, characterized in that, It also includes a first dielectric layer and a first electrode, wherein the first dielectric layer and the first electrode are sequentially disposed on the outer periphery of at least a portion of the source region away from the first channel region.

7. The memory according to claim 3, characterized in that, Along the first direction, the gates of each semiconductor structure located in the same vertical column are connected to form a word line.

8. The memory according to claim 7, characterized in that, Along a second direction parallel to the substrate, the memory structure includes multiple rows of semiconductor structures, and a bit line is disposed on one side of the drain region of the semiconductor structures in the same row, the bit line extending along the second direction.

9. The memory according to claim 3, characterized in that, The source region, the first channel region, and the drain region are all of the same doped dielectric type.

10. The memory according to claim 3 or 9, characterized in that, The gate insulating layer and the gate are sequentially disposed around the outer periphery of the first channel region; along the extending direction of the first channel region, the gate insulating layer extends to a portion of the source region and a portion of the drain region.

11. The memory according to claim 3 or 9, characterized in that, The gate is disposed around the outer periphery of the first channel region, the gate insulating layer is disposed around the outer periphery of the gate, a portion of the gate insulating layer is disposed between the gate and the first channel region, and the orthographic projection of the gate on the substrate coincides with the orthographic projection of the first channel region on the substrate.

12. An electronic device, characterized in that, Includes the memory described in any one of claims 3 to 11.

13. A method for manufacturing a memory, characterized in that, For manufacturing the memory according to any one of claims 3-11, comprising: An initial storage structure is fabricated on one side of a substrate by an array of multiple phase-insulating layers. The initial storage structure includes semiconductor layers spaced apart along a first direction perpendicular to the substrate, and a first insulating layer disposed on both sides of the semiconductor layers along a third direction parallel to the substrate and between the two ends of two adjacent semiconductor layers. A gate insulating layer and a gate are sequentially disposed on the outer periphery of a first channel region of the semiconductor layer, such that one end of the gate insulating layer forms isolation between the gate and at least a portion of the source region of the semiconductor layer, and / or the other end of the gate insulating layer forms isolation between the gate and at least a portion of the drain region of the semiconductor layer.

14. The manufacturing method according to claim 13, characterized in that, Manufacturing a gate insulating layer and a gate disposed on the outer periphery of the first channel region of the semiconductor layer, comprising: Fabricate a gate insulating layer surrounding the first channel region of the semiconductor layer; A word line is fabricated around the outer periphery of the gate insulating layer and extending along a second direction, and a second insulating layer is formed between two adjacent word lines, the second direction being parallel to the substrate and perpendicular to the third direction; the word line includes the gates of each semiconductor structure in the same column.

15. The manufacturing method according to claim 14, characterized in that, After fabricating the gate insulating layer and the gate disposed in the first channel region of the semiconductor layer, the method further includes: A first dielectric layer and a first electrode are sequentially formed on the outer periphery of at least a portion of the source region of the semiconductor layer away from the first channel region; A bit line is created between the drain region of a semiconductor layer of one semiconductor structure located in the same row along the second direction and the drain region of a semiconductor layer of another semiconductor structure, such that the bit line extends along the first direction.

16. The manufacturing method according to claim 13, characterized in that, Manufacturing a gate insulating layer and a gate sequentially disposed on the outer periphery of the first channel region of the semiconductor layer includes: Along the first direction, a gate insulating layer is conformally formed on the outer periphery of each of the first channel regions located in the same vertical column and in the first groove between two adjacent first channel regions. The word lines are manufactured such that they fill a first groove between two adjacent first channel regions in the same vertical column, the word lines including each of the gates located in the same vertical column and extending along a first direction.

17. The manufacturing method according to claim 13, characterized in that, An initial memory structure is fabricated on one side of a substrate, comprising an array of phase-insulating layers arranged at intervals along a first direction perpendicular to the substrate, and a first insulating layer disposed between the two sides of the semiconductor layers along a third direction parallel to the substrate and between the two ends of two adjacent semiconductor layers. An alternating initial sacrificial layer and an initial semiconductor layer are fabricated on one side of the substrate; The initial sacrificial layer and the initial semiconductor layer are patterned to form an array of initial memory structure regions, resulting in trenches between adjacent memory structure regions, and intermediate sacrificial layers and semiconductor layers in the memory structure regions. The intermediate sacrificial layer is laterally etched along a third direction to obtain a sacrificial layer, such that the side of the sacrificial layer along the second direction forms a groove with the end of the two adjacent semiconductor layers; A first insulating layer is formed within the trench and the recess; Remove the sacrificial layer to obtain the initial storage structure.

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