Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: forming a laminated structure on a substrate; a first isolation structure, a sacrificial structure and a filling layer are formed in the laminated structure, the first semiconductor layer is patterned to form initial active patterns arranged in an array, the first isolation structure comprises a first isolation part and a second isolation part, and the size of the first isolation part in the second direction is larger than that of the second isolation part in the second direction; the adjacent first isolation parts in the second direction are in contact; removing part of the filling layer and forming an initial word line layer; removing the sacrificial structure to respectively form a bit line slot and a capacitance slot, patterning the initial active pattern as an active structure, and patterning the initial word line layer as a word line structure; bit line structures and capacitor structures are formed in the bit line grooves and the capacitor grooves respectively, and the bit line structures and the capacitor structures are alternately arranged in the first direction and the second direction. According to the preparation method of the semiconductor structure, the manufacturing process difficulty of the word line structure is simplified.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same. Background Art

[0002] The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures based on existing structures is a favorable means to break through existing technical barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal memory cells (Multilayer Horizontal Cell, MHC), which usually includes multiple transistors stacked on a substrate, meets the above needs.

[0004] However, since the transistors are suspended on the substrate, the manufacturing process of the horizontal word lines is difficult and it is easy for the word lines to be broken or adjacent word lines to be short-circuited, thus affecting the performance of the semiconductor structure. Summary of the invention

[0005] According to a first aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: forming a stacked structure located on a substrate, the stacked structure comprising a first semiconductor layer and a second semiconductor layer alternately stacked in a vertical direction; forming a first isolation structure, a sacrificial structure and a filling layer in the stacked structure, and patterning the first semiconductor layer to form an initial active pattern arranged in an array, wherein the first isolation structure is arranged in an array along a first direction and a second direction, the first isolation structure comprises a first isolation portion located in a layer where the initial active pattern is located and a second isolation portion located in a layer where the second semiconductor layer is located, and the size of the first isolation portion along the second direction is greater than The second isolation portion has a size along the second direction and is in contact with the first isolation portion adjacent to the second direction, the sacrificial structure is located between the first isolation structures adjacent to the second direction, and the filling layer is located in the layer where the second semiconductor layer is located; part of the filling layer is removed, and an initial word line layer is formed; the sacrificial structure and at least part of the filling layer are removed to form a bit line groove and a capacitor groove respectively, and the initial active pattern is patterned as an active structure, and the patterned initial word line layer is a word line structure extending along the first direction; a bit line structure and a capacitor structure are formed in the bit line groove and the capacitor groove respectively, and the bit line structure and the capacitor structure are alternately arranged in the first direction and alternately arranged in the second direction.

[0006] In some embodiments, forming a first isolation structure, a sacrificial structure, and a filling layer in a stacked structure, and patterning the first semiconductor layer to form an initial active pattern arranged in an array includes: etching the stacked structure to form a plurality of rectangular grooves, the rectangular grooves exposing a portion of the surface of the substrate, the plurality of rectangular grooves being arranged in an array along a first direction and a second direction, the spacing between adjacent rectangular grooves along the first direction being greater than the spacing between adjacent rectangular grooves along the second direction; removing a portion of the first semiconductor layer along the rectangular grooves to form an initial active pattern and isolation grooves arranged in an array; and forming a first isolation structure filling the isolation grooves.

[0007] In some embodiments, after forming multiple rectangular grooves, it also includes: filling an initial isolation structure in the rectangular groove; etching the stacked structure to form multiple columnar grooves, the columnar grooves expose part of the surface of the substrate, and the columnar grooves are located between the initial isolation structures adjacent to each other along the second direction; removing the second semiconductor layer along the columnar grooves to form interlayer gaps between the first semiconductor layers; filling the first dielectric layer, the second dielectric layer and the third dielectric layer in the columnar grooves and the interlayer gaps to form a sacrificial structure located in the columnar grooves and a filling layer located in the interlayer gaps; removing part of the first semiconductor layer along the rectangular grooves to form an initial active pattern and isolation grooves arranged in an array, including: removing at least part of the initial isolation structure to expose the rectangular grooves; removing the exposed part of the first semiconductor layer along the rectangular grooves to form an isolation groove, the isolation groove comprising a first isolation groove portion located in the layer where the first semiconductor layer is located, the first isolation groove portions are connected in the second direction and disconnect the initial active pattern in the first direction.

[0008] In some embodiments, a first dielectric layer covers a surface of an initial active pattern, a second dielectric layer covers a surface of a second dielectric layer and fills an interlayer gap, a portion of the filling layer is removed, and an initial word line layer is formed, including: removing a portion of the first dielectric layer to form an initial word line groove; and forming the initial word line layer in the initial word line groove.

[0009] In some embodiments, the initial word line layer includes a gate oxide material layer and a conductive material layer; forming the initial word line layer in the initial word line groove includes: forming a gate oxide material layer covering the surface of the initial active pattern in the initial word line groove; forming a conductive material layer covering the surface of the gate oxide material layer and filling the initial word line groove.

[0010] In some embodiments, the sacrificial structure includes a first sacrificial structure and a second sacrificial structure, the first sacrificial structure and the second sacrificial structure are arranged alternately in a first direction and alternately in a second direction; the sacrificial structure and at least part of the filling layer are removed to form a bit line groove and a capacitor groove, respectively, and the initial active pattern is patterned as an active structure, and the patterned initial word line layer is a word line structure extending along the first direction, including: removing the first sacrificial structure to expose the capacitor vertical groove, removing part of the initial active pattern along the capacitor vertical groove to form a capacitor horizontal groove, the capacitor vertical groove and the capacitor horizontal groove constitute a capacitor groove; filling the capacitor groove with a third sacrificial structure; removing the second sacrificial structure to expose the bit line vertical groove, removing part of the initial active pattern along the bit line vertical groove to form a bit line horizontal groove, the bit line vertical groove and the bit line horizontal groove constitute a bit line groove, and the remaining initial active pattern is used as an active structure.

[0011] In some embodiments, after removing the second sacrificial structure to expose the bit line vertical groove and before removing a portion of the initial active pattern along the capacitor vertical groove, it also includes: removing a portion of the initial word line layer along the bit line vertical groove, and the remaining initial word line layer serves as a word line structure; forming a second isolation structure, the second isolation structure is sandwiched between the word line structure and the bit line vertical groove.

[0012] According to a second aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a stacked structure located on a substrate, the stacked structure comprising a plurality of storage layers stacked in a vertical direction, each storage layer comprising a plurality of active structures arranged in an array along a first direction and a second direction and a word line structure extending along the first direction; a bit line structure and a capacitor structure located on both sides of each active structure along the second direction, the bit line structure and the capacitor structure being alternately arranged in the first direction and alternately arranged in the second direction; a first isolation structure running through the stacked structure, the first isolation structure being arranged in an array along the first direction and the second direction, the first isolation structure comprising a first isolation portion located in a layer where the active structure is located and a second isolation portion located in a layer where the word line structure is located, the size of the first isolation portion along the second direction being larger than the size of the second isolation portion along the second direction, the first isolation portions adjacent to each other along the second direction being in contact with each other, and the bit line structure and the capacitor structure being located between the first isolation structures adjacent to each other along the second direction.

[0013] In some embodiments, the bit line structure includes a bit line vertical portion and a bit line horizontal portion, the bit line vertical portion penetrates the stack structure along the vertical direction, the bit line horizontal portion is located on both sides of the bit line vertical portion along the second direction and is arranged at intervals in the vertical direction, and the bit line horizontal portion contacts the active structure.

[0014] In some embodiments, the capacitor structure includes a vertical capacitor portion and a horizontal capacitor portion, the vertical capacitor portion penetrates the stacked structure along the vertical direction, the horizontal capacitor portion is located on both sides of the vertical capacitor portion along the second direction and is arranged at intervals in the vertical direction, the horizontal capacitor portion includes a first electrode portion, a capacitor dielectric layer and a second electrode portion, the capacitor dielectric layer is sandwiched between the first electrode portion and the second electrode portion, the first electrode portion is in contact with the active structure, and the second electrode portion is in contact with the vertical capacitor portion.

[0015] In some embodiments, the word line structure includes a first word line portion and a second word line portion alternately connected along a first direction, the first word line portion at least covers the active structure, the second word line portion is located between adjacent first isolation structures along a second direction, and the size of the first word line portion along the second direction is greater than the size of the second word line portion along the second direction.

[0016] In some embodiments, it also includes: a second isolation structure, the second isolation structure is sandwiched between the first word line portion and the bit line structure; and a third isolation structure, the third isolation structure is sandwiched between the first word line portion and the capacitor structure.

[0017] In some embodiments, the first word line portion has arc-shaped sidewalls opposite to each other along the second direction.

[0018] In some embodiments, the size of the active structure in the first direction is non-uniform, and the active structure has a protrusion facing the contact surface between adjacent first isolation structures.

[0019] In the disclosed embodiments, an isolation structure and a sacrificial structure are formed in the stacked structure, which can define and divide the device structure setting area in advance, improve the integration between the device structures and effectively improve the isolation effect between the device structures. By forming a filling layer to occupy the space and then removing the filling layer to form an initial word line layer, the manufacturing process difficulty of the horizontal word line is simplified, and it can be ensured that the initial word line layer is arranged at intervals in the vertical direction, avoiding the occurrence of short circuits or open circuits in the word line structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment; Figure 2 is a flow chart of a method for preparing a semiconductor structure according to an exemplary embodiment; Figure 3A and FIG. 3B to FIG. 19A and Fig.19B is a schematic diagram of a semiconductor structure showing a process of preparing a semiconductor structure according to an embodiment of the present disclosure, wherein: Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A It is a schematic diagram of a vertical section of a semiconductor structure during the preparation process. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B and Fig.19B This is a schematic diagram of a horizontal cross-section of a semiconductor structure during the preparation process. DETAILED DESCRIPTION

[0021] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0022] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0023] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, such that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0024] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0025] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0026] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0027] Figure 1 is a three-dimensional schematic diagram of a semiconductor structure 10 according to an embodiment of the present disclosure; Figure 2 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure; Figure 3A and FIG. 3B to FIG. 19A and Fig.19B is a schematic diagram of a semiconductor structure preparation process according to an embodiment of the present disclosure, wherein: FIG. 3A to FIG. 19A It is a schematic diagram of a vertical section of a semiconductor structure during the preparation process. FIG. 3B to FIG. 19B This is a schematic diagram of a horizontal cross-section of a semiconductor structure during the preparation process. Figure 1 and FIG. 3A to FIG. 19B In the figure, the first direction D1 and the second direction D2 are horizontal directions parallel to the plane where the substrate 100 is located, and the first direction D1 intersects with the second direction D2, for example, the first direction D1 may be perpendicular to the second direction D2, and the vertical direction D3 is a direction intersecting with the plane where the substrate 100 is located, for example, the vertical direction D3 is perpendicular to the plane where the substrate 100 is located.

[0028] The following will describe in detail the method for preparing the semiconductor structure provided by the embodiment of the present disclosure in conjunction with the accompanying drawings. Figure 2 As shown, the preparation method comprises at least the following steps: S210: forming a stacked structure on a substrate, the stacked structure comprising first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction; S220: forming a first isolation structure, a sacrificial structure and a filling layer in the stacked structure, and patterning the first semiconductor layer to form an initial active pattern arranged in an array; S230: removing part of the filling layer and forming an initial word line layer; S240: removing the sacrificial structure and at least a portion of the filling layer to form a bit line trench and a capacitor trench respectively, and patterning the initial active pattern into an active structure, and patterning the initial word line layer into a word line structure extending along the first direction; S250: forming a bit line structure and a capacitor structure in the bit line trench and the capacitor trench respectively, wherein the bit line structure and the capacitor structure are alternately arranged in the first direction and alternately arranged in the second direction.

[0029] It should be understood that Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0030] In the preparation method of the semiconductor structure provided by the present disclosure, in the first aspect, by forming an isolation structure and a sacrificial structure in the stacked structure before each device structure (such as a transistor, a bit line and a capacitor) is formed, the area where each device structure is set can be defined and divided in advance, the integration between each device structure is improved, and the isolation effect between the device structures is effectively improved. In the second aspect, a filling layer is formed to occupy a place, and then the filling layer is removed to form an initial word line layer, which simplifies the difficulty of the manufacturing process of the horizontal word line, and can ensure that the initial word line layer is arranged at intervals in the vertical direction, avoiding the occurrence of a short circuit in the word line structure in the vertical direction. In the third aspect, after forming the initial active pattern and the initial word line layer, the initial active pattern is patterned into an active structure using a bit line groove and a capacitor groove, and the initial word line layer is patterned into a horizontally extending word line structure using a bit line groove and a capacitor groove, which can accurately control the morphology of the active structure and the word line structure, avoiding the occurrence of a break or short circuit in the horizontal direction of the word line structure, which is conducive to improving the performance of the semiconductor structure.

[0031] In some embodiments, reference Figure 3A and Figure 3B As shown, Figure 3A Vertical section diagram, Figure 3B The middle left picture is Figure 3A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Figure 3B The middle right picture is Figure 3A Schematic diagram of a horizontal section of the second horizontal section H2-H2' in FIG. After providing the substrate 100, a stacked structure SG located on the substrate 100 is formed. The stacked structure SG includes a first semiconductor layer 101 and a second semiconductor layer 102 alternately stacked along a vertical direction D3. The first horizontal section H1-H1' is a section at the level where the first semiconductor layer 101 is located, and the second horizontal section H2-H2' is a section at the level where the second semiconductor layer 102 is located. In the figure, the first semiconductor layer 101 is used as an example as the top layer of the stacked structure SG. In fact, the top layer of the stacked structure SG can also be the second semiconductor layer 102.

[0032] The material of the substrate 100 includes a semiconductor material, for example, a single-element semiconductor material (for example, silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art.

[0033] The materials of the first semiconductor layer 101 and the second semiconductor layer 102 are different. The materials of the first semiconductor layer 101 and the second semiconductor layer 102 can be single crystal silicon, polycrystalline silicon, germanium, silicon germanium or oxide semiconductor materials (for example, zinc tin oxide (ZnO x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn x O), Indium Gallium Zinc Oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium oxide silicon (In x Ga y Si z O, commonly known as "IGSO") and one or more of other similar materials). For example, the first semiconductor layer 101 is single crystal silicon, and the second semiconductor layer 102 is silicon germanium. The first semiconductor layer 101 and the second semiconductor layer 102 can be formed alternately in sequence by an epitaxial growth process or a deposition process, and the deposition process can include chemical vapor deposition, atomic layer deposition process, plasma enhanced physical vapor deposition, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition. The thickness of the first semiconductor layer 101 in the vertical direction is greater than the thickness of the second semiconductor layer 102 in the vertical direction, which is conducive to improving the material quality of the first semiconductor layer 101.

[0034] In some embodiments, reference Figure 4A and Figure 4B As shown, Figure 4A The middle left picture is Figure 4B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Figure 4A The middle right picture is Figure 4B A schematic diagram of a vertical section of the second vertical section V2-V2', Figure 4B The middle left picture is Figure 4A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Figure 4B The middle right picture is Figure 4ASchematic diagram of a horizontal section of the second horizontal section H2-H2' in FIG. The stacked structure SG is etched to form a plurality of rectangular grooves T1, the rectangular grooves T1 exposing a portion of the surface of the substrate 100, and the plurality of rectangular grooves T1 are arranged in an array along the first direction D1 and the second direction D2, and the spacing between adjacent rectangular grooves T1 along the first direction D1 is greater than the spacing between adjacent rectangular grooves T1 along the second direction D2. The bottom surface of the rectangular groove T1 may be lower than or flush with the top surface of the substrate 100. The shape of the projection of each rectangular groove T1 along the vertical direction D3 is a rectangle or a rounded rectangle, and the length of each rectangular groove T1 along the second direction D2 is greater than the width of the rectangular groove T1 along the first direction D1. The plurality of rectangular grooves T1 arranged at intervals along the first direction D1 may be defined as a column of rectangular grooves T1, and the plurality of rectangular grooves T1 arranged at intervals along the second direction D2 may be defined as a row of rectangular grooves T1. The two ends of each column of rectangular grooves T1 arranged along the first direction D1 along the second direction D2 are aligned in the second direction D2, that is, the projections of the multiple rectangular grooves T1 in each column of rectangular grooves T1 along the first direction D1 are substantially overlapped. The two ends of each row of rectangular grooves T1 arranged along the second direction D2 are aligned in the first direction D1, that is, the projections of the multiple rectangular grooves T1 in each row of rectangular grooves T1 along the second direction D2 are substantially overlapped. The first vertical section V1-V1' spans the space between the multiple rectangular grooves T1 along the second direction D2, and the second vertical section V2-V2' spans the multiple rectangular grooves T1 along the second direction D2.

[0035] In some embodiments, after forming a mask layer on the top surface of the stacked structure SG, the mask layer and the stacked structure SG may be patterned. The mask layer may be used to protect the top surface of the stacked structure SG to avoid damage to the first semiconductor layer 101 or the second semiconductor layer 102 at the top layer of the stacked structure SG during the etching process.

[0036] In some embodiments, reference Figure 5A and Figure 5B As shown, Figure 5A The middle left picture is Figure 5B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Figure 5A The middle right picture is Figure 5B A schematic diagram of a vertical section of the second vertical section V2-V2', Figure 5B The middle left picture is Figure 5A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Figure 5B The middle right picture is Figure 5ASchematic diagram of a horizontal section of the second horizontal section H2-H2' in the figure. An initial isolation structure 110 is filled in the rectangular groove T1, and the initial isolation structure 110 is planarized. For example, the top surface of the initial isolation structure 110 may be flush with the top surface of the mask layer on the stacked structure SG. The initial isolation structure 110 may be a single-layer structure or a multi-layer structure. For example, the initial isolation structure 110 may include a first initial isolation layer 111 that conformally covers the inner wall of the rectangular groove T1 and a second initial isolation layer 112 that fills the inside of the rectangular groove T1. The material of the initial isolation structure 110 includes a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. The material of the initial isolation structure 110 may also include a sacrificial material, such as aluminum oxide, amorphous carbon, polycrystalline silicon, and the like. In this example, the first initial isolation layer 111 is silicon nitride, and the second initial isolation layer 112 is polycrystalline silicon.

[0037] In some embodiments, reference Fig. 6A and Figure 6B As shown, Fig. 6A The middle left picture is Figure 6B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig. 6A The middle right picture is Figure 6B A schematic diagram of a vertical section of the second vertical section V2-V2', Figure 6B The middle left picture is Fig. 6A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Figure 6B The middle right picture is Fig. 6A Schematic diagram of a horizontal section of the second horizontal section H2-H2' in the figure. The stacked structure SG is etched to form a plurality of columnar grooves T2, the columnar grooves T2 expose a portion of the surface of the substrate 100, and the columnar grooves T2 are located between the initial isolation structures 110 adjacent along the second direction D2. The bottom surface of the columnar groove T2 may be lower than or flush with the top surface of the substrate 100. The shape of the projection of each columnar groove T2 along the vertical direction D3 is circular or elliptical. A columnar groove T2 is formed between every two initial isolation structures 110 adjacent along the second direction D2, and the plurality of columnar grooves T2 are arranged in an array along the first direction D1 and the second direction D2. Both ends of the columnar groove T2 along the first direction D1 are in contact with the initial isolation structure 110.

[0038] In some embodiments, reference Fig. 7A and Figure 7B As shown, Fig. 7A The middle left picture is Figure 7B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig. 7A The middle right picture is Figure 7B A schematic diagram of a vertical section of the second vertical section V2-V2', Figure 7B The middle left picture is Fig. 7A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Figure 7B The middle right picture is Fig. 7A The second semiconductor layer 102 is removed along the columnar groove T2 to form an interlayer gap G1 between the first semiconductor layers 101, and the remaining first semiconductor layer 101 is supported by the initial isolation structure 110. The second semiconductor layer 102 is laterally etched by a wet etching process.

[0039] In some embodiments, reference Fig. 8A and Figure 8B As shown, Fig. 8A The middle left picture is Figure 8B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig. 8A The middle right picture is Figure 8B A schematic diagram of a vertical section of the second vertical section V2-V2', Figure 8B The middle left picture is Fig. 8A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Figure 8B The middle right picture is Fig. 8A Schematic diagram of a horizontal section of the second horizontal section H2-H2' in FIG. Through the interlayer gap G1, the remaining first semiconductor layer 101 is thinned to increase the spatial height of the interlayer gap G1 in the vertical direction D3. The thickness of the thinned first semiconductor layer 101 in the vertical direction D3 may be less than the spatial height of the increased interlayer gap G1 in the vertical direction D3, and the thinned first semiconductor layer 101 is used to form a device structure, for example, to form the source, drain and channel layer of a transistor. By first forming a second semiconductor layer 102 with a smaller thickness and a first semiconductor layer 101 with a larger thickness, and then thinning the first semiconductor layer 101, the quality of the first semiconductor layer 101 can be effectively improved, thereby improving the electrical performance of the subsequently formed device structure.

[0040] In some embodiments, reference Fig. 9A and Fig. 9B As shown, Fig. 9A The middle left picture is Fig. 9B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig. 9A The middle right picture is Fig. 9B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig. 9B The middle left picture is Fig. 9A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig. 9B The middle right picture is Fig. 9ASchematic diagram of a horizontal section of the second horizontal section H2-H2' in FIG. A first dielectric layer 121, a second dielectric layer 122 and a third dielectric layer 123 are sequentially formed in the columnar groove T2 and the interlayer gap G1 to form a sacrificial structure 120a located in the columnar groove T2 and a filling layer 120b located in the interlayer gap G1. The first dielectric layer 121 covers the exposed surface of the first semiconductor layer 101, and the first dielectric layer 121 also covers the exposed surface of the substrate 100. The second dielectric layer 122 covers the surface of the first dielectric layer 121 and fills the interlayer gap G1. The second dielectric layer 122 is also partially located on the sidewall of the columnar groove T2. The third dielectric layer 123 covers the second dielectric layer 122 and fills the columnar groove T2. The sacrificial structure 120a includes the third dielectric layer 123 and a portion of the second dielectric layer 122, and the filling layer 120b includes the first dielectric layer 121 and a portion of the second dielectric layer 122. The materials of the first dielectric layer 121, the second dielectric layer 122 and the third dielectric layer 123 include dielectric materials, such as silicon oxide, silicon nitride or silicon oxynitride, or sacrificial materials, such as aluminum oxide, amorphous carbon, polysilicon, etc. In one example, the material of the first dielectric layer 121 is silicon nitride, the material of the second dielectric layer 122 is silicon oxide, and the material of the third dielectric layer 123 is polysilicon.

[0041] In some embodiments, the sacrificial structure 120a includes a first sacrificial structure 120a1 and a second sacrificial structure 120a2, and the first sacrificial structure 120a1 and the second sacrificial structure 120a2 are alternately arranged in the first direction D1 and alternately arranged in the second direction D2. A portion of the sacrificial structure 120a is used as the first sacrificial structure 120a1 to form a capacitor structure later, and another portion of the sacrificial structure 120a is used as the second sacrificial structure 120a2 to form a bit line structure later.

[0042] In some embodiments, reference Fig. 10A and Fig. 10B As shown, Fig. 10A The middle left picture is Fig. 10B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig. 10A The middle right picture is Fig. 10B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig. 10B The middle left picture is Fig. 10A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig. 10B The middle right picture is Fig. 10ASchematic diagram of a horizontal section of the third horizontal section H3-H3' in FIG. At least a portion of the initial isolation structure 110 is removed to expose the rectangular groove T1. For example, dry etching can be used to remove the initial isolation structure 110 using a mask layer as a mask. The sidewall of the rectangular groove T1 exposes a portion of the sacrificial structure 120a. The size of the remaining portion of the first semiconductor layer 101 located between adjacent columns of rectangular grooves T1 is smaller than the size of the remaining portion of the first semiconductor layer 101 located between adjacent rows of rectangular grooves T1.

[0043] In some embodiments, reference Fig.11A and Fig. 11B As shown, Fig.11A The middle left picture is Fig. 11B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig.11A The middle right picture is Fig. 11B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig. 11B The middle left picture is Fig.11A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig. 11B The middle right picture is Fig.11A A schematic diagram of a horizontal section of the third horizontal section H3-H3' in FIG. A portion of the first semiconductor layer 101 is removed along the rectangular groove T1 to form an initial active pattern 201 and an isolation groove T3 arranged in an array, and a first isolation structure 130 is formed to fill the isolation groove T3. The portion of the first semiconductor layer 101 is removed along the rectangular groove T1 to form an initial active pattern 201 and an isolation groove T3 arranged in an array, including: Fig. 10A and Fig. 10B As shown, after removing at least part of the initial isolation structure 110 to expose the rectangular groove T1, the exposed part of the first semiconductor layer 101 is removed along the rectangular groove T1 to form an isolation groove T3, the isolation groove T3 includes a first isolation groove portion T3a located at the layer where the original first semiconductor layer 101 is located, the first isolation groove portion T3a of each row of isolation grooves T3 are connected in the second direction D2 and disconnect the initial active pattern 201 in the first direction D1. The isolation groove T3 also includes a second isolation groove portion T3b located at the layer where the first dielectric layer 121 on the surface of the first semiconductor layer 101 is located, the size of the first isolation groove portion T3a along the second direction D2 is greater than the size of the second isolation groove portion T3b along the second direction D2, and the size of the first isolation groove portion T3a along the first direction D1 is greater than the size of the second isolation groove portion T3b along the first direction D1.

[0044] The initial active patterns 201 arranged in an array are arranged in four directions along the first direction D1 and the second direction D2. A plurality of initial active patterns 201 arranged at intervals along the second direction D2 may be defined as a row of initial active patterns 201, and a plurality of initial active patterns 201 arranged at intervals along the first direction D1 may be defined as a column of initial active patterns 201. Both ends of each column of initial active patterns 201 arranged along the first direction D1 along the direction of the second direction D2 are aligned in the second direction D2, that is, the projections of the plurality of initial active patterns 201 in each column of initial active patterns 201 along the first direction D1 are substantially overlapped. Both ends of each row of initial active patterns 201 arranged along the second direction D2 along the direction of the first direction D1 are aligned in the first direction D1, that is, the projections of the plurality of initial active patterns 201 in each row of initial active patterns 201 along the second direction D2 are substantially overlapped.

[0045] In some embodiments, the exposed portion of the first semiconductor layer 101 can be laterally etched along the rectangular groove T1 by a wet etching process. Since the size of the portion of the first semiconductor layer 101 located between adjacent columns of rectangular grooves T1 is smaller than the size of the portion of the first semiconductor layer 101 located between adjacent rows of rectangular grooves T1, the portion of the first semiconductor layer 101 located between adjacent columns of rectangular grooves T1 is basically removed, that is, the portion of the first semiconductor layer 101 located between adjacent rectangular grooves T1 in the second direction D2 is basically removed, while the portion of the first semiconductor layer 101 located between adjacent rows of rectangular grooves T1 is still retained, and the first semiconductor layer 101 retained after the wet etching process is used as the initial active pattern 201, so that the initial active pattern 201 is disconnected in the first direction D1, that is, the first semiconductor layer 101 is separated into a plurality of initial active patterns 201 arranged at intervals in the first direction D1. The final formed initial active pattern 201 has a protrusion toward the contact surface between adjacent first isolation structures 130 in the second direction D2. The size of the initial active pattern 201 in the first direction D1 is uneven. Along the second direction D2, the size of the middle part of the initial active pattern 201 is larger than the size of the two ends of the initial active pattern 201.

[0046] In some embodiments, when removing the exposed portion of the first semiconductor layer 101 , the portion of the first dielectric layer 121 in the columnar trench T2 exposed by the portion of the rectangular trench T1 is also removed, thereby exposing a portion of the second dielectric layer 122 in the sacrificial structure 120 a .

[0047] In some embodiments, the first isolation structure 130 is arranged in an array along the first direction D1 and the second direction D2. The first isolation structure 130 includes a first isolation portion 130a located at a layer where the initial active pattern 201 is located and a second isolation portion 130b located at a layer where the second semiconductor layer 102 is located. The size of the first isolation portion 130a along the second direction D2 is greater than the size of the second isolation portion 130b along the second direction D2, and the adjacent first isolation portions 130a along the second direction D2 are in contact.

[0048] In some embodiments, the first isolation structure 130 may be a single-layer structure or a multi-layer structure. For example, the first isolation structure 130 may include a first isolation layer 131 that conformally covers the inner wall of the rectangular groove T1, a second isolation layer 132, and a third isolation layer 133 that fills the inside of the rectangular groove T1. In this example, the first isolation structure 130 is an ONO (Oxide-Nitride-Oxide) structure, the first isolation layer 131 is silicon oxide, the second isolation layer 132 is silicon nitride, and the third isolation layer 133 is silicon oxide. The first isolation layer 131 may fill the portion between adjacent rectangular grooves T1 in the second direction D2.

[0049] In some embodiments, reference Fig. 12A and Fig. 12B As shown, Fig. 12A The middle left picture is Fig. 12B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig. 12A The middle right picture is Fig. 12B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig. 12B The middle left picture is Fig. 12A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig. 12B The middle right picture is Fig. 12A Schematic diagram of a horizontal section of the third horizontal section H3-H3' in FIG. The first sacrificial structure 120a1 is removed to expose the capacitor vertical groove T21. For example, a mask layer may be formed to protect a portion of the sacrificial structures 120a among the multiple sacrificial structures 120a, namely, the first sacrificial structure 120a2, and then the mask layer is used as a mask to remove another portion of the sacrificial structures 120a among the multiple sacrificial structures 120a, namely, the first sacrificial structure 120a1, by dry etching. In the process of removing the first sacrificial structure 120a1, only the second dielectric layer 122 and the third dielectric layer 123 are removed, and the first dielectric layer 121 of the side wall of the initial active pattern 201 is retained to avoid damage to the side wall morphology of the initial pattern 201 by dry etching. The third horizontal section H3-H3' is a section at the level where the first dielectric layer 121 is located.

[0050] In some embodiments, reference Fig.13A and Fig. 13B As shown, Fig.13A The middle left picture is Fig. 13B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig.13A The middle right picture is Fig. 13B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig. 13B The middle left picture is Fig.13A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig. 13B The middle right picture is Fig.13A Schematic diagram of a horizontal section of the third horizontal section H3-H3' in FIG. Along the capacitor vertical groove T21, a portion of the first dielectric layer 121 is laterally etched by a wet etching process, and the side wall of the initial active pattern 201 is exposed. Along the capacitor vertical groove T21, a portion of the initial active pattern 201 is continuously removed to form a capacitor horizontal groove T22, and the capacitor vertical groove T21 and the capacitor horizontal groove T22 constitute a capacitor groove CAt. The size of the space formed by the laterally removed portion of the first dielectric layer 121 in the second direction D2 is greater than the size of the space formed by the laterally removed portion of the initial active pattern 201 in the second direction D2, that is, the etched initial active pattern 201 protrudes from the etched first dielectric layer 121 in the second direction D2. In the process of removing part of the initial active pattern 201, the third dielectric layer 123 remaining at the bottom of the columnar groove T2 can be removed, and the first dielectric layer 121 and the second dielectric layer 122 at the bottom of the columnar groove T2 will protect the substrate 100 to avoid etching damage and leakage problems in the subsequently formed device structure.

[0051] In some embodiments, reference Fig.14A and Fig. 14B As shown, Fig.14A The middle left picture is Fig. 14B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig.14A The middle right picture is Fig. 14B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig. 14B The middle left picture is Fig.14A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig. 14B The middle right picture is Fig.14ASchematic diagram of a horizontal section of the third horizontal section H3-H3' in FIG. A third sacrificial structure 140 is filled in the capacitor groove CAt. The third sacrificial structure 140 may be a single-layer structure or a multi-layer structure. For example, the third sacrificial structure 140 may include a first sacrificial layer 141 filling the capacitor horizontal groove T22 and a second sacrificial layer 142 filling the capacitor vertical groove T21. The material of the first sacrificial layer 141 may include a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, and the material of the second sacrificial layer 142 may include a sacrificial material, such as aluminum oxide, amorphous carbon, polysilicon, etc. In one example, the first sacrificial layer 141 includes a silicon oxide layer and a silicon nitride layer, and the second sacrificial layer 142 includes polysilicon.

[0052] In some embodiments, reference Fig.15A and Fig. 15B As shown, Fig.15A The middle left picture is Fig. 15B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig.15A The middle right picture is Fig. 15B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig. 15B The middle left picture is Fig.15A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig. 15B The middle right picture is Fig.15A Schematic diagram of a horizontal section of the third horizontal section H3-H3' in FIG. Removing the second sacrificial structure 120a2 to expose the bit line vertical groove T23. Removing part of the filling layer 120b and forming an initial word line layer includes: removing the remaining first dielectric layer 121 along the bit line vertical groove T23 to form an initial word line groove G0.

[0053] In some embodiments, reference Fig.16A and Fig. 16B As shown, Fig.16A The middle left picture is Fig. 16B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig.16A The middle right picture is Fig. 16B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig. 16B The middle left picture is Fig.16A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig. 16B The middle right picture is Fig.16ASchematic diagram of a horizontal section of the third horizontal section H3-H3' in FIG. An initial word line layer 202 is formed in the initial word line groove G0. The initial word line layer 202 includes a gate oxide material layer 202a and a conductive material layer 202b; the initial word line layer 202 is formed in the initial word line groove G0, including: forming a gate oxide material layer 202a covering the surface of the initial active pattern 201 in the initial word line groove G0; forming a conductive material layer 202b covering the surface of the gate oxide material layer 202a and filling the initial word line groove G0.

[0054] An in-situ steam generation process (ISSG) or a rapid thermal oxidation process (RTO) may be used to form a gate oxide material layer 202a on the surface of the initial active pattern 201. The gate oxide material layer 202a may only cover the surface of the initial active pattern 201. The gate oxide material layer 202a may also be formed by an atomic layer deposition process or a plasma vapor deposition process. The gate oxide material layer 202a may also cover the surface of the second dielectric layer 122.

[0055] In some embodiments, the conductive material layer 202b is formed by a deposition process, for example, a conductive material is deposited along the bit line vertical groove T23, the conductive material fills the initial word line groove G0 and the bit line vertical groove T23, and then the conductive material in the bit line vertical groove T23 is removed by a dry etching process. The material of the conductive material layer 202b is a conductive material. The conductive material may include one or more of the following: metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloy (e.g., Co-based alloy, Ti-based alloy, Co and Ni-based alloy, Fe and Co-based alloy); conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide); and conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped silicon germanium). For example, the conductive material layer 202 b may be made of titanium nitride.

[0056] In some embodiments, reference Fig.17A and Fig. 17B As shown, Fig.17A The middle left picture is Fig. 17B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig.17A The middle right picture is Fig. 17B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig. 17B The middle left picture is Fig.17A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig. 17B The middle right picture is Fig.17A Schematic diagram of a horizontal section of the third horizontal section H3-H3' in FIG. A portion of the initial word line layer 202 is removed along the bit line vertical groove T23, so that the initial word line layer 202 is patterned into a word line structure 220 extending along the first direction D1. Only a portion of the conductive material layer 202b can be removed, or a portion of the gate oxide material layer 202a and a portion of the conductive material layer 202b can be removed. After removing a portion of the initial word line layer 202, it also includes filling and forming a second isolation structure 203 in the space where the initial word line layer 202 is removed. The material of the second isolation structure 203 can be a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride or silicon oxynitride. After forming the second isolation structure 203, the patterned initial active pattern 201 is an active structure 210, including: removing part of the initial active pattern 201 along the bit line vertical groove T23 to form a bit line horizontal groove T24, the bit line vertical groove T23 and the bit line horizontal groove T24 constitute a bit line groove BLt, and the remaining initial active pattern 201 is used as the active structure 210. Both ends of the etched conductive layer in the word line structure 220 along the second direction are indented at both ends of the active structure 210, and the etched gate oxide layer in the word line structure 220 can be indented at both ends of the active structure 210 along the second direction, or only one end of the gate oxide layer can be indented at one end of the active structure 210 and the other end of the gate oxide layer is flush with the other end of the active structure 210. The word line structure 220 and the active structure 210 are used to form a transistor structure.

[0057] In some embodiments, the patterned word line structure 220 includes a first word line portion 221 and a second word line portion 222 alternately connected along a first direction D1, the first word line portion 221 at least covers the active structure 210, the second word line portion 222 is located between the second isolation portions 130b of the first isolation structure 130 adjacent to each other along the second direction D2, and the size of the first word line portion 221 along the second direction D2 is greater than the size of the second word line portion 222 along the second direction D2. By providing a larger first word line portion 221, the channel length can be increased and the short channel effect of the transistor can be reduced, and by providing a smaller second word line portion 222, the coupling between adjacent word line structures 220 can be reduced.

[0058] In some embodiments, reference Fig.18A and Fig.18B As shown, Fig.18A The middle left picture is Fig.18B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig.18A The middle right picture is Fig.18B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig.18B The middle left picture is Fig.18A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig.18B The middle right picture is Fig.18A Schematic diagram of a horizontal section of the third horizontal section H3-H3' in FIG. A bit line structure 300 is formed in the bit line groove BLt, and the bit line structure 300 includes a bit line vertical portion 310 and a bit line horizontal portion 320. The bit line vertical portion 310 refers to the portion of the bit line structure 300 located in the bit line vertical groove T23, and the bit line horizontal portion 320 refers to the portion of the bit line structure 300 located in the bit line horizontal groove T24. Among them, the bit line horizontal portion 320 protrudes from both sides of the bit line vertical portion 310 along the second direction D2, and a plurality of bit line horizontal portions 320 are arranged in the same layer as the active structure 210, and are arranged at intervals in the vertical direction D3. The bit line horizontal portion 320 is in contact with and connected to the active structure 210. The material of the bit line structure 300 is a conductive material, and the bit line structure 300 can be a single-layer structure or a multi-layer structure, for example, the bit line structure 300 includes a conductive doped polysilicon layer and a titanium nitride layer.

[0059] In some embodiments, reference Fig.19A and Fig.19B As shown, Fig.19A The middle left picture is Fig.19B A schematic diagram of a vertical section of the first vertical section V1-V1' in FIG. Fig.19A The middle right picture is Fig.19B A schematic diagram of a vertical section of the second vertical section V2-V2', Fig.19B The middle left picture is Fig.19A Schematic diagram of the horizontal section of the first horizontal section H1-H1', Fig.19B The middle right picture is Fig.19A The third sacrificial structure 140 in the capacitor groove CAt can be at least partially removed to expose the capacitor groove CAt, and the first sacrificial layer 141 located on the conductive layer side of the word line structure 220 is retained as the third isolation structure 204. In other examples, the third sacrificial structure 140 in the capacitor groove CAt can also be completely removed to fill the third isolation structure 204 on the conductive layer side of the word line structure 220.

[0060] A capacitor structure 400 is formed in the exposed capacitor groove CAt, and the capacitor structure 400 includes a capacitor vertical portion 410 and a capacitor horizontal portion 420. The capacitor vertical portion 410 refers to the portion of the capacitor structure 400 located in the capacitor vertical groove T21, and the capacitor horizontal portion 420 refers to the portion of the capacitor structure 400 located in the capacitor horizontal groove T22. Among them, the capacitor horizontal portion 420 protrudes from both sides of the capacitor vertical portion 410 along the second direction D2, and multiple capacitor horizontal portions 420 are arranged in the same layer as the active structure 210, and are arranged at intervals in the vertical direction D3. The capacitor horizontal portion 420 is in contact with the active structure 210. The capacitor horizontal portion 420 can be a double-sided capacitor structure, a columnar capacitor structure or a cylindrical capacitor structure, and the capacitor vertical portion 410 can be used as a common upper electrode of multiple capacitor horizontal portions 420 arranged at intervals in the vertical direction D3.

[0061] Each capacitor structure 400 and a transistor electrically connected thereto constitute a memory cell MC, and multiple memory cells MC located in the same layer constitute a memory layer ML. Multiple memory layers ML are stacked in the vertical direction D3 to form a stacked structure MG. The stacked structure MG has a high degree of integration, and each device structure in the stacked structure MG has a good isolation effect.

[0062] In other examples, the bit line structure 300 may be formed first, and then the capacitor structure 400 may be formed.

[0063] In some embodiments, a bit line structure 300 and a capacitor structure 400 are formed in the bit line groove BLt and the capacitor groove CAt, respectively, and the bit line structure 300 and the capacitor structure 400 are alternately arranged in the first direction D1 and alternately arranged in the second direction D2. The bit line structure 300 is arranged in a staggered manner. Compared with the symmetrical arrangement, this structural layout can effectively increase the spacing between the bit line structures 300, thereby reducing the coupling between the bit line structures 300, thereby improving the sensing margin of the semiconductor structure.

[0064] Based on the above-mentioned method for preparing the semiconductor structure, the embodiment of the present disclosure further provides a semiconductor structure 10. Figure 1 is a three-dimensional schematic diagram of a semiconductor structure 10 according to an embodiment of the present disclosure. Fig.19A is a schematic diagram of a vertical section of a semiconductor structure 10 according to an embodiment of the present disclosure and Fig.19B is a schematic horizontal cross-sectional view of a semiconductor structure 10 according to an embodiment of the present disclosure.

[0065] Reference Fig.19A and Fig.19B Shown and combined Figure 1As shown, the semiconductor structure 10 includes: a stacked structure MG located on a substrate 100, the stacked structure MG includes a plurality of storage layers ML stacked along a vertical direction D3, each storage layer ML includes a plurality of active structures 210 arrayed along a first direction D1 and a second direction D2 and a word line structure 220 extending along the first direction D1; a bit line structure 300 and a capacitor structure 400 located on both sides of each active structure 210 along the second direction D2, the bit line structure 300 and the capacitor structure 400 are alternately arranged in the first direction D1 and alternately arranged in the second direction D2; and a plurality of active structures 210 arrayed along a first direction D1 and a second direction D2 are arranged in a plurality of memory layers ML stacked along a vertical direction D3, each memory layer ML includes a plurality of active structures 210 arrayed along a first direction D1 and a second direction D2 and a word line structure 220 extending along the first direction D1; ... first direction D3 and a second direction D2; and a plurality of active structures 210 arrayed along a first direction D1 and a second direction D2 are arranged in a plurality of memory layers ML stacked along a first direction D3 and a second direction D2; and a plurality of active structures 210 arrayed along a first direction D1 and a second direction D2 are arranged in a plurality of memory layers ML stacked along a first direction D3 and a second direction D2. The first isolation structure 130 is arranged in an array along the first direction D1 and the second direction D2. The first isolation structure 130 includes a first isolation portion 130a located at a layer where the active structure 210 is located and a second isolation portion 130b located at a layer where the word line structure 220 is located. The size of the first isolation portion 130a along the second direction D2 is greater than the size of the second isolation portion 130b along the second direction D2, and the first isolation portions 130a adjacent to each other along the second direction D2 are in contact with each other, and the bit line structure 300 and the capacitor structure 400 are located between the first isolation structures 130 adjacent to each other along the second direction D2.

[0066] In the semiconductor structure provided by the present disclosure, on the first hand, by providing a bit line structure and a capacitor structure alternately arranged in the first direction and the second direction, the spacing between the bit line structures can be increased, thereby reducing the coupling between the bit line structures, thereby improving the sensing margin of the semiconductor structure. On the second hand, by providing an integrated first isolation structure between each device structure, and the first isolation structure having a first isolation portion and a second isolation portion that are alternately wide and narrow in the vertical direction, the isolation effect between the word line structures can be effectively improved, the morphology of the word line structure can be accurately defined, and the word line structure can be prevented from being disconnected or short-circuited in the horizontal direction, which is beneficial to improving the performance of the semiconductor structure.

[0067] In some embodiments, the bit line structure 300 includes a bit line vertical portion 310 and a bit line horizontal portion 320. The bit line vertical portion 310 penetrates the stack structure MG along the vertical direction D3. The bit line horizontal portion 320 is located on both sides of the bit line vertical portion 310 along the second direction D2 and is arranged at intervals in the vertical direction D3. The bit line horizontal portion 320 contacts the active structure 210. The material of the bit line structure 300 is a conductive material. The bit line structure 300 can be a single-layer structure or a multi-layer structure. For example, the bit line structure 300 includes a conductive doped polysilicon layer and a titanium nitride layer. The transistors of the memory cells on both sides of the bit line structure 300 along the second direction D2 share a bit line structure 300, which can improve the integration of the semiconductor structure.

[0068] In some embodiments, the capacitor structure 400 includes a capacitor vertical portion 410 and a capacitor horizontal portion 420, the capacitor vertical portion 410 penetrates the stacked structure along the vertical direction D3, the capacitor horizontal portion 420 is located on both sides of the capacitor vertical portion 410 along the second direction D2 and is arranged at intervals in the vertical direction D3, and the capacitor horizontal portion 420 includes a first electrode portion 421, a capacitor dielectric layer 422 and a second electrode portion 423. The capacitor dielectric layer 422 is sandwiched between the first electrode portion 421 and the second electrode portion 423, the first electrode portion 421 contacts the active structure 210, and the second electrode portion 423 contacts the capacitor vertical portion 410. The capacitor vertical portion 410 can be used as a common upper electrode of multiple capacitor horizontal portions 420 arranged at intervals along the vertical direction D3, and can also further improve the integration of the semiconductor structure. The materials of the first electrode portion 421, the second electrode portion 423 and the capacitor vertical portion 410 are conductive materials, for example, the materials of the first electrode portion 421 and the second electrode portion 423 are titanium nitride, and the material of the capacitor vertical portion 410 is tungsten. The material of the capacitor dielectric layer 422 includes a high dielectric constant material, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0069] In some embodiments, the word line structure 220 includes a first word line portion 221 and a second word line portion 222 alternately connected along a first direction D1, the first word line portion 221 at least covers the active structure 210, the second word line portion 222 is located between adjacent first isolation structures 130 along a second direction D2, and the size of the first word line portion 221 along the second direction D2 is greater than the size of the second word line portion 222 along the second direction D2. The active structure 210 includes a channel portion 211 and a first source-drain portion 212 and a second source-drain portion 213 located on both sides of the channel portion 211, the first source-drain portion 212 is electrically connected to the capacitor structure 400, and the second source-drain portion 213 is electrically connected to the bit line structure 300. The first word line portion 221 at least covers the channel portion 211 in the active structure 210, that is, the projection of the first word line portion 221 on the substrate 100 intersects with the projection of the active structure 210 on the substrate 100, and the projection of the first word line portion 221 on the substrate 100 covers the projection of the channel portion 211 on the substrate 100. By providing a larger first word line portion 221, the channel length can be increased and the short channel effect of the transistor can be reduced, and by providing a smaller second word line portion 222, the coupling between adjacent word line structures 220 can be reduced.

[0070] In some embodiments, the first isolation structure 130 formed by the first isolation portion 130a and the second isolation portion 130b is an integrated structure. The first isolation structure 130 may be a single-layer structure or a multi-layer structure. For example, the first isolation structure 130 may include a first isolation layer 131, a second isolation layer 132, and a third isolation layer 133. In this example, the first isolation structure 130 is an ONO (Oxide-Nitride-Oxide) structure, the first isolation layer 131 is silicon oxide, the second isolation layer 132 is silicon nitride, and the third isolation layer 133 is silicon oxide. The first isolation structure 130 has excellent isolation performance, can prevent signal crosstalk between word line structures 220, and can improve the structural stability of the storage layer ML, thereby improving the reliability of the semiconductor structure 10.

[0071] In some embodiments, the semiconductor structure further includes a second isolation structure 203, which is sandwiched between the first word line portion 221 and the bit line structure 300; and a third isolation structure 204, which is sandwiched between the first word line portion 221 and the capacitor structure 400. The materials of the second isolation structure 203 and the third isolation structure 204 may include low dielectric constant materials, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride, so as to reduce the coupling between the word line structure 220 and the bit line structure 300 and the capacitor structure 400.

[0072] In some embodiments, the first word line portion 221 has arc-shaped sidewalls that are opposite to each other along the second direction D2. The arc-shaped sidewalls of the first word line portion 221 are connected to the second isolation structure 203 and the third isolation structure 204. The arc-shaped sidewalls that are opposite to each other refer to that the two arc-shaped sidewalls are convex toward each other, and the two arc-shaped sidewalls may not be completely symmetrical, for example, the curvature of the arc-shaped sidewall that contacts the second isolation structure 203 is smaller than the curvature of the arc-shaped sidewall that contacts the third isolation structure 204.

[0073] In some embodiments, the size of the active structure 210 in the first direction D1 is non-uniform, and the active structure 210 has a protrusion 210a facing the contact surface between adjacent first isolation structures 130. The portion of the active structure 210 having the protrusion 210a is located in the middle of the active structure 210 and is used as the channel portion 211, that is, the size of the channel portion 211 along the first direction D1 is larger than the size of the first source drain portion 212 and the second source drain portion 213 along the first direction D1, which can reduce the short channel effect of the transistor.

[0074] In some embodiments, the semiconductor structure 10 includes: a memory, which may be a dynamic random access memory, specifically a three-dimensional dynamic random access memory. The memory may also be a memory known in the art, such as a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).

[0075] The various semiconductor structures shown in this specific embodiment can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by a memory including the above semiconductor structure.

[0076] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: forming a stacked structure on a substrate, the stacked structure comprising first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction; A first isolation structure, a sacrificial structure and a filling layer are formed in the stacked structure, and the first semiconductor layer is patterned to form an initial active pattern arranged in an array, wherein the first isolation structure is arranged in an array along a first direction and a second direction, wherein the first isolation structure comprises a first isolation portion located in a layer where the initial active pattern is located and a second isolation portion located in a layer where the second semiconductor layer is located, wherein the size of the first isolation portion along the second direction is greater than the size of the second isolation portion along the second direction, and the first isolation portions adjacent to each other along the second direction are in contact, wherein the sacrificial structure is located between the first isolation structures adjacent to each other along the second direction, and the filling layer is located in the layer where the second semiconductor layer is located; removing part of the filling layer and forming an initial word line layer; Removing the sacrificial structure and at least a portion of the filling layer to form a bit line trench and a capacitor trench respectively, and patterning the initial active pattern into an active structure, and patterning the initial word line layer into a word line structure extending along a first direction; A bit line structure and a capacitor structure are formed in the bit line trench and the capacitor trench, respectively. The bit line structure and the capacitor structure are alternately arranged in the first direction and alternately arranged in the second direction.

2. The preparation method according to claim 1, characterized in that: The forming of a first isolation structure, a sacrificial structure and a filling layer in the stacked structure, and patterning the first semiconductor layer to form an initial active pattern arranged in an array comprises: Etching the stacked structure to form a plurality of rectangular grooves, wherein the rectangular grooves expose a portion of the surface of the substrate, the plurality of rectangular grooves are arranged in an array along a first direction and a second direction, and a spacing between adjacent rectangular grooves along the first direction is greater than a spacing between adjacent rectangular grooves along the second direction; Removing a portion of the first semiconductor layer along the rectangular grooves to form an initial active pattern and isolation grooves arranged in an array; A first isolation structure filling the isolation trench is formed.

3. The preparation method according to claim 2, characterized in that: After forming the plurality of rectangular grooves, the method further comprises: filling an initial isolation structure in the rectangular groove; Etching the stacked structure to form a plurality of columnar grooves, wherein the columnar grooves expose a portion of the surface of the substrate, and the columnar grooves are located between initial isolation structures adjacent to each other along the second direction; removing the second semiconductor layer along the columnar grooves to form interlayer gaps between the first semiconductor layers; Filling the first dielectric layer, the second dielectric layer and the third dielectric layer in the columnar groove and the interlayer gap to form a sacrificial structure in the columnar groove and a filling layer in the interlayer gap; Removing a portion of the first semiconductor layer along the rectangular groove to form an initial active pattern and isolation grooves arranged in an array, comprising: removing at least a portion of the initial isolation structure to expose the rectangular groove; The exposed portion of the first semiconductor layer is removed along the rectangular groove to form an isolation groove, wherein the isolation groove includes a first isolation groove portion located at the layer where the first semiconductor layer is located, the first isolation groove portions are connected in the second direction and disconnect the initial active pattern in the first direction.

4. The preparation method according to claim 3, characterized in that: The first dielectric layer covers the surface of the initial active pattern, the second dielectric layer covers the surface of the second dielectric layer and fills the interlayer gap, a portion of the filling layer is removed, and an initial word line layer is formed, including: removing a portion of the first dielectric layer to form an initial word line trench; An initial word line layer is formed in the initial word line groove.

5. The preparation method according to claim 4, characterized in that: The initial word line layer includes a gate oxide material layer and a conductive material layer; Forming an initial word line layer in the initial word line groove comprises: forming a gate oxide material layer in the initial word line groove to cover the surface of the initial active pattern; A conductive material layer is formed to cover the surface of the gate oxide material layer and fill the initial word line groove.

6. The preparation method according to claim 1, characterized in that: The sacrificial structure comprises a first sacrificial structure and a second sacrificial structure, wherein the first sacrificial structure and the second sacrificial structure are alternately arranged in the first direction and alternately arranged in the second direction; The sacrificial structure and at least a portion of the filling layer are removed to form a bit line groove and a capacitor groove respectively, and the initial active pattern is patterned into an active structure, and the initial word line layer is patterned into a word line structure extending along a first direction, comprising: Removing the first sacrificial structure to expose the capacitor vertical groove, removing a portion of the initial active pattern along the capacitor vertical groove to form a capacitor horizontal groove, wherein the capacitor vertical groove and the capacitor horizontal groove constitute a capacitor groove; Filling a third sacrificial structure in the capacitor groove; The second sacrificial structure is removed to expose the bit line vertical groove, and a portion of the initial active pattern is removed along the bit line vertical groove to form a bit line horizontal groove, wherein the bit line vertical groove and the bit line horizontal groove constitute a bit line groove, and the remaining initial active pattern serves as an active structure.

7. The preparation method according to claim 6, characterized in that: After removing the second sacrificial structure to expose the bit line vertical groove and before removing a portion of the initial active pattern along the capacitor vertical groove, the method further includes: removing a portion of the initial word line layer along the bit line vertical groove, and using the remaining initial word line layer as a word line structure; A second isolation structure is formed, wherein the second isolation structure is sandwiched between the word line structure and the bit line vertical trench.

8. A semiconductor structure, characterized in that: include: A stacked structure located on a substrate, the stacked structure comprising a plurality of storage layers stacked in a vertical direction, each of the storage layers comprising a plurality of active structures arrayed in a first direction and a second direction and a word line structure extending in the first direction; bit line structures and capacitor structures located on both sides of each of the active structures along the second direction, the bit line structures and the capacitor structures are alternately arranged in the first direction and alternately arranged in the second direction; A first isolation structure runs through the stacked structure, the first isolation structure is arranged in an array along a first direction and a second direction, the first isolation structure includes a first isolation portion located at a layer where the active structure is located and a second isolation portion located at a layer where a word line structure is located, a size of the first isolation portion along the second direction is greater than a size of the second isolation portion along the second direction, and first isolation portions adjacent to each other along the second direction are in contact, and the bit line structure and the capacitor structure are located between first isolation structures adjacent to each other along the second direction.

9. The semiconductor structure according to claim 8, characterized in that: The bit line structure includes a bit line vertical portion and a bit line horizontal portion, the bit line vertical portion penetrates the stacking structure along the vertical direction, the bit line horizontal portion is located on both sides of the bit line vertical portion along the second direction and is arranged at intervals in the vertical direction, and the bit line horizontal portion contacts the active structure.

10. The semiconductor structure according to claim 8, characterized in that The capacitor structure includes a vertical capacitor portion and a horizontal capacitor portion, the vertical capacitor portion penetrates the stacked structure along the vertical direction, the horizontal capacitor portion is located on both sides of the vertical capacitor portion along the second direction and is arranged at intervals in the vertical direction, the horizontal capacitor portion includes a first electrode portion, a capacitor dielectric layer and a second electrode portion, the capacitor dielectric layer is sandwiched between the first electrode portion and the second electrode portion, the first electrode portion is in contact with the active structure, and the second electrode portion is in contact with the vertical capacitor portion.

11. The semiconductor structure according to claim 8, characterized in that: The word line structure includes a first word line portion and a second word line portion alternately connected along the first direction, the first word line portion at least covers the active structure, the second word line portion is located between adjacent first isolation structures along the second direction, and the size of the first word line portion along the second direction is greater than the size of the second word line portion along the second direction.

12. The semiconductor structure according to claim 11, characterized in that: Also includes: a second isolation structure, the second isolation structure being sandwiched between the first word line portion and the bit line structure; A third isolation structure is sandwiched between the first word line portion and the capacitor structure.

13. The semiconductor structure according to claim 11, characterized in that: The first word line portion has arc-shaped side walls opposite to each other along the second direction.

14. The semiconductor structure according to claim 8, characterized in that The active structure has a non-uniform size in the first direction, and has a protruding portion facing a contact surface between adjacent first isolation structures.

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