A 1.5T SONOS device and its preparation method

Abstract

This invention discloses a 1.5T SONOS device and its fabrication method. Without increasing the ONO layer thickness or the lateral length of the gate, this invention forms a slope on the substrate surface and deposits an ONO layer, thereby increasing the gate's control over the channel, increasing the ONO layer length, and increasing the total number of defects in the ONO layer. This improves the device's charge storage capacity and enhances its performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, specifically a 1.5T SONOS device and its fabrication method. Background Technology

[0002] Flash memory, an essential storage device in computers, plays a crucial role in storing processed information and is widely used in various embedded electronic products such as financial IC cards and automotive electronics. However, flash memory, with its floating gate structure, requires high-voltage operation during read, write, and erase processes, while complementary metal-oxide-semiconductor (CMOS) does not. Furthermore, flash memory has a two-layer polysilicon structure with a floating gate and a control gate, while CMOS has a single-layer polysilicon structure. Therefore, integrating flash memory with CMOS devices is challenging and involves complex processes. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology, on the other hand, is highly compatible with CMOS processes. SONOS memory can be embedded simply on a logic platform. Moreover, SONOS memory operates at lower voltages, has good memory retention, and is less expensive, making it highly competitive in terms of manufacturing, usage, and cost.

[0003] Traditional SONOS devices use silicon oxide-silicon nitride-silicon oxide (ONO) instead of a floating gate. The silicon nitride layer is a trapping layer, and the traps in the trapping layer serve as the locations for storing charges. Therefore, the size of the silicon nitride layer determines the amount of charge stored. The bottom silicon oxide is a tunneling oxide layer, and the top silicon oxide is a blocking layer.

[0004] A traditional 1.5T (transistor) SONOS memory unit includes a select transistor and a storage transistor, see... Figure 1 In section a, the selector transistor primarily functions as the on / off switch for the memory transistor, reducing leakage current. The memory transistor, on the other hand, is mainly used to store charge, achieving data storage through different Vt states. Arranging the two transistors close together significantly reduces the memory cell area compared to the 2T SONOS structure. (See section a for more details.) Figure 1 b in the text.

[0005] In 1.5T SONOS devices, the lateral length of the ONO layer is limited by the lateral length of the polysilicon gate of the memory transistor. Furthermore, with the further development of electronic products, there is a growing demand for smaller and higher-performance memory devices, leading to a continuous reduction in the lateral length of the polysilicon gate. Consequently, the lateral length of the ONO layer also decreases. This not only reduces the contact area between the memory gate and the ONO layer above the channel, thus decreasing the gate's control over the channel, but also reduces the charge storage capacity of the silicon nitride layer. To maintain the silicon nitride's storage capacity, its thickness must be increased. However, this increase in thickness results in a tall and thin device, making deposition and etching processes increasingly difficult and leading to lower yield rates. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a 1.5T SONOS device and its fabrication method.

[0007] One aspect of the present invention provides a method for fabricating a 1.5T SONOS device, comprising:

[0008] Step 1: On the semiconductor substrate, doping is first performed to form PWell, and then the substrate is oxidized to form a silicon dioxide oxide layer;

[0009] Step 2: Deposit a layer of polycrystalline silicon on the already grown silicon dioxide oxide layer, and then perform ion doping implantation on the polycrystalline silicon, implanting As;

[0010] Step 3: Fabricate a patterned photomask. Coat a layer of photoresist on the silicon wafer and transfer the pattern on the photomask to the photoresist layer using photolithography.

[0011] Next, a development process is performed to remove the photoresist in the exposed areas, exposing the areas to be etched on the silicon wafer surface; excess polysilicon is removed and grooves with slopes on both sides are generated.

[0012] Step 4: Generate an ONO layer on the surface;

[0013] Step 5: Perform light doping implantation on both sides of the gate of the memory transistor and the gate of the select transistor, followed by heavy ion doping;

[0014] Step 6: Generate a silicon dioxide oxide layer by oxidizing silicon itself;

[0015] Step 7: After the oxide layer growth in step 6 is completed, a layer of polycrystalline silicon is deposited on the entire silicon wafer surface;

[0016] Step 8: Create a patterned mask, then perform photolithography to remove excess polysilicon. After photolithography, dope the polysilicon.

[0017] Step 9: Deposit a silicon nitride thin film on the surface, and then perform photolithography to remove the excess silicon nitride to form sidewalls;

[0018] Step 10: Deposit NiSi to form a metal electrode, and deposit high-density silicon dioxide;

[0019] Step 11: Use a patterned mask to etch high-density silicon dioxide to open vias; deposit a layer of TiN on the surface of the vias, and then deposit tungsten metal in the vias to form metal interconnect vias.

[0020] Another aspect of the present invention provides a 1.5TSONOS device prepared by the above method.

[0021] The beneficial effects of the present invention are as follows: The storage medium of the device in the present invention is a sloped ONO layer, which increases the contact area between the storage gate and the storage medium, effectively increases the control capability of the storage gate over the channel, and can extend the length of the ONO layer, so that the device has better charge storage capability. Attached Figure Description

[0022] Figure 1 It is a traditional SONOS storage unit;

[0023] Figure 2 A schematic diagram of the 1.5T SONOS device structure provided in this application;

[0024] Figure 3 This is a schematic diagram of the PWell process in step 1 of this embodiment;

[0025] Figure 4 This is a schematic diagram of the oxide layer formation process in step 1 of this embodiment;

[0026] Figure 5 This is a schematic diagram of step 2 of this embodiment;

[0027] Figure 6 This is a schematic diagram of step 3 of this embodiment;

[0028] Figure 7 This is a schematic diagram of step 4 of this embodiment;

[0029] Figure 8 This is a schematic diagram of the process of removing the excess ONO layer in step 5 of this embodiment;

[0030] Figure 9 This is a schematic diagram of the doping process in step 5 of this embodiment;

[0031] Figure 10 This is a schematic diagram of step 6 in this embodiment;

[0032] Figure 11This is a schematic diagram of the polysilicon deposition process in step 7 of this embodiment;

[0033] Figure 12 This is a schematic diagram of the CMP polishing process using silicon dioxide as a barrier layer in step 7 of this embodiment;

[0034] Figure 13 This is a schematic diagram of step 8 of this embodiment;

[0035] Figure 14 This is a schematic diagram of step 9 in this embodiment;

[0036] Figure 15 This is a schematic diagram of the metal electrode formation process in step 10 of this embodiment;

[0037] Figure 16 This is a schematic diagram of the high-density silica deposition process in step 10 of this embodiment;

[0038] Figure 17 This is a schematic diagram of step 11 in this embodiment; Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings and examples.

[0040] Step 1: In such Figure 3 On the semiconductor substrate shown, doping is first performed to form a PWell, followed by self-oxidation to form a silicon dioxide oxide layer with a thickness of approximately [missing information]. like Figure 4 As shown.

[0041] Step 2: As Figure 5 A layer of polycrystalline silicon is deposited on top of the already grown silica oxide layer. The thickness of the polycrystalline silicon layer is approximately... Then, the polycrystalline silicon was subjected to ion doping implantation with an implantation concentration of 10. 15 cm -2 As.

[0042] Step 3: Fabricate a patterned photomask according to design requirements. Coat a layer of photoresist onto the silicon wafer, and transfer the pattern from the photomask to the photoresist layer using photolithography. Then, perform development to remove the photoresist in the exposed areas, exposing the areas to be etched on the silicon wafer surface. Use etching methods to remove excess polysilicon and create... Figure 6 The groove shown has sloping sides and a depth of approximately After etching is complete, the remaining photoresist is removed and the area is cleaned.

[0043] Step 4: Generate an ONO layer (silicon oxide-silicon nitride-silicon oxide) on the surface. Using thermal oxidation or chemical vapor deposition (CVD) techniques, grow a layer of silicon oxide on the silicon wafer surface, with a thickness of approximately [missing information]. On top of the silicon oxide layer, a layer of silicon nitride with a thickness of approximately [thickness missing] is deposited using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) techniques. Silicon nitride provides excellent electrical isolation and physical protection. Finally, a layer of silicon oxide is deposited on top of the silicon nitride layer, with a thickness of approximately [thickness missing]. A deposition method similar to that used for the first silicon oxide layer can be employed to ensure a tight bond between this silicon oxide layer and the underlying silicon nitride layer, forming a complete ONO layer, such as... Figure 7 .

[0044] Step 5: Perform etching to remove excess ONO layer, such as... Figure 8 As shown in the diagram. Then, light doping implantation is performed on both sides of the gate of the memory transistor and the gate of the select transistor, followed by the implantation of heavy ions. Shallow nodules are formed with energy on the order of 10 keV, and the injection dose is 10. 14 cm -2 Light doping implantation can suppress the drain-induced barrier reduction effect. induced Lowering (DIBL), followed by ion redoping, also with As implantation at a dose of 10. 15 cm -2 The magnitude forms the source and drain electrodes. For example... Figure 9 As shown.

[0045] Step 6: As Figure 10 As shown, after the source and drain electrodes are formed, a silicon dioxide oxide layer is generated by silicon self-oxidation, with a thickness of approximately [missing information].

[0046] Step 7: As Figure 11 As shown, after the oxide layer growth is complete, a layer of polysilicon is deposited on the entire silicon wafer surface. After the polysilicon deposition is complete, CMP polishing is performed using silicon dioxide as a barrier layer, as shown. Figure 12 As shown.

[0047] Step 8: Create a patterned photomask, then perform photolithography to remove excess polysilicon, such as... Figure 13 As shown, after photolithography, the polysilicon is doped with an implantation concentration of 10. 15 cm -2 As.

[0048] Step 9: Deposit a silicon nitride thin film on the surface, then perform photolithography to remove excess silicon nitride to form sidewalls, such as... Figure 14 As shown.

[0049] Step 10: Deposit NiSi to form a metal electrode, such as Figure 15 As shown. Deposition High-density silica (HDPOX), such as Figure 16 As shown.

[0050] Step 11: Use a patterned mask to etch the HDP OX to open vias. First, deposit a TiN layer on the surface of the via, then deposit tungsten metal in the via to form metal interconnect vias. Figure 17 As shown.

[0051] The preparation method of the present invention forms a slope on the substrate surface and deposits an ONO layer without increasing the thickness of the ONO layer or the lateral length of the gate of the storage transistor. This increases the control capability of the storage gate over the channel and increases the length of the ONO layer, thereby increasing the total number of defects in the ONO layer and achieving the effect of improving the charge storage capacity of the device, which can improve the working performance of the device.

[0052] This invention also provides a 1.5T SONOS memory device prepared according to the above method, such as... Figure 2 As shown, this device employs a channel hot carrier injection mechanism during writing, applying a high voltage to the CG and source, causing electrons to be accelerated from the source side by a horizontal high electric field, and then injected into the ONO layer under the influence of a vertical electric field. This mechanism generates a higher current but requires a lower voltage.

[0053] Erasing employs a BTBT (Band-to-band tunneling hot-hole injection) mechanism, applying a positive high voltage to the source and a negative high voltage to the storage gate to complete the erase operation. BTBT injection offers a lower operating voltage and faster erase speed compared to FN tunneling. Reading involves applying a voltage V to the select gate, storage gate, and drain, respectively. DD The operating voltages are shown in the table below.

[0054] Operation Vd Vs Vsg Vcg Erase 0 3V 0 -7V Program 0 3V 0 7V Read 1.2V 0 1.2V 1.2V

[0055] The above description is a preferred embodiment of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for fabricating a 1.5T SONOS device, characterized in that, The method includes the following steps: Step 1: On the semiconductor substrate, doping is first performed to form PWell, and then the substrate is oxidized to form a silicon dioxide oxide layer; Step 2: Deposit a first polycrystalline silicon layer on the already grown silicon dioxide oxide layer, and then perform ion doping implantation on the first polycrystalline silicon to implant As; Step 3: Fabricate a patterned photomask. Coat a layer of photoresist on the silicon wafer and transfer the pattern on the photomask to the photoresist layer using photolithography. Next, a development process is performed to remove the photoresist in the exposed area, exposing the area to be etched on the silicon wafer surface; the first polysilicon and the silicon dioxide oxide layer in the area to be etched are removed, and a groove with slopes on both sides is generated in the PWell along one side of the remaining first polysilicon. Step 4: Generate an ONO layer on the surface; Step 5: Remove the ONO layer outside the first polysilicon sidewall, the silicon dioxide oxide layer sidewall below the first polysilicon, and the groove sidewall; perform light doping implantation on the other side of the first polysilicon and the PWell at the bottom of the groove, and then perform heavy ion doping. Step 6: Generate a silicon dioxide oxide layer by oxidizing silicon itself; Step 7: After the oxide layer growth in step 6 is completed, a second polycrystalline silicon layer is deposited on the entire silicon wafer surface, and CMP polishing is performed with silicon dioxide as a barrier layer. Step 8: Create a patterned mask and then perform photolithography to remove excess second polysilicon, retaining only the second polysilicon on the sidewall of the first polysilicon facing the groove and the second polysilicon on the slope. Then, dope the retained second polysilicon. Step 9: Deposit a silicon nitride thin film on the surface, and then perform photolithography to remove excess silicon nitride, forming sidewalls on the ONO layer sidewall on the other side of the first polysilicon and on the sidewall of the second polysilicon. Step 10: Deposit NiSi to form a metal electrode, and deposit high-density silicon dioxide; Step 11: Use a patterned mask to etch high-density silicon dioxide to open vias; deposit a layer of TiN on the surface of the vias, and then deposit tungsten metal in the vias to form metal interconnect vias.

2. The method for fabricating a 1.5T SONOS device according to claim 1, characterized in that, The thickness of the oxide layer in step 1 is 90 Å.

3. The method for fabricating a 1.5T SONOS device according to claim 1, characterized in that, In step 2, the thickness of the first polysilicon layer is 650 Å, and the As implantation concentration is 10. 15 cm -2 .

4. The method for fabricating a 1.5T SONOS device according to claim 1, characterized in that, The groove depth described in step 3 is 300 Å.

5. The method for fabricating a 1.5T SONOS device according to claim 1, characterized in that, In step 5, the energy of the light doping implantation is on the order of 10 keV, and the implantation dose is 10. 14 cm -2 Order of magnitude; heavy doping implantation dose is 10 15 cm -2 The magnitude is so high that it forms the source and drain electrodes; the injected ions are all As.

6. The method for fabricating a 1.5T SONOS device according to claim 1, characterized in that, In step 8, the implantation concentration during the doping of the second polysilicon is 10. 15 cm -2 As.

7. The method for fabricating a 1.5T SONOS device according to claim 1, characterized in that, In step 10, 1400 Å of high-density silicon dioxide is deposited.

8. A 1.5T SONOS device, obtained by the fabrication method according to any one of claims 1 to 7.

9. A 1.5T SONOS device according to claim 8, characterized in that: The device uses a channel hot carrier injection mechanism to write data and a BTBT mechanism to erase data.

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