Implementation method of gallium nitride P-channel transistor with self-aligned gate electrode

Abstract

The invention relates to the technical field of semiconductor devices, and discloses an implementation method of a gallium nitride (GaN) P channel transistor with a self-aligned gate electrode. The structure of the transistor sequentially comprises a substrate, a nucleating layer, a buffer layer, a P-type GaN channel layer, a P-type GaN heavily doped layer and an N-type GaN heavily doped layer from bottom to top. The upper surface of the N-type GaN heavily doped layer is etched to form a gate groove, the depth of the gate groove enters the P-type GaN channel layer, and the gate groove is filled with gate dielectric and gate metal to form a gate electrode. The N-type GaN heavily-doped layer and the P-type GaN heavily-doped layer on the two sides of the gate groove form a tunnel junction, and the source electrode metal and the drain electrode metal are in ohmic contact with the P-type GaN channel layer through the tunnel junction. By introducing the tunnel junction structure and the gate groove, the gallium nitride P-type GaN channel transistor with the self-aligned gate electrode is realized, and the manufactured transistor is small in on resistance, high in current, simple in process and low in cost, and is compatible with a GaN HEMT power device epitaxial material structure and process based on a P-GaN gate.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode. Background Art

[0002] As a representative of the third generation of semiconductor materials, gallium nitride has shown great application potential in power electronics, radio frequency communications, optoelectronics, etc. due to its unique physical and chemical properties such as high power density output, high energy conversion efficiency, ultrafast switching capability, and low on-resistance. Especially in high-frequency and high-power electronic devices, the high electron mobility, high critical breakdown electric field, and high thermal conductivity of GaN (gallium nitride) materials make them ideal candidate materials.

[0003] Digital circuits and analog circuits require CMOS devices, and both N-channel transistors and P-channel transistors are required. The presence of high-concentration, high-mobility two-dimensional electron gas at the GaN heterojunction interface gives N-channel GaN transistors better performance, but there are still many problems to be solved in GaN P-channel transistors. P-type GaN semiconductor materials have high ionization energy due to doped impurities, low hole concentration, low mobility, high sheet resistance, and low conductivity, which seriously affects the performance of GaN P-channel transistors. Summary of the invention

[0004] The present application provides a method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode to solve one or more technical problems existing in the prior art and at least provide a beneficial choice or create conditions.

[0005] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0006] According to one aspect of an embodiment of the present application, a method for implementing a gallium nitride P-channel transistor with a self-aligned gate electrode is provided, the method comprising the following steps:

[0007] S1, selecting a substrate (1) and cleaning the surface of the substrate (1);

[0008] S2. Growing a nucleation layer (2), a buffer layer (3), a P-type GaN channel layer (4), a P-type GaN heavily doped layer (5) and an N-type GaN heavily doped layer (6) in sequence on the substrate (1) by using an epitaxial method;

[0009] S3, isolating the device;

[0010] S4, depositing a source electrode metal (7) and a drain electrode metal (8) on the surface of the N-type GaN heavily doped layer (6);

[0011] S5, etching a gate groove between the source electrode (7) and the drain electrode (8);

[0012] S6, depositing a gate dielectric layer (9) on the surface of the gate groove;

[0013] S7, depositing a gate metal on the surface of the gate dielectric layer (9) to form a gate electrode (10);

[0014] The N-type GaN heavily doped layer (5) and the P-type GaN heavily doped layer (6) form a tunnel junction, and the source electrode metal (7) and the drain electrode metal (8) respectively form an ohmic contact with the P-type GaN channel layer (4) through the tunnel junction. Since the surface resistance of the N-type GaN heavily doped layer (6) is very low, the N-type GaN heavily doped layer (6) in contact with the source electrode metal (7) or the drain electrode metal (8) below becomes a part of the effective source electrode and the effective drain electrode, so that the gate electrode (10) is self-aligned with the effective source electrode and the effective drain electrode.

[0015] In one embodiment of the present application, based on the above-mentioned scheme, the material of the substrate (1) is any one or more of Si, SiC, sapphire, and diamond; the material of the nucleation layer (2) is a group III nitride semiconductor with a thickness of 0.1-0.3 μm; the material of the buffer layer (3) includes one or more of AlGaN and GaN with a thickness of 0.1-5 μm.

[0016] In one embodiment of the present application, based on the above solution, the material of the P-type GaN channel layer (4) is GaN, and the doping impurities include one or more of Mg and Zn, and the doping concentration is 1.0×10 17 -1.0×10 20 cm -3 , with a thickness of 5-100 nm; the material of the P-type GaN heavily doped layer (5) is GaN, and the doping impurities include one or more of Mg and Zn, with a doping concentration of 1.0×10 19 -1.0×10 21 cm -3 , with a thickness of 5-100 nm; the material of the N-type GaN heavily doped layer (6) is GaN, and the doping impurities include Si, and the doping concentration is 1.0×10 19 -1.0×10 21 cm -3 , thickness is 5-100nm.

[0017] In one embodiment of the present application, based on the aforementioned scheme, the material of the drain electrode (8) or the material of the source electrode (7) includes at least two of Ti, Al, Ta, Mo, Au, and Ni; the material of the gate electrode (10) includes at least two of Ti, Al, Ta, Mo, Au, and Ni.

[0018] In one embodiment of the present application, based on the above solution, the P-type GaN heavily doped layer (5) and the N-type GaN heavily doped layer (6) are further provided with an InGaN barrier layer (12). The material of the InGaN barrier layer (12) is InGaN, with a composition of 0.1-0.5 and a thickness of 1-10 nm.

[0019] In one embodiment of the present application, based on the above-mentioned solution, a barrier layer (11) is further provided between the buffer layer (3) and the P-type GaN channel layer (4); the material of the barrier layer (11) includes one or more of AlGaN, InAlN, and AlN, and has a thickness of 3-30 nm.

[0020] In one embodiment of the present application, based on the above-mentioned solution, the material of the gate dielectric layer is one or more of Al2O3, SiO2, SiN, HfO2, ZrO2, and Ta2O5.

[0021] In one embodiment of the present application, based on the above scheme, in steps S5, S6, and S7, the same photoresist is used as a mask for etching the gate groove, depositing the gate dielectric layer (9) on the surface, and depositing the gate metal, and the gate dielectric layer (9) and the gate electrode (10) are realized using a photoresist stripping process, so that the gate dielectric layer (9) and the gate electrode (10) do not exist on the upper surface of the N-type GaN heavily doped layer (6), thereby achieving self-alignment.

[0022] In one embodiment of the present application, based on the above solution, steps S4-S7 are:

[0023] S4, etching a gate groove between the source electrode (7) and the drain electrode (8);

[0024] S5, depositing a gate dielectric layer (9) on the surface of the gate groove;

[0025] S6, depositing a gate metal on the surface of the gate dielectric layer (9) to form a gate electrode (10);

[0026] S7, depositing a source electrode metal (7) and a drain electrode metal (8) on the surface of the N-type GaN heavily doped layer (6).

[0027] Beneficial effects of the present application: The present application realizes a gallium nitride P-type GaN channel transistor with a self-aligned gate electrode by introducing a tunneling junction structure and a gate groove. The transistor has a small on-resistance, a high current, a simple process, and a low cost. It is compatible with the epitaxial material structure and process of a GaN HEMT power device based on a P-GaN gate.

[0028] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0030] Figure 1 A schematic diagram of a gallium nitride P-channel transistor with a self-aligned gate electrode provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of a gallium nitride P-channel transistor with a self-aligned gate electrode having an inserted barrier layer 11 and an InGaN barrier layer 12 provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of a process for preparing a gallium nitride P-channel transistor with a self-aligned gate electrode provided in Example 2 of the present application;

[0033] Figure 4 A schematic diagram of the process of a method for preparing a gallium nitride P-channel transistor with a self-aligned gate electrode provided in Example 3 of the present application.

[0034] Reference numerals:

[0035] Substrate (1), nucleation layer (2), buffer layer (3), P-type GaN channel layer (4), P-type GaN heavily doped layer (5), N-type GaN heavily doped layer (6), source electrode (7), drain electrode (8), gate dielectric layer (9), gate electrode (10), barrier layer (11), and InGaN barrier layer (12). DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0037] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the present application.

[0038] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or micro-control node devices.

[0039] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0040] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0041] The implementation details of the technical solution of the embodiment of the present application are described in detail below:

[0042] Example 1

[0043] This embodiment provides a gallium nitride P-channel transistor with a self-aligned gate electrode, which includes a substrate 1, a nucleation layer 2, a buffer layer 3, a P-type GaN channel layer 4, a P-type GaN heavily doped layer 5 and an N-type GaN heavily doped layer 6 from bottom to top; a gate groove is formed by etching on the upper surface of the N-type GaN heavily doped layer 6, and the depth of the gate groove enters the P-type GaN channel layer 5. A gate dielectric 9 and a gate metal are filled in the gate groove to realize a gate electrode 10. The N-type GaN heavily doped layer 6 and the P-type GaN heavily doped layer 5 on both sides of the gate groove form a tunnel junction, and the source electrode metal and the drain electrode metal respectively form an ohmic contact with the P-type GaN channel layer 4 through the tunnel junction.

[0044] Specifically, the P-type GaN heavily doped layer 5 and the N-type GaN heavily doped layer 6 are heavily doped in order to realize a tunnel junction.

[0045] Specifically, the gate electrode 10 contacts the N-type GaN heavily doped layer 6 , the P-type GaN heavily doped layer 5 , and the P-type GaN channel layer 4 through the gate dielectric layer 9 to form a metal-insulating layer-semiconductor structure.

[0046] The following is a description of each layer in the embodiments of the present application.

[0047] In an optional embodiment, the material of the substrate 1 is any one or more of Si, SiC, MgO, sapphire, and diamond; the material of the buffer layer 2 includes one or more of AlGaN and GaN, and the thickness is 0.1-5 μm.

[0048] In an optional embodiment, the material of the P-type GaN channel layer 4 is GaN, and the doping impurities include one or more of Mg and Zn, and the doping concentration is 1.0×10 17 -1.0×10 20 cm -3 , with a thickness of 5-100nm; the material of the P-type GaN heavily doped layer 5 is GaN, and the doping impurities include one or more of Mg and Zn, and the doping concentration is 1.0×10 19 -1.0×10 21 cm -3 , with a thickness of 5-100nm; the material of the N-type GaN heavily doped layer 6 is GaN, and the doping impurities include Si, and the doping concentration is 1.0×10 19 -1.0×10 21 cm -3 , thickness is 5-100nm.

[0049] In an optional embodiment, the material of the drain electrode 8 and the material of the source electrode 7 include at least two of Ti, Al, Ta, Mo, Au, and Ni; the material of the gate electrode 12 includes at least two of Ti, Al, Ta, Mo, Au, and Ni.

[0050] In an optional implementation manner, a barrier layer 11 is further provided between the buffer layer 3 and the P-type GaN channel layer 4; the material of the barrier layer 11 includes one or more of AlGaN, InAlN, and AlN, and has a thickness of 3-30 nm.

[0051] In an optional implementation manner, the P-type GaN heavily doped layer 5 and the N-type GaN heavily doped layer 6 are further provided with an InGaN barrier layer 12. The material of the InGaN barrier layer 12 is InGaN, with a composition of 0.1-0.5 and a thickness of 1-10 nm.

[0052] In an optional implementation manner, a gate dielectric layer 9 is further provided between the gate groove and the gate electrode 12; the material of the gate dielectric layer is one or more of Al2O3, SiO2, SiN, HfO2, ZrO2, and Ta2O5.

[0053] Compared with the traditional P-channel transistor, the present application adopts a tunnel junction formed by a P-type heavily doped layer 5, an InGaN barrier layer 12, and an N-type heavily doped layer 6, which avoids large gate-drain resistance and gate-source resistance and increases the current.

[0054] Example 2

[0055] The present application also includes a method for preparing a gallium nitride P-channel transistor with a self-aligned gate electrode, which is specifically implemented according to the following steps:

[0056] S1. Select substrate 1 and clean the surface of substrate 1. Specifically, at 1000° C., introduce hydrogen into the reaction chamber to remove pollutants on the surface of substrate 1 and form a microscopic step structure on the surface of substrate 1 to facilitate the growth of subsequent epitaxial layers.

[0057] S2, using a metal organic chemical vapor deposition process to sequentially grow a nucleation layer 2, a buffer layer 3, a P-type GaN channel layer 4, a P-type GaN heavily doped layer 5 and an N-type GaN heavily doped layer 6 on the substrate 1;

[0058] S3, using a photolithography process, using Cl2 and BCl3 to etch on the surface of the wafer, removing part of the P-type GaN channel layer 4, the P-type GaN heavily doped layer 5 and the N-type GaN heavily doped layer 6, and isolating different devices on the wafer;

[0059] S4, manufacturing the drain electrode 8 and the source electrode 7. Specifically, using electron beam evaporation equipment, the source electrode 7 is deposited on one end of the surface of the N-type GaN heavily doped layer 6, and the drain electrode 8 is deposited on the other end, and annealing is performed.

[0060] S5, using photolithography technology to carve out a gate groove region between the source electrode 7 and the drain electrode 8. Specifically, on the surface of the N-type heavily doped layer 6, a photoresist is spin-coated, and a photolithography machine is used to expose and develop the gate groove region, and then the ICP technology is used to etch out the gate groove;

[0061] S6, depositing a gate dielectric layer 9 on the surface of the gate groove;

[0062] S7, manufacturing the gate electrode 10. Specifically, an electron beam evaporation device is used to deposit a gate metal on the surface of the gate dielectric layer 9 to form the gate electrode 10, and finally the photoresist is washed away.

[0063] Example 3

[0064] The present application also includes another method for preparing a gallium nitride P-channel transistor with a self-aligned gate electrode, which is specifically implemented according to the following steps:

[0065] S1. Select substrate 1 and clean the surface of substrate 1. Specifically, at 1000° C., introduce hydrogen into the reaction chamber to remove pollutants on the surface of substrate 1 and form a microscopic step structure on the surface of substrate 1 to facilitate the growth of subsequent epitaxial layers.

[0066] S2, using a metal organic chemical vapor deposition process to sequentially grow a nucleation layer 2, a buffer layer 3, a P-type GaN channel layer 4, a P-type GaN heavily doped layer 5 and an N-type GaN heavily doped layer 6 on the substrate 1;

[0067] S3, using a photolithography process, using Cl2 and BCl3 to etch on the surface of the wafer, removing part of the buffer layer 3, the P-type GaN channel layer 4, the P-type GaN heavily doped layer 5 and the N-type GaN heavily doped layer 6, and isolating different devices on the wafer;

[0068] S4, using photolithography technology to carve out a gate groove region between the source electrode 7 and the drain electrode 8. Specifically, a photoresist is spin-coated on the surface of the N-type heavily doped layer 6, a photolithography machine is used to expose and develop the gate groove region, and then an ICP technology is used to etch out the gate groove;

[0069] S5, depositing a gate dielectric layer 9 on the surface of the gate groove;

[0070] S6, manufacturing the gate electrode 10. Specifically, using electron beam evaporation equipment to deposit gate metal on the surface of the gate dielectric layer 9 to form the gate electrode 10, and finally washing away the photoresist;

[0071] S7, manufacturing the drain electrode 7 and the source electrode 8. Specifically, using electron beam evaporation equipment, the source electrode 7 is deposited on one end of the surface of the N-type GaN heavily doped layer 6, and the drain electrode 8 is deposited on the other end, and annealing is performed.

[0072] In the preparation method provided in the embodiment of the present application, since the surface resistance of the N-type GaN heavily doped layer 6 is very low, the N-type GaN heavily doped layer in contact with the source electrode metal 7 or the drain electrode metal 8 becomes a part of the effective source electrode and the effective drain electrode respectively, so that the gate electrode achieves self-alignment with the effective source electrode and the effective drain electrode.

[0073] In the description of the present application, it should be noted that the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application; unless otherwise clearly specified and limited, the terms "install", "connect", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediary medium, and it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0074] The device includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device; in the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device that includes the elements.

[0075] The above description is only a specific implementation mode of the present application, which is convenient for those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined in this article can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in this article, but will conform to the widest scope consistent with the principles and novel features of the application in this article.

Claims

1. A method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode, characterized in that: The gallium nitride P-channel transistor comprises, from bottom to top, a substrate (1), a nucleation layer (2), a buffer layer (3), a P-type GaN channel layer (4), a P-type GaN heavily doped layer (5) and an N-type GaN heavily doped layer (6), and a preparation method thereof comprises the steps of: S1, selecting a substrate (1) and cleaning the surface of the substrate (1); S2. Growing a nucleation layer (2), a buffer layer (3), a P-type GaN channel layer (4), a P-type GaN heavily doped layer (5) and an N-type GaN heavily doped layer (6) in sequence on the substrate (1) by using an epitaxial method; S3, isolate the device; S4, depositing a source electrode metal (7) and a drain electrode metal (8) on the surface of the N-type GaN heavily doped layer (6); S5, etching a gate groove between the source electrode (7) and the drain electrode (8); S6, depositing a gate dielectric layer (9) on the surface of the gate groove; S7, depositing a gate metal on the surface of the gate dielectric layer (9) to form a gate electrode (10); The N-type GaN heavily doped layer (5) and the P-type GaN heavily doped layer (6) form a tunnel junction, and the source electrode metal (7) and the drain electrode metal (8) respectively form an ohmic contact with the P-type GaN channel layer (4) through the tunnel junction. Since the surface resistance of the N-type GaN heavily doped layer (6) is very low, the N-type GaN heavily doped layer (6) contacted below the source electrode metal (7) or the drain electrode metal (8) becomes a part of the effective source electrode and the effective drain electrode, so that the gate electrode (10) is self-aligned with the effective source electrode and the effective drain electrode.

2. A method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode according to claim 1, characterized in that: The material of the substrate (1) is any one or more of Si, SiC, sapphire, and diamond; the material of the nucleation layer (2) is a group III nitride semiconductor with a thickness of 0.1-0.3 μm; the material of the buffer layer (3) includes one or more of AlGaN and GaN with a thickness of 0.1-5 μm.

3. A method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode according to claim 1, characterized in that: The material of the P-type GaN channel layer (4) is GaN, and the doping impurities include one or more of Mg and Zn, and the doping concentration is 1.0×10 17 -1.0×10 20 cm -3 , with a thickness of 5-100 nm; the material of the P-type GaN heavily doped layer (5) is GaN, and the doping impurities include one or more of Mg and Zn, with a doping concentration of 1.0×10 19 -1.0×10 21 cm -3 , with a thickness of 5-100 nm; the material of the N-type GaN heavily doped layer (6) is GaN, and the doping impurities include Si, and the doping concentration is 1.0×10 19 -1.0×10 21 cm -3 , thickness is 5-100nm.

4. A method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode according to claim 1, characterized in that: The material of the drain electrode (8) or the material of the source electrode (7) includes at least two of Ti, Al, Ta, Mo, Au, and Ni; the material of the gate electrode (10) includes at least two of Ti, Al, Ta, Mo, Au, and Ni.

5. A method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode according to claim 1, characterized in that: An InGaN barrier layer (12) is also provided between the P-type GaN heavily doped layer (5) and the N-type GaN heavily doped layer (6); the material of the InGaN barrier layer (12) is InGaN, with a composition of 0.1-0.5 and a thickness of 1-10 nm.

6. A method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode according to claim 1, characterized in that: A barrier layer (11) is also provided between the buffer layer (3) and the P-type GaN channel layer (4); the material of the barrier layer (11) includes one or more of AlGaN, InAlN, and AlN, and has a thickness of 3-30 nm.

7. A method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode according to claim 1, characterized in that: The material of the gate dielectric layer is one or more of Al2O3, SiO2, SiN, HfO2, ZrO2, and Ta2O5.

8. A method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode according to claim 1, characterized in that In steps S5, S6 and S7, the same photoresist is used as a mask for etching the gate groove, depositing the gate dielectric layer (9) on the surface and depositing the gate metal. The gate dielectric layer (9) and the gate electrode (10) are realized by using a photoresist stripping process, so that the gate dielectric layer (9) and the gate electrode (10) do not exist on the upper surface of the N-type GaN heavily doped layer (6), thereby achieving self-alignment.

9. A method for realizing a gallium nitride P-channel transistor with a self-aligned gate electrode according to claim 1, characterized in that , steps S4-S7 are: S4, etching a gate groove between the source electrode (7) and the drain electrode (8); S5, depositing a gate dielectric layer (9) on the surface of the gate groove; S6, depositing a gate metal on the surface of the gate dielectric layer (9) to form a gate electrode (10); S7, depositing a source electrode metal (7) and a drain electrode metal (8) on the surface of the N-type GaN heavily doped layer (6).

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