A method for manufacturing a selectively activated p-gan gate HEMT device
By selectively activating the p-GaN gate HEMT device fabrication method, the problems of surface damage and high-frequency application requirements of traditional etching processes are solved, realizing high-performance and high-reliability p-GaN gate HEMT devices.
Patent Information
- Application Number
- CN202411661696.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2044-11-20
AI Technical Summary
Traditional p-GaN etching processes damage the surface, making it difficult to achieve a T-shaped gate electrode shape, which affects device performance and reliability and cannot meet the requirements of high-frequency applications.
A selectively activated p-GaN gate HEMT device fabrication method is adopted. By depositing an n-GaN layer in a partial area and combining it with thermal annealing, a local p-GaN gate is formed to prepare a T-type gate structure. Chemical mechanical polishing and inductively coupled plasma technology are used to replace dry etching, and the fabrication of source/drain electrodes and gate metal electrodes is optimized.
It improves device performance stability and reliability, reduces contact resistance, meets the requirements of high-frequency applications, enhances the repeatability of the manufacturing process and device consistency, and reduces the impact of etching damage on two-dimensional electron gas.
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Figure CN119789451B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor devices, in particular to a manufacturing method of a selectively activated p-GaN gate HEMT device. BACKGROUND
[0002] In the field of modern semiconductor devices, new wide-bandgap semiconductor materials represented by GaN have become the ideal choice for power semiconductor devices due to their superior intrinsic characteristics. GaN materials have characteristics such as wide bandgap, high electron mobility, high breakdown field strength, high saturation electron velocity, and high thermal conductivity, which make them have obvious advantages in high-power and high-frequency applications. In addition, the unique spontaneous polarization and piezoelectric polarization effect of GaN materials enables the formation of a high-concentration two-dimensional electron gas (2DEG) at the AlGaN / GaN interface, thereby realizing efficient conduction of the device channel.
[0003] Based on the heterojunction characteristics of GaN materials, traditional GaN high electron mobility transistor (HEMT) devices are generally depletion mode (normally on) structures. In practical applications, such devices require a negative voltage source to maintain the off state, which not only increases the complexity of circuit design, but also poses a risk of circuit misactivation, further increasing system power consumption. In contrast, enhancement mode GaN HEMT devices, which are in the off state at zero gate voltage, do not require a negative voltage drive, can significantly reduce additional power consumption and simplify circuit design, and are a more ideal solution. To achieve an enhancement mode GaN HEMT, p-GaN cap layer technology has become the mainstream method. This technology forms an enhancement mode characteristic by growing a p-GaN layer on the surface of the device, without the need for additional processing of the gate. Its advantages include stable performance, high repeatability, and strong reliability, and has become an important technical approach for the commercialization of GaN power devices. However, traditional p-GaN dry etching processes have significant limitations. First, the etching process can easily cause damage to the surface and introduce defects, affecting device performance and reliability. Second, etching precision has a significant impact on device performance, and etching too shallow or too deep can lead to depletion of the two-dimensional electron gas, thereby reducing the saturated output current of the device. In addition, it is difficult to achieve a T-shaped gate electrode shape using traditional dry etching processes, limiting the design requirements of short gate legs and wide gate heads for radio frequency devices, and failing to meet the needs of high-frequency applications. SUMMARY
[0004] The purpose of the present application is to provide a manufacturing method of a selectively activated p-GaN gate HEMT device to solve the problems existing in the prior art.
[0005] To achieve the above-mentioned purpose, the present application provides the following technical scheme: a manufacturing method of a selectively activated p-GaN gate HEMT device, the method comprising:
[0006] S1, selecting an epitaxial wafer, the epitaxial wafer comprising a substrate layer, a buffer layer, a channel layer, and a barrier layer, a heterojunction interface between the channel layer and the barrier layer forming a two-dimensional electron gas as a conductive channel;
[0007] S2, depositing a p-GaN layer with a thickness of 50-140 nm on the epitaxial wafer, the Mg doping concentration being 5×10 17 -5×10 20 cm -3 , and the Mg impurity being non-activated;
[0008] S3, depositing an n-GaN layer on a partial region of the p-GaN layer obtained in step S2, the n-GaN layer serving as a barrier layer to inhibit the activation of the partial p-GaN layer, the thickness of the n-GaN layer being 5-200 nm, and the Si doping concentration being 1×10 16 -1×10 20 cm -3 ;
[0009] S4, performing a thermal annealing treatment on the epitaxial wafer obtained in step S3 to activate the Mg impurity in the p-GaN layer not covered by the n-GaN layer in a N2 atmosphere, thereby forming a p-GaN gate;
[0010] S5, preparing a gate metal electrode on the p-GaN gate, the structure of the gate metal electrode from bottom to top being Ni / Au or TiN or W, and the gate metal electrode forming a Schottky contact with the p-GaN gate, the conductive channel of the two-dimensional electron gas being regulated by the p-GaN gate and the gate metal electrode.
[0011] Preferably, between step S4 and step S5 or after step S5, the following steps are further included:
[0012] preparing a source electrode and a drain electrode on the surface of the barrier layer on both sides of the p-GaN gate and the gate metal electrode, the source electrode and the drain electrode respectively forming an ohmic contact with the two-dimensional electron gas;
[0013] the metal structure of the source electrode and the drain electrode being Ti, Al, Ni, and Au in sequence.
[0014] Preferably, a layer of SiO2 with a thickness of 30-50 nm is deposited on the surface of the epitaxial wafer, and the SiO2 and the remaining n-GaN layer are removed by chemical mechanical polishing.
[0015] Preferably, the length of the p-GaN gate in step S4 is 10 nm-1 μm, and the gate metal electrode and the p-GaN gate form a "T" shaped gate structure for high frequency radio frequency devices.
[0016] Preferably, mesa etching or ion implantation is added between step S2 and step S3 or between step S3 and step S4 to achieve device isolation.
[0017] Preferably, each epitaxial layer of the epitaxial wafer is grown by metal organic chemical vapor deposition method, and the mesa etching is realized by inductively coupled plasma technology.
[0018] Preferably, the temperature of the heat annealing in S4 is 700-850℃, the holding time is 30-35 seconds, and the annealing atmosphere is nitrogen.
[0019] Preferably, the Mg doping concentration of the p-GaN layer is specifically 2.5×10 18 -1×10 20 cm 3 , and the Si doping concentration of the n-GaN layer is specifically 3×10 17 -8×10 20 cm 3 .
[0020] Preferably, the gate metal electrode in S5 is deposited by electron beam evaporation technology, and the metal materials are Ni / Au in sequence, wherein the thickness of Ni is 30-50nm, and the thickness of Au is 100-150nm.
[0021] Preferably, the mask area of the n-GaN layer is accurately defined between S3 and S4 by a photoetching process.
[0022] From the above technical solution, the present application has the following beneficial effects:
[0023] The selective activation p-GaN gate HEMT device manufacturing method, by depositing n-GaN layer in part of the area of p-GaN layer, forms shielding effect to p-GaN layer, and in combination with heat annealing process, precisely activates Mg doping in p-GaN layer not shielded, realizes selective activation of local area, significantly improves the performance of p-GaN gate, and at the same time avoids the problem of device performance degradation caused by full activation, by introducing chemical mechanical polishing and inductively coupled plasma technology, replaces the traditional dry etching process, reduces the physical damage and defect density of the surface of p-GaN and n-GaN layer, improves the performance stability and long-term reliability of the device, and the source electrode and the drain electrode prepared by using Ti / Al / Ni / Au metal combination can form excellent ohmic contact with two-dimensional electron gas, effectively reduce the contact resistance, improve the conductivity of the device, improve the power efficiency, by precisely defining the length (10nm to 1μm) of p-GaN gate and the T-shaped structure design of gate metal electrode, meet the special requirements of short gate foot and wide gate head of high frequency radio frequency device, improve the gain and efficiency of the device in high frequency environment, the gate metal electrode is deposited by electron beam evaporation process, the Ni / Au metal combination realizes stable Schottky contact, the thickness of the metal layer is accurately controllable, further improves the preparation precision and conductivity of the gate electrode, the mask area of n-GaN layer is accurately defined by photolithography process, in combination with mesa etching technology, the structure size of n-GaN layer and p-GaN layer is highly controllable, greatly improves the repeatability of the manufacturing process and the consistency of the device, each epitaxial layer is grown by metal organic chemical vapor deposition technology, the process is mature and suitable for batch production, in combination with accurate heat annealing and photolithography technology, the manufacturing efficiency is significantly improved, the cost is reduced, the influence of etching damage on two-dimensional electron gas density and device dynamic characteristics in the manufacturing process of conventional enhancement mode GaN HEMT device can be effectively reduced, which is beneficial to improve the cutoff frequency of the device, reduce the dynamic on-resistance and parasitic capacitance of the device, and enhance the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 It is a device structure schematic diagram formed after the steps S1 and S2 of the application;
[0025] Figure 2 It is a device structure schematic diagram formed after the step S3 of the application;
[0026] Figure 3 It is a device structure schematic diagram formed after the step S4 of the application;
[0027] Figure 4 、 Figure 5 It is a device structure schematic diagram of the process between steps S4 and S5 of the application;
[0028] Figure 6This is a schematic diagram of the device structure formed after the steps of claim 2 of the present invention;
[0029] Figure 7 This is a schematic diagram of the device structure formed after the steps of claim 5 of the present invention;
[0030] Figure 8 This is a schematic diagram of the device structure formed after step S5 of the present invention;
[0031] Figure 9 This is a top view of the device structure formed after step S5.
[0032] In the figure: 1. Substrate layer; 2. Buffer layer; 3. Channel layer; 4. Barrier layer; 5. p-GaN layer; 6. n-GaN layer; 7. p-GaN gate; 8. Source electrode; 9. Drain electrode; 10. Gate metal electrode. Detailed Implementation
[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] like Figures 1-9 As shown, the present invention provides a technical solution: a method for manufacturing a selectively activated p-GaN gate HEMT device, comprising the following steps:
[0035] S1. Selection of epitaxial wafer: Select epitaxial wafer 11, which includes a substrate layer 1, a buffer layer 2, a channel layer 3 and a barrier layer 4. The heterojunction interface between the channel layer 3 and the barrier layer 4 forms a two-dimensional electron gas, which serves as a conductive channel.
[0036] S2, p-GaN layer deposition: A p-GaN layer 5 with a thickness of 50nm-140nm is deposited on epitaxial wafer 11, with a Mg doping concentration of 5×10⁻⁶. 17 -5×10 20 cm －3 Mg impurities do not activate the cells.
[0037] S3. n-GaN layer deposition: An n-GaN layer 6 is deposited in a portion of the p-GaN layer 5 obtained in step S2. The n-GaN layer 6 acts as a barrier layer to suppress the activation of this portion of the p-GaN layer 5. The thickness of the n-GaN layer 6 is 5nm-200nm, and the Si doping concentration is 1×10⁻⁶. 16 -1×10 20 cm －3 .
[0038] S4, thermal annealing treatment: the epitaxial wafer 11 obtained in step S3 is subjected to thermal annealing treatment to activate the Mg impurities in the p-GaN layer 5 not covered by the n-GaN layer 6 in a N2 atmosphere, forming a p-GaN gate 7.
[0039] S5, gate metal electrode preparation: a gate metal electrode 10 is prepared on the p-GaN gate 7, the structure of the gate metal electrode 10 from bottom to top is Ni / Au or TiN or W, forming a Schottky contact with the p-GaN gate 7, and the conductive channel of the two-dimensional electron gas is regulated by the p-GaN gate 7 and the gate metal electrode 10.
[0040] The p-GaN layer 5 is selectively covered by the n-GaN layer 6, ensuring that only the Mg impurities in the uncovered area are activated during thermal annealing, forming a p-GaN gate 7 with local function. The gate metal electrode 10 forms a Schottky contact with the p-GaN gate 7, effectively regulating the conductive channel of the two-dimensional electron gas, and realizing the function control of the HEMT device. Through the blocking effect of the n-GaN layer 6, only the p-GaN layer 5 needs to be activated locally, reducing energy consumption, and the Schottky contact improves the current control ability and high frequency performance of the device, suitable for high power and high frequency scenarios. The selective activation technology avoids the complexity of activating the whole p-GaN layer, improves the process efficiency.
[0041] In one possible implementation, source and drain electrode preparation: source and drain electrodes 8 and 9 are prepared on the surface of the barrier layer 4 on both sides of the p-GaN gate 7 and the gate metal electrode 10, and the source and drain electrodes 8 and 9 respectively form an ohmic contact with the two-dimensional electron gas. The metal structure of the source and drain electrodes 8 and 9 is Ti, Al, Ni and Au in turn. The source and drain electrodes 8 and 9 form a low resistance channel through ohmic contact with the two-dimensional electron gas, supporting efficient transmission of electrons in the channel layer 3, and the multi-layer metal structure optimizes the contact performance, ensuring good conductivity and reliability. The multi-layer structure of Ti, Al, Ni and Au significantly reduces the contact resistance, optimizes the electron transmission efficiency, and through the selection of multi-layer metal, the thermal stability and mechanical strength of the electrode are improved.
[0042] In one possible implementation, a layer of SiO2 is deposited on the surface of the epitaxial wafer 11 with a thickness of 30-50 nm, and then chemical mechanical polishing is used to remove the SiO2 and the remaining n-GaN layer 6. After the formation of the p-GaN gate 7, a protective layer of SiO2 is deposited to cover the surface of the epitaxial wafer 11. The SiO2 layer and the remaining n-GaN layer 6 are selectively removed by chemical mechanical polishing technology, so that the surface of the p-GaN gate 7 is cleaned while ensuring the integrity of other areas. Precise control of chemical mechanical polishing can avoid damage to the p-GaN layer 5, thereby ensuring the quality and functionality of the gate area. Effective removal of the remaining n-GaN layer 6 and surface impurities optimizes the surface conditions of the p-GaN gate 7. By using the high precision of chemical mechanical polishing, precise control of the surface material is achieved, improving process reliability. By cleaning the gate surface, the contact performance of the metal electrode with the p-GaN gate 7 is improved.
[0043] In one possible implementation, the length of the p-GaN gate 7 is 10 nm-1 μm, and the gate metal electrode 10 and the p-GaN gate 7 form a "T" gate structure for high-frequency radio frequency devices. By designing the p-GaN gate 7 to have a length of 10 nm-1 μm, the size of the gate area of the HEMT device is optimized, ensuring good capacitance characteristics and gate control performance in high-frequency applications. The gate metal electrode 10 adopts a "T" gate design, which improves the mechanical stability and heat dissipation performance of the electrode while reducing the gate resistance. The top expansion part of the "T" gate structure can serve as a heat dissipation layer, improving the power capacity and thermal management performance of the radio frequency device. By shortening the gate length, the switching speed and high-frequency performance of the device are improved. The "T" gate design enhances the heat dissipation capability, improving the stability under high power conditions. It is suitable for applications such as 5G communication that require high frequency and low power consumption.
[0044] In one possible implementation, a mesa etching or ion implantation step is added between steps S2 and S3 or between steps S3 and S4. Mesa etching or ion implantation is used to partially etch the surface of the p-GaN layer 5 or the n-GaN layer 6 to form a more distinct hierarchical structure and area separation. Through the etching process, the contact characteristics of the p-GaN gate 7 with the surrounding layers can be adjusted to optimize the gate control effect and interface quality. This etching step can also provide a smoother surface for subsequent photolithography masking or metal electrode deposition, improving process precision. Through etching technology, a clear boundary between the p-GaN gate 7 area and the n-GaN layer 6 is ensured, improving device performance. Etching cleans the surface defects and residual materials, improving the deposition effect and contact performance of the gate metal electrode 10. A smoother and more regular surface is provided for subsequent process steps, reducing the error rate in the process.
[0045] In one possible implementation, each epitaxial layer is grown by metal organic chemical vapor deposition (MOCVD) method, and mesa etching is achieved by inductively coupled plasma (ICP) technology. Each epitaxial layer of the epitaxial wafer 11, including the buffer layer 2, the channel layer 3, the barrier layer 4, and the p-GaN layer 5 and the n-GaN layer 6, is grown by the MOCVD method, ensuring the uniformity of the material and the high-quality crystal structure. The mesa etching is achieved by the ICP technology, which uses the high energy and high directionality of the high-density plasma to achieve precise etching of the surface of the epitaxial layer and form a clear etching boundary. The ICP technology can also control the etching rate to avoid excessive damage to the underlying material and improve the processing quality. High-quality epitaxial layer: The MOCVD process ensures the high uniformity and excellent crystal characteristics of the epitaxial wafer, reducing the defect density. High etching precision: The high directionality and high selectivity of the ICP technology ensure the clarity of the etching boundary, optimizing the integrity of the structure and the performance of the device. Wide applicability: Both MOCVD and ICP technologies are mature processes suitable for large-scale production with high process repeatability.
[0046] In one possible implementation, the heat annealing temperature in step S4 is 700-850°C, the holding time is 30-35 seconds, and the annealing atmosphere is nitrogen. During the heat annealing process, the Mg impurities in the p-GaN layer 5 that is not covered by the n-GaN layer 6 are activated in the high-temperature nitrogen atmosphere to form a p-type conductive region (p-GaN gate 7). The optimization of the annealing temperature range (700-850°C) and the holding time (30-35 seconds) ensures the activation efficiency of the p-GaN layer 5 while avoiding thermal damage to the underlying structure. The use of pure nitrogen as the annealing atmosphere avoids the potential impact of oxidation or hydrogenation on the performance of the p-GaN layer 5. Through precise control of the annealing temperature and time, the sufficient activation of the Mg impurities in the p-GaN layer 5 is ensured, and the conductivity of the p-GaN gate 7 is improved. The use of a nitrogen atmosphere avoids the introduction of impurities and the degradation of material performance, ensuring the reliability of the process. The optimized annealing parameters reduce the impact of heat treatment on other layers in the epitaxial wafer 11, improving the overall performance stability of the device.
[0047] In one possible implementation, the Mg doping concentration of the p-GaN layer 5 is 2.5×10 18 -1×10 20 cm －3 , and the Si doping concentration of the n-GaN layer 6 is 3×10 17 -8×10 20 cm －3 . Adjusting the Mg doping concentration of the p-GaN layer 5 ensures that it has an appropriate hole concentration after activation, thereby optimizing the conductivity and gate control ability of the p-GaN gate 7. The Si doping concentration range of the n-GaN layer 6 is optimized to 3×10 17 -8×10 20cm －3 To provide an effective barrier effect, inhibit the activation of the p-GaN layer 5 in a specific area, and form a clear functional partition. By controlling the doping concentration, the electron gas channel is precisely regulated, and the device performance is optimized. Conductive performance optimization: The Mg doping concentration range of the p-GaN layer 5 ensures that the activated hole concentration meets the high performance requirements. Clear functional area: The doping concentration optimization of the n-GaN layer 6 inhibits the local activation of the p-GaN layer 5, significantly improving the clarity and stability of the functional partition. High frequency characteristic enhancement: By precisely controlling the doping concentration, the switching characteristics of the electron gas channel are optimized, and the high frequency performance of the HEMT device is improved.
[0048] In one possible implementation, the gate metal electrode 10 in step S5 is deposited using electron beam evaporation technology, and the metal materials are Ni / Au, with the thickness of Ni being 30-50 nm and the thickness of Au being 100-150 nm. The gate metal electrode 10 is deposited on the surface of the p-GaN gate 7 using electron beam evaporation technology, ensuring the uniformity of the thickness of the metal layer and the surface quality. Ni serves as a Schottky contact layer, forming a stable Schottky barrier with the p-GaN gate 7 and regulating the conductive channel of the two-dimensional electron gas. Au serves as a protective layer and a conductive layer, providing excellent electrical performance and oxidation resistance, while ensuring thermal stability. The Schottky contact of the Ni / Au structure has a low work function difference and high stability, improving the gate control effect. Electron beam evaporation technology can precisely control the thickness and deposition rate of the metal, ensuring the repeatability of the process and the formation of high-quality metal layers. The addition of the Au layer significantly improves the oxidation resistance of the electrode, prolonging the service life of the device.
[0049] In one possible implementation, the mask area of the n-GaN layer 6 is precisely defined between steps S3 and S4 through a photolithography process. The mask pattern is made on the surface of the n-GaN layer 6 through a photolithography process to clearly define the boundaries of the activation area and the barrier area. The photolithography mask process adopts steps such as resist coating, exposure, development, and etching to ensure the precise position and boundary quality of the mask area. The definition of the mask area provides a basis for the selective activation of the p-GaN layer 5 in the subsequent thermal annealing process, ensuring the accuracy and effect of the activation. Activation area is accurate: the photolithography process defines the mask area of the n-GaN layer 6, achieving high-precision control of the activation area and improving the consistency and stability of the device. High process compatibility: the photolithography process is highly compatible with the conventional semiconductor process flow and is easy to integrate into large-scale production. Flexible structure design: through the design of the mask pattern, the coverage area of the n-GaN layer 6 can be flexibly adjusted to adapt to different device design requirements.
[0050] Also provided is an embodiment of the transistor structure of the application, which comprises: a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a p-GaN layer 5, a p-GaN gate 7 obtained by selectively activating the p-GaN layer 5, a source electrode 8 and a drain electrode 9 arranged above the barrier layer 4, and a gate metal electrode 10 arranged above the p-GaN gate 7.
[0051] The substrate layer 1 is made of Si and has a thickness of 200 μm; the buffer layer 2 is made of GaN and has a thickness of 5000 nm; the channel layer 3 is made of GaN and has a thickness of 200 nm. The barrier layer 4 is made of AlGaN and has a thickness of 15 nm, with an Al component of 0.21 and a Ga component of 0.79. The source electrode 8 and the drain electrode 9 are successively made of Ti / Al / Ni / Au from bottom to top, with thicknesses of 20 / 120 / 45 / 55 nm, respectively. The source electrode 8 and the drain electrode 9 form an ohmic contact with the barrier layer 4. The p-GaN layer 5 has a thickness of 90 nm and a Mg doping concentration of 2.5×1019 cm-3. The n-GaN layer 5 has a thickness of 10 nm and a Si doping concentration of 3×1019 cm-3. The gate metal electrode 10 is successively made of Ni / Au from bottom to top, with thicknesses of 30 / 120 nm, respectively. The gate metal electrode 10 forms a Schottky contact with the p-GaN gate 7. The heterojunction interface formed by the channel layer 3 and the barrier layer 4 generates a two-dimensional electron gas as a conductive channel, which is regulated by the p-GaN gate 7 and the gate metal electrode 10. The p-GaN gate 7 can deplete the two-dimensional electron gas below the gate, so that the GaN transistor operates in an enhancement mode. 19 -3 18 -3 The heterojunction interface formed by the channel layer 3 and the barrier layer 4 generates a two-dimensional electron gas as a conductive channel, which is regulated by the p-GaN gate 7 and the gate metal electrode 10. The p-GaN gate 7 can deplete the two-dimensional electron gas below the gate, so that the GaN transistor operates in an enhancement mode.
[0052] A method for manufacturing a selectively activated p-GaN gate HEMT device, comprising the following steps:
[0053] 1. Material epitaxy is performed on a Si substrate, and a composite buffer layer, a channel layer, a barrier layer, a p-GaN layer and an n-GaN layer are successively grown, as shown in Figure 1 ;
[0054] 2. The epitaxial wafer obtained in step 1 is cleaned, first immersed in a piranha solution of H2SO4:H2O2=7:3 for 1 minute to remove oxides and impurities on the surface of the epitaxial wafer, and then subjected to organic cleaning, i.e. acetone solution and isopropanol solution are each ultrasonically treated for five minutes;
[0055] 3. Gluing, pre-baking and exposure operations are performed on the cleaned epitaxial wafer; an AZ5214 photoresist reverse process is adopted, and exposure is performed by an MA6 photoetching machine to prepare a photoresist pattern except for the p-GaN gate;
[0056] 4. The n-GaN in the gate region is removed by ICP dry etching, as shown in Figure 2 As shown;
[0057] 5. Perform rapid thermal annealing on the epitaxial wafer, holding it at 700℃ for 35 minutes in an N2 atmosphere to activate the Mg impurities in the gate region of p-GaN layer 5, obtaining p-GaN gate 7, as shown. Figure 3 As shown;
[0058] 6. Deposit a layer of SiO2 with a thickness of 50 nm on the surface of the epitaxial wafer, such as... Figure 4 As shown; chemical mechanical polishing (CMP) was used to remove SiO2 along with the remaining n-GaN layer 6, as follows. Figure 5 As shown;
[0059] 7. Using AZ6112 photoresist, the photoresist pattern of the mesa is prepared by exposure using an MA6 lithography machine; the areas outside the mesa are removed by ICP dry etching to a depth of 200nm, completing device isolation, such as... Figure 6 As shown;
[0060] 8. Using the AZ5214 photoresist inversion process, the photoresist pattern other than the source and drain electrodes was prepared by exposure using an MA6 lithography machine; a multilayer metal Ti / Al / Ni / Au was grown by electron beam evaporation, wherein the thickness of Ti was 20nm, the thickness of Al was 120nm, the thickness of Ni was 45nm, and the thickness of Au was 55nm. After lift-off, the source electrode 8 and drain electrode 9 were formed, as shown below. Figure 7 As shown;
[0061] 9. Rapid thermal annealing was performed at 820℃ in a N2 atmosphere for 32s to form an ohmic contact between the source electrode 8 and the drain electrode 9 and the AlGaN barrier layer.
[0062] 10. Using an AZ5214 photoresist inversion process, a photoresist pattern was prepared on the p-GaN gate 7 surface through exposure using an MA6 lithography machine. Ni / Au was then grown by electron beam evaporation, with Ni having a thickness of 30 nm and Au a thickness of 120 nm. After lift-off, the gate metal electrode 10 was obtained. Figure 8 As shown, the gate metal electrode 10 forms a Schottky contact with the p-GaN gate 7, and the two-dimensional electron gas in the lower channel is depleted through the p-GaN gate 7 to obtain a selectively activated p-GaN gate HEMT device.
[0063] Another embodiment is provided, wherein the transistor structure used in the present invention includes: a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a p-GaN layer 5, selectively activating the p-GaN layer 5 to obtain a p-GaN gate 7, an active electrode 8 and a drain electrode 9 are disposed above the barrier layer 4, and a gate metal electrode 10 is disposed above the p-GaN gate 7.
[0064] The material of the substrate layer 1 is sapphire with a thickness of 500 μm; the material of the buffer layer 2 is AlN with a thickness of 2000 nm; the material of the channel layer 3 is GaN with a thickness of 300 nm. The thickness of the barrier layer 4 is 20 nm, the Al component is 0.25, and the Ga component is 0.75. The structure of the source electrode 8 and the drain electrode 9 is Ti / Al / Ni / Au from bottom to top, and the thicknesses are 20 / 120 / 40 / 50 nm respectively. The source electrode 8 and the drain electrode 9 form ohmic contact with the barrier layer 4. The thickness of the p-GaN layer 5 is 100 nm, and the Mg doping concentration is 1×1019cm-3. The thickness of the n-GaN layer 5 is 5 nm, and the Si doping concentration is 6×1018cm-3. The structure of the gate metal electrode 10 is Ni / Au from bottom to top, and the thicknesses are 30 / 120 nm respectively. The gate metal electrode 10 forms Schottky contact with the p-GaN gate 7. The heterojunction interface formed by the channel layer 3 and the barrier layer 4 generates a two-dimensional electron gas as a conductive channel, which is regulated by the p-GaN gate 7 and the gate metal electrode 10. The p-GaN gate 7 can deplete the two-dimensional electron gas below the gate, so that the GaN transistor works in an enhancement mode. 18 -3 20 -3 The structure of the gate metal electrode 10 is Ni / Au from bottom to top, and the thicknesses are 30 / 120 nm respectively. The gate metal electrode 10 forms Schottky contact with the p-GaN gate 7. The heterojunction interface formed by the channel layer 3 and the barrier layer 4 generates a two-dimensional electron gas as a conductive channel, which is regulated by the p-GaN gate 7 and the gate metal electrode 10. The p-GaN gate 7 can deplete the two-dimensional electron gas below the gate, so that the GaN transistor works in an enhancement mode.
[0065] A selective activation p-GaN gate HEMT device manufacturing method, comprising the following steps:
[0066] 1. Using a Si substrate for material epitaxy, growing a buffer layer, a channel layer, a barrier layer, a p-GaN layer and an n-GaN layer in sequence, as shown in Figure 1 ;
[0067] 2. Cleaning the epitaxial wafer obtained in step 1, first immersing it in an arowana solution of H2SO4:H2O2=7:3 for 1 minute to remove oxides and impurities on the surface of the epitaxial wafer, and then performing organic cleaning, i.e. ultrasonic treatment in acetone solution and isopropyl alcohol solution for five minutes each;
[0068] 3. Performing glue coating, pre-baking and exposure operations on the cleaned epitaxial wafer; using AZ5214 photoresist reverse process, exposure is performed by an MA6 photoetching machine to prepare a photoresist pattern except for the p-GaN gate;
[0069] 4. Removing the n-GaN in the gate region by ICP dry etching, as shown in Figure 2 ;
[0070] 5. Rapid thermal annealing treatment is performed on the epitaxial wafer, which is kept at 700℃ for 35 minutes in N2 atmosphere to activate the Mg impurities in the gate region of the p-GaN layer 5, and the p-GaN gate 7 is obtained, as shown in Figure 3 ;
[0071] 6. A layer of SiO2 is deposited on the surface of the epitaxial wafer with a thickness of 30 nm, as shown in Fig. 2; the SiO2 and the remaining n-GaN layer 6 are removed by chemical mechanical polishing (CMP), as shown in Fig. 3; Figure 4 Figure 5
[0072] 7. A photoresist pattern is prepared by exposing the mesa using AZ6112 photoresist and MA6 photoetching machine; the part outside the mesa is removed by ICP dry etching with an etching depth of 200 nm, as shown in Fig. 4; and device isolation is completed. Figure 6
[0073] 8. A photoresist pattern is prepared by exposing the source and drain electrodes using AZ5214 photoresist reversal process and MA6 photoetching machine; a multi-layer metal Ti / Al / Ni / Au is grown by electron beam evaporation, wherein the thickness of Ti is 20 nm, the thickness of Al is 120 nm, the thickness of Ni is 40 nm, and the thickness of Au is 50 nm; and the source electrode 8 and the drain electrode 9 are formed after stripping, as shown in Fig. 5. Figure 7
[0074] 9. Rapid thermal annealing is performed at 850°C in N2 atmosphere for 30 s, and the source electrode 8 and the drain electrode 9 form ohmic contact with the AlGaN barrier layer.
[0075] 10. A photoresist pattern is prepared by exposing the gate metal electrode using AZ5214 photoresist reversal process and MA6 photoetching machine on the surface of the p-GaN gate 7; a multi-layer metal Ni / Au is grown by electron beam evaporation, wherein the thickness of Ni is 30 nm and the thickness of Au is 120 nm; and the gate metal electrode 10 is prepared after stripping, as shown in Fig. 6; the gate metal electrode 10 forms Schottky contact with the p-GaN gate 7, and the two-dimensional electron gas in the channel below is depleted through the p-GaN gate 7, thereby obtaining a selectively activated p-GaN gate HEMT device. Figure 8 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8
[0076] Although the embodiments of the present application have been shown and described, it is to be understood that various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.
Claims
1. A method of fabricating a selectively activated p-GaN gate HEMT device, comprising: The method comprises: S1, selecting an epitaxial wafer (11), the epitaxial wafer (11) comprising a substrate layer (1), a buffer layer (2), a channel layer (3), and a barrier layer (4), a heterojunction interface between the channel layer (3) and the barrier layer (4) forming a two-dimensional electron gas as a conductive channel; S2, depositing a p-GaN layer (5) on the epitaxial wafer (11) having a thickness of 50 nm to 140 nm and a Mg doping concentration of 5 x 1018 cm-3, the Mg impurities being not activated; 17 - 5 x 1018 cm-3, the Mg impurities being not activated; 20 cm-3, the Mg impurities being not activated; -3 S3, depositing an n-GaN layer (6) on a part of the p-GaN layer (5) obtained in step S2, the n-GaN layer (6) serving as a barrier layer to inhibit activation of the part of the p-GaN layer (5), the n-GaN layer (6) having a thickness of 5 nm to 200 nm and a Si doping concentration of 1 x 1018cm"3to 1 x 1020cm"3. 16 -1 x 1018cm"3 20 cm -3 ; S4, performing a thermal annealing treatment on the epitaxial wafer (11) obtained in step S3 to activate Mg impurities in a p-GaN layer (5) not covered by an n-GaN layer (6) in a N2 atmosphere, thereby forming a p-GaN gate (7); S5, preparing a gate metal electrode (10) on the p-GaN gate (7), the structure of the gate metal electrode (10) from bottom to top being Ni / Au or TiN or W, thereby forming a Schottky contact with the p-GaN gate (7), and the conductive channel of the two-dimensional electron gas being regulated by the p-GaN gate (7) and the gate metal electrode (10); Between step S4 and step S5 or after step S5, the following steps are further included: Preparation of a source electrode (8) and a drain electrode (9) on the surface of the barrier layer (4) on both sides of the p-GaN gate (7) and the gate metal electrode (10), the source electrode (8) and the drain electrode (9) respectively forming an ohmic contact with the two-dimensional electron gas; The metal structure of the source electrode (8) and the drain electrode (9) is Ti, Al, Ni, and Au in sequence.
2. The method of claim 1, wherein the method further comprises: A layer of SiO2 with a thickness of 30-50 nm is deposited on the surface of the epitaxial wafer (11), and the SiO2 and the remaining n-GaN layer (6) are removed by chemical mechanical polishing.
3. The method of claim 1, wherein the method further comprises: The length of the p-GaN gate (7) in step S4 is 10-1 μm, and the gate metal electrode (10) and the p-GaN gate (7) form a "T" gate structure for high-frequency radio frequency devices.
4. The method of claim 1, wherein the method further comprises: A mesa etching or ion implantation is added between step S2 and step S3 or between step S3 and step S4 to achieve device isolation.
5. The method of claim 1, wherein the method further comprises: Each epitaxial layer of the epitaxial wafer (11) is grown by a metal organic chemical vapor deposition method, and the mesa etching is achieved by an inductively coupled plasma technology.
6. The method of claim 1, wherein the method further comprises: The temperature of the thermal annealing treatment in step S4 is 700-850℃, the holding time is 30-35 seconds, and the annealing atmosphere is nitrogen.
7. The method of claim 1, wherein the method further comprises: The Mg doping concentration of the p-GaN layer (5) is specifically 2.5 x 10 18 -1 x 10 20 cm 3 -3, and the Si doping concentration of the n-GaN layer (6) is specifically 3 x 10 17 -8 x 10 20 cm 3 .
8. The method of claim 1, wherein the method further comprises: The gate metal electrode (10) in step S5 is deposited by an electron beam evaporation technology, and the metal materials are Ni / Au in sequence, wherein the thickness of Ni is 30-50 nm, and the thickness of Au is 100-150 nm.
9. The method of claim 1, wherein the method further comprises: The mask area of the n-GaN layer (6) is precisely defined by a photolithography process between step S3 and step S4.
Citation Information
Patent Citations
P-type nitride enhanced HEMT device and preparation method thereof
CN115000168A