Vertical gallium nitride-based fin radio frequency junction field effect transistor and method of fabrication

Abstract

The present invention discloses a vertical gallium nitride-based fin-type radio frequency junction field effect transistor and a preparation method thereof, which relate to the technical field of semiconductor devices, and comprise a substrate layer, a nucleation layer, a buffer layer, and a drain contact layer stacked in sequence from bottom to top; a channel layer, arranged on the drain contact layer, consisting of a fin channel layer and a non-fin channel layer; a source contact layer, arranged on the fin channel layer; a P-type gate, arranged on both sides of the fin channel layer and on part of the surface of the non-fin channel layer; a gate electrode, arranged on an extension portion of the P-type gate, forming an ohmic contact or a Schottky contact with the P-type gate; a drain electrode, arranged on the drain contact layer, forming an ohmic contact with the drain contact layer; the vertical gallium nitride-based fin-type radio frequency junction field effect transistor and the preparation method thereof are beneficial to achieving enhanced operation, and improve the voltage resistance of the gate electrode, expand the dynamic range of the gate signal input, and improve the long-term reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a vertical gallium nitride-based fin-type radio frequency junction field effect transistor and a preparation method thereof. BACKGROUND

[0002] With the rapid development of semiconductor technology, based on the prediction of Moore's law, semiconductor technology has been widely used in many fields such as aerospace, wireless communication and electric vehicle. The performance of semiconductor devices has always been the focus of attention, among which, silicon (Si) as the first generation of semiconductor material, due to its mature process and superior physical properties, has long dominated the semiconductor devices. However, with the continuous progress of technology, the performance of silicon material has approached its physical limit, resulting in a bottleneck in improving the performance of semiconductor devices based on silicon material. This problem also makes the continuous effectiveness of Moore's law questionable.

[0003] In order to cope with the limitations of silicon material, people gradually turn their attention to new generation of semiconductor materials. Among them, gallium nitride (GaN) as a typical representative of the third generation of wide bandgap semiconductors, with its wide bandgap, high critical electric field strength, high electron saturation velocity and high breakdown field, has shown great application potential in high power and high frequency device field. At present, gallium nitride devices are mainly in the form of lateral structure, especially high electron mobility transistor (HEMT). However, the lateral structure GaN device has the following problems in application: for high power devices, in order to meet the performance requirements, the width and number of gate electrodes need to be increased, which leads to significant increase of device area and introduces more parasitic capacitance, affecting the performance of the device; the conduction channel of lateral structure GaN HEMT device depends on two-dimensional electron gas (2DEG), and 2DEG is easily affected by surface state, which reduces the stability of the device; the lateral structure device is prone to the phenomenon of charge concentration at both ends of the channel, resulting in serious local heat production at both ends and low breakdown voltage of the device, and the reliability is reduced. SUMMARY

[0004] The purpose of the present application is to provide a vertical gallium nitride-based fin-type radio frequency junction field effect transistor and a preparation method thereof, which solves the problems existing in the prior art.

[0005] To achieve the above purpose, the present application provides the following technical scheme: a vertical gallium nitride-based fin-type radio frequency junction field effect transistor, comprising:

[0006] a substrate layer, a nucleation layer, a buffer layer and a drain contact layer are sequentially stacked from bottom to top;

[0007] a channel layer, disposed on the drain contact layer, composed of a fin channel layer and a non-fin channel layer;

[0008] a source contact layer, disposed on the fin channel layer;

[0009] A P-type gate is provided on both sides of the fin channel layer and a portion of the surface of the non-fin channel layer;

[0010] a gate electrode, disposed on the P-type gate extension portion, and forming an ohmic contact or a Schottky contact with the P-type gate;

[0011] a drain electrode, disposed on the drain contact layer and forming an ohmic contact with the drain contact layer;

[0012] a source electrode, disposed on the source contact layer and forming an ohmic contact with the source contact layer;

[0013] The materials of the buffer layer, the drain contact layer, the channel layer, the source contact layer and the P-type gate are group III nitride semiconductor materials.

[0014] Preferably, the drain contact layer is made of GaN, AlGaN or InGaN, has a thickness of 50 nm to 2 μm, and is doped with Si at a doping concentration of 1×10 17 to 1×10 21 cm -3 .

[0015] Preferably, the material of the channel layer is gallium nitride, AlGaN or InGaN, with a thickness of 100nm to 10μm, and the doping impurity is Si, with a doping concentration of 1×10 15 to 1×10 18 cm -3 .

[0016] Preferably, the height of the fin channel layer is 40 nm to 10 μm, and the width of the fin is 10 nm to 1 μm.

[0017] Preferably, the doping impurity of the P-type gate is Mg, and the doping concentration is 1×10 15 to 1×10 18 cm -3 , thickness is 5nm to 100nm, and height is 5nm to 1μm.

[0018] Preferably, the source contact layer is made of GaN, AlGaN or InGaN, has a thickness of 10 nm to 1 μm, and is doped with Si at a doping concentration of 1×10 17 to 1×10 21 cm -3 .

[0019] Preferably, the height of the P-type gate does not exceed the height of the fin channel layer.

[0020] The application discloses a preparation method of a vertical gallium nitride-based fin-type radio frequency junction field effect transistor.

[0021] S1, selecting a substrate layer;

[0022] S2, sequentially epitaxially growing a nucleation layer, a buffer layer, a drain contact layer, a channel layer and a source contact layer on the substrate layer;

[0023] S3, etching the channel layer and the source contact layer to form a fin channel layer;

[0024] S4, performing P-GaN regrowth on part of the surface of the channel layer to form a P-type gate;

[0025] S5, etching the channel layer to expose both ends of the drain contact layer;

[0026] S6, preparing a source electrode above the source contact layer and preparing a drain electrode at both ends of the drain contact layer;

[0027] S7, preparing a gate electrode on an extended part of the P-type gate.

[0028] The material of the substrate layer is silicon, sapphire or SiC, and the surface is subjected to chemical cleaning treatment and then used for epitaxial growth.

[0029] The material of the nucleation layer is AlN, and the epitaxial growth temperature is 950 DEG C.

[0030] According to the technical scheme, the application has the following beneficial effects:

[0031] The vertical gallium nitride-based fin-type radio frequency junction field effect transistor and the preparation method thereof, by adopting a vertical structure design, significantly reduces the local heating problem caused by charge concentration in a lateral structure device, improves the breakdown voltage and long-term stability of the device. At the same time, the vertical current path effectively distributes the power density, reduces the heat dissipation difficulty, through the innovative design of the fin channel layer, the device of the application effectively reduces the gate area while improving the current density, reduces the parasitic capacitance, thereby improving the switching speed and performance in high frequency application, adopting a P-type gate structure and optimizing the doping process, effectively avoiding the instability of the two-dimensional electron gas caused by the influence of the surface state, enhancing the reliability of the conductive channel and the consistency of the device, the application proposes an epitaxial growth scheme compatible with various substrate materials (such as silicon, sapphire or SiC), and through optimization of the material and thickness of the nucleation layer and buffer layer, high-quality epitaxial layer growth is realized. This not only improves the adaptability of the material, but also reduces the process complexity and cost, the use of wide bandgap materials and innovative fin structure design, the device shows excellent performance in high power and high frequency application scenarios (such as radio frequency amplifiers and high efficiency switching power supplies), meeting the needs of the next generation of high power density devices, the introduction of P-type gate between the gate electrode and the channel layer is beneficial to realize the enhancement type work, and improves the voltage resistance of the gate electrode, expands the dynamic range of the gate signal input, improves the long-term reliability of the device, the non-fin channel layer and the P-type gate and gate electrode on the surface have a certain field plate effect, which improves the breakdown voltage of the device and suppresses the current collapse effect of the device. Compared with the lateral structure transistor, the vertical gallium nitride-based fin-type radio frequency transistor provided by the application only needs to increase the thickness of the non-fin part of the channel layer to improve the voltage resistance of the device, so that the device area is smaller and the cost is lower under the same voltage resistance and current conditions. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a vertical gallium nitride-based fin-type radio frequency transistor structure schematic diagram of the application;

[0033] Figure 2 It is a vertical gallium nitride-based fin-type radio frequency transistor preparation method process schematic diagram of the application;

[0034] Figure 3 It is a vertical gallium nitride-based fin-type radio frequency transistor preparation method process schematic diagram of the application;

[0035] Figure 4 It is a vertical gallium nitride-based fin-type radio frequency transistor preparation method process schematic diagram of the application;

[0036] Figure 5 It is a vertical gallium nitride-based fin-type radio frequency transistor preparation method process schematic diagram of the application;

[0037] Figure 6Process flow chart for preparing the vertical gallium nitride-based finned radio frequency transistor of the present application;

[0038] Figure 7 Process flow chart for preparing the vertical gallium nitride-based finned radio frequency transistor of the present application;

[0039] Figure 8 Process flow chart for preparing the vertical gallium nitride-based finned radio frequency transistor of the present application;

[0040] Figure 9 Process flow chart for preparing the vertical gallium nitride-based finned radio frequency transistor of the present application;

[0041] Figure 10 Process flow chart for preparing the vertical gallium nitride-based finned radio frequency transistor of the present application;

[0042] Figure 11 Process flow chart for preparing the vertical gallium nitride-based finned radio frequency transistor of the present application;

[0043] Figure 12 Process flow chart for preparing the vertical gallium nitride-based finned radio frequency transistor of the present application;

[0044] Figure: 1, substrate layer; 2, nucleation layer; 3, buffer layer; 4, drain contact layer; 5, channel layer; 51, fin channel layer; 52, non-fin channel layer; 6, source contact layer; 7, gate electrode; 71, P-type gate; 8, drain electrode; 9, source electrode. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0046] As Figures 1-12As shown, the present application provides a technical solution: a vertical gallium nitride-based fin-type radio frequency junction field effect transistor includes a substrate layer 1, a nucleation layer 2, a buffer layer 3, a drain contact layer 4, which are sequentially stacked from bottom to top; a channel layer 5 composed of a fin channel layer 51 and a non-fin channel layer 52, disposed on the drain contact layer 4; a source contact layer 6 disposed on the fin channel layer 51; a P-type gate 71 disposed on both sides of the fin channel layer 51 and part of the surface of the non-fin channel layer 52; a gate electrode 7 disposed on the extended part of the P-type gate 71, forming ohmic contact or Schottky contact with the P-type gate 71; a drain electrode 8 disposed on the drain contact layer 4, forming ohmic contact with the drain contact layer 4; a source electrode 9 disposed on the source contact layer 6, forming ohmic contact with the source contact layer 6; wherein the materials of the buffer layer 3, the drain contact layer 4, the channel layer 5, the source contact layer 6 and the P-type gate 71 are III-nitride semiconductor materials.

[0047] The transistor uses a fin structure to realize vertical current path and optimize radio frequency performance. The existence of the P-type gate 71 forms local depletion control of the channel layer 5. The fin channel layer 51 increases the effective gate area of the transistor, improving the gate control ability and current density. The ohmic contact between the drain contact layer 4 and the drain electrode 8 ensures low resistance conduction, and the ohmic contact between the source contact layer 6 and the source electrode 9 realizes efficient current injection, enhancing the performance of the transistor. The overall structure uses III-nitride material, which has the characteristics of high breakdown voltage and low loss. The design of this structure realizes high-efficiency radio frequency signal amplification function, with the advantages of high frequency performance and low power consumption. The vertical structure simplifies the device layout, improves the heat dissipation performance and power density. The design of the P-type gate further improves the switching speed and control accuracy of the transistor, and the overall structure has higher stability under high temperature and high voltage conditions.

[0048] In one possible implementation, the material of the drain contact layer 4 is GaN, Al GaN or InGaN, the thickness is 50nm to 2μm, the doping impurity is Si, and the doping concentration is 1×10 17 to 1×10 21 cm -3 . The drain contact layer 4 increases the concentration of electrons by doping Si elements, reduces the internal resistance of the layer, and realizes efficient drain current transmission. The material thickness is controlled between 50nm and 2μm, taking into account the electrical conductivity and the integrity of the device structure. The use of the above doping concentration range and material combination makes the drain contact layer have low resistance and high reliability, meets the high power and high frequency operation requirements, and further enhances the radio frequency performance of the transistor.

[0049] In one possible implementation, the material of the channel layer 5 is gallium nitride, Al GaN or InGaN, the thickness is 100nm to 10μm, the doping impurity is Si, and the doping concentration is 1×1015 1 x 10 18 cm -3 The channel layer 5 is optimized by doping control, and the selection of the thickness range ensures the stability of the current channel and the balance of the transistor switching performance. The optimization of the doping concentration provides adjustable performance suitable for different working voltage and frequency conditions. The optimized channel layer material and doping concentration achieve the comprehensive performance of low leakage current, high switching speed and high breakdown voltage, significantly improving the radio frequency output power and reliability of the device.

[0050] In a possible implementation, the height of the fin channel layer 51 is 40 nm to 10 μm, and the fin width is 10 nm to 1 μm. The fin channel layer 51 is designed by a specific height and width to optimize the electric field distribution and current density of the transistor. Higher fin structure increases the effective gate area and improves the gate control efficiency; narrower fin width increases the electric field control ability of the gate to the channel, thereby effectively suppressing the short channel effect. This design makes the transistor have the advantages of high switching speed, high current density and low leakage current, while ensuring the stability support in high frequency applications. The fin structure also improves the power density and withstand voltage capability of the transistor.

[0051] In a possible implementation, the doping impurity of the P-type gate 71 is Mg, and the doping concentration is 1 x 10 15 1 x 10 18 cm -3 The thickness is 5 nm to 100 nm, and the height is 5 nm to 1 μm. The P-type gate 71 is doped with Mg element to form P-type characteristics and provide a depletion or enhancement control mechanism for the channel layer. The optimization of the thickness and height range ensures the uniformity of the gate coverage area, while reducing the parasitic capacitance of the device. This design makes the transistor exhibit excellent control ability in different working modes, ensuring high-speed switching characteristics and low-power operation. In addition, the presence of the P-type gate also improves the controllability of the switching threshold and the anti-interference ability of the transistor.

[0052] In a possible implementation, the material of the source contact layer 6 is GaN, Al GaN or InGaN, the thickness is 10 nm to 1 μm, the doping impurity is Si, and the doping concentration is 1 x 10 17 1 x 10 21 cm -3 The source contact layer 6 realizes high-concentration electron injection by doping Si to form ohmic contact with low contact resistance. The selection of the material and thickness takes into account the conductivity and device stability, supporting efficient source current injection. This structure design effectively reduces the source resistance, improves the power efficiency and output characteristics of the transistor, and improves the reliability and anti-interference ability of high-frequency operation.

[0053] In one possible implementation, the height of the P-type gate 71 does not exceed the height of the fin channel layer 51. By limiting the height of the P-type gate 71, it is ensured that it only exerts control over the effective area of the channel layer, avoiding unnecessary parasitic effects due to excessive area coverage, while maintaining the strength and uniformity of the gate electric field. This limiting design significantly reduces the parasitic capacitance of the device, improves the switching speed and high-frequency performance of the transistor, while reducing the leakage current and power consumption, and improves the overall performance stability.

[0054] Also provided is a preparation method of a vertical gallium nitride-based fin-type RF JFET, which adopts the vertical gallium nitride-based fin-type RF JFET.

[0055] S1, selecting a substrate layer 1;

[0056] S2, epitaxially growing a nucleation layer 2, a buffer layer 3, a drain contact layer 4, a channel layer 5, and a source contact layer 6 in sequence on the substrate layer 1;

[0057] S3, etching the channel layer 5 and the source contact layer 6 to form a fin channel layer 51;

[0058] S4, P-GaN regrowth on part of the surface of the channel layer 5 to form a P-type gate 71;

[0059] S5, etching the channel layer 5 to expose both ends of the drain contact layer 4;

[0060] S6, preparing a source electrode 9 above the source contact layer 6 and a drain electrode 8 at both ends of the drain contact layer 4;

[0061] S7, preparing a gate electrode 7 on the extended part of the P-type gate 71.

[0062] The preparation method precisely controls the fin structure of the channel layer and the formation position of the P-type gate through selective etching and regrowth technology, thereby realizing local regulation of the channel layer. The epitaxial growth process of steps S1-S2 ensures high-quality growth and material integrity of each layer of the transistor. The etching process in step S3 defines the geometric parameters of the fin channel layer, which helps to optimize the electrical performance of the device. The P-GaN regrowth in S4 forms a P-type gate for regulating the depletion region of the channel layer. The electrode preparation steps of S6 and S7 ensure the ohmic contact and gate signal transmission capability of the device. This method provides a high-precision manufacturing process, realizing low power consumption, high efficiency, and high-frequency performance of the transistor. The formation process of the fin structure simplifies the control of the vertical current path, improves the power density and heat dissipation performance of the device. The selective regrowth technology of the P-type gate ensures local control of the channel layer, improving the working efficiency and reliability of the device.

[0063] In a possible implementation, the material of the substrate layer 1 is silicon, sapphire or SiC, and the surface is subjected to chemical cleaning treatment before epitaxial growth. By selecting different materials of the substrate layer 1, a stable lattice matching basis can be provided for epitaxial growth. The chemical cleaning treatment can remove oxides and other contaminants on the surface of the substrate, thereby improving the crystal quality and adhesion of the epitaxial growth layer. The silicon substrate has the advantages of low cost and good thermal conductivity; the sapphire substrate has good electrical insulation and heat resistance; and the SiC substrate provides excellent thermal conductivity and lattice matching. The selection of different substrate materials meets the different needs of devices in terms of cost, thermal conductivity and mechanical properties. The introduction of chemical cleaning treatment significantly improves the uniformity and defect density control capability of the epitaxial layer, and finally improves the overall performance of the device.

[0064] In a possible implementation, the material of the nucleation layer 2 is AlN, and the epitaxial growth temperature is 950℃. The use of AlN material for the nucleation layer 2 can effectively reduce the stress caused by lattice mismatch during epitaxial growth, while optimizing the crystal quality of the subsequent epitaxial layer. The epitaxial growth temperature of 950℃ ensures uniform deposition and low defect density of the AlN layer, providing a high-quality nucleation substrate. By using an AlN nucleation layer and precise temperature control, the crystal defects and interface stress are greatly reduced, the adhesion and crystalline quality of the subsequent growth layer are improved, and thus the reliability and performance of the device are improved.

[0065] In another embodiment, a vertical gallium nitride-based fin-type RF JFET includes, from bottom to top, a substrate layer 1, a nucleation layer 2, a buffer layer 3, and a drain contact layer 4.

[0066] A channel layer 5 is disposed on the drain contact layer 4 and includes a fin channel layer 51 and a non-fin channel layer 52.

[0067] A source contact layer 6 is disposed on the fin channel layer 51.

[0068] A P-type gate 71 is disposed on both sides of the fin channel layer 51 and part of the surface of the non-fin channel layer 52.

[0069] A gate electrode 7 is disposed on the extended part of the P-type gate 71 and forms an ohmic contact or a Schottky contact with the P-type gate 71 in the channel layer.

[0070] A drain electrode 8 is disposed on the upper surface of the drain contact layer 4 and forms an ohmic contact with the drain contact layer 4.

[0071] A source electrode 9 is disposed on the source contact layer 6 and forms an ohmic contact with the source contact layer 6.

[0072] The materials of the buffer layer 3, the drain contact layer 4, the channel layer 5, the source contact layer 6 and the P-type gate 71 are all III-V nitride semiconductor materials, which are one of GaN, AlN and InN or a compound composed of multiple materials; the fin channel layer 51 improves the control of the gate electrode 7 on the conductive channel, improves the transconductance of the device, suppresses the short channel effect and is beneficial to the realization of the enhancement mode; the non-fin channel layer 52 has a certain field plate effect, improves the breakdown voltage of the device and suppresses the current collapse effect of the device; the introduction of the P-type gate 71 between the gate electrode 7 and the channel layer 5 is beneficial to the realization of the enhancement mode and improves the voltage resistance of the gate electrode 7, expands the dynamic range of the gate signal input and improves the long-term reliability of the device.

[0073] The material of the drain contact layer 4 is gallium nitride or AlGaN or InGaN, the thickness is 50nm-2μm, the doping impurity is Si and the doping concentration is 1x10 17 -1 x10 21 cm -3 -1 x10 20 cm -3 The material of the channel layer 5 is gallium nitride or AlGaN or InGaN, the thickness is 100nm-10μm, the doping impurity is Si and the doping concentration is 1x10 15 -1 x10 18 cm -3 -1 x10 17 cm -3 The height of the fin channel layer 51 is 40nm-5μm and the fin width is 10nm-1μm; the height of the fin channel layer 51 is 500nm and the fin width is 200nm. The doping impurity of the P-type gate 71 is Mg and the doping concentration is 1x10 15 -1x10 18 cm -3 -1x10 17 cm -3 The material of the source contact layer 6 is gallium nitride or AlGaN or InGaN, the thickness is 10nm-1μm, the doping impurity is Si and the doping concentration is 1x10 17 -1x10 21 cm -3 The material of the source contact layer is gallium nitride, the thickness can be 500nm, the doping impurity is Si and the doping concentration is 1x10 20cm -3 The height of the P-type gate 71 does not exceed the height of the fin channel layer 51.

[0074] Also provided is a method for manufacturing a vertical gallium nitride-based fin-type radio frequency junction field effect transistor, comprising:

[0075] A substrate layer 1 is selected. The material of the substrate layer is silicon. The chemical cleaning of the silicon substrate can be divided into the following steps: dirt removal, etching, cleaning, and drying.

[0076] A nucleation layer 2 is epitaxially grown on the substrate layer. The material of the nucleation layer is, for example, ALN. The chamber of the MOCVD is heated to 950 degrees Celsius. The substrate wafer is subjected to nitriding treatment at 950 degrees Celsius, so that the surface of the sapphire substrate AL2O3 forms ALN molecules, and the ALN nucleation layer is grown, so as to improve the quality of the epitaxial growth of GaN on the sapphire substrate.

[0077] A buffer layer 3 is epitaxially grown on the nucleation layer. The material of the buffer layer is ALN. By passing in NH3 and TMAL sources, a chemical reaction occurs on the surface of the substrate at high temperature to generate an ALN thin film.

[0078] A drain contact layer 4 is epitaxially grown on the buffer layer. A channel layer 5 is epitaxially grown on the drain contact layer. A source contact layer 6 is epitaxially grown on the channel layer 5. By using the MOCVD method, a thickness of 1 μm and a doping concentration of 1x10 20 cm -3 Si-doped gallium nitride is epitaxially grown on the drain contact layer as the drain contact layer. 17 cm -3 Si-doped gallium nitride is epitaxially grown on the channel layer as the channel layer. 20 cm -3 Si-doped gallium nitride is epitaxially grown on the channel layer as the source contact layer.

[0079] The source contact layer 6 and the channel layer 5 are etched to form a fin channel layer 51. In a plasma system, dry etching is performed based on Cl2 / BCl3. The etching starts from the source contact layer, and the channel layer is etched to a "convex" shape. In order to obtain a vertical and smooth channel sidewall, the device after dry etching needs to be treated by wet etching based on hot TMAH (for example, 85°C water bath heating for 1h). After the treatment, the mesa should have a straight edge and a steep sidewall. The photoresist is reserved for the next step.

[0080] P-GaN is regrown on part of the surface of the channel layer 5 to form a P-type gate 71; a Mg-doped gallium nitride with a thickness of 0.3 um and a doping concentration of 5x10 17 cm -3 is deposited on part of the channel layer as a P-type column of the channel layer.

[0081] The channel layer is etched to expose both ends of the drain contact layer. A photoresist is used as a mask to transfer a pattern to a photosensitive film layer on the semiconductor wafer by photolithography. Then, the channel layer is etched by ICP dry etching and TMAH wet etching to expose the drain contact layer to the surface to prepare a drain electrode.

[0082] A source electrode is prepared on the source contact layer, and a drain electrode is prepared above both ends of the drain contact layer. A photoresist is used as a mask to transfer a pattern to a photosensitive film layer on the semiconductor wafer by photolithography. Then, a source metal is deposited on the source electrode area (above the source contact layer) by electron beam evaporation or magnetron sputtering, and a drain metal is deposited on the drain electrode area (on both sides above the drain contact layer) by electron beam evaporation or magnetron sputtering.

[0083] A gate electrode 7 is prepared on the extended part of the P-type gate 71. A photoresist is used as a mask to transfer a pattern to a photosensitive film layer on the semiconductor wafer by photolithography. Then, a gate metal is deposited on the gate electrode area by electron beam evaporation or magnetron sputtering. Thus, the preparation of the vertical gallium nitride-based fin-type RF transistor is completed. The preparation method of the vertical gallium nitride-based fin-type RF transistor provided in this embodiment has simple manufacturing processes and relatively low process cost, and is compatible with existing processes.

[0084] Although embodiments of the present application have been shown and described, it is to be understood that various modifications, substitutions, replacements and changes can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A method for preparing a vertical gallium nitride-based fin-type radio frequency junction field effect transistor, the transistor comprising a substrate layer (1), a nucleation layer (2), a buffer layer (3), and a drain contact layer (4) stacked in sequence from bottom to top; a channel layer (5), arranged on the drain contact layer (4), and consisting of a non-fin channel layer (52) and a plurality of fin channel layers (51); a source contact layer (6), arranged on the fin channel layer (51); a P-type gate (71), The P-type gate (71) is provided on both sides of the fin channel layer (51) and on a portion of the surface of the non-fin channel layer (52); the gate electrode (7) is provided on the extension portion of the P-type gate (71) and forms an ohmic contact or a Schottky contact with the P-type gate (71); the drain electrode (8) is provided on the drain contact layer (4) and forms an ohmic contact with the drain contact layer (4); the source electrode (9) is provided on the source contact layer (6) and forms an ohmic contact with the source contact layer (6); wherein, The materials of the buffer layer (3) and the P-type gate (71) are group III nitride semiconductor materials; the material of the drain contact layer (4) is GaN, AlGaN or InGaN, with a thickness of 50nm to 2μm, and the doping impurity is Si with a doping concentration of 1×10 17 to 1×10 21 cm -3 The channel layer (5) is made of gallium nitride, AlGaN or InGaN, with a thickness of 100 nm to 10 μm, and is doped with Si at a doping concentration of 1×10 15 to 1×10 18 cm -3 The source contact layer (6) is made of GaN, AlGaN or InGaN, has a thickness of 10 nm to 1 μm, and is doped with Si at a doping concentration of 1×10 17 to 1×10 21 cm -3 , characterized in that the method comprises: S1, select the substrate layer (1); S2, epitaxially growing a nucleation layer (2), a buffer layer (3), a drain contact layer (4), a channel layer (5), and a source contact layer (6) in sequence on the substrate layer (1); S3, etching the channel layer (5) and the source contact layer (6) to form a fin channel layer (51); S4, regrowing P-GaN on a portion of the surface of the channel layer (5) to form a P-type gate (71); S5, etching the channel layer (5) to expose both ends of the drain contact layer (4); S6, preparing a source electrode (9) above the source contact layer (6), and preparing drain electrodes (8) at both ends of the drain contact layer (4); S7. Prepare a gate electrode (7) on the extended portion of the P-type gate (71).

2. The method for preparing a vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The material of the substrate layer (1) is silicon, sapphire or SiC, and the surface is chemically cleaned and used for epitaxial growth.

3. The method for preparing a vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The material of the nucleation layer (2) is AlN, and the epitaxial growth temperature is 950°C.

4. The method for preparing a vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, wherein: The height of the fin channel layer (51) is 40nm to 10μm, and the fin width is 10nm to 1μm.

5. The method for preparing a vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The doping impurity of the P-type gate (71) is Mg, and the doping concentration is 1×10 15 to 1×10 18 cm -3 , thickness is 5nm to 100nm, and height is 5nm to 1μm.

6. The method for preparing a vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The height of the P-type gate (71) does not exceed the height of the fin channel layer (51).

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