Semiconductor structure, semiconductor device and forming method thereof

Abstract

The semiconductor structure according to an embodiment of the present disclosure comprises: a substrate; a first source / drain feature and a second source / drain feature disposed over the substrate; and a plurality of nanostructures extending between the first source / drain feature and the second source / drain feature. Each of the first source / drain feature and the second source / drain feature includes a first epitaxial layer in contact with sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer. The first epitaxial layer includes a semiconductor material doped with carbon (C) and boron (B). The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures, semiconductor devices, and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling; reducing off-state current; and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the gate wraps the top and sidewalls of a semiconductor material "fin" extending from a substrate). A GAA transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, a GAA transistor can also be referred to as a gate-around transistor (SGT) or a multi-bridge channel (MBC) transistor. The channel region of the GAA transistor may be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures.

[0004] The GAA transistor can be manufactured using a gate-last process. When the source / drain components are formed, a dummy gate stack is formed over the channel region. After the source / drain components are formed, the dummy gate stack is removed and the channel layer in the channel region is released as a suspended channel member. A functional gate structure is then formed to wrap around each of the suspended channel members. The removal of the dummy gate stack and the release of the channel member require more than one etching step. Summary of the invention

[0005] Some embodiments of the present application provide a semiconductor structure, comprising: a substrate; a first source / drain component and a second source / drain component, arranged above the substrate; and a plurality of nanostructures extending between the first source / drain component and the second source / drain component, wherein each of the first source / drain component and the second source / drain component comprises a first epitaxial layer contacting sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer, wherein the first epitaxial layer comprises a semiconductor material doped with carbon (C) and boron (B).

[0006] Other embodiments of the present application provide a semiconductor device, comprising: a substrate including an n-type well; a source / drain component disposed above the n-type well; and a plurality of nanostructures extending from sidewalls of the source / drain component and contacting the sidewalls of the source / drain component, wherein the source / drain component comprises a first epitaxial layer contacting the sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer, wherein a portion of the first epitaxial layer is disposed on a top surface of a topmost one of the plurality of nanostructures and contacting the top surface of the topmost one of the plurality of nanostructures.

[0007] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a fin-shaped structure above a substrate, the fin-shaped structure comprising a plurality of channel layers interlaced by a plurality of sacrificial layers; forming a dummy gate stack above a channel region of the fin-shaped structure; forming a gate spacer layer along the sidewalls of the dummy gate stack; recessing a source / drain region of the fin-shaped structure to form a source / drain groove extending into the substrate and exposing a portion of the substrate; selectively depositing a first epitaxial layer on the sidewalls of the plurality of channel layers and the exposed portion of the substrate; depositing a second epitaxial layer above the first epitaxial layer; removing the dummy gate stack above the channel region of the fin-shaped structure; selectively removing the plurality of sacrificial layers in the channel region to release the plurality of channel layers as a plurality of channel components; and forming a gate structure to wrap each of the plurality of channel components, wherein the selective deposition comprises using a semiconductor source, a carbon source, and a boron source. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1A flow chart of a method for forming a semiconductor device according to one or more aspects of an embodiment of the present disclosure is shown.

[0010] Figures 2 to 16 The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 A partial cross-sectional view during the manufacturing process of the method.

[0011] Fig.17 One or more aspects of the present disclosure are shown. Fig.14 An enlarged partial cross-sectional view of the first epitaxial layer in FIG. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] In addition, when "about," "approximately," etc. are used to describe a value or a range of values, as understood by one of ordinary skill in the art, the terms are intended to encompass values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / - 15%.

[0015] As semiconductor devices continue to shrink, GAA transistors can replace FinFETs for smaller technology nodes to provide better electrostatic and short channel control. In the gate-after process for manufacturing GAA transistors, the pseudo gate stack (also known as the polysilicon gate stack) can be removed by an etchant containing ammonium hydroxide. Since the etchant leaks through the weak point between the gate spacer layer and the topmost channel component, this etchant may cause damage to the silicon channel component and the source / drain component. This leakage may cause damage to the p-type source / drain component, which may include silicon germanium. The p-type source / drain component may have a leakage path through the underlying bulk substrate. In addition, the p-type dopant in the p-type source / drain component may diffuse outward into the bulk substrate, thereby exacerbating the leakage.

[0016] The disclosed embodiment includes a process for depositing a protective epitaxial layer above the sidewall of the channel member and the top surface of the substrate below. In some embodiments, the protective epitaxial layer covers weak points and cracks and reduces leakage into the substrate. In some instances, the protective epitaxial layer may include a semiconductor material doped with carbon (C) and boron (B).

[0017] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 1 is a flow chart illustrating a method 100 for forming a semiconductor structure from a workpiece according to an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the disclosed embodiments to those explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2 to 17 Describing method 100, Figures 2 to 17 is based on Figure 1 1 and 1. A partial cross-sectional view of a workpiece 200 of an embodiment of the method 100 at different manufacturing stages. Because the workpiece 200 will be manufactured into a semiconductor structure or a semiconductor device, the workpiece 200 may be referred to herein as a semiconductor structure or a semiconductor device 200 as the context requires. To avoid, Figures 2 to 17 The X, Y and Z directions are perpendicular to each other. Throughout the embodiments of the present disclosure, the same reference numerals denote the same components unless otherwise explicitly described.

[0018] refer to Figure 1 and Figure 2 , the method 100 includes a block 102, in which a stack 204 of alternating semiconductor layers is formed above a workpiece 200. Figure 2As shown in , workpiece 200 includes substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various doping configurations depending on design requirements as known in the art. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, an n-type dopant for forming an n-type well may include phosphorus (P) or arsenic (As). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on substrate 202. In some embodiments, a p-type dopant for forming a p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn) or diamond. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Additionally, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained for enhanced performance, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0019] In some embodiments, stack 204 includes sacrificial layers 206 of a first semiconductor composition interleaved with channel layers 208 of a second semiconductor composition. In other words, channel layers 208 are interleaved with sacrificial layers 206. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, sacrificial layers 206 include silicon germanium (SiGe) and channel layers 208 include silicon (Si). It should be noted that four (4) layers of sacrificial layers 206 and three (3) layers of channel layers 208 are arranged alternately, as shown in FIG. Figure 2 , which is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It is understood that any number of epitaxial layers may be formed in stack 204. The number of layers depends on the desired number of channel components for semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10. Figure 2 In the embodiment shown in FIG. 2 , the stack 204 includes a bottommost sacrificial layer 206 and a topmost sacrificial layer 206. In an embodiment, the topmost sacrificial layer 206 is used to protect the topmost channel layer and can be completely removed in a subsequent process.

[0020] All sacrificial layers 206 may have a first thickness. In some instances, the first thickness may be between about 4nm and about 7nm. Channel layer 208 may have a second thickness greater than the first thickness. In some instances, the second thickness may be between about 8.5nm and about 10.5nm. The second thickness is greater because each of channel layer 208 may also be partially etched when the sacrificial layer is selectively removed to release the channel layer as a channel member. Although not explicitly shown in the figure, the topmost channel layer 208 may have a third thickness greater than the second thickness. In some instances, the third thickness may be between about 10.5nm and about 12nm. Because the topmost channel layer 208 is most likely to be damaged during the patterning process, the third greater thickness is in place to compensate for material loss during the process step.

[0021] The sacrificial layer 206 and the channel layer 208 in the stack 204 can be deposited using a molecular beam epitaxy (MBE) process, a vapor phase deposition (VPE) process, and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and the channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially free of dopants (i.e., have a dopant density of from about 0 atoms / cm 3 About 1×10 17 Atom / cm 3 extrinsic dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process for the stack 204. In some alternative embodiments, the sacrificial layer 206 may include silicon germanium (SiGe) and the channel layer 208 includes silicon (Si).

[0022] Still reference Figure 1 , Figure 2 and Figure 3 , the method 100 includes a block 104, in which a fin structure 212 is formed from a portion of the stack 204 and the substrate 202. To pattern the stack 204, a hard mask layer 210 ( Figure 2 ) to form an etching mask. The hard mask layer 210 may be a single layer or a multilayer. For example, the hard mask layer 210 may include a pad oxide layer and a pad nitride layer disposed above the pad oxide layer. The fin structure 212 may be patterned by the stack 204 and the substrate 202 using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. As Figure 3As shown in , the etching process in box 104 forms a trench that extends vertically through the stack 204 and a portion of the substrate 202. The trench defines a fin structure 212. In some embodiments, a double patterning or multiple patterning process can be used to define a fin structure having a pitch that is, for example, less than a pitch that can be obtained using a single, direct photolithography process. For example, in one embodiment, a material layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching the stack 204. As shown in FIG. Figure 3 As shown in FIG. 1 , the fin structure 212 including the sacrificial layer 206 and the channel layer 208 extends vertically along the Z direction and longitudinally along the X direction. Figure 3 As shown in FIG. 2 , the fin structure 212 includes a base fin structure 212B patterned by the substrate 202. The patterned stack 204 (including the sacrificial layer 206 and the channel layer 208) is disposed directly above the base fin structure 212B. The base fin structure 212B may also be referred to as a mesa 212B.

[0023] An isolation feature 214 is formed adjacent to the fin structure 212. Figure 3 In some embodiments shown in , the isolation feature 214 is disposed on the sidewalls of the base fin structure 212B. In some embodiments, the isolation feature 214 can be formed in a trench to isolate the fin structure 212 from an adjacent fin structure. The isolation feature 214 can also be referred to as a shallow trench isolation (STI) feature 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials. In various instances, the dielectric layer can be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form Figure 3 After recessing, the fin structure 212B rises above the STI feature 214 , while the base fin structure 212B is embedded or buried in the isolation feature 214 .

[0024] refer to Figure 1 , Figure 4 and Figure 5The method 100 includes a block 106 in which a dummy gate stack 220 is formed over the channel region 212C of the fin structure 212. In some embodiments, a gate replacement process (or a gate-last process) is used, in which the dummy gate stack 220 ( Figure 4 and Figure 5 ) is used as a reserved position to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 5 In some embodiments shown in , the dummy gate stack 220 is formed above the fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 5 As shown in FIG. 2 , the channel region 212C is disposed between two source / drain regions 212SD along the X direction.

[0025] Forming the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning the layers. Figure 4 , a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 may be blanket deposited over the workpiece 200. In some embodiments, the dummy dielectric layer 216 may be formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable process. In some instances, the dummy dielectric layer 216 may include silicon oxide. Thereafter, the dummy electrode layer 218 may be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable process. In some instances, the dummy electrode layer 218 may include polysilicon. For patterning purposes, the gate top hard mask layer 222 may be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable process. Then, the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 may be patterned to form a dummy gate stack 220, such as Figure 5 As shown in . For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 above the silicon oxide layer 223. As shown in Figure 5As shown in , the dummy gate stack 220 is patterned such that it is disposed only over the channel region 212C and not over the source / drain regions 212SD.

[0026] refer to Figure 1 and Figure 6 , the method 100 includes frame 108, in which a gate spacer layer 226 is deposited over the workpiece 200 (including over the dummy gate stack 220). In some embodiments, the gate spacer layer 226 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 220. The term "conformal" may be used herein to facilitate describing a layer having a substantially uniform thickness over various regions. The gate spacer layer 226 may be a single layer or a multilayer. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process. As Figure 6 As shown in , it has been observed that the gate spacer layer 226 may have a footing profile and not completely conformally cover the corner region between the dummy dielectric layer 216 and the topmost channel layer 208, leaving a void 219. The void 219 may not be filled at all by the gate spacer layer 226, or may be incompletely filled by the gate spacer layer 226. The presence of the void 219 weakens the etching resistance of the gate spacer layer 226 around the corner region.

[0027] refer to Figure 1 and Figure 7 , method 100 includes box 110, in which the source / drain region 212SD of the fin structure 212 is anisotropically recessed to form a source / drain trench 228. The anisotropic etching may include dry etching or a suitable etching process to etch the source / drain region 212SD and a portion of the substrate 202 located below the source / drain region 212SD. The resulting source / drain trench 228 extends vertically through the depth of the stack 204 and extends partially into the substrate 202. An exemplary dry etching process for box 110 may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. As Figure 7 As shown in , the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Figure 7In some embodiments shown in , the source / drain trenches 228 do not extend substantially below the stack 204 into the substrate 202. Fig.15 In some other embodiments shown in , the source / drain trench 228 extends through the stack 204 and partially extends into the substrate 202, and the source / drain trench 228 includes a bottom surface and lower sidewalls defined in the substrate 202. Figure 7 In some embodiments shown in , the voids 219 at the corner regions may be covered only by a thin layer of the gate spacer layer 226 .

[0028] refer to Figure 1 , Figure 8 and Fig. 9 , the method 100 includes block 112, in which an inner spacer feature 234 is formed. The operations in block 112 may include: selectively and partially removing the sacrificial layer 206 to form the inner spacer recess 230 ( Figure 8 ); depositing an inner spacer material (not explicitly shown) over the workpiece 200; and etching back the inner spacer material to form an inner spacer member 234 ( Fig. 9 ). Figure 8 , the sacrificial layer 206 exposed in the source / drain trench 228 is selectively and partially recessed to form an inner spacer recess 230, while the gate spacer layer 226, the exposed portion of the substrate 202, and the channel layer 208 are substantially not etched. Recessing to form the inner spacer recess 230 can further thin or weaken the gate spacer layer 226 covering the gap 219. In an embodiment where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), the selective recessing of the sacrificial layer 206 can be implemented using a selective wet etching process or a selective dry etching process. Exemplary selective dry etching processes can include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Exemplary selective wet etching processes can include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0029] After forming the internal spacer recess 230, an internal spacer material is deposited over the workpiece 200 (including over the internal spacer recess 230). The internal spacer material may include silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbon nitride, or a low-k dielectric material. Although not explicitly shown, the internal spacer material may be a single layer or multiple layers. In one embodiment, the internal spacer material includes silicon oxycarbonitride. In some embodiments, the internal spacer material can be deposited using CVD, PECVD, SACVD, ALD, or other suitable methods. The internal spacer material is deposited into the internal spacer recess 230 and over the sidewalls of the channel layer 208 exposed in the source / drain trench 228. Reference Fig. 9 , and then etch back the deposited internal spacer material to remove the internal spacer material from the sidewalls of the channel layer 208 to form the internal spacer feature 234 in the internal spacer recess 230. In block 112, the internal spacer material may also be removed from the top surface and / or sidewalls of the gate top hard mask layer 222 and the gate spacer layer 226. In some embodiments, the etch back operation performed in block 112 may include using hydrogen fluoride (HF), fluorine gas (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. Fig. 9 As shown in FIG. 2 , each of the inner spacer members 234 is in direct contact with the recessed sacrificial layer 206 and is disposed vertically (along the Z direction) between two adjacent channel layers 208 .

[0030] Although not explicitly shown, prior to forming any of the epitaxial layers, method 100 may include a cleaning process to clean the surface of workpiece 200. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some instances, wet cleaning may include using Standard Clean 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2)), Standard Clean 2 (RCA SC-2, a mixture of DI water, hydrochloric acid (HCl), and hydrogen peroxide (H2O2)), SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. The dry cleaning process may include helium (He) and hydrogen (H2) treatment. The hydrogen treatment may convert silicon on the surface into silane (SiH4), which may be extracted for removal.

[0031] refer to Fig. 9 The etch-back and cleaning process of the inner spacer material can remove the gate spacer layer 226 covering the gap 219 and form a crack 229 at the interface between the gate spacer layer 226 and the topmost channel layer 208. Fig. 9In some embodiments shown in , the crack 229 can be defined by the bottom surface of the gate spacer layer 226, the sidewalls of the dummy dielectric layer 216, and the top surface of the topmost channel layer 208. The crack 229 reduces the structural integrity of the dielectric layer around the dummy gate stack 220 (including the gate spacer layer 226 and the dummy dielectric layer 216) and becomes a weak point.

[0032] refer to Figure 1 and Fig.10 , the method 100 includes block 114, in which a first epitaxial layer 236 is selectively deposited over the exposed sidewalls of the channel layer 208 and the exposed surface of the substrate 202. Fig.10 In some embodiments shown in , the first epitaxial layer 236 can be deposited using a growth-etch deposition process or a cyclic deposition process. As the name implies, the growth-etch deposition process includes a growth component (or growth cycle) and an etching component (or etching cycle). The growth component (or growth cycle) selectively deposits the first epitaxial layer 236 mainly on the semiconductor surface, and the etching component (or etching cycle) removes the first epitaxial layer 236 deposited on the non-semiconductor surface. Fig.16 In some alternative embodiments shown in , the first epitaxial layer 236 can be deposited using a straight-up epitaxial deposition process without any etching components. Although more of the first epitaxial layer 236 is deposited on the semiconductor surface, some can also be deposited on the dielectric surface. Thus, a thin first epitaxial layer 2364 can be deposited over the sidewalls of the inner spacer features 234, such as Fig.16 As shown in Fig.10 and Fig.16 As shown in FIG. 2 , the filler portion 238 of the first epitaxial layer 236 may fill the crack 229 ( Fig. 9 ), and directly contacts the bottom surface of the gate spacer layer 226, the sidewalls of the dummy dielectric layer 216, and the top surface of the topmost channel layer 208. The first epitaxial layer 236 also includes a bottom portion 236B disposed on the substrate 202 exposed in the source / drain region 212SD.

[0033] According to an embodiment of the present disclosure, the material for the first epitaxial layer 236 is selected based on at least three criteria. First, it must include a semiconductor material that can be satisfactorily deposited above the surface of the channel layer 208. Second, it must be more etch-resistant than the second epitaxial layer 240 during the removal of the dummy gate stack 220. Third, the first epitaxial layer 236 should be able to prevent or reduce the dopant in the subsequently deposited second epitaxial layer 240 from diffusing outward into the substrate fin 212B (i.e., the mesa 212B) to reduce leakage. When the second epitaxial layer 240 is a p-type source / drain component including silicon germanium (SiGe) doped with a p-type dopant such as boron (B), the first epitaxial layer 236 may include silicon (Si), silicon germanium (SiGe), or germanium (Ge) doped with boron (B) and carbon (C). In some embodiments, the first epitaxial layer 236 includes silicon (Si) doped with carbon (C) and boron (B), silicon germanium (SiGe) doped with carbon (C) and boron (B), or germanium (Ge) doped with carbon (C) and boron (B). That is, the first epitaxial layer 236 may include SiCB (Si:CB), SiGeCB (SiGe:CB), or GeCB (Ge:CB). Boron (B) dopant is used to make the first epitaxial layer 236 more etch-resistant than the second epitaxial layer 240. In order to prevent boron (B) from diffusing outward, carbon (C) dopant is added to capture the boron (B) dopant and prevent excessive boron from diffusing out of the semiconductor material matrix of the first epitaxial layer 236. In one embodiment, the first epitaxial layer 236 includes carbon and boron doped silicon, wherein silicon (Si) is more etch-resistant than silicon germanium (SiGe), and carbon (C) slows down the outward diffusion of boron (B). In some embodiments, the carbon doping concentration in the first epitaxial layer 236 can be about 1E19 cm -3 and about 1E21 cm -3 ) (i.e., about 0.02% to about 2%), and the boron doping concentration in the first epitaxial layer 236 may be about 5E20 cm -3 and about 1E22 cm -3 Since the first epitaxial layer 236 plays a protective and leakage barrier function, it may also be referred to as a protective epitaxial layer, a barrier epitaxial layer, or a semiconductor liner.

[0034] When the first epitaxial layer 236 includes silicon (Si), it can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), VPE, or MBE using dichlorosilane (DCS, SiCl2H2) as a silicon source. When the first epitaxial layer 236 includes silicon germanium (SiGe), it can be deposited using dichlorosilane (DCS, SiCl2H2) as a silicon source and germanium (GeH4) as a germanium source. When the first epitaxial layer 236 includes germanium (Ge), it can be deposited using germanium (GeH4) as a germanium source. Dopants including carbon (C) and boron (B) can be in-situ doped using methylmethylenesilane (MMS) as a carbon (C) source and diborane (B2H6) as a boron (B) source. When a growth-etch process is employed, the growth component (or growth cycle) may include using dichlorosilane or germane as silicon and germanium sources, and the etching component (or growth cycle) may include using hydrogen chloride (HCl) as an etchant and hydrogen (H2) as a carrier gas.

[0035] Fig.17 Shows Fig.10 Magnified view of the dashed area in . Fig.17 As shown in , along the gate length direction (or Y direction), the first epitaxial layer 236 along the sidewall of the channel layer 208 may exhibit facet growth. Fig.17 In some embodiments shown in , the first epitaxial layer 236 grown from the sidewall of the channel layer 208 may have a pentagonal shape or a diamond shape. Each of the pentagonal shapes may have a first thickness T1 measured from the sidewall of the channel layer 208 and a second thickness T2 measured as the thickest part of the pentagonal shape along the Z direction. In some instances, the first thickness T1 may be between about 5nm and about 10nm, and the second thickness T2 may be between about 8nm and about 16nm. The filler portion 238 of the first epitaxial layer may have a third thickness T3 along the Z direction. The third thickness T3 may be between about 0.1nm and about 10nm. The thickness range of the first epitaxial layer 236 is not insignificant. For example, when the first thickness T1 is less than 5nm, the first epitaxial layer 236 may not provide sufficient protection for the second epitaxial layer 240. When the first thickness T1 is greater than 10nm, the first epitaxial layer 236 of less conductivity may excessively increase the contact resistance. Each of the pentagonal shapes of the first epitaxial layer 236 includes an angle α between a departure edge and a sidewall of the channel layer 208, an angle β between a departure edge and an extension edge of the pentagonal shape, and an angle γ between two extension edges of the pentagonal shape. In some examples, the angle α may be between about 100° and about 130°, the angle β may be between about 90° and about 130°, and the angle γ may be between about 80° and about 160°.

[0036] Various properties of the first epitaxial layer 236 are observable or measurable. For example, the carbon doping concentration, boron doping concentration, or composition of the first epitaxial layer 236 can be measured using a secondary ion mass spectrometer (SIMS) or an energy dispersive X-ray spectrometer (EDX). The thickness and angle of the diamond shape of the first epitaxial layer 236 can be observed using a transmission electron microscope (TEM).

[0037] refer to Figure 1 and Fig.11 , the method 100 includes a block 116, wherein a second epitaxial layer 240 is deposited over the surface of the first epitaxial layer 236 and the inner spacer member 234. In some embodiments, the deposition of the second epitaxial layer 240 is performed in situ in the same process chamber because there are fewer dopant contamination issues. In some embodiments, the second epitaxial layer 240 can be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The second epitaxial layer 240 is a heavily doped semiconductor layer to reduce contact resistance. Fig.11 As shown in , the second epitaxial layer 240 can be deposited on the surface of the first epitaxial layer 236. In some embodiments, although the second epitaxial layer 240 merges above the gap of the first epitaxial layer 236, a gap 241 can be formed between two adjacent diamond shapes. In some embodiments, the second epitaxial layer 240 includes silicon germanium (SiGe) and is doped with a p-type dopant, such as boron (B). The boron (B) doping concentration in the second epitaxial layer 240 can be about 5E19 cm -3 and about 1E20 cm -3 Between. Depending on the deposition conditions, the second epitaxial layer 240 can be crystalline or amorphous. When crystalline, the second epitaxial layer 240 can apply strain on the channel layer 208 to increase carrier mobility. When amorphous, the second epitaxial layer 240 can apply little or no strain on the channel layer 208. The crystallinity of the second epitaxial layer 240 can be detected using X-ray diffraction (XRD) or reciprocal space mapping (RSM) techniques. The first epitaxial layer 236 and the second epitaxial layer 240 in the source / drain region 212SD can be collectively referred to as a source / drain component 242. In the depicted embodiment, the source / drain component 242 is a p-type source / drain component.

[0038] refer to Figure 1 and Figure 12 to Figure 14 , the method 100 includes block 118, where the dummy gate stack 220 is replaced with a gate structure 250. Block 118 may include depositing a contact etch stop layer (CESL) 244 ( Fig.12 ); an interlayer dielectric (ILD) layer 246 is deposited over the CESL 244 ( Fig.12 ); removing the dummy gate stack 220 ( Fig.13 ); selectively removing the sacrificial layer 206 in the channel region 212C to release the channel layer 208 as a channel member 2080 ( Fig.13 ); and forming a gate structure 250 to wrap each of the channel members 2080 ( Fig.14 ). Fig.12 , CESL 244 is deposited over the workpiece 200, including over the source / drain features 242 and along the sidewalls of the gate spacer layer 226. CESL 244 may include silicon nitride. Then, an ILD layer 246 is deposited over the CESL 244. In some embodiments, the ILD layer 246 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 246 may be deposited using CVD, FCVD, spin coating, or a suitable deposition technique. CESL may include silicon nitride. After depositing the ILD layer 246, the workpiece 200 may be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. Exposing the dummy gate stack 220 allows the dummy gate stack 220 to be removed.

[0039] refer to Fig.13 , remove the dummy gate stack 220. Removing the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220. For example, removing the dummy gate stack 220 may be performed using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 220. After removing the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed. Still referring to Fig.13 After removing the dummy gate stack 220, the sacrificial layer 206 between the channel layers 208 in the channel region 212C is selectively removed. The selective removal of the sacrificial layer 206 releases the channel layers 208 ( Fig.12 ), to form Fig.13. The sacrificial layer 206 is selectively removed to form a gate trench 248, which includes a space between adjacent channel members 2080. The selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). Still referring to Fig.13 The filler portion 238 of the first epitaxial layer 236 is plugged in the crack 229 to prevent an etchant, such as ammonium hydroxide (NH 4 OH), from overflowing through a weak point at the crack 229 to damage the second epitaxial layer 240 .

[0040] refer to Fig.14 , after releasing the channel member 2080, a gate structure 250 is formed to wrap each of the channel member 2080. The gate structure 250 includes a gate dielectric layer 252 and a gate electrode 254 above the gate dielectric layer 252. Although not explicitly shown, the gate dielectric layer 252 includes an interface layer intersecting the channel member 2080 and the mesa 212B and a high-k dielectric layer above the interface layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD) and / or other suitable methods. The high-k dielectric layer may include hafnium oxide. Alternatively, the high-k dielectric layer may include other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-k dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0041] The gate electrode 254 may include a single layer or optionally a multilayer structure, such as various combinations of a work function metal layer, a liner layer, a wetting layer, an adhesion layer, a metal filling layer, or a metal silicide. For example, the gate electrode 254 may include a p-type work function metal layer, such as titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), or nickel silicide (NiSi2). The gate electrode 254 may also include a metal filling layer, such as tungsten (W). In various embodiments, the gate electrode 254 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a substantially flat top surface of the gate structure 250. The gate structure 250 includes a portion between the channel members 2080 in the channel region 212C. In the depicted embodiment, Fig.14 The semiconductor device 200 shown in FIG. 2 is a p-type GAA transistor. In these embodiments, the source / drain feature 242 includes boron-doped silicon germanium (SiGe:B), the gate structure 250 includes a p-type work function metal, and the channel member 2080 and the source / drain feature 242 are disposed above the n-type well 202N.

[0042] Figure 15 to Figure 16 An optional embodiment of the present disclosure is shown. Fig.15 . The source / drain trenches 228 extending into the substrate 202 are formed during the operation in block 110. Therefore, the first epitaxial layer 236 deposited in block 114 may include a curved bottom portion 2362B extending into the substrate 202. Then refer to Fig.16 When the deposition of the first epitaxial layer 236 in block 114 is performed at a lower temperature, the deposition may become less selective and a thin first epitaxial layer 2364 may be deposited over the sidewalls of the inner spacer features 234. The thin first epitaxial layer 2364 has a much smaller Fig.17 Although the low temperature deposition of the first epitaxial layer 236 may affect the quality of the first epitaxial layer 236, the presence of the thin first epitaxial layer 2364 may facilitate the deposition of the second epitaxial layer 240 over the inner spacer member 234, thereby preventing the formation of Fig.14 The gap 241 shown in FIG.

[0043] In one exemplary aspect, the disclosed embodiments relate to a semiconductor structure. The semiconductor structure includes: a substrate; a first source / drain component and a second source / drain component disposed above the substrate; and a plurality of nanostructures extending between the first source / drain component and the second source / drain component. Each of the first source / drain component and the second source / drain component includes a first epitaxial layer in contact with a sidewall of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer. The first epitaxial layer includes a semiconductor material doped with carbon (C) and boron (B).

[0044] In some embodiments, the semiconductor material includes silicon (Si), silicon germanium (SiGe), or germanium (Ge). In some embodiments, the first source / drain component and the second source / drain component include silicon germanium (SiGe) doped with boron (B). In some embodiments, the semiconductor structure further includes: a gate structure encapsulating each of the plurality of nanostructures; and a gate spacer layer disposed along a sidewall of a portion of the gate structure extending above the plurality of nanostructures. A portion of the first epitaxial layer extends between a top surface of a topmost nanostructure of the plurality of nanostructures and a top surface of the gate spacer layer. In some embodiments, a portion of the first epitaxial layer includes a thickness between about 0.1 nm and about 1 nm. In some embodiments, a carbon (C) doping concentration in the first epitaxial layer is about 1E19 cm -3 and about 1E21 cm -3 In some embodiments, the boron (B) doping concentration in the first epitaxial layer is about 5E20 cm -3 and about 1E22cm -3 In some examples, the semiconductor structure further includes: a plurality of internal spacer features interlaced with the plurality of nanostructures. Portions of the first epitaxial layer extend over sidewalls of the plurality of internal spacer features.

[0045] In another exemplary aspect, the disclosed embodiments relate to a semiconductor device. The semiconductor device includes: a substrate having an n-type well; a source / drain component disposed above the n-type well; and a plurality of nanostructures extending from and contacting the sidewalls of the source / drain component. The source / drain component includes a first epitaxial layer in contact with the sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer. A portion of the first epitaxial layer is disposed on a top surface of a topmost one of the plurality of nanostructures and in contact with a top surface of a topmost one of the plurality of nanostructures.

[0046] In some embodiments, the first epitaxial layer includes a semiconductor material doped with carbon (C) and boron (B). In some embodiments, the carbon (C) doping concentration in the first epitaxial layer is about 1E19 cm -3 and about 1E21 cm-3 and the boron (B) doping concentration in the first epitaxial layer is about 5E20 cm -3 and about 1E22 cm -3 In some embodiments, the semiconductor material includes silicon (Si), silicon germanium (SiGe) or germanium (Ge). In some instances, the source / drain component includes silicon germanium (SiGe) doped with boron (B). In some embodiments, the semiconductor device further includes: a gate structure encapsulating each of the plurality of nanostructures. A portion of the gate structure is disposed above and in contact with a portion of the first epitaxial layer. In some embodiments, the semiconductor device further includes: a gate spacer disposed along a sidewall of the gate structure. A portion is sandwiched between a top surface of a topmost one of the plurality of nanostructures and a bottom surface of the gate spacer.

[0047] In another exemplary aspect, the disclosed embodiments relate to a method. The method includes: forming a fin-shaped structure above a substrate, the fin-shaped structure having multiple channel layers interleaved by multiple sacrificial layers; forming a dummy gate stack above a channel region of the fin-shaped structure; forming a gate spacer layer along the sidewalls of the dummy gate stack; recessing the source / drain region of the fin-shaped structure to form a source / drain groove extending into the substrate and exposing a portion of the substrate; selectively depositing a first epitaxial layer on the sidewalls of the multiple channel layers and the exposed portion of the substrate; depositing a second epitaxial layer above the first epitaxial layer; removing the dummy gate stack above the channel region of the fin-shaped structure; selectively removing multiple sacrificial layers in the channel region to release multiple channel layers as multiple channel components; and forming a gate structure to wrap each of the multiple channel components. The selective deposition includes using a semiconductor source, a carbon source, and a boron source.

[0048] In some embodiments, the semiconductor source includes dichlorosilane or germane, the carbon source includes methylmethylenesilane, and the boron source includes diborane. In some embodiments, removing the dummy gate stack forms a crack between a top surface of a topmost one of the plurality of channel layers and the gate spacer layer. In some embodiments, the first epitaxial layer includes silicon (Si) doped with carbon (C) and boron (B). In some instances, removing the dummy gate stack includes using ammonium hydroxide.

[0049] Some embodiments of the present application provide a semiconductor structure, comprising: a substrate; a first source / drain component and a second source / drain component, arranged above the substrate; and a plurality of nanostructures extending between the first source / drain component and the second source / drain component, wherein each of the first source / drain component and the second source / drain component comprises a first epitaxial layer contacting sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer, wherein the first epitaxial layer comprises a semiconductor material doped with carbon (C) and boron (B).

[0050] In some embodiments, the semiconductor material includes silicon (Si), silicon germanium (SiGe), or germanium (Ge). In some embodiments, the first source / drain component and the second source / drain component include silicon germanium (SiGe) doped with boron (B). In some embodiments, the semiconductor structure further includes: a gate structure encapsulating each of the plurality of nanostructures; and a gate spacer layer disposed along a sidewall of a portion of the gate structure extending above the plurality of nanostructures, wherein a portion of the first epitaxial layer extends between a top surface of a topmost nanostructure of the plurality of nanostructures and a top surface of the gate spacer layer. In some embodiments, the portion of the first epitaxial layer includes a thickness between about 0.1 nm and about 1 nm. In some embodiments, the carbon (C) doping concentration in the first epitaxial layer is about 1E19 cm -3 and about 1E21 cm -3 In some embodiments, the boron (B) doping concentration in the first epitaxial layer is about 5E20 cm -3 and about 1E22cm -3 In some embodiments, the semiconductor structure further comprises: a plurality of internal spacer features interlaced with the plurality of nanostructures, wherein portions of the first epitaxial layer extend over sidewalls of the plurality of internal spacer features.

[0051] Other embodiments of the present application provide a semiconductor device, comprising: a substrate including an n-type well; a source / drain component disposed above the n-type well; and a plurality of nanostructures extending from sidewalls of the source / drain component and contacting the sidewalls of the source / drain component, wherein the source / drain component comprises a first epitaxial layer contacting the sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer, wherein a portion of the first epitaxial layer is disposed on a top surface of a topmost one of the plurality of nanostructures and contacting the top surface of the topmost one of the plurality of nanostructures.

[0052] In some embodiments, the first epitaxial layer includes a semiconductor material doped with carbon (C) and boron (B). In some embodiments, the carbon (C) doping concentration in the first epitaxial layer is about 1E19 cm -3 and about 1E21 cm -3 wherein the boron (B) doping concentration in the first epitaxial layer is about 5E20 cm -3 and about 1E22 cm -3 In some embodiments, the semiconductor material comprises silicon (Si), silicon germanium (SiGe) or germanium (Ge). In some embodiments, the source / drain component comprises silicon germanium (SiGe) doped with boron (B). In some embodiments, the semiconductor device further comprises: a gate structure encapsulating each of the plurality of nanostructures, wherein a portion of the gate structure is disposed above and in contact with the portion of the first epitaxial layer. In some embodiments, the semiconductor device further comprises: a gate spacer disposed along a sidewall of the gate structure, wherein the portion is sandwiched between the top surface of the topmost one of the plurality of nanostructures and a bottom surface of the gate spacer.

[0053] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a fin-shaped structure above a substrate, the fin-shaped structure comprising a plurality of channel layers interlaced by a plurality of sacrificial layers; forming a dummy gate stack above a channel region of the fin-shaped structure; forming a gate spacer layer along the sidewalls of the dummy gate stack; recessing a source / drain region of the fin-shaped structure to form a source / drain groove extending into the substrate and exposing a portion of the substrate; selectively depositing a first epitaxial layer on the sidewalls of the plurality of channel layers and the exposed portion of the substrate; depositing a second epitaxial layer above the first epitaxial layer; removing the dummy gate stack above the channel region of the fin-shaped structure; selectively removing the plurality of sacrificial layers in the channel region to release the plurality of channel layers as a plurality of channel components; and forming a gate structure to wrap each of the plurality of channel components, wherein the selective deposition comprises using a semiconductor source, a carbon source, and a boron source.

[0054] In some embodiments, the semiconductor source comprises dichlorosilane or germane, wherein the carbon source comprises methylmethylenesilane, and wherein the boron source comprises diborane. In some embodiments, removing the dummy gate stack forms a crack between a top surface of a topmost one of the plurality of channel layers and the gate spacer layer. In some embodiments, the first epitaxial layer comprises silicon doped with carbon (C) and boron (B). In some embodiments, removing the dummy gate stack comprises using ammonium hydroxide.

[0055] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor structure comprising: substrate; a first source / drain feature and a second source / drain feature disposed above the substrate; as well as a plurality of nanostructures extending between the first source / drain feature and the second source / drain feature, wherein each of the first source / drain feature and the second source / drain feature comprises a first epitaxial layer in contact with sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer, Wherein, the first epitaxial layer includes a semiconductor material doped with carbon (C) and boron (B).

2. The semiconductor structure according to claim 1, wherein: The semiconductor material includes silicon (Si), silicon germanium (SiGe) or germanium (Ge).

3. The semiconductor structure according to claim 1, wherein: The first source / drain feature and the second source / drain feature include silicon germanium (SiGe) doped with boron (B).

4. The semiconductor structure according to claim 1, further comprising: a gate structure encapsulating each of the plurality of nanostructures; as well as a gate spacer layer disposed along sidewalls of a portion of the gate structure extending over the plurality of nanostructures, Wherein a portion of the first epitaxial layer extends between a top surface of a topmost nanostructure of the plurality of nanostructures and a top surface of the gate spacer layer.

5. The semiconductor structure according to claim 4, wherein: The portion of the first epitaxial layer includes a thickness between about 0.1 nm and about 1 nm.

6. The semiconductor structure according to claim 1, wherein: The carbon (C) doping concentration in the first epitaxial layer is about 1E19 cm -3 and about 1E21 cm -3 between.

7. The semiconductor structure according to claim 1, wherein: The boron (B) doping concentration in the first epitaxial layer is about 5E20 cm -3 and about 1E22 cm -3 between.

8. The semiconductor structure according to claim 1, further comprising: a plurality of internal spacer members interlaced with the plurality of nanostructures, Wherein a portion of the first epitaxial layer extends over sidewalls of the plurality of inner spacer features.

9. A semiconductor device comprising: a substrate including an n-type well; a source / drain component disposed above the n-type well; as well as a plurality of nanostructures extending from and contacting sidewalls of the source / drain feature, wherein the source / drain component comprises a first epitaxial layer in contact with sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer, Part of the first epitaxial layer is disposed on a top surface of a topmost one of the plurality of nanostructures and contacts a top surface of the topmost one of the plurality of nanostructures.

10. A method of forming a semiconductor device, comprising: forming a fin structure over a substrate, the fin structure comprising a plurality of channel layers interleaved by a plurality of sacrificial layers; forming a dummy gate stack above the channel region of the fin structure; forming a gate spacer layer along sidewalls of the dummy gate stack; recessing a source / drain region of the fin structure to form a source / drain recess extending into the substrate and exposing a portion of the substrate; selectively depositing a first epitaxial layer on sidewalls of the plurality of channel layers and the exposed portion of the substrate; depositing a second epitaxial layer over the first epitaxial layer; removing the dummy gate stack above the channel region of the fin structure; selectively removing the plurality of sacrificial layers in the channel region to release the plurality of channel layers as a plurality of channel members; as well as forming a gate structure to wrap each of the plurality of channel members, Wherein, the selective deposition includes using a semiconductor source, a carbon source and a boron source.

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