Semiconductor device and preparation method thereof, chip, and electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, a chip, and an electronic device, which relate to the field of semiconductor technology and solve the problem that in a trench-type semiconductor device, a current tunneling effect is prone to occur at the bottom of the trench, causing device failure. The semiconductor device includes a substrate, a modified layer, a gate dielectric layer, a gate, a source electrode, and a drain electrode. The substrate includes a first surface and a second surface arranged opposite to each other in the thickness direction thereof, and the first surface is provided with a groove. The modified layer is arranged on the bottom surface of the groove. The gate dielectric layer is arranged on a side of the modified layer away from the second surface, and on the sidewall surface of the groove. The gate is arranged in the groove and is covered by the gate dielectric layer. The source electrode and the drain electrode are respectively arranged on opposite sides of the substrate in the thickness direction thereof. Among them, the thickness of the gate dielectric layer arranged on the modified layer is greater than the thickness of the gate dielectric layer arranged on the sidewall surface of the groove.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] With the continuous development of modern electronic technology, higher requirements are placed on semiconductor materials, especially in the fields of high voltage, high frequency, high power, high temperature and radiation resistance. Wide bandgap semiconductor materials, such as silicon carbide (SiC), have become ideal materials for the preparation of power electronic devices due to their excellent performance. Silicon carbide has the advantages of wide bandgap, high critical breakdown field strength, high saturated electron mobility, high melting point and high thermal conductivity, which can meet the needs of high-performance power electronic devices.

[0003] Among silicon carbide power devices, silicon carbide metal oxide semiconductor field-effect transistors (MOSFET) are widely used in high-frequency and high-voltage power electronic devices due to their advantages such as fast switching speed, high voltage resistance, and low power consumption. The structures of silicon carbide MOSFET include planar and trench types. Trench silicon carbide MOSFET adopts a vertical channel design. Compared with the planar type, the trench type device has higher electron mobility, can achieve lower on-resistance, and has excellent high temperature performance and better stability. Based on these advantages, trench silicon carbide MOSFET shows broad application prospects.

[0004] However, in trench MOSFET, current tunneling effect is easy to occur at the bottom of the trench, causing device failure. Therefore, an improved semiconductor device is expected to solve the above problems. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device, aiming to solve the problem that in a trench-type semiconductor device, a current tunneling effect is prone to occur at the bottom of the trench, causing device failure.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a semiconductor device is provided, comprising a substrate, a modified layer, a gate dielectric layer, a gate, a source and a drain. The substrate comprises a first surface and a second surface arranged opposite to each other in the thickness direction thereof, and the first surface is provided with a groove. The modified layer is arranged on the bottom surface of the groove. The gate dielectric layer is arranged on the side of the modified layer away from the second surface, and on the sidewall surface of the groove. The gate is arranged in the groove and is covered by the gate dielectric layer. The source and the drain are respectively arranged on opposite sides of the substrate in the thickness direction thereof. The thickness of the gate dielectric layer arranged on the modified layer is greater than the thickness of the gate dielectric layer arranged on the sidewall surface of the groove.

[0008] In the above semiconductor device, by providing a modified layer at the bottom of the groove, the thickness of the gate dielectric layer provided on the modified layer is greater than the thickness of the gate dielectric layer provided on the side wall surface of the groove, and the breakdown strength of the gate dielectric layer provided on the modified layer can be improved, so that the semiconductor device can operate at a higher voltage without the gate dielectric layer being broken down, thereby improving the breakdown voltage of the semiconductor device and significantly improving the long-term reliability of the semiconductor device. At the same time, in working environments such as high frequency, high current, and high temperature, the improvement of the breakdown strength can effectively reduce the hot carrier injection effect, thereby extending the service life of the semiconductor device.

[0009] Moreover, the thickness of the gate dielectric layer disposed on the modified layer is greater than the thickness of the gate dielectric layer disposed on the side wall surface of the groove, which means that when the thickness of the gate dielectric layer at the bottom of the groove meets the actual application requirements, the thickness of the gate dielectric layer disposed on the side wall surface of the groove in the semiconductor device is smaller, which can reduce the threshold voltage of the semiconductor device, thereby reducing the power consumption of the semiconductor device and improving its switching efficiency.

[0010] The material of the modified layer 120 includes polysilicon, and part of the electric field formed by the gate 140 cannot penetrate the polysilicon used as a conductive material, thereby achieving an electric field shielding effect to a certain extent.

[0011] In a feasible embodiment, the material of the modified layer includes polysilicon.

[0012] When the material of the substrate includes silicon carbide, the deposition rate of the gate dielectric layer on the polysilicon surface is greater than the deposition rate of the gate dielectric layer on the silicon carbide surface, so that the thickness of the gate dielectric layer disposed on the modified layer is greater than the thickness of the gate dielectric layer disposed on the side wall surface of the groove.

[0013] In a feasible embodiment, the material of the substrate includes silicon carbide.

[0014] Since the deposition rate of the gate dielectric layer on the surface of the modified layer including polycrystalline silicon is greater than the deposition rate on the side wall surface of the groove including silicon carbide, under the same deposition time, the thickness of the gate dielectric layer disposed on the modified layer is greater than the thickness of the gate dielectric layer disposed on the side wall surface of the groove.

[0015] In a feasible embodiment, the semiconductor device also includes: an ion implantation region located in the substrate; the surface of the ion implantation region includes at least a portion of the side wall surface of the groove; the deposition rate of the gate dielectric layer on the surface of the ion implantation region is less than the deposition rate of the gate dielectric layer on the surface of the modified layer.

[0016] By performing ion implantation on the side wall surface of the groove to form an ion implantation area, it is ensured that the deposition rate of the gate dielectric layer on the surface of the ion implantation area including silicon oxide is lower than the deposition rate of the gate dielectric layer on the surface of the modified layer including polysilicon, thereby making the thickness of the gate dielectric layer on the modified layer greater than the thickness of the gate dielectric layer on the side wall surface of the groove.

[0017] Furthermore, since the deposition rate of the gate dielectric layer on the surface of the ion implantation region including silicon oxide is lower than the deposition rate on the surface of the region of the substrate including silicon carbide where ion implantation is not performed, compared with directly depositing the gate dielectric layer on the sidewall of the trench of the substrate material, the deposition rate of the gate dielectric layer on the sidewall surface of the groove can be further reduced, thereby making the thickness of the gate dielectric layer disposed on the surface of the ion implantation region smaller, that is, under the premise that the thickness of the gate dielectric layer on the sidewall of the groove is constant, the thickness of the gate dielectric layer on the modified layer can be obtained to be thicker, that is, the semiconductor device has a greater breakdown strength and a lower threshold voltage.

[0018] In a feasible embodiment, the ion implantation region includes oxygen ions.

[0019] In a feasible embodiment, the groove includes a first sub-groove and a second sub-groove; the opening of the first sub-groove is located on the first surface; the second sub-groove is located on the side of the first sub-groove away from the first surface, the second sub-groove is connected to the first sub-groove, and the opening size of the second sub-groove is smaller than the opening size of the first sub-groove; the modified layer is at least arranged on the bottom surface of the second sub-groove.

[0020] In the semiconductor device, the first sub-groove and the second sub-groove with different opening sizes form a groove with a step structure, which in turn makes the gate dielectric layer formed in the groove also have a step structure, which can effectively adjust the electric field distribution and reduce the electric field concentration, thereby improving the breakdown voltage of the semiconductor device. At the same time, the gate can also control the channel current more evenly, avoid the short channel effect and threshold voltage fluctuation caused by uneven electric field distribution, and improve the device performance and stability of the semiconductor device.

[0021] In a feasible embodiment, the modified layer is also provided on the side wall surface of the second sub-groove.

[0022] The modified layer is arranged on the bottom surface and side wall surface of the second sub-groove. Since the gate dielectric layer arranged on the modified layer is thicker, the gate dielectric layer located in the second sub-groove is thicker. Combined with the gate dielectric layer with a step structure, it can effectively adjust the electric field distribution and reduce the electric field concentration, thereby improving the breakdown voltage of the semiconductor device.

[0023] In a feasible embodiment, the surface of the ion implantation region includes a side wall surface of the first sub-recess.

[0024] In a feasible embodiment, the surface of the ion implantation region also includes the bottom surface of the first sub-groove.

[0025] The surface of the ion implantation region includes the sidewalls and bottom of the first sub-recess. Setting the ion implantation region in this way can make the gate dielectric layer arranged on the sidewalls and bottom of the first sub-recess have better thickness uniformity, thereby improving its electric field distribution.

[0026] In a feasible embodiment, the thickness of the gate dielectric layer disposed on the modified layer is greater than or equal to 500 angstroms and less than or equal to 900 angstroms.

[0027] In a feasible embodiment, the substrate includes: a base region and a drift region arranged along the thickness direction of the substrate, the drift region is farther away from the first surface than the base region; the groove runs through the base region, and the bottom surface of the groove is located in the drift region.

[0028] On the other hand, a chip is provided, comprising a packaging substrate and the above-mentioned semiconductor device, wherein the packaging substrate is coupled to the semiconductor device.

[0029] On the other hand, an electronic device is provided, comprising a circuit board and the above chip, wherein the chip is arranged on the circuit board.

[0030] On the other hand, a method for preparing a semiconductor device is provided, comprising: etching a substrate to form a groove, the substrate comprising a first surface and a second surface arranged opposite to each other in a thickness direction thereof, the opening of the groove being located on the first surface; forming a modified layer on a bottom surface of the groove; forming a gate dielectric layer on a side of the modified layer away from the second surface and on a sidewall surface of the groove; the thickness of the gate dielectric layer arranged on the modified layer is greater than the thickness of the gate dielectric layer arranged on the sidewall surface of the groove; forming a gate in the groove, and forming a source and a drain on opposite sides of the substrate in a thickness direction thereof.

[0031] In a feasible embodiment, after forming the modified layer on the bottom surface of the groove, the method further includes: injecting oxygen ions into the sidewall surface of the groove to form an ion implantation area.

[0032] In a feasible embodiment, a deposition rate of the gate dielectric layer on the surface of the modified layer is greater than a deposition rate of the gate dielectric layer on the sidewall surface of the groove.

[0033] In a feasible embodiment, a deposition rate of the gate dielectric layer on the surface of the ion implantation region is lower than a deposition rate of the gate dielectric layer on the surface of the modified layer.

[0034] In a feasible embodiment, a deposition rate of the gate dielectric layer on the surface of the ion implantation region is lower than a deposition rate on the surface of a region of the substrate where ion implantation is not performed.

[0035] It can be understood that the beneficial effects that can be achieved by the semiconductor device manufacturing method, chip, and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0037] Figure 1 A structural diagram of an electronic device provided according to some embodiments;

[0038] Figure 2 A structural diagram of a chip provided according to some embodiments;

[0039] Figure 3 A structural diagram of a semiconductor device provided according to some embodiments;

[0040] Figure 4 A structural diagram of another semiconductor device provided according to some embodiments;

[0041] Figure 5 A structural diagram of another semiconductor device provided according to some embodiments;

[0042] Figure 6 A structural diagram of another semiconductor device provided according to some embodiments;

[0043] Figure 7 A structural diagram of another semiconductor device provided according to some embodiments;

[0044] Figure 8 A flowchart of a method for preparing a semiconductor device according to some embodiments;

[0045] Fig. 9 A flowchart of another method for preparing a semiconductor device according to some embodiments;

[0046] Figures 10 to 23 It is a structural diagram of the semiconductor device corresponding to each step in the preparation method. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0048] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0049] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0050] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0051] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0052] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0053] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0054] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0055] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0056] In addition, in the present application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the components in the drawings.

[0057] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0058] Figure 1 FIG. 1 is a structural diagram of an electronic device provided according to some embodiments. Figure 1 As shown, the embodiment of the present disclosure provides an electronic device 1, which can be a product or component with power conversion function such as a power conversion system of an electric vehicle, a charging device of a mobile phone, a power adapter device of a laptop computer, etc. The electronic device 1 can also be different types of user equipment or terminal equipment such as a laptop computer, a tablet computer, a mobile phone, a wearable device, and a vehicle-mounted device, or a power amplification device used in the above electronic equipment. It should be understood that the electronic device 1 can also be a device or component with signal receiving / transmitting function in equipment such as an amplifier, a modulator, a base station, a radar, etc., and the embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device 1.

[0059] The following takes the electronic device 1 as an electronic device with a power conversion function as an example to schematically illustrate some embodiments of the present disclosure, but the implementation of the present disclosure is not limited to this, and any other display device can also be considered as long as the same technical concept is applied.

[0060] exist Figure 1 In the embodiment, the electronic device 1 includes, for example, a chip 10 and a circuit board 20. The chip 10 is disposed on the circuit board 20, and the circuit board 20 is configured to supply power to the chip 10 and transmit signals. Figure 2 , Figure 2 FIG. 1 is a structural diagram of a chip according to some embodiments. The chip 10 includes a semiconductor device 100 and a package substrate 300 , and the semiconductor device 100 is coupled to the package substrate 300 .

[0061] Figure 3 The semiconductor device 100 includes a substrate 110 , a gate dielectric layer 130 , a gate 140 , a source 150 , and a drain 160 .

[0062] Specifically, the substrate 110 includes a first surface 110A and a second surface 110B that are disposed opposite to each other in the thickness direction thereof, and the first surface 110A is provided with a groove 180 .

[0063] In some feasible embodiments, the substrate 110 includes a drift region 111 and a base region 112 arranged along its thickness direction, and the drift region 111 is farther from the first surface 110A than the base region 112. Exemplarily, the groove 180 penetrates the base region 112, and the bottom surface 180A of the groove 180 is located in the drift region 111.

[0064] The material of the gate dielectric layer 130 includes silicon oxide, for example. The gate dielectric layer 130 is disposed on the bottom surface 180A of the recess 180 . The gate dielectric layer 130 is also disposed on the sidewall surface 180B of the recess 180 .

[0065] The gate 140 is disposed in the groove 180, and the gate 140 is covered by the gate dielectric layer 130. In some feasible embodiments, the gate 140 is also provided with a gate dielectric layer 130 on a side away from the second surface 110B. Exemplarily, the gate 140 can be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials.

[0066] The source 150 and the drain 160 are respectively arranged on opposite sides of the substrate 110 in the thickness direction thereof. Exemplarily, the source 150 is arranged on a side of the substrate 110 close to the first surface 110A. Exemplarily, the surface of the source 150 includes a portion of the side wall surface 180B of the groove 180 and a portion of the first surface 110A of the substrate 110.

[0067] In some feasible embodiments, the semiconductor device 100 further includes a source metal layer (not shown in the figure), which is disposed on a side of the substrate 110 away from the second surface 110B and connected to the source 150 .

[0068] The drain 160 is disposed on the second surface 110B of the substrate 110. In some feasible embodiments, a silicon carbide layer is further included between the drain 160 and the substrate 110.

[0069] When preparing the gate dielectric layer 130 of the semiconductor device 100, the growth rates of the gate dielectric layer 130 on each crystal plane of the groove 180 are different. The bottom surface 180A of the groove 180 is an epitaxial crystal plane (0001), and the crystal planes of the sidewall surface 180B of the groove 180 are vertical crystal planes (11-20) and (1-100). Since the growth rate of the epitaxial crystal plane is lower than that of the vertical crystal plane, the thickness of the gate dielectric layer 130 arranged on the bottom surface 180A of the groove 180 is lower than the thickness of the gate dielectric layer 130 arranged on the sidewall surface 180B of the groove 180.

[0070] In some cases, the growth rate of the gate dielectric layer 130 on the epitaxial crystal plane is one order of magnitude smaller than the growth rate on the vertical crystal plane, so the thickness of the gate dielectric layer 130 disposed on the bottom surface 180A of the groove 180 is significantly smaller than the thickness of the gate dielectric layer 130 disposed on the sidewall surface 180B of the groove 180, as shown in Table 1. If the gate dielectric layer 130 disposed on the bottom surface 180A of the groove 180 is too thin, the electric field strength at that location and the surrounding area will increase. When the semiconductor device 100 is reverse biased, the too thin gate dielectric layer 130 will cause a current tunneling effect due to the excessively strong electric field, thereby shortening the device life.

[0071] Table 1. Relationship between the thickness of the gate dielectric layer at the bottom and sidewall of the groove and its growth time at 1200°C

[0072]

[0073]

[0074] Figure 4 This is a structural diagram of another semiconductor device provided according to some embodiments. The semiconductor device 101 includes a substrate 110 , a modified layer 120 , a gate dielectric layer 130 , a gate 140 , a source 150 , and a drain 160 .

[0075] Specifically, the substrate 110 includes a first surface 110A and a second surface 110B that are disposed opposite to each other in the thickness direction thereof, and the first surface 110A is provided with a groove 180 .

[0076] In some feasible embodiments, the substrate 110 includes a drift region 111 and a base region 112 arranged along its thickness direction, and the drift region 111 is farther from the first surface 110A than the base region 112. Exemplarily, the groove 180 penetrates the base region 112, and the bottom surface 180A of the groove 180 is located in the drift region 111.

[0077] The modified layer 120 is disposed on the bottom surface 180A of the groove 180. The material of the modified layer 120 includes polysilicon, and an exemplary material of the modified layer 120 includes undoped polysilicon.

[0078] The material of the substrate 110 includes, for example, silicon carbide, and the deposition rate of the gate dielectric layer 130 on the polysilicon surface is greater than the deposition rate of the gate dielectric layer 130 on the silicon carbide surface, so that the thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than the thickness of the gate dielectric layer 130 disposed on the side wall surface 180B of the groove 180.

[0079] The material of the gate dielectric layer 130 includes, for example, silicon oxide. The gate dielectric layer 130 is disposed on a side of the modified layer 120 away from the second surface 110B, and the gate dielectric layer 130 is also disposed on the sidewall surface 180B of the groove 180. The thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than the thickness of the gate dielectric layer 130 disposed on the sidewall surface 180B of the groove 180. This is because the deposition rate of the gate dielectric layer 130 on the modified layer 120 is greater than the deposition rate of the gate dielectric layer on the sidewall surface 180B of the groove 180. Exemplarily, the thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than or equal to 500A, and less than or equal to 900A.

[0080] In some feasible embodiments, the gate dielectric layer 130 disposed on the modified layer 120 may have a thickness of 500A, 550A, 600A, 650A, 700A, 750A, 800A, 850A or 900A, etc.

[0081] The gate 140 is disposed in the groove 180 , and the gate 140 is covered by the gate dielectric layer 130 . In some feasible embodiments, a gate dielectric layer 130 is also disposed on a side of the gate 140 away from the second surface 110B.

[0082] The source 150 and the drain 160 are respectively arranged on opposite sides of the substrate 110 in the thickness direction thereof. Exemplarily, the source 150 is arranged on a side of the substrate 110 close to the first surface 110A. Exemplarily, the surface of the source 150 includes a portion of the side wall surface 180B of the groove 180 and a portion of the first surface 110A of the substrate 110.

[0083] The drain 160 is disposed on the second surface 110B of the substrate 110. In some feasible embodiments, a silicon carbide layer is further included between the drain 160 and the substrate 110.

[0084] In the semiconductor device 101, the thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than the thickness of the gate dielectric layer 130 disposed on the sidewall surface 180B of the groove 180, which can improve the breakdown strength of the gate dielectric layer 130 disposed on the modified layer 120, so that the semiconductor device 101 can operate at a higher voltage without the gate dielectric layer 130 being broken down, thereby improving the breakdown voltage of the semiconductor device 101 and significantly improving the long-term reliability of the semiconductor device 101. At the same time, in working environments such as high frequency, high current, and high temperature, the improvement of the breakdown strength can effectively reduce the hot carrier injection effect, thereby extending the service life of the semiconductor device 101.

[0085] Furthermore, since the deposition rate of the gate dielectric layer 130 on the surface of the modified layer 120 is greater than the deposition rate on the side wall surface 180B of the groove 180, under the same deposition time, the thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than the thickness of the gate dielectric layer 130 disposed on the side wall surface 180B of the groove 180, which means that when the thickness of the gate dielectric layer 130 at the bottom of the groove 180 meets the actual application requirements, the thickness of the gate dielectric layer 130 disposed on the side wall surface 180B of the groove 180 in the semiconductor device 101 is smaller, which can reduce the threshold voltage of the semiconductor device 101, thereby reducing the power consumption of the semiconductor device 101 and improving its switching efficiency.

[0086] The material of the modified layer 120 includes polysilicon, and part of the electric field formed by the gate 140 cannot penetrate the polysilicon used as a conductive material, thereby achieving an electric field shielding effect to a certain extent.

[0087] Figure 5 is a structural diagram of another semiconductor device provided according to some embodiments, Figure 5 The structures and relative positions of the substrate 110, the modified layer 120, the gate dielectric layer 130, the gate 140, the source 150 and the drain 160 of the semiconductor device 102 are shown in FIG. Figure 4 The semiconductor device 101 shown is substantially identical.

[0088] Figure 5 The illustrated semiconductor device 102 also includes an ion implantation region 170 .

[0089] The ion implantation region 170 is located in the substrate 110 , and the surface of the ion implantation region 170 includes at least a portion of the sidewall surface 180B of the groove 180 . The deposition rate of the gate dielectric layer 130 on the surface of the ion implantation region 170 is lower than the deposition rate of the gate dielectric layer 130 on the surface of the modified layer 120 .

[0090] In some feasible embodiments, the ion implantation region 170 includes oxygen ions. For example, the material of the ion implantation region 170 may include silicon carbide, silicon oxide, and oxygen ions.

[0091] In some feasible embodiments, the deposition rate of the gate dielectric layer 130 on the surface of the ion implantation region 170 is lower than the deposition rate of the gate 140 on the surface of the substrate 110 where the ions are not implanted.

[0092] Since the deposition rate of the gate dielectric layer 130 on the surface of the ion implantation area 170 is lower than the deposition rate on the surface of the area of ​​the substrate 110 where ion implantation is not performed, the deposition rate of the gate dielectric layer 130 on the surface of the side wall 180B of the groove 180 can be further reduced compared to directly depositing the gate dielectric layer on the side wall of the groove of the substrate material, so that the thickness of the gate dielectric layer 130 arranged on the surface of the ion implantation area 170 is smaller, that is, under the premise that the thickness of the gate dielectric layer 130 on the side wall 180B of the groove 180 is constant, the thickness of the gate dielectric layer 130 on the modified layer 120 can be obtained to be thicker, and the semiconductor device 101 has a greater breakdown strength and a lower threshold current.

[0093] Figure 6 FIG. 1 is a structural diagram of another semiconductor device according to some embodiments. The semiconductor device 103 includes a substrate 110 , a modified layer 120 , a gate dielectric layer 130 , a gate 140 , a source 150 , and a drain 160 .

[0094] Specifically, the substrate 110 includes a first surface 110A and a second surface 110B that are disposed opposite to each other in the thickness direction thereof, and the first surface 110A is provided with a groove 180 .

[0095] In some feasible embodiments, the groove 180 includes a first sub-groove 181 and a second sub-groove 182, wherein the opening of the first sub-groove 181 is located on the first surface 110A, the second sub-groove 182 is located on the side of the first sub-groove 181 away from the first surface 110A, and the second sub-groove 182 is connected to the first sub-groove 181.

[0096] In some feasible embodiments, the opening size of the second sub-groove 182 is smaller than the opening size of the first sub-groove 181, and the first sub-groove 181 and the second sub-groove 182 with different opening sizes form a groove 180 with a step structure, thereby making the gate dielectric layer 130 formed in the groove 180 also have a step structure.

[0097] Exemplarily, the substrate 110 includes a drift region 111 and a base region 112 arranged along its thickness direction, and the drift region 111 is farther from the first surface 110A than the base region 112. Exemplarily, the groove 180 penetrates the base region 112, and the bottom surface 182A of the second sub-groove 182 is located in the drift region 111.

[0098] The modified layer 120 is disposed on the bottom surface 182A of the second sub-recess 182. The material of the modified layer 120 includes polysilicon. Exemplarily, the material of the modified layer 120 includes undoped polysilicon.

[0099] The gate dielectric layer 130 is disposed on a side of the modified layer 120 away from the second surface 110B, and the gate dielectric layer 130 is also disposed on the sidewall surface 182B of the second sub-recess 182, the sidewall surface 181A of the first sub-recess 181, and the bottom surface 181B of the first sub-recess 181. The thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than the thickness of the gate dielectric layer 130 disposed on the sidewall surface 181A of the first sub-recess 181 and the bottom surface 181B of the first sub-recess 181. This is because the deposition rate of the gate dielectric layer 130 on the modified layer 120 is greater than the deposition rate of the gate dielectric layer 130 on the sidewall surface 181A of the first sub-recess 181 and the bottom surface 181B of the first sub-recess 181. Exemplarily, the thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than or equal to 500A, and less than or equal to 900A.

[0100] In some feasible embodiments, the gate dielectric layer 130 disposed on the modified layer 120 may have a thickness of 500A, 550A, 600A, 650A, 700A, 750A, 800A, 850A or 900A, etc.

[0101] The gate 140 is disposed in the groove 180 , and the gate 140 is covered by the gate dielectric layer 130 . In some feasible embodiments, a side of the gate 140 away from the second surface 110B is also provided with the gate dielectric layer 130 .

[0102] The source 150 and the drain 160 are respectively arranged on opposite sides of the substrate 110 in the thickness direction thereof. Exemplarily, the source 150 is arranged on a side of the substrate 110 close to the first surface 110A. Exemplarily, the surface of the source 150 includes a portion of the side wall surface 180B of the groove 180 and a portion of the first surface 110A of the substrate 110.

[0103] The drain 160 is disposed on the second surface 110B of the substrate 110. In some feasible embodiments, a silicon carbide layer is further included between the drain 160 and the substrate 110.

[0104] In the semiconductor device 103, the first sub-recess 181 and the second sub-recess 182 with different opening sizes also form a gate dielectric layer 130 with a step structure, which can effectively adjust the electric field distribution and reduce the electric field concentration, thereby improving the breakdown voltage of the semiconductor device 103. At the same time, the gate 140 can also control the channel current more evenly, avoid the short channel effect and threshold voltage fluctuation caused by uneven electric field distribution, and improve the device performance and stability of the semiconductor device 103.

[0105] In some feasible embodiments, the semiconductor device 103 further includes an ion implantation region 170, the ion implantation region 170 is located in the substrate 110, and the surface of the ion implantation region 170 includes at least a portion of the sidewall surface 181A of the second sub-recess 182. The deposition rate of the gate dielectric layer 130 on the surface of the ion implantation region 170 is lower than the deposition rate of the gate dielectric layer 130 on the surface of the modified layer 120. The deposition rate of the gate dielectric layer 130 on the sidewall surface 181A of the first sub-recess 181 can be further reduced, so that the thickness of the gate dielectric layer 130 disposed on the modified layer 120 can be larger, and the thickness of the gate dielectric layer 130 disposed on the surface of the ion implantation region 170 can be smaller, that is, the semiconductor device 103 has a greater breakdown strength and a lower threshold voltage.

[0106] In some feasible embodiments, the ion implantation region 170 includes oxygen ions. For example, the material of the ion implantation region 170 may include silicon carbide, silicon oxide, and oxygen ions.

[0107] In some feasible embodiments, the deposition rate of the gate dielectric layer 130 on the surface of the ion implantation region 170 is lower than the deposition rate of the gate 140 on the surface of the substrate 110 where the ions are not implanted.

[0108] Figure 7 FIG. 4 is a structural diagram of another semiconductor device provided according to some embodiments. Figure 7 The structures and relative positions of the substrate 110, gate dielectric layer 130, gate 140, source 150 and drain 160 of the semiconductor device 104 are shown in FIG. Figure 6 The semiconductor devices 103 shown are substantially identical.

[0109] In the semiconductor device 104 , the modified layer 120 is further disposed on the sidewall surface 182B of the second sub-recess 182 . At this time, the gate dielectric layer 130 is further disposed on a side of the modified layer 120 away from the sidewall surface 182B of the second sub-recess 182 .

[0110] The modified layer 120 is arranged on the bottom surface 182A and the side wall surface 182B of the second sub-recess 182. Since the gate dielectric layer 130 arranged on the modified layer 120 is thicker, the gate dielectric layer 130 located in the second sub-recess 182 is thicker. In combination with the step-structured gate dielectric layer 130, the electric field distribution can be effectively adjusted, and the electric field concentration can be reduced, thereby improving the breakdown voltage of the semiconductor device 104.

[0111] In some feasible embodiments, the surface of the ion implantation region 170 also includes the bottom surface 181B of the first sub-recess 181. Figure 7 shown.

[0112] The surface of the ion implantation region 170 includes the sidewall surface 181A and the bottom surface 181B of the first sub-recess 181. The ion implantation region 170 is arranged in this way so that the gate dielectric layer 130 arranged on the sidewall surface 181A and the bottom surface 181B of the first sub-recess 181 has better thickness uniformity, thereby improving its electric field distribution.

[0113] Figure 8 FIG. 1 is a flow chart of a method for preparing a semiconductor device according to some embodiments. Figure 8 The method for preparing the semiconductor device includes steps S10 to S40:

[0114] See also Fig.15 In step S10, the substrate 110 is etched to form a groove 180. The substrate 110 includes a first surface 110A and a second surface 110B arranged opposite to each other in the thickness direction thereof, and the opening of the groove 180 is located at the first surface 110A. Exemplarily, the substrate 110 includes a drift region 111 and a base region 112 arranged in the thickness direction thereof, and the drift region 111 is farther from the first surface 110A than the base region 112.

[0115] In some feasible embodiments, the groove 180 formed by etching the substrate 110 penetrates the base region 112 , and a bottom surface 180A of the groove 180 is located in the drift region 111 .

[0116] In some feasible embodiments, the material of the substrate 110 includes silicon carbide.

[0117] See also Fig.19 In step S20 , a modified layer 120 is formed on the bottom surface of the groove 180 .

[0118] In some feasible embodiments, the groove 180 includes a first sub-groove 181 and a second sub-groove 182 , and the bottom surface of the groove 180 is, for example, the bottom surface 182A of the second sub-groove 182 .

[0119] See also Fig.23 In step S30, a gate dielectric layer 130 is formed on the side of the modified layer 120 away from the second surface 110B and on the sidewall surface of the groove. The thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than the thickness of the gate dielectric layer 130 disposed on the sidewall surface of the groove, because the material of the modified layer 120 includes undoped polysilicon, the material of the sidewall surface of the groove includes silicon carbide, and the growth rate of the gate dielectric layer 130 on the modified layer 120 is greater than the growth rate on the sidewall surface of the groove.

[0120] See also Figure 7In step S40, a gate electrode 140 is formed in the groove 180, and a source electrode 150 and a drain electrode 160 are respectively formed on opposite sides of the substrate 110 in the thickness direction.

[0121] In some feasible embodiments, the preparation method further includes step S50, and step S50 is located after step S20 and before step S30.

[0122] See also Fig. 22 In step S50 , oxygen ions are implanted into the sidewall surface of the groove to form an ion implantation region 170 . Exemplarily, the sidewall surface of the groove is, for example, the sidewall surface 181A of the first sub-groove 181 .

[0123] Finally, we get Figure 5 The semiconductor device 101 is shown. Figure 5 It can be seen that the thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than the thickness of the gate dielectric layer 130 disposed on the surface of the ion implantation area 170. This is because the material of the modified layer 120 includes undoped polysilicon, and the material of the ion implantation area 170 includes oxygen-doped silicon carbide, and, as shown in Table 2, the growth rate of the gate dielectric layer 130 on the modified layer 120 is greater than the growth rate of the gate dielectric layer 130 on the surface of the ion implantation area 170. In Table 2, SACVD is Semi-Atmosphere Chemical Vapor Deposition, i.e., semi-atmosphere pressure chemical vapor deposition. HARP is High Aspect Ratio Process, i.e., a processing technology for high aspect ratio structures. The calculation formula for surface sensitivity is: (thickness on various substrates / thickness on Si)*100%.

[0124] Table 2. Deposition sensitivity of SACVD on different substrate surfaces

[0125]

[0126]

[0127] Since the growth rate of the gate dielectric layer 130 on the surface of the ion implantation region 170 is lower than the deposition rate of the ion implantation region 170 on the surface of the substrate 110 where ions are not implanted, when the thickness of the gate dielectric layer 130 disposed on the sidewall surface 180B of the groove 180 is the same, Figure 2 In the semiconductor device 101 shown, the thickness of the gate dielectric layer 130 disposed on the surface of the modified layer 120 is greater than Figure 7 In the semiconductor device 104 shown, the thickness of the gate dielectric layer 130 disposed on the surface of the modified layer 120 further increases the thickness of the gate dielectric layer 130 at the bottom of the groove 180 .

[0128] For Figure 6 or Figure 7 The semiconductor device shown in the figure has a step structure at the bottom of the groove. The steps of forming the groove, the modified layer and the gate dielectric layer can be as follows: Fig. 9 The preparation method shown. Fig. 9 The present invention is a flow chart of another method for preparing a semiconductor device according to some embodiments. Figures 10 to 23 The structure diagram of the semiconductor device corresponding to each step in the preparation method. The preparation method includes steps S61 to S74:

[0129] In step S61, a mask layer 210 is formed on one side of the substrate 110. Fig.10 The semiconductor structure shown in FIG. 1 is a substrate 110 including a first surface 110A and a second surface 110B which are arranged opposite to each other in the thickness direction thereof, and a mask layer 210 is located on one side of the first surface 110A.

[0130] Exemplarily, the material of the mask layer 210 includes oxide, such as silicon oxide.

[0131] In some feasible embodiments, PECVD (Plasma-Enhanced Chemical Vapor Deposition) or PETEOS (Plasma-Enhanced Tetraethyl Orthosilicate) is used to grow oxide on the first surface 110A of the substrate 110 to form the mask layer 210 .

[0132] Exemplarily, the thickness of the mask layer 210 is 1 micrometer.

[0133] In step S62, the mask layer 210 is patterned and etched to form the third sub-recess 183. Fig.11 The semiconductor structure shown.

[0134] In some feasible embodiments, a RIE (Reactive Ion Etching) process is used, and fluorine-based gas and chlorine-based gas are used for etching. Exemplarily, CL2 and CF4 are used for etching.

[0135] Exemplarily, the third sub-groove 183 has a depth of 0.9 micrometers and a width of 0.5 micrometers.

[0136] In step S63, the sidewall surface of the third sub-recess 183 is etched to form the first sub-recess 181. Fig.12 The semiconductor structure shown.

[0137] In some feasible embodiments, an ICP (Inductively Coupled Plasma Etching) process is used, and fluorine-based gas and chlorine-based gas are used for etching. Exemplarily, CL2 and CF4 are used for etching.

[0138] In step S64, a sacrificial layer 220 is formed on the side of the substrate 110 away from the first surface 110A. Fig.13 The semiconductor structure shown.

[0139] In some feasible embodiments, LPCVD (Low Pressure Chemical Vapor Deposition) is used to form a sacrificial layer 220 on the sidewall surface 181A, the bottom surface 181B of the first sub-recess 181, and the side of the mask layer 210 away from the substrate 110. The thickness of the sacrificial layer 220 may be 50A to 100A, and the material of the sacrificial layer 220 includes polysilicon.

[0140] For example, the thickness of the sacrificial layer 220 may be 50A, 60A, 70A, 80A, 90A, or 100A, etc.

[0141] In step S65, the sacrificial layer 220 disposed on the side of the mask layer 210 away from the substrate 110 is removed. Fig.14 The semiconductor structure shown.

[0142] Exemplarily, an etch-back process is used to remove the sacrificial layer 220 on the side of the mask layer 210 away from the substrate 110 .

[0143] In some feasible embodiments, an etch-back process is used to further remove a portion of the sacrificial layer 220 disposed on the sidewall surface 181A of the groove 181 , for example, the sacrificial layer 220 on the sidewall surface 181A not covered by the mask layer 210 is removed.

[0144] In step S66, the bottom surface 181B of the first sub-recess 181 is etched to remove the sacrificial layer 220 located on the bottom surface 181B, and the second sub-recess 182 is formed. Fig.15 The semiconductor structure shown.

[0145] In some feasible embodiments, an etching process is used to remove the sacrificial layer 220 on the bottom surface 181B of the first sub-recess 181, and the substrate 110 is overetched to form the second sub-recess 182. The overetching depth may be 30A to 100A.

[0146] For example, the over-etching depth may be 30A, 40A, 50A, 60A, 70A, 80A, 90A, or 100A, etc.

[0147] In step S67, an initial modified layer 121 is formed on the side of the substrate 110 away from the second surface 110B. Fig.16 The semiconductor structure shown.

[0148] In some feasible embodiments, LPCVD is used to form the initial modified layer 121 on the bottom surface 182A of the second sub-recess 182, the sidewall surface 182B of the second sub-recess 182, the surface of the sacrificial layer 220 away from the sidewall surface 181A of the first sub-recess 181, and the surface of the mask layer 210 away from the substrate 110. Exemplary materials of the initial modified layer 121 include polysilicon, and the material of the initial modified layer 121 may include undoped polysilicon.

[0149] In some feasible embodiments, the thickness of the initial modified layer 121 is 50A to 100A. For example, the thickness of the initial modified layer 121 can be 50A, 60A, 70A, 80A, 90A or 100A.

[0150] In step S68, the initial modified layer 121 disposed on the side of the mask layer 210 away from the substrate 110 is removed. Fig.17 The semiconductor structure shown.

[0151] In some feasible embodiments, a CMP (Chemical Mechanical Planarization) process is used with an Overpolish parameter to remove the initial modified layer 121 on the side of the mask layer 210 away from the substrate 110 .

[0152] In step S69, a photoresist layer 230 is formed in the second sub-groove 182. Fig.18 The semiconductor structure shown.

[0153] In some feasible embodiments, the photoresist layer 230 is formed in the second sub-recess 182 using a spin coating process.

[0154] In step S70, the sacrificial layer 220, the initial modified layer 121 on the surface of the sacrificial layer 220, and the mask layer 210 are removed. Fig.19 The semiconductor structure shown.

[0155] In some feasible embodiments, the photoresist layer 230 in the second sub-recess 182 is removed at the same time.

[0156] In step S71, a photoresist layer 230 is formed in the second sub-groove 182 and the first surface 110A of the substrate 110. Fig. 20 The semiconductor structure shown.

[0157] In some feasible embodiments, a photoresist layer 230 is formed in the second sub-recess 182 and on the first surface 110A of the substrate 110 using a spin coating process.

[0158] In step S72, oxygen ions are implanted into the sidewall surface 181A of the first sub-recess 181 to form an ion implantation region 170, and the result is as follows: Fig.21 The semiconductor structure shown.

[0159] In some feasible embodiments, step S72 further includes implanting oxygen ions into the bottom surface 181B of the first sub-recess 181 to form an ion implantation region 170. Exemplarily, the ion implantation region 170 includes silicon carbide, silicon oxide, and oxygen ions.

[0160] In step S73, the photoresist layer 230 in the second sub-groove 182 is removed, and the photoresist layer 230 disposed on the first surface 110A of the substrate 110 is removed. Fig. 22 The semiconductor structure shown in FIG. 1 is shown in FIG. 1 . Exemplarily, a spin coating process is used to remove the photoresist layer 230 in a spin coating device.

[0161] In step S74, a gate dielectric layer 130 is formed on a side of the substrate 110 away from the second surface 110B. Fig.23 The semiconductor structure shown.

[0162] In some feasible embodiments, a SACVD process is used to form a gate dielectric layer 130 on the surface of the modified layer 120, the surface of the ion implantation region 170, and the first surface 110A of the substrate 110. Exemplarily, the material of the gate dielectric layer 130 includes silicon oxide.

[0163] SACVD has the characteristic of selective growth. Since the deposition rate of the gate dielectric layer 130 on the modified layer 120 is greater than the deposition rate of the gate dielectric layer 130 on the surface of the ion implantation area 170, the thickness of the gate dielectric layer 130 disposed on the modified layer 120 is greater than the thickness of the gate dielectric layer 130 disposed on the surface of the ion implantation area 170.

[0164] Thereafter, a gate is formed in the groove 180, and a source and a drain are formed on opposite sides of the substrate 110 in the thickness direction, respectively, to obtain Figure 7 A semiconductor device 104 is shown.

[0165] Method for preparing gate, source and drain Figure 8 Step S40 in the manufacturing method shown is basically the same and will not be described in detail here. In some feasible embodiments, before forming the gate in the groove 180 , step S75 is further included to remove the gate dielectric layer 130 disposed on the first surface 110A of the substrate 110 .

[0166] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a first surface and a second surface disposed opposite to each other in a thickness direction thereof, wherein the first surface is provided with a groove; A modified layer, disposed on the bottom surface of the groove; a gate dielectric layer, disposed on a side of the modified layer away from the second surface, and on a sidewall surface of the groove; A gate, disposed in the groove and covered by the gate dielectric layer; The source electrode and the drain electrode are respectively arranged on two opposite sides of the substrate in the thickness direction of the substrate; Wherein, the thickness of the gate dielectric layer disposed on the modified layer is greater than the thickness of the gate dielectric layer disposed on the sidewall surface of the groove.

2. The semiconductor device according to claim 1, wherein: The material of the modified layer includes polysilicon.

3. The semiconductor device according to claim 1, wherein: The material of the substrate includes silicon carbide.

4. The semiconductor device according to claim 1, wherein: Also includes: An ion implantation region is located in the substrate; a surface of the ion implantation region includes at least a portion of a sidewall surface of the groove; The material of the ion implantation region at least includes silicon oxide.

5. The semiconductor device according to claim 4, characterized in that The ion implantation region includes oxygen ions.

6. The semiconductor device according to claim 4 or 5, characterized in that: The groove includes a first sub-groove and a second sub-groove; The opening of the first sub-groove is located on the first surface; The second sub-groove is located at a side of the first sub-groove away from the first surface, the second sub-groove is connected to the first sub-groove, and the opening size of the second sub-groove is smaller than the opening size of the first sub-groove; The modified layer is at least disposed on the bottom surface of the second sub-groove.

7. The semiconductor device according to claim 6, characterized in that The modified layer is also disposed on the sidewall surface of the second sub-groove.

8. The semiconductor device according to claim 6, characterized in that The surface of the ion implantation region includes a sidewall surface of the first sub-recess.

9. The semiconductor device according to claim 8, characterized in that The surface of the ion implantation region also includes a bottom surface of the first sub-recess.

10. The semiconductor device according to any one of claims 1 to 5 and 7 to 9, characterized in that: The thickness of the gate dielectric layer disposed on the modified layer is greater than or equal to 500 angstroms and less than or equal to 900 angstroms.

11. The semiconductor device according to any one of claims 1 to 5 and 7 to 9, characterized in that: The substrate comprises: A base region and a drift region are arranged along the thickness direction of the substrate, wherein the drift region is farther away from the first surface than the base region; the groove passes through the base region, and the bottom surface of the groove is located in the drift region.

12. A chip, characterized in that: The invention comprises a packaging substrate and a semiconductor device according to any one of claims 1 to 11, wherein the packaging substrate is coupled to the semiconductor device.

13. An electronic device, characterized in that: It comprises a circuit board and the chip as claimed in claim 12, wherein the chip is arranged on the circuit board.

14. A method for preparing a semiconductor device, characterized in that: include: Etching a substrate to form a groove, wherein the substrate comprises a first surface and a second surface which are arranged opposite to each other in a thickness direction thereof, and an opening of the groove is located on the first surface; forming a modified layer on the bottom surface of the groove; forming a gate dielectric layer on a side of the modified layer away from the second surface and on a sidewall surface of the groove; The thickness of the gate dielectric layer disposed on the modified layer is greater than the thickness of the gate dielectric layer disposed on the sidewall surface of the groove; A gate is formed in the groove, and a source and a drain are respectively formed on opposite sides of the substrate in its thickness direction.

15. The preparation method according to claim 14, characterized in that: After forming the modified layer on the bottom surface of the groove, the method further comprises: Oxygen ions are implanted into the sidewall surface of the groove to form an ion implantation region.

16. The preparation method according to claim 14, characterized in that: The deposition rate of the gate dielectric layer on the surface of the modified layer is greater than the deposition rate of the gate dielectric layer on the sidewall surface of the groove.

17. The preparation method according to claim 15, characterized in that: The deposition rate of the gate dielectric layer on the surface of the ion implantation region is lower than the deposition rate of the gate dielectric layer on the surface of the modified layer.

18. The preparation method according to claim 15, characterized in that: The deposition rate of the gate dielectric layer on the surface of the ion implantation region is lower than the deposition rate on the surface of the region of the substrate where the ions are not implanted.

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