Field effect transistor device and battery management system

Abstract

A field effect transistor device includes a substrate divided into a first region on an upper side in a longitudinal direction of the substrate and a second region on a lower side in the longitudinal direction of the substrate, with an imaginary line perpendicular to the longitudinal direction of the substrate and located at a middle position of the substrate as a reference, the first region being located at an upper side in the longitudinal direction of the substrate, and the second region being located at a lower side in the longitudinal direction of the substrate; a first field effect transistor structure is formed on the substrate in the first region, a first gate structure is formed on the substrate in the first region, a first source structure is formed on the first gate structure, a second field effect transistor structure is formed on the substrate in the second region, a second gate structure is formed on the substrate in the second region, and a second source structure is formed on the second gate structure. A second source structure is formed below the second gate structure, and interconnection of the first drain structure of the first field effect transistor structure and the second drain structure of the second field effect transistor structure is achieved through the substrate of the first region and the substrate of the second region. The invention further provides a battery management system.

Description

Technical Field

[0001] The present disclosure relates to a field effect transistor device and a battery management system. Background Art

[0002] Power field effect transistor devices have the advantages of high integration, low on-resistance, fast switching speed, and low switching loss, and are widely used in various power management and switch conversion. However, the unidirectional withstand voltage and unidirectional conductivity characteristics of power field effect transistor devices caused by the drain-source asymmetric structure of traditional power field effect transistor devices limit the application of power field effect transistor devices.

[0003] In situations such as BMS (battery management system) that require bidirectional voltage resistance and bidirectional conductivity, a single power field effect transistor device cannot meet the requirements. The traditional solution is to short-circuit the drains of two power field effect transistor devices and use them in series to achieve the purpose of bidirectional voltage resistance and bidirectional conductivity (for example Figure 1 As shown). However, this solution requires two large-area power field effect transistor devices, which increases the cost and reduces the system integration. On the other hand, the two power field effect transistor devices connected in series also greatly increase the on-resistance of the circuit, increase the circuit loss, and the lateral flow of current in the traditional integrated drain shorting power field effect transistor device will also bring about problems such as premature breakdown of the device due to insufficient lateral withstand voltage and uneven opening of cells due to lateral parasitic resistance. Summary of the invention

[0004] In order to solve one of the above technical problems, the present disclosure provides a field effect transistor device and a battery management system.

[0005] According to one aspect, a field effect transistor device includes: a substrate, the substrate is divided into a first region and a second region, with an imaginary line perpendicular to the longitudinal direction of the substrate and located in the middle of the substrate as a reference, the first region is located on the upper side of the longitudinal direction of the substrate, and the second region is located on the lower side of the longitudinal direction of the substrate, a first field effect transistor structure is formed on the substrate of the first region, wherein a first gate structure is formed on the substrate of the first region, a first source structure is formed on the first gate structure, and a second field effect transistor structure is formed on the substrate of the second region, wherein a second gate structure is formed on the substrate of the second region, a second source structure is formed under the second gate structure, and a first drain structure of the first field effect transistor structure and a second drain structure of the second field effect transistor structure are connected to each other through the substrate of the first region and the substrate of the second region, wherein when the first field effect transistor structure and the second field effect transistor structure are turned on, the voltage applied to the first gate structure and the second gate structure is changed. direction, so that the current flows in two directions of the longitudinal direction, the first field effect transistor structure includes: a first well region, the first well region is located on the surface of the substrate of the first region, a first cathode contact region and a second cathode contact region, the first cathode contact region and the second cathode contact region are located in the first well region, and an edge of the first cathode contact region is tangent to an edge of the second cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the first cathode contact region is the second conductivity type, and the conductivity type of the second cathode contact region is the first conductivity type; a first gate dielectric layer, the first gate dielectric layer is located on the substrate of the first region and above the first well region; a first polysilicon gate, the first polysilicon gate is located above the first gate dielectric layer; a first dielectric isolation layer, the first dielectric isolation layer is located at the periphery of the first polysilicon gate and the first dielectric isolation layer completely wraps the first polysilicon gate; and a first metal contact layer, the first metal contact layer is located above the first dielectric isolation layer, the first cathode contact region and the second cathode contact region.

[0006] In addition, the second field effect transistor structure includes: a second well region, the second well region is located on the surface of the substrate of the second region, a third cathode contact region and a fourth cathode contact region are located in the second well region, and an edge of the third cathode contact region is tangent to an edge of the fourth cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the third cathode contact region is the second conductivity type, and the conductivity type of the fourth cathode contact region is the first conductivity type; a second gate dielectric layer, the second gate dielectric layer is located on the substrate of the second region and below the second well region; a second polysilicon gate, the second polysilicon gate is located below the second gate dielectric layer; a second dielectric isolation layer, the second dielectric isolation layer is located at the periphery of the second polysilicon gate and the second dielectric isolation layer completely wraps the second polysilicon gate; and a second metal contact layer, the second metal contact layer is located below the second dielectric isolation layer, the third cathode contact region and the fourth cathode contact region.

[0007] In addition, a third dielectric isolation layer is disposed between the bottom of the first well region and the substrate of the first region.

[0008] In addition, a fourth dielectric isolation layer is disposed between the top of the second well region and the substrate of the second region.

[0009] In addition, the number of the first well region, the first cathode contact region and the second cathode contact region are two respectively, and they are located at two sides of the longitudinal direction respectively.

[0010] In addition, the number of the second well region, the third cathode contact region and the fourth cathode contact region are two respectively, and they are located at two sides of the longitudinal direction respectively.

[0011] According to another aspect, a battery management system comprises the field effect transistor device as described in any one of the above items, wherein the field effect transistor device is used as a charging switch and a discharging switch in the battery management system to charge and discharge a battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0013] Figure 1 A schematic diagram of a field effect transistor device according to the prior art is shown.

[0014] Figure 2 A schematic diagram of a field effect transistor device according to an embodiment of the present disclosure is shown.

[0015] Figure 3 A schematic diagram of a field effect transistor device according to an embodiment of the present disclosure is shown.

[0016] Figure 4 A schematic diagram of a field effect transistor device according to an embodiment of the present disclosure is shown.

[0017] Figures 5 to 9 The figure shows a process for preparing a field effect transistor device according to an embodiment of the present disclosure.

[0018] Figures 10 to 13 The figure shows a process for preparing a field effect transistor device according to an embodiment of the present disclosure.

[0019] Fig.14 A schematic diagram of a battery management system according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0020] The present disclosure is further described in detail below in conjunction with the accompanying drawings and implementations. It is understood that the specific implementations described herein are only used to explain the relevant content, rather than to limit the present disclosure. It should also be noted that, for ease of description, only the parts related to the present disclosure are shown in the accompanying drawings.

[0021] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] Unless otherwise specified, the exemplary embodiments / embodiments shown will be understood as providing exemplary features of various details of some ways in which the technical concept of the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features of the various embodiments / embodiments can be combined, separated, interchanged and / or rearranged without departing from the technical concept of the present disclosure.

[0023] The use of cross-hatching and / or shading in the accompanying drawings is generally used to make the boundaries between adjacent components clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the accompanying drawings, the sizes and relative sizes of the components may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two successively described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same figure numbers represent the same components.

[0024] When a component is referred to as being "on" or "over," "connected to," or "coupled to" another component, the component may be directly on, directly connected to, or directly coupled to the other component, or intervening components may be present. However, when a component is referred to as being "directly on," "directly connected to," or "directly coupled to" another component, there are no intervening components. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, etc., with or without intervening components.

[0025] For descriptive purposes, the present disclosure may use spatially relative terms such as "under," "beneath," "under," "down," "over," "upper," "above," "higher," and "side (e.g., as in "sidewall")," to describe the relationship of one component to another (other) component as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, components described as "under" or "beneath" other components or features would subsequently be positioned "over" the other components or features. Thus, the exemplary term "under" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0026] The terms used here are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used here, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, parts, assemblies and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, parts, assemblies and / or their groups. It should also be noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, so that they are used to explain the inherent deviations of the measured values, calculated values ​​and / or the values ​​provided that will be recognized by those of ordinary skill in the art.

[0027] According to one embodiment of the present disclosure, a field effect transistor device is provided. According to the field effect transistor device of the present disclosure, a gate and a source are formed on the surface and back of a silicon wafer, realizing a bidirectional power field effect transistor device composed of two power field effect transistor devices with a common drain, which can be used for the protection of a battery management system (BMS) of a lithium battery. Compared with the method of using a pair of tubes or a double tube in series in a traditional BMS, the device proposed in the present disclosure has the following advantages: First, the device proposed in the present disclosure only needs to occupy half or even less area than the traditional method, which greatly improves the integration; second, the current and electric field direction of the device proposed in the present disclosure is longitudinal, which not only greatly reduces the risk of lateral breakdown of the device, but also greatly reduces the problem of uneven cell current caused by the lateral flow of current; third, the device proposed in the present disclosure eliminates the substrate resistance and part of the drift region resistance, shortens the current conduction path, and reduces the overall on-resistance of the device.

[0028] Figure 2 and Figure 3 A first embodiment and a second embodiment of a field effect transistor device according to the present disclosure are shown.

[0029] like Figure 2 and Figure 3 As shown, the field effect transistor device disclosed in the present invention includes a substrate, which is divided into a first region and a second region. Taking an imaginary line L which is perpendicular to the longitudinal direction of the substrate and located in the middle of the substrate as a reference, the first region is located on the upper side of the longitudinal direction of the substrate, and the second region is located on the lower side of the longitudinal direction of the substrate.

[0030] A first field effect transistor structure is formed on the front substrate 100, wherein a first gate structure is formed on the front substrate 100, a first source structure is formed on the first gate structure, and a second field effect transistor structure is formed on the substrate of the second region, wherein a second gate structure is formed on the substrate of the second region, a second source structure is formed under the second gate structure, and a first drain structure of the first field effect transistor structure and a second drain structure of the second field effect transistor structure are interconnected through the front substrate 100 and the substrate of the second region.

[0031] When the first field effect transistor structure and the second field effect transistor structure are turned on, current flows in two directions in the longitudinal direction by changing the direction of the voltage applied to the first gate structure and the second gate structure.

[0032] Preferably, the first field effect transistor structure and the second field effect transistor structure may be symmetrical structures with respect to the imaginary line L.

[0033] Figure 2 A field effect transistor device according to a first embodiment of the present disclosure is shown. Figure 2The field effect transistor device shown is a trench field effect transistor device. By forming field effect transistor structures on the front side (first area) and the back side (second area) of the silicon wafer substrate at the same time, a dual field effect transistor with a common drain can be realized in the area of ​​a single power field effect transistor device. It should be noted that the substrate of the first area and the second area is one substrate.

[0034] In the present disclosure, the substrate is of the first conductivity type and may be a lightly doped substrate.

[0035] like Figure 2 As shown, a first field effect transistor structure is formed on the front substrate 100. The first field effect transistor structure includes: a first polysilicon gate 110, a first gate oxide layer 120, a first well region 130, a first source region 140, a first body contact region 150 and a first metal contact layer 160. A first dielectric trench is formed on the substrate 100.

[0036] The first polysilicon gate 110 is located inside a first dielectric trench formed in the front substrate 100 .

[0037] The first gate oxide layer 120 is sandwiched between the first polysilicon gate 110 and the front substrate 100. The thickness of the first gate oxide layer 120 may be determined by the working potential of the gate.

[0038] The first well region 130 is located on the front substrate 100, the bottom of the first well region 130 is higher than the bottom of the first polysilicon gate 110 or flush with the bottom of the first polysilicon gate 110, the edge of the first well region 130 is tangent to the edge of the first dielectric groove (the first gate oxide layer 120), and the first well region 130 is of the second conductivity type and the substrate is of the first conductivity type.

[0039] The first source region 140 is located above the first well region 130 , the bottom of the first source region 140 is lower than the top of the first polysilicon gate 110 , the edge of the first source region 140 is tangent to the edge of the first dielectric trench, and the first source region 140 is of the first conductivity type.

[0040] The bottom of the first body contact region 150 is located between the bottom of the first source region 140 and the bottom of the first well region 130. The first body contact region 150 has a width smaller than that of the first source region 140 and is located in the middle of the first source region 140.

[0041] A first dielectric layer 170 is disposed above the first polysilicon gate 110 and is located in the first dielectric trench. The top of the first dielectric layer 170 may be tangent to the upper surface of the substrate 100 or may be lower than the upper surface of the substrate 100 .

[0042] The bottom of the first metal contact layer 160 is tangent to the upper surfaces of the first dielectric layer 170, the first source region 140 and the first body contact region 150 to form a source structure. The first metal contact layer 160 forms a front source.

[0043] The thickness of the first gate oxide layer 120 is determined by the potential of the operating voltage of the first gate structure.

[0044] like Figure 2 As shown, the number of the first dielectric grooves, the first polysilicon gate 110 and the first gate oxide layer 120 are two respectively, and they are respectively located on both sides of the longitudinal direction Y, the first well region 130 is located between the two first dielectric grooves, and the left edge and the right edge (in the X direction) of the first well region 130 are tangent to the two first dielectric grooves respectively.

[0045] The left edge and the right edge (in the X direction) of the first source region 140 are tangent to the two first dielectric grooves respectively.

[0046] The first body contact region 150 forms an ohmic contact or a Schottky contact with the first well region 130. When the ohmic contact is replaced by a Schottky contact, the turning on of the parasitic PNP transistor can be suppressed.

[0047] like Figure 2 As shown, a second field effect transistor structure is formed on the back substrate 200. The second field effect transistor structure includes: a second polysilicon gate 210, a second gate oxide layer 220, a second well region 230, a second source region 240, a second body contact region 250 and a second metal contact layer 260. A second dielectric trench is formed on the substrate 200.

[0048] The second polysilicon gate 210 is located inside the second dielectric trench formed in the back substrate 200. The second gate oxide layer 220 is sandwiched between the second polysilicon gate 210 and the back substrate 200 .

[0049] The second well region 230 is located on the back substrate 200, the top of the second well region 230 is lower than the top of the first polysilicon gate 110 or flush with the top of the first polysilicon gate 110, the edge of the second well region 230 is tangent to the edge of the second dielectric groove, and the second well region 230 is of the second conductivity type.

[0050] The second source region 240 is located below the second well region 230 , the top of the second source region 240 is higher than the bottom of the second polysilicon gate 210 , the edge of the second source region 240 is tangent to the edge of the second dielectric trench, and the second source region 240 is of the first conductivity type.

[0051] The top of the second body contact region 250 is located between the top of the second source region 240 and the top of the second well region 230 . The width of the second body contact region 250 is smaller than that of the second source region 240 and is located in the middle of the second source region 240 .

[0052] A second dielectric layer 270 is disposed below the second polysilicon gate 210 and is located in the second dielectric trench. The second dielectric layer 270 may be tangent to the lower surface of the back substrate 200 or may be higher than the lower surface of the back substrate 200 .

[0053] The top of the second metal contact layer 260 is tangent to the lower surfaces of the second dielectric layer 270, the second source region 240 and the second body contact region 250 to form a source structure. The second metal contact layer 260 forms a back source.

[0054] The thickness of the second gate oxide layer 220 is determined by the potential of the operating voltage of the second gate structure.

[0055] like Figure 2 As shown, the number of the second dielectric grooves, the second polysilicon gate 210 and the second gate oxide layer 220 are two respectively, and they are respectively located on both sides of the longitudinal direction, the second well region 230 is located between the two second dielectric grooves, and the left edge and the right edge (in the X direction) of the second well region 230 are tangent to the two second dielectric grooves respectively.

[0056] The left edge and the right edge (in the X direction) of the second source region 240 are tangent to the two second dielectric grooves respectively.

[0057] The second body contact region 250 forms an ohmic contact or a Schottky contact with the second well region 230. When the ohmic contact is replaced by a Schottky contact, the turning on of the parasitic PNP transistor can be suppressed.

[0058] In this power field effect transistor device, a field effect transistor structure is formed on the surface and back side of the substrate respectively, and the two field effect transistors share a drift region. When the channels of the two field effect transistors are closed, no matter which electrode has a high potential, the high voltage can be withstood by the depletion of the drift region, thereby achieving the purpose of bidirectional voltage resistance; when the channels of the two field effect transistors are opened, the current direction will change with the voltage direction, thereby achieving the purpose of bidirectional current conduction.

[0059] Figure 3 FIG. 4 shows a field effect transistor device according to a second embodiment of the present disclosure. Figure 3The field effect transistor device shown is a planar gate field effect transistor device. By forming the field effect transistor structure on the front side (first area) and the back side (second area) of the silicon wafer substrate at the same time, a dual field effect transistor with a common drain can be realized in the area of ​​a single power field effect transistor device. It should be noted that the substrate of the first area and the second area is one substrate.

[0060] In the present disclosure, the substrate is of the first conductivity type and may be a lightly doped substrate.

[0061] like Figure 3 As shown, the first field effect transistor structure includes: a front substrate 300, a first well region 310, a first cathode contact region 320, a second cathode contact region 330, a first gate dielectric layer 340, a first polysilicon gate 350, a first metal contact layer 360, and a first dielectric isolation layer 370.

[0062] The first well region 310 is located on the surface of the front substrate 100 .

[0063] The first cathode contact region 320 and the second cathode contact region 330 are located in the first well region 210, and one edge of the first cathode contact region 320 is tangent to one edge of the second cathode contact region 330, wherein the conductivity type of the substrate 300 is the first conductivity type, the conductivity type of the first cathode contact region 320 is the second conductivity type, and the conductivity type of the second cathode contact region 330 is the first conductivity type.

[0064] The first gate dielectric layer 340 is located on the front substrate 100 and above the first well region 130 . Meanwhile, the first gate dielectric layer 340 may also be located above a portion of the second cathode contact region 330 .

[0065] The first polysilicon gate 350 is located above the first gate dielectric layer 340 .

[0066] The first dielectric isolation layer 370 is located between the first metal contact layer 360 and the first polysilicon gate 350 .

[0067] The first metal contact layer 360 is located above the first polysilicon gate 350 , the first cathode contact region 320 , and the second cathode contact region 330 .

[0068] like Figure 3 As shown, the number of the first well region 310 , the first cathode contact region 320 and the second cathode contact region 330 are respectively two, and they are located at both sides of the longitudinal direction Y in the X direction.

[0069] According to a preferred embodiment of the present disclosure, Figure 4 As shown, a third dielectric isolation layer 380 may be further disposed between the bottom of the first well region 310 and the front substrate 300 .

[0070] like Figure 3 As shown, the second field effect transistor structure includes: a back substrate 400, a second well region 410, a third cathode contact region 420, a fourth cathode contact region 430, a second gate dielectric layer 440, a second polysilicon gate 450, a second metal contact layer 460, and a second dielectric isolation layer 470.

[0071] The second well region 410 is located on the surface of the back substrate.

[0072] The third cathode contact region 420 and the fourth cathode contact region 430 are located in the second well region 410, and one edge of the third cathode contact region 420 is tangent to an edge of the fourth cathode contact region 430, wherein the conductivity type of the back substrate 400 is the first conductivity type, the conductivity type of the third cathode contact region 420 is the second conductivity type, and the conductivity type of the fourth cathode contact region 430 is the first conductivity type.

[0073] The second gate dielectric layer 440 is located on the back substrate 400 and below the second well region 410 .

[0074] The second polysilicon gate 450 is located below the second gate dielectric layer 440 .

[0075] The second dielectric isolation layer 470 is located at the periphery of the second polysilicon gate 450 and completely wraps the second polysilicon gate 450 .

[0076] The second metal contact layer 460 is located below the second dielectric isolation layer 470 , the third cathode contact region 420 , and the fourth cathode contact region 430 .

[0077] like Figure 4 As shown, the number of the second well region 410 , the third cathode contact region 420 and the fourth cathode contact region 430 are respectively two, and they are located at both sides of the longitudinal direction Y in the X direction.

[0078] According to a preferred embodiment of the present disclosure, Figure 4 As shown, a fourth dielectric isolation layer 480 may be further disposed between the bottom of the second well region 410 and the back substrate 400 .

[0079] In this power field effect transistor device, a field effect transistor structure is formed on the surface and back side of the substrate respectively, and the two field effect transistors share a drift region. When the channels of the two field effect transistors are closed, no matter which electrode has a high potential, the high voltage can be withstood by the depletion of the drift region, thereby achieving the purpose of bidirectional voltage resistance; when the channels of the two field effect transistors are opened, the current direction will change with the voltage direction, thereby achieving the purpose of bidirectional current conduction.

[0080] According to an embodiment of the present disclosure, a method for preparing a field effect transistor device is also provided. The method may include the following contents.

[0081] A lightly doped substrate of the first conductivity type is selected. A dielectric layer is formed on the substrates 100 and 200 of the first conductivity type, wherein a silicon dioxide film is thermally grown or deposited on the surface of the substrate of the first conductivity type to form the dielectric layer, which serves as a mask for trench etching. The thickness of the dielectric layer can be determined by the trench etching depth.

[0082] like Figure 5 A U-shaped groove is etched on the surface of the substrate, and a first polysilicon gate 110 and a first gate oxide layer 120 are formed in the groove, wherein the first gate oxide layer 120 is located between the first dielectric groove and the first gate oxide layer 120, and the top of the first polysilicon gate 110 is lower than the upper surface of the substrate 100.

[0083] like Figure 6 As shown, a first well region 130 is formed on the surface of the substrate. For example, the first well region 130 of the second conductivity type can be formed on the surface of the first conductivity type substrate by one or more second conductivity type impurity ion implantations. The first well region 130 is located on the upper surface of the front substrate 100, the bottom of the first well region 130 is higher than the bottom of the first polysilicon gate 110 or flush with the bottom of the first polysilicon gate 110, and the edge of the first well region 130 is tangent to the edge of the first dielectric groove.

[0084] like Figure 7 As shown, a first source region 140 is formed on the surface of the substrate. For example, the first source region 140 can be formed on the surface of the first conductive type substrate by one or more first conductive type impurity ion implantations. The first source region 140 is located on the upper surface of the first well region 130, the bottom of the first source region 140 is lower than the top of the first polysilicon gate 110, the edge of the first source region 140 is tangent to the edge of the first dielectric groove, and the first source region 140 is of the first conductive type.

[0085] like Figure 8 As shown, a first body contact region 150 is formed on the surface of the substrate. Through photolithography and etching processes, the first body contact region 150 is etched in the middle of the first source region 140 on the surface of the substrate of the first conductivity type. The width of the first body contact region 150 is smaller than the width of the first source region 140 of the first conductivity type, and the bottom of the first body contact region 150 is located between the bottom of the first source region 140 and the bottom of the first well region 130. The first body contact region 150 forms an ohmic contact or a Schottky contact with the first well region 130.

[0086] like Fig. 9As shown, a first dielectric layer 170 and a first metal contact layer 160 are formed. For example, the first dielectric layer 170 and the contact hole can be formed by deposition, photolithography, and etching processes, and the surface is metallized. By photolithography and etching processes, a surface first metal contact layer 160 is formed to form a front source. The first dielectric layer 170 is located between the first polysilicon gate 110 and the first metal contact layer 160, and the top of the first dielectric layer 170 is flush with or lower than the upper surface of the substrate 100. The bottom of the first metal contact layer 160 is tangent to the upper surfaces of the first dielectric layer 170, the first source region 140, and the first body contact region 150, respectively.

[0087] In the present disclosure, preferably, after forming the first metal contact layer 160 , the back side of the substrate is thinned.

[0088] Afterwards, the above steps can be repeated to form the same trench gate structure on the back side of the substrate to form a back side source. Figure 2 The structure shown.

[0089] There are two first dielectric grooves, two first polysilicon gates 110 and two first gate oxide layers 120, respectively, and they are located on both sides of the longitudinal direction. The first well region 130 is located between the two first dielectric grooves, and the left edge and the right edge of the first well region 130 are tangent to the two first dielectric grooves respectively.

[0090] There are two second dielectric grooves, two second polysilicon gates 210 and two second gate oxide layers 220, respectively, and they are located on both sides of the longitudinal direction. The second well region 230 is located between the two second dielectric grooves, and the left edge and the right edge of the second well region 230 are tangent to the two second dielectric grooves respectively.

[0091] As described above, although the front structure is formed first and then the back structure is formed, those skilled in the art should understand that the front structure or the back structure may also be formed at the same time.

[0092] According to a further embodiment of the present disclosure, a method for preparing a field effect transistor device is also provided, comprising the following steps.

[0093] like Fig.10 As shown, a substrate of a first conductivity type is selected ( 100 and 200 ).

[0094] like Fig.11 As shown, gate oxide layers and gate polysilicon are grown on the front and back sides of the substrate, and a first gate dielectric layer 340 and a first polysilicon gate 350, a second gate dielectric layer 440 and a second polysilicon gate 450 are formed by photolithography and etching processes.

[0095] like Fig.12As shown, the first polysilicon gate 350 and the second polysilicon gate 450 are used as masks to form the first well region 310, the first cathode contact region 320 and the second cathode contact region 330, and the second well region 410, the third cathode contact region 420 and the fourth cathode contact region 430. For example, the second conductivity type impurities and the first conductivity type impurities are respectively implanted on the surface and the back of the substrate and then pushed at high temperature to form the first well region 310 of the second conductivity type, the first cathode contact region 320 of the second conductivity type, the second cathode contact region 330 of the first conductivity type, the second well region 410 of the second conductivity type, the third cathode contact region 420 of the second conductivity type and the fourth cathode contact region 430 of the first conductivity type.

[0096] The first cathode contact region and the second cathode contact region are located in the first well region, and an edge of the first cathode contact region is tangent to an edge of the second cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the first cathode contact region is the second conductivity type, and the conductivity type of the second cathode contact region is the second conductivity type, the third cathode contact region and the fourth cathode contact region are located in the second well region, and an edge of the third cathode contact region is tangent to an edge of the fourth cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the third cathode contact region is the second conductivity type, and the conductivity type of the fourth cathode contact region is the second conductivity type.

[0097] A first dielectric isolation layer 370 is formed on the front surface of the first conductive type substrate, and a second dielectric isolation layer 470 is formed on the back surface of the first conductive type substrate, wherein the first dielectric isolation layer completely wraps the first polysilicon gate. For example, dielectric layers can be deposited on the surface and back surface of a silicon wafer and then photolithographically etched. Fig.13 As shown, a first metal contact layer 360 and a second metal contact layer 460 are formed on the front and back sides of the substrate, respectively, wherein the first metal contact layer 360 is located above the first dielectric isolation layer 370, the first cathode contact region 310 and the second cathode contact region 320, and the second metal contact layer 460 is located below the second dielectric isolation layer 470, the third cathode contact region 420 and the fourth cathode contact region 430. For example, this can be achieved by metallizing the surface and back sides of the silicon wafer and by photolithography and etching.

[0098] In addition, a third dielectric isolation layer may be formed between the bottom of the first well region and the front surface of the substrate, and a fourth dielectric isolation layer may be provided between the top of the second well region and the back surface of the substrate.

[0099] The number of the first well region, the first cathode contact region and the second cathode contact region are two respectively, and they are located on both sides of the longitudinal direction of the substrate. The number of the second well region, the third cathode contact region and the fourth cathode contact region are two respectively, and they are located on both sides of the longitudinal direction of the substrate.

[0100] The present disclosure also provides a battery management system, comprising the field effect transistor device as above, wherein the field effect transistor device serves as a charging switch and a discharging switch in the battery management system to charge and discharge the battery.

[0101] like Fig.14 As shown, the above field effect transistor device can be used as Fig.14 The M1 and M2 shown in the figure thus serve as a charging switch and a discharging switch.

[0102] In summary, the following technical solutions are provided in the present disclosure.

[0103] 1. A field effect transistor device, comprising: a substrate, wherein the substrate is divided into a first region and a second region, and based on an imaginary line perpendicular to the longitudinal direction of the substrate and located in the middle of the substrate, the first region is located on the upper side of the longitudinal direction of the substrate, and the second region is located on the lower side of the longitudinal direction of the substrate, A first field effect transistor structure is formed on the substrate of the first region, wherein a first gate structure is formed on the substrate of the first region, a first source structure is formed on the first gate structure, and a second field effect transistor structure is formed on the substrate of the second region, wherein a second gate structure is formed on the substrate of the second region, a second source structure is formed under the second gate structure, and a first drain structure of the first field effect transistor structure and a second drain structure of the second field effect transistor structure are connected to each other through the substrate of the first region and the substrate of the second region, When the first field effect transistor structure and the second field effect transistor structure are turned on, the current flows in two directions of the longitudinal direction by changing the direction of the voltage applied to the first gate structure and the second gate structure.

[0104] 2. In the field effect transistor device as described in Technical Solution 1, the first field effect transistor structure and the second field effect transistor structure are symmetrical structures relative to the imaginary line.

[0105] 3. According to the field effect transistor device of technical solution 1 or 2, the first field effect transistor structure comprises: A first polysilicon gate, wherein the first polysilicon gate is located inside a first dielectric trench formed in the substrate of the first region, and a top of the first polysilicon gate is lower than an upper surface of the substrate; a first gate oxide layer, the first gate oxide layer being sandwiched between the first polysilicon gate and the substrate of the first region; a first well region, wherein the first well region is located on the substrate of the first region, the bottom of the first well region is higher than the bottom of the first polysilicon gate or is flush with the bottom of the first polysilicon gate, the edge of the first well region is tangent to the edge of the first dielectric groove, and the conductivity type of the first well region is the second conductivity type; a first source region, wherein the first source region is located above the first well region, the bottom of the first source region is lower than the top of the first polysilicon gate, the edge of the first source region is tangent to the edge of the first dielectric groove, and the first source region is of a first conductivity type; a first body contact region, wherein the first body contact region is located in the first source region, and a bottom of the first body contact region is located between a bottom of the first source region and a bottom of the first well region; and A first metal contact layer, wherein the bottom of the first metal contact layer is tangent to the upper surfaces of the first source region and the first body contact region to form a source structure.

[0106] 4. According to the field effect transistor device of technical solution 3, the second field effect transistor structure comprises: a second polysilicon gate, wherein the second polysilicon gate is located inside a second dielectric trench formed in the substrate of the second region, and a bottom of the second polysilicon gate is higher than a lower surface of the substrate; a second gate oxide layer, the second gate oxide layer being sandwiched between the second polysilicon gate and the substrate of the second region; a second well region, the second well region being located on the substrate of the second region, the top of the second well region being lower than the top of the first polysilicon gate or flush with the top of the first polysilicon gate, the edge of the second well region being tangent to the edge of the second dielectric groove, and the conductivity type of the second well region being the second conductivity type; a second source region, wherein the second source region is located below the second well region, a top of the second source region is higher than a bottom of the second polysilicon gate, an edge of the second source region is tangent to an edge of the second dielectric groove, and the second source region is of the first conductivity type; a second body contact region, the second body contact region being located in the second source region, a top of the second body contact region being located between a top of the second source region and a top of the second well region; and A second metal contact layer, wherein the top of the second metal contact layer is tangent to the lower surfaces of the second source region and the second body contact region to form a source structure.

[0107] 5. In the field effect transistor device as described in Technical Solution 3 or 4, a first dielectric layer is arranged between the first polysilicon gate and the first metal contact layer.

[0108] 6. In the field effect transistor device as described in Technical Solution 5, the thickness of the first gate oxide layer is determined by the potential of the operating voltage of the first gate structure.

[0109] 7. In the field effect transistor device as described in Technical Solution 6, the number of the first dielectric grooves, the first polysilicon gate and the first gate oxide layer are two respectively, and they are respectively located on both sides of the longitudinal direction, the first well region is located between the two first dielectric grooves, and the left edge and the right edge of the first well region are respectively tangent to the two first dielectric grooves.

[0110] 8. In the field effect transistor device as described in Technical Solution 7, the left edge and the right edge of the first source region are tangent to the two first dielectric grooves respectively.

[0111] 9. In the field effect transistor device as described in Technical Solution 8, the first body contact region forms an ohmic contact or a Schottky contact with the first well region.

[0112] 10. In the field effect transistor device as described in any one of technical solutions 5 to 9, a second dielectric layer is arranged between the second polysilicon gate and the second metal contact layer.

[0113] 11. In the field effect transistor device as described in technical solution 10, the thickness of the second gate oxide layer is determined by the potential of the operating voltage of the second gate structure.

[0114] 12. In the field effect transistor device as described in technical solution 11, the number of the second dielectric grooves, the second polysilicon gate and the second gate oxide layer are two respectively, and they are respectively located on both sides of the longitudinal direction, the second well region is located between the two second dielectric grooves, and the left edge and the right edge of the second well region are respectively tangent to the two second dielectric grooves.

[0115] 13. In the field effect transistor device as described in technical solution 12, the left edge and the right edge of the second source region are tangent to the two second dielectric grooves respectively.

[0116] 14. In the field effect transistor device as described in technical solution 13, the second body contact region forms an ohmic contact or a Schottky contact with the second well region.

[0117] 15. The field effect transistor device according to technical solution 1 or 2, wherein the first field effect transistor structure comprises: a first well region, the first well region being located on a surface of the substrate of the first region, a first cathode contact region and a second cathode contact region, wherein the first cathode contact region and the second cathode contact region are located in the first well region, and an edge of the first cathode contact region is tangent to an edge of the second cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the first cathode contact region is the second conductivity type, and the conductivity type of the second cathode contact region is the first conductivity type; a first gate dielectric layer, the first gate dielectric layer being located on the substrate of the first region and above the first well region; a first polysilicon gate, wherein the first polysilicon gate is located above the first gate dielectric layer; A first dielectric isolation layer, wherein the first dielectric isolation layer is located at the periphery of the first polysilicon gate and the first dielectric isolation layer completely wraps the first polysilicon gate; and above the first dielectric isolation layer, the first cathode contact area and the second cathode contact area.

[0118] 16. The field effect transistor device according to technical solution 15, wherein the second field effect transistor structure comprises: a second well region, the second well region being located on a surface of the substrate of the second region, A third cathode contact region and a fourth cathode contact region are located in the second well region, and an edge of the third cathode contact region is tangent to an edge of the fourth cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the third cathode contact region is the second conductivity type, and the conductivity type of the fourth cathode contact region is the first conductivity type; a second gate dielectric layer, the second gate dielectric layer being located on the substrate of the second region and below the second well region; a second polysilicon gate, wherein the second polysilicon gate is located below the second gate dielectric layer; A second dielectric isolation layer, wherein the second dielectric isolation layer is located at the periphery of the second polysilicon gate and the second dielectric isolation layer completely wraps the second polysilicon gate; and A second metal contact layer is disposed below the second dielectric isolation layer, the third cathode contact region and the fourth cathode contact region.

[0119] 17. In the field effect transistor device as described in technical solution 15 or 16, a third dielectric isolation layer is arranged between the bottom of the first well region and the substrate of the first region.

[0120] 18. In the field effect transistor device as described in Technical Solution 17, a fourth dielectric isolation layer is arranged between the top of the second well region and the substrate of the second region.

[0121] 19. In the field effect transistor device as described in technical solution 15 or 16, the number of the first well region, the first cathode contact region and the second cathode contact region are two respectively, and they are respectively located on both sides of the longitudinal direction.

[0122] 20. In the field effect transistor device as described in technical solution 19, the number of the second well region, the third cathode contact region and the fourth cathode contact region are two respectively, and they are respectively located on both sides of the longitudinal direction.

[0123] 21. A method for preparing a field effect transistor device, comprising: Forming a dielectric layer on a substrate of a first conductivity type, and then forming a first dielectric groove, wherein the first dielectric groove is located on the upper side of the substrate in the longitudinal direction, and forming a first polysilicon gate and a first gate oxide layer in the first dielectric groove, wherein the first gate oxide layer is located between the first dielectric groove and the first gate oxide layer, and the top of the first polysilicon gate is lower than the upper surface of the substrate; forming a first well region on the surface of the substrate, wherein the first well region is located on the upper surface of the substrate in the first region, the bottom of the first well region is higher than the bottom of the first polysilicon gate or flush with the bottom of the first polysilicon gate, the edge of the first well region is tangent to the edge of the first dielectric groove, and the first well region is of the second conductivity type; forming a first source region on the surface of the substrate, wherein the first source region is located on the upper surface of the first well region, the bottom of the first source region is lower than the top of the first polysilicon gate, the edge of the first source region is tangent to the edge of the first dielectric groove, and the conductivity type of the first source region is the first conductivity type; forming a first body contact region on the surface of the substrate, wherein the first body contact region is located in the first source region, and a bottom of the first body contact region is located between a bottom of the first source region and a bottom of the first well region; forming a first metal contact layer, wherein the bottom of the first metal contact layer is tangent to the upper surfaces of the first source region and the first body contact region; A second dielectric groove is formed, wherein the second dielectric groove is located at the lower side of the substrate in the longitudinal direction; a second polysilicon gate and a second gate oxide layer are formed in the second dielectric groove, wherein the second gate oxide layer is located between the second dielectric groove and the second gate oxide layer; and the bottom of the second polysilicon gate is higher than the lower surface of the substrate forming a second well region on the surface of the substrate, wherein the second well region is located on the lower surface of the substrate in the second region, the top of the second well region is lower than the top of the first polysilicon gate, the edge of the second well region is tangent to the edge of the second dielectric groove, and the conductivity type of the second well region is the second conductivity type; forming a second source region on the surface of the substrate, wherein the second source region is located on the lower surface of the second well region, the top of the second source region is higher than the bottom of the second polysilicon gate, the edge of the second source region is tangent to the edge of the second dielectric groove, and the conductivity type of the second source region is the first conductivity type; forming a second body contact region on the surface of the substrate, wherein the second body contact region is located in the second source region, and a top of the second body contact region is located between a top of the second source region and a top of the second well region; and A second metal contact layer is formed, wherein a top of the second metal contact layer is tangent to lower surfaces of the second source region and the second body contact region.

[0124] 22. The method for preparing a field effect transistor device as described in Technical Solution 21 further includes: after forming the first metal contact layer, thinning the back side of the substrate.

[0125] 23. The method for preparing a field effect transistor device as described in technical solution 21 or 22 further includes: forming a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is located between the first polysilicon gate and the first metal contact layer, and the second dielectric layer is located between the second polysilicon gate and the second metal contact layer.

[0126] 24. In the method for preparing a field effect transistor device as described in technical solution 23, the number of the first dielectric groove, the first polysilicon gate and the first gate oxide layer are two respectively, and they are respectively located on both sides of the longitudinal direction, the first well region is located between the two first dielectric grooves, and the left edge and the right edge of the first well region are respectively tangent to the two first dielectric grooves.

[0127] 25. In the method for preparing a field effect transistor device as described in technical solution 24, the left edge and the right edge of the first source region are respectively tangent to the two first dielectric grooves.

[0128] 26. In the method for preparing a field effect transistor device as described in technical solution 25, the first contact region forms an ohmic contact or a Schottky contact with the first well region.

[0129] 27. In the method for preparing a field effect transistor device as described in technical solution 24, the number of the second dielectric grooves, the second polysilicon gate and the second gate oxide layer are two respectively, and they are respectively located on both sides of the longitudinal direction, the second well region is located between the two second dielectric grooves, and the left edge and the right edge of the second well region are respectively tangent to the two second dielectric grooves.

[0130] 28. In the method for preparing a field effect transistor device as described in Technical Solution 27, the left edge and the right edge of the second source region are respectively tangent to the two second dielectric grooves.

[0131] 29. In the method for preparing a field effect transistor device as described in technical solution 28, the second contact region forms an ohmic contact or a Schottky contact with the second well region.

[0132] 30. A method for preparing a field effect transistor device, comprising: Forming a first gate dielectric layer and a first polysilicon gate on the front surface of the substrate of the first conductivity type, and forming a second gate dielectric layer and a second polysilicon gate on the back surface of the substrate of the first conductivity type; Using the first polysilicon gate and the second polysilicon gate as masks, respectively forming a first well region, a first cathode contact region and a second cathode contact region, and a second well region, a third cathode contact region and a fourth cathode contact region, wherein the first cathode contact region and the second cathode contact region are located in the first well region, and an edge of the first cathode contact region is tangent to an edge of the second cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the first cathode contact region is the second conductivity type, and the conductivity type of the second cathode contact region is the first conductivity type, the third cathode contact region and the fourth cathode contact region are located in the second well region, and an edge of the third cathode contact region is tangent to an edge of the fourth cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the third cathode contact region is the second conductivity type, and the conductivity type of the fourth cathode contact region is the first conductivity type; forming a first dielectric isolation layer on the front side of the substrate, and forming a second dielectric isolation layer on the back side of the substrate, wherein the first dielectric isolation layer completely wraps the first polysilicon gate, and the second dielectric isolation layer completely wraps the second polysilicon gate; and A first metal contact layer and a second metal contact layer are formed on the front and back sides of the substrate, respectively, wherein the first metal contact layer is located above the first dielectric isolation layer, the first cathode contact area, and the second cathode contact area, and the second metal contact layer is located below the second dielectric isolation layer, the third cathode contact area, and the fourth cathode contact area.

[0133] 31. In the method for preparing a field effect transistor device as described in technical solution 30, a third dielectric isolation layer is formed between the bottom of the first well region and the front side of the substrate, and a fourth dielectric isolation layer is arranged between the top of the second well region and the back side of the substrate.

[0134] 32. In the method for preparing a field effect transistor device as described in technical solution 30 or 31, the number of the first well region, the first cathode contact region and the second cathode contact region are two respectively, and are respectively located on both sides of the longitudinal direction of the substrate.

[0135] 33. In the method for preparing a field effect transistor device as described in technical solution 30 or 31, the number of the second well region, the third cathode contact region and the fourth cathode contact region are two respectively, and are respectively located on both sides of the longitudinal direction of the substrate.

[0136] 34. A battery management system, comprising a field effect transistor device as described in any one of technical solutions 1 to 20, wherein the field effect transistor device serves as a charging switch and a discharging switch in the battery management system to charge and discharge the battery.

[0137] In the description of this specification, the description with reference to the terms "one embodiment / method", "some embodiments / methods", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment / method or example are included in at least one embodiment / method or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment / method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments / methods or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments / methods or examples described in this specification and the features of the different embodiments / methods or examples, unless they are contradictory.

[0138] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0139] Those skilled in the art should understand that the above embodiments are only for the purpose of clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications may be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A field effect transistor device, characterized in that: The invention comprises: a substrate, wherein the substrate is divided into a first area and a second area, and based on an imaginary line perpendicular to the longitudinal direction of the substrate and located in the middle of the substrate, the first area is located on the upper side of the longitudinal direction of the substrate, and the second area is located on the lower side of the longitudinal direction of the substrate, A first field effect transistor structure is formed on the substrate of the first region, wherein a first gate structure is formed on the substrate of the first region, a first source structure is formed on the first gate structure, and a second field effect transistor structure is formed on the substrate of the second region, wherein a second gate structure is formed on the substrate of the second region, a second source structure is formed under the second gate structure, and a first drain structure of the first field effect transistor structure and a second drain structure of the second field effect transistor structure are connected to each other through the substrate of the first region and the substrate of the second region, When the first field effect transistor structure and the second field effect transistor structure are turned on, the current flows in two directions of the longitudinal direction by changing the direction of the voltage applied to the first gate structure and the second gate structure. The first field effect transistor structure comprises: a first well region, the first well region being located on a surface of the substrate of the first region, a first cathode contact region and a second cathode contact region, wherein the first cathode contact region and the second cathode contact region are located in the first well region, and an edge of the first cathode contact region is tangent to an edge of the second cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the first cathode contact region is the second conductivity type, and the conductivity type of the second cathode contact region is the first conductivity type; a first gate dielectric layer, the first gate dielectric layer being located on the substrate of the first region and above the first well region; a first polysilicon gate, wherein the first polysilicon gate is located above the first gate dielectric layer; A first dielectric isolation layer, wherein the first dielectric isolation layer is located at the periphery of the first polysilicon gate and the first dielectric isolation layer completely wraps the first polysilicon gate; and A first metal contact layer is located above the first dielectric isolation layer, the first cathode contact region and the second cathode contact region.

2. The field effect transistor device according to claim 1, characterized in that The second field effect transistor structure comprises: a second well region, the second well region being located on a surface of the substrate of the second region, A third cathode contact region and a fourth cathode contact region are located in the second well region, and an edge of the third cathode contact region is tangent to an edge of the fourth cathode contact region, wherein the conductivity type of the substrate is the first conductivity type, the conductivity type of the third cathode contact region is the second conductivity type, and the conductivity type of the fourth cathode contact region is the first conductivity type; a second gate dielectric layer, the second gate dielectric layer being located on the substrate of the second region and below the second well region; a second polysilicon gate, wherein the second polysilicon gate is located below the second gate dielectric layer; A second dielectric isolation layer, wherein the second dielectric isolation layer is located at the periphery of the second polysilicon gate and the second dielectric isolation layer completely wraps the second polysilicon gate; and A second metal contact layer is disposed below the second dielectric isolation layer, the third cathode contact region and the fourth cathode contact region.

3. The field effect transistor device according to claim 2, characterized in that A third dielectric isolation layer is arranged between the bottom of the first well region and the substrate of the first region.

4. The field effect transistor device according to claim 3, characterized in that A fourth dielectric isolation layer is arranged between the top of the second well region and the substrate of the second region.

5. The field effect transistor device according to claim 2, characterized in that: The number of the first well region, the first cathode contact region and the second cathode contact region are two respectively, and they are located at two sides of the longitudinal direction respectively.

6. The field effect transistor device according to claim 5, characterized in that The number of the second well region, the third cathode contact region and the fourth cathode contact region are two respectively, and they are located at two sides of the longitudinal direction respectively.

7. A battery management system, characterized in that: It comprises the field effect transistor device as claimed in any one of claims 1 to 6, wherein the field effect transistor device is used as a charging switch and a discharging switch in the battery management system to charge and discharge the battery.

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