Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, the array substrate comprises a substrate, a first thin film transistor and a second thin film transistor, the first thin film transistor and the second thin film transistor are located on one side of the substrate, the first thin film transistor comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, the second thin film transistor comprises a second active layer, a second grid electrode, a second source electrode and a second drain electrode, the first active layer and the second active layer are at least partially overlapped in the direction perpendicular to the plane where the substrate is located, the first thin film transistor is connected with the first pixel electrode, and the second thin film transistor is connected with the second pixel electrode. The first pixel electrode and the second pixel electrode are located on the same layer. The problem of how to realize miniaturization of the display panel in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Thin Film Transistor (TFT) is a special transistor that uses thin-layer technology to deposit semiconductor materials and other materials on a substrate to form a transistor. TFT technology can be applied to display fields such as televisions, computer monitors, mobile phone screens, and other portable electronic devices. With the advancement of technology, the demand for miniaturization of display panels is increasing. Summary of the invention

[0003] The main purpose of the present invention is to provide an array substrate and a display panel to solve the problem of how to achieve miniaturization of the display panel in the prior art.

[0004] To achieve the above-mentioned purpose, according to one aspect of the present invention, there is provided an array substrate, comprising a substrate, a first thin film transistor and a second thin film transistor located on one side of the substrate, wherein the first thin film transistor comprises a first active layer, a first gate, a first source and a first drain, and the second thin film transistor comprises a second active layer, a second gate, a second source and a second drain, in a direction perpendicular to the plane where the substrate is located, the first active layer and the second active layer at least partially overlap, the first thin film transistor is connected to a first pixel electrode, the second thin film transistor is connected to a second pixel electrode, and the first pixel electrode and the second pixel electrode are located on the same layer.

[0005] Furthermore, the first active layer is located between the second active layer and the substrate.

[0006] Further, an extension direction of the first active layer is the same as an extension direction of the second active layer, wherein the extension direction is a direction from the source region to the drain region.

[0007] Further, the distance between the first source and the first drain is a first distance, the distance between the second source and the second drain is a second distance, and the first distance is greater than the second distance.

[0008] Furthermore, along the extension direction of the first active layer, the straight-line length of the channel region of the first thin film transistor is D1, and the channel region of the first thin film transistor is the overlapping region of the first gate and the first active layer; along the extension direction of the second active layer, the straight-line length of the channel region of the second thin film transistor is D2, and the channel region of the second thin film transistor is the overlapping region of the second gate and the second active layer, wherein D1≥D2.

[0009] Furthermore, along the extension direction of the first active layer, the straight-line length of the channel region of the first thin film transistor is D1, and the channel region of the first thin film transistor is the overlapping region of the first gate and the first active layer; along the extension direction of the second active layer, the straight-line length of the channel region of the second thin film transistor is D2, and the channel region of the second thin film transistor is the overlapping region of the second gate and the second active layer, wherein D1≥D2.

[0010] Further, along an extension direction of the first active layer, a sum of a width of the first source electrode and a width of the first drain electrode is greater than a sum of a width of the second source electrode and a width of the second drain electrode.

[0011] Further, a direction in which the first source points to the first drain is the same as a direction in which the second source points to the second drain.

[0012] Further, a direction in which the first source points to the first drain is opposite to a direction in which the second source points to the second drain.

[0013] Further, an extension direction of the first active layer intersects with an extension direction of the second active layer, wherein the extension direction is a direction from the source region to the drain region.

[0014] Further, along the extension direction of the first active layer, the straight-line length of the channel region of the first thin film transistor is D1, and the channel region of the first thin film transistor is the overlapping region of the first gate and the first active layer; along the extension direction of the second active layer, the straight-line length of the channel region of the second thin film transistor is D2, and the channel region of the second thin film transistor is the overlapping region of the second gate and the second active layer; wherein, D1=D2.

[0015] Further, a channel length of the first thin film transistor is equal to a channel length of the second thin film transistor.

[0016] Further, the first gate is located between the first active layer and the second active layer, and / or the second gate is located between the first active layer and the second active layer.

[0017] Further, in a direction perpendicular to the plane where the substrate is located, a distance between the first pixel electrode and the first active layer is not equal to a distance between the second pixel electrode and the second active layer.

[0018] Furthermore, the array substrate further includes: a common electrode layer located between the first pixel electrode and the second thin film transistor.

[0019] In order to achieve the above objective, according to one aspect of the present invention, a display panel is provided, comprising any one of the above array substrates.

[0020] By applying the technical solution of the present invention, an array substrate is provided. By stacking a first thin film transistor and a second thin film transistor, and connecting the first pixel electrode and the second pixel electrode respectively, when the number of thin film transistors is the same, compared with the prior art, the present solution can reduce the area occupied by the thin film transistors on the display panel, thereby reducing the area occupied by the array substrate, and finally reducing the area of ​​the display panel. The technical problem of how to miniaturize the display panel in the prior art is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0022] Figure 1 A cross-sectional schematic diagram of an array substrate provided according to an embodiment of the present invention is shown;

[0023] Figure 2 A schematic top view of an array substrate provided according to an embodiment of the present invention is shown;

[0024] Figure 3 A cross-sectional schematic diagram of another array substrate provided according to an embodiment of the present invention is shown;

[0025] Figure 4 A cross-sectional schematic diagram of another array substrate provided according to an embodiment of the present invention is shown;

[0026] Figure 5 A cross-sectional schematic diagram of another array substrate provided according to an embodiment of the present invention is shown;

[0027] Figure 6 A cross-sectional schematic diagram of another array substrate provided according to an embodiment of the present invention is shown;

[0028] Figure 7 A schematic top view of another array substrate provided according to an embodiment of the present invention is shown;

[0029] Figure 8 A cross-sectional schematic diagram of another array substrate provided according to an embodiment of the present invention is shown;

[0030] Fig. 9 A cross-sectional schematic diagram of another array substrate provided according to an embodiment of the present invention is shown;

[0031] Fig.10 A cross-sectional schematic diagram of another array substrate provided according to an embodiment of the present invention is shown;

[0032] Fig.11 A cross-sectional schematic diagram of another array substrate provided according to an embodiment of the present invention is shown;

[0033] Fig.12 A schematic structural diagram of a display device provided according to an embodiment of the present invention is shown.

[0034] The above drawings include the following reference numerals:

[0035] 10. substrate; 20. first thin film transistor; 201. first active layer; 202. first gate; 203. first source; 204. first drain; 30. second thin film transistor; 301. second active layer; 302. second gate; 303. second source; 304. second drain; 40. first pixel electrode; 50. second pixel electrode; 60. common electrode layer; L1. first distance; L2. second distance; W1. first width; W2. second width; W3. third width; W4. fourth width; 100. display panel. DETAILED DESCRIPTION

[0036] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0039] As introduced in the background technology, there is an increasing demand for miniaturization of display panels in the prior art. In order to solve the above technical problems, the present application proposes an array substrate and a display panel.

[0040] Figure 1 is a schematic diagram of the structure of an array substrate according to an embodiment of the present application. Figures 1 to 11As shown, it includes a substrate 10, a first thin film transistor 20 and a second thin film transistor 30 located on one side of the substrate 10, that is, the first thin film transistor 20 and the second thin film transistor 30 are stacked, the first thin film transistor 20 can be located on the side of the second thin film transistor 30 away from the substrate 10, and the second thin film transistor 30 can be located on the side of the first thin film transistor 20 away from the substrate 10. The first thin film transistor 20 includes a first active layer 201, a first gate 202, a first source electrode 203 and a first drain electrode 204, and the second thin film transistor 30 includes a second active layer 301, a second gate 302, a second source electrode 303 and a second drain electrode 304. The positional relationship of the second active layer 301, the second gate 302, the second source electrode 303 and the second drain electrode 304 can be the same as or different from the positional relationship of the first active layer 201, the first gate 202, the first source electrode 203 and the first drain electrode 204. In a direction perpendicular to the plane where the substrate 10 is located, the first active layer 201 and the second active layer 301 at least partially overlap, that is, the first active layer 201 and the second active layer 301 may partially overlap or completely overlap. The first thin film transistor 20 is connected to the first pixel electrode 40, and the second thin film transistor 30 is connected to the second pixel electrode 50. The first pixel electrode 40 and the second pixel electrode 50 are located in the same layer. Since the film layer where the first pixel electrode 40 and the second pixel electrode 50 are located may be different from the film layer where the first thin film transistor 20 or the second thin film transistor 30 is located, the first pixel electrode 40 may be electrically connected to the first source 203 or the first drain 204 of the first thin film transistor 20 through a through hole, and the second pixel electrode 50 may be electrically connected to the second source 303 or the second drain 304 of the second thin film transistor 30 through a through hole.

[0041] In practical applications, the materials for making the first active layer and the second active layer can be selected from polysilicon materials or indium gallium zinc oxide materials. Among them, the active layer made of polysilicon material takes advantage of the characteristics of fast electron movement speed and high electron mobility of polysilicon material, thereby making the thin film transistor device require a larger turn-on current, while the active layer made of indium gallium zinc oxide material takes advantage of the characteristics that the electron movement speed of indium gallium zinc oxide material is slower than that of polysilicon material and the electron mobility is lower, thereby making the thin film transistor device have a smaller leakage current. The number of thin film transistors is not limited to the two thin film transistors of the first thin film transistor and the second thin film transistor mentioned above, and more than three thin film transistors can be set, which can further reduce the footprint of the thin film transistor. For example, in the case of three stacked thin film transistors, compared with the same number of thin film transistors in the prior art, the area occupied by the thin film transistor is one third of the original.

[0042] By applying the technical solution of the present invention, an array substrate is provided. By stacking a first thin film transistor and a second thin film transistor, and connecting the first pixel electrode and the second pixel electrode respectively, when the number of thin film transistors is the same, compared with the prior art, the present solution can reduce the area occupied by the thin film transistors on the display panel, thereby reducing the area occupied by the array substrate, and finally reducing the area of ​​the display panel. The technical problem of how to miniaturize the display panel in the prior art is solved.

[0043] In some embodiments, Figure 1 As shown, the first active layer 201 is located between the second active layer 301 and the substrate 10. That is, the first thin film transistor 20 is located between the second thin film transistor 30 and the substrate 10. In the case where the area of ​​the display panel is the same, the above arrangement can reduce the occupied area of ​​the array substrate, achieve the technical effect of increasing the occupied area of ​​the pixel unit, and then increase the pixel density, further providing a more delicate and clearer display effect.

[0044] In some other embodiments, Figure 2 As shown, the extension direction of the first active layer 201 is the same as the extension direction of the second active layer 301, wherein the extension direction is the direction from the source region to the drain region. That is to say, the extension direction of the first active layer 201 is the direction from the source region of the first active layer 201 to the drain region of the first active layer 201, and the extension direction of the second active layer 301 is the direction from the source region of the second active layer 301 to the drain region of the second active layer 301. The first active layer 201 and the second active layer 301 are arranged in parallel, that is, the first thin film transistor 20 and the second thin film transistor 30 are arranged in parallel. It should be noted that in Figure 2 In the top view shown, since some structures of the first thin film transistor 20 and the second thin film transistor 30 overlap, Figure 2 The structure shown in FIG. 1 can actually be regarded as a structure in the first thin film transistor 20 and a structure in the second thin film transistor 30. Figure 2 Taking the first gate 202 in the figure as an example, it can also be represented as the second gate 302. Since the first thin film transistor and the second thin film transistor have the same extension direction, there is no need to adjust the setting direction of the thin film transistor in the manufacturing process. The first thin film transistor and the second thin film transistor can be set in the same direction, further reducing the process complexity.

[0045] Specifically, the source region and the drain region are two conductive regions in the active layer, the source region is the input terminal of the thin film transistor, the drain region is the output terminal of the thin film transistor, and the current flows from the source region to the drain region. The drain region of the first active layer is electrically connected to the first drain, the source region of the first active layer is electrically connected to the first source, the drain region of the second active layer is electrically connected to the second drain, and the source region of the second active layer is electrically connected to the second source.

[0046] In another specific embodiment, Figure 1 As shown, the distance between the first source 203 and the first drain 204 is the first distance L1, which is the distance between the center point of the first source 203 and the center point of the first drain 204, and the distance between the second source 303 and the second drain 304 is the second distance L2, that is, the second distance L2 is the distance between the center point of the second source 303 and the center point of the second drain 304. The first distance L1 is greater than the second distance L2. The distance between the first source 203 and the first drain 204 of the first thin film transistor 20 is greater than the distance between the second source 303 and the second drain 304 of the second thin film transistor 30, so that part of the first source 203 or the first drain 204 of the first thin film transistor 20 is not covered by the second thin film transistor 30, which is further beneficial to the subsequent punching overlap between the first pixel electrode and the first source 203 or the first drain 204.

[0047] Specifically, the first distance is Figure 1 In addition to the structure shown in FIG. 1 , the first distance may also be the distance between the same positions of the first source and the first drain, that is, the first distance is the distance between the first end of the first source and the first end of the first drain, or the first distance is the distance between the second end of the first source and the second end of the first drain. Figure 1 In addition to the structure shown in , the second distance can also be the distance between the same positions of the second source and the second drain, that is, the second distance is the distance between the first end of the second source and the first end of the second drain, or, the second distance is the distance between the second end of the second source and the second end of the second drain.

[0048] In some other embodiments, Figure 3As shown, along the extension direction of the first active layer 201, the straight length of the channel region of the first thin film transistor 20 is D1, and the channel region of the first thin film transistor 20 is the region where the first gate electrode 202 and the first active layer 201 overlap. Along the extension direction of the second active layer 301, the straight length of the channel region of the second thin film transistor 30 is D2, and the channel region of the second thin film transistor 30 is the region where the second gate electrode 302 and the second active layer 301 overlap, wherein D1≥D2. The straight length of the channel region of the first thin film transistor 20 is greater than or equal to the straight length of the channel region of the second thin film transistor 30, so that part of the first source 203 or the first drain 204 of the first thin film transistor 20 is not covered by the second thin film transistor 30, which is further beneficial to the subsequent punching overlap between the first pixel electrode 40 and the first source 203 or the first drain 204.

[0049] In another specific embodiment, Figure 3 As shown, when the shape of the channel region is a straight line, the above D1 is the length of the channel region of the first thin film transistor 20, and the above D2 is the length of the channel region of the second thin film transistor 30. In another specific embodiment, as Figure 4 As shown, the shape of the channel region is non-linear, therefore, the above D1 is the length of the distance between the starting point and the end point of the channel region of the first thin film transistor 20, and the above D2 is the length of the distance between the starting point and the end point of the channel region of the second thin film transistor 30.

[0050] In some embodiments, Figure 5 As shown, the channel length of the first thin film transistor 20 is equal to the channel length of the second thin film transistor 30. That is, D1=D2. Since the channel lengths of the first thin film transistor and the second thin film transistor are the same, the above configuration can further simplify the manufacturing process of the array substrate.

[0051] In some other embodiments, Figure 3As shown, along the extension direction of the first active layer 201, the sum of the width of the first source 203 and the width of the first drain 204 is greater than the sum of the width of the second source 303 and the width of the second drain 304. Along the extension direction of the first active layer 201, the width of the first source 203 is a first width W1, along the extension direction of the first active layer 201, the width of the first drain 204 is a second width W2, along the extension direction of the first active layer 201, the width of the second source 303 is a third width W3, along the extension direction of the first active layer 201, the width of the second drain 304 is a fourth width W4, the W1 and W3 may be equal or unequal, and the W2 and W4 may be equal or unequal. W1+W2>W3+W4, and D1≥D2, so W1+W2+D1>W3+W4+D2. It can be achieved that part of the first source 203 or the first drain 204 of the first thin film transistor 20 is not covered by the second thin film transistor 30 , which is further beneficial to the subsequent punching overlap between the first pixel electrode 40 and the first source 203 or the first drain 204 .

[0052] In another specific embodiment, Figure 1 As shown, the direction in which the first source electrode 203 points to the first drain electrode 204 is the same as the direction in which the second source electrode 303 points to the second drain electrode 404. That is, in the process of manufacturing the display substrate, the first thin film transistor 20 and the second thin film transistor 30 are placed in the same direction, and the above arrangement can further simplify the manufacturing process of the array substrate.

[0053] In another specific embodiment, Figure 6 As shown, the direction in which the first source electrode 203 points to the first drain electrode 204 is opposite to the direction in which the second source electrode 303 points to the second drain electrode 304. That is, the first source electrode 203 and the second drain electrode 304 are located on the same side of the active layer, and the first drain electrode 204 and the second source electrode 303 are located on the other side of the active layer. Since the first pixel electrode 40 is electrically connected to the first drain electrode 204, the second pixel electrode 50 is electrically connected to the second drain electrode 304, and the first drain electrode 204 and the second drain electrode 304 are located on different sides of the active layer, the distance between the first pixel electrode 40 and the second pixel electrode 50 can be increased, thereby reducing the crosstalk between the first pixel electrode 40 and the second pixel electrode 50, reducing the influence of electromagnetic interference on the display quality, and further improving the anti-interference ability of the display panel.

[0054] In some other embodiments, Figure 7As shown, the extension direction of the first active layer 201 and the extension direction of the second active layer 301 intersect, which includes two situations: the extension direction of the first active layer 201 and the extension direction of the second active layer 301 intersect, and the extension direction of the first active layer 201 and the extension direction of the second active layer 301 are perpendicular. The extension direction is the direction from the source region to the drain region. In other words, the orthographic projection of the first source 203 on the substrate 10 does not overlap with the orthographic projection of the second source 303 or the second drain 304, and the orthographic projection of the first drain 204 on the substrate 10 does not overlap with the orthographic projection of the second source 303 or the second drain 304, thereby increasing the distance between the first source 203 and the second source 303 or the second drain 304 and the distance between the first drain 204 and the second source 303 or the second drain 304, reducing the risk of short circuit between the first source and the second source and the drain, and further improving the performance of the first thin film transistor and the second thin film transistor.

[0055] In some embodiments, Figure 7 As shown, along the extension direction of the first active layer 201, the straight length of the channel region of the first thin film transistor 20 is D1, and the channel region of the first thin film transistor 20 is the region where the first gate and the first active layer overlap; along the extension direction of the second active layer, the straight length of the channel region of the second thin film transistor is D2, and the channel region of the second thin film transistor is the region where the second gate and the second active layer overlap; wherein, D1=D2. Since the channel lengths of the first thin film transistor and the second thin film transistor are the same, the above arrangement can further simplify the manufacturing process of the array substrate.

[0056] Specifically, the shape of the channel region is non-linear, therefore, the above D1 is the length of the distance between the start point and the end point of the channel region of the first thin film transistor 20 , and the above D2 is the length of the distance between the start point and the end point of the channel region of the second thin film transistor 30 .

[0057] In some other embodiments, Figure 7 As shown, the channel length of the first thin film transistor 20 is equal to the channel length of the second thin film transistor 30. That is, D1=D2. Since the channel lengths of the first thin film transistor and the second thin film transistor are the same, the above configuration can further simplify the manufacturing process of the array substrate.

[0058] Specifically, when the shape of the channel region is a straight line, the above D1 is the length of the channel region of the first thin film transistor, and the above D2 is the length of the channel region of the second thin film transistor.

[0059] In another specific embodiment, Figure 8As shown, the first gate electrode 202 is located between the first active layer 201 and the second active layer 301, and / or the second gate electrode 302 is located between the first active layer 201 and the second active layer 301. In other words, the first thin film transistor 20 is a top gate structure, and the second thin film transistor 30 is a bottom gate structure, which can achieve better electric field distribution, so that the first thin film transistor 20 and the second thin film transistor 30 have a higher current density, thereby improving the performance of the device and further enhancing the display effect of the display panel.

[0060] In practical applications, the positions of the first gate and the second gate are not limited to the above positional relationship. The first gate may also be located between the first active layer and the substrate, that is, the first thin film transistor is a bottom gate structure. The second gate may also be located on the side of the second active layer away from the first active layer, that is, the second thin film transistor is a top gate structure. Furthermore, the first thin film transistor and / or the second thin film transistor may also adopt a dual-gate structure, that is, the first thin film transistor includes two first gates located on both sides of the first active layer, or the second thin film transistor includes two second gates located on both sides of the second active layer. Fig. 9 As shown, in the first thin film transistor 20, the first gate 202 is located between the first active layer 201 and the substrate 10; in the second thin film transistor 30, the second gate 302 is located on the side of the second active layer 301 away from the substrate 10. Fig.10 As shown, in the first thin film transistor 20, the first gate 202 is located between the first active layer 201 and the second active layer 301, and in the second thin film transistor 30, the second gate 302 is located on the side of the second active layer 301 away from the substrate 10. The top gate structure of the thin film transistor can reduce the cost by improving the photolithography process and obtain higher device characteristic parameters, such as a mobility of 1.6 cm 2 / V·s. In addition, the transistor adopts a bottom gate structure, and the opaque gate metal layer in the bottom gate can well block the backlight, preventing light from shining on the substrate to generate carriers and affecting the off-state current characteristics of the thin film transistor. In another embodiment, the first thin film transistor and the second thin film transistor can also adopt a dual-gate structure, that is, the first thin film transistor includes two first gates respectively located on both sides of the first active layer, and the second thin film transistor includes two second gates respectively located on both sides of the second active layer. Among them, the dual-gate structure can adjust the threshold voltage by adjusting the back gate voltage, which can increase the threshold stability of the device. In addition, the dual-gate structure can effectively reduce the feedback capacitance between the gate and the drain.

[0061] In some further embodiments, in a direction perpendicular to the plane where the substrate is located, the distance between the first pixel electrode and the first active layer is not equal to the distance between the second pixel electrode and the second active layer. Since the first pixel electrode and the second pixel electrode are located in the same layer, and the distance between the first pixel electrode and the first active layer is not equal to the distance between the second pixel electrode and the second active layer, the first active layer and the second active layer are located in different layers.

[0062] Specifically, the distance between the first pixel electrode and the first active layer may be greater than the distance between the second pixel electrode and the second active layer, and the distance between the first pixel electrode and the first active layer may be less than the distance between the second pixel electrode and the second active layer.

[0063] In some other embodiments, Fig.11 As shown, the array substrate further includes: a common electrode layer 60, located between the first pixel electrode and the second thin film transistor. The common electrode layer 60 includes a plurality of common electrodes, which can provide data voltages for applying display images and further control the display of each sub-pixel unit.

[0064] Specifically, the common electrode can be used to provide a reference voltage (eg, 0V), and the common electrode layer and the pixel electrode layer are arranged relative to each other, an electric field is formed between the common electrode and the pixel electrode, the liquid crystal molecules are twisted by the electric field, and the light propagation path is changed.

[0065] In another typical embodiment of the present application, a display panel is provided, comprising: any one of the above-mentioned array substrates.

[0066] In another typical embodiment of the present application, Fig.12 As shown, a display device is provided, comprising: any one of the above-mentioned display panels 100 .

[0067] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0068] 1) The array substrate of the present application is stacked with a first thin film transistor and a second thin film transistor, and connected to a first pixel electrode and a second pixel electrode respectively. When the number of thin film transistors is the same, the present solution can reduce the area occupied by the thin film transistors on the display panel, thereby reducing the area occupied by the array substrate, and finally reducing the area of ​​the display panel. The technical problem of how to miniaturize the display panel in the prior art is solved.

[0069] 2) The display panel of the present application includes an array substrate. By stacking a first thin film transistor and a second thin film transistor, and connecting the first pixel electrode and the second pixel electrode respectively, when the number of thin film transistors is the same, compared with the prior art, this solution can reduce the area occupied by the thin film transistors in the display panel, thereby reducing the area occupied by the array substrate, and finally reducing the area of ​​the display panel. This solves the technical problem of how to miniaturize the display panel in the prior art.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: The invention comprises a substrate, a first thin film transistor and a second thin film transistor located on one side of the substrate, wherein the first thin film transistor comprises a first active layer, a first gate electrode, a first source electrode and a first drain electrode, and the second thin film transistor comprises a second active layer, a second gate electrode, a second source electrode and a second drain electrode, and in a direction perpendicular to the plane where the substrate is located, the first active layer and the second active layer at least partially overlap, the first thin film transistor is connected to a first pixel electrode, the second thin film transistor is connected to a second pixel electrode, and the first pixel electrode and the second pixel electrode are located on the same layer.

2. The array substrate according to claim 1, characterized in that: The first active layer is located between the second active layer and the substrate.

3. The array substrate according to claim 2, characterized in that: An extension direction of the first active layer is the same as an extension direction of the second active layer, wherein the extension direction is a direction from the source region to the drain region.

4. The array substrate according to claim 3, characterized in that: The distance between the first source and the first drain is a first distance, the distance between the second source and the second drain is a second distance, and the first distance is greater than the second distance.

5. The array substrate according to claim 4, characterized in that: Along the extension direction of the first active layer, the straight-line length of the channel region of the first thin film transistor is D1, and the channel region of the first thin film transistor is the overlapping region of the first gate and the first active layer. Along the extension direction of the second active layer, the straight-line length of the channel region of the second thin film transistor is D2, and the channel region of the second thin film transistor is the overlapping region of the second gate and the second active layer, wherein D1≥D2.

6. The array substrate according to claim 5, characterized in that: A channel length of the first thin film transistor is equal to a channel length of the second thin film transistor.

7. The array substrate according to claim 5, characterized in that: Along an extension direction of the first active layer, a sum of a width of the first source electrode and a width of the first drain electrode is greater than a sum of a width of the second source electrode and a width of the second drain electrode.

8. The array substrate according to claim 3, characterized in that: The direction in which the first source points to the first drain is the same as the direction in which the second source points to the second drain.

9. The array substrate according to claim 3, characterized in that: The direction in which the first source points to the first drain is opposite to the direction in which the second source points to the second drain.

10. The array substrate according to claim 1, characterized in that: An extension direction of the first active layer intersects with an extension direction of the second active layer, wherein the extension direction is a direction from the source region to the drain region.

11. The array substrate according to claim 10, characterized in that: Along the extension direction of the first active layer, the straight-line length of the channel region of the first thin film transistor is D1, and the channel region of the first thin film transistor is the overlapping region of the first gate and the first active layer; along the extension direction of the second active layer, the straight-line length of the channel region of the second thin film transistor is D2, and the channel region of the second thin film transistor is the overlapping region of the second gate and the second active layer; wherein, D1=D2.

12. The array substrate according to claim 11, characterized in that: A channel length of the first thin film transistor is equal to a channel length of the second thin film transistor.

13. The array substrate according to claim 1, characterized in that: The first gate is located between the first active layer and the second active layer, and / or the second gate is located between the first active layer and the second active layer.

14. The array substrate according to claim 1, characterized in that: In a direction perpendicular to the plane where the substrate is located, a distance between the first pixel electrode and the first active layer is not equal to a distance between the second pixel electrode and the second active layer.

15. The array substrate according to claim 1, characterized in that: The array substrate further includes: The common electrode layer is located between the first pixel electrode and the second thin film transistor.

16. A display panel, characterized in that: The invention comprises the array substrate as claimed in any one of claims 1 to 15.

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