A high holding voltage bidirectional thyristor structure

Abstract

The invention discloses a high-maintaining voltage bidirectional thyristor structure, comprising a first P-type epitaxial layer and a second P-type epitaxial layer, characterized in that it also comprises a first N-type well doping type well region, wherein the first P-type epitaxial layer is provided with a first P-type high-voltage doping type well region, a first P-type semiconductor, a first N-type heavily doped active region and a first P-type heavily doped active region arranged side by side in sequence from the inside to the outside, the first P-type high-voltage doping type well region wraps the first P-type semiconductor, and the first P-type semiconductor wraps the first N-type heavily doped active region and the first P-type heavily doped active region; and the second P-type epitaxial layer is provided with a second P-type high-voltage doping type well region, a second P-type semiconductor, a second N-type heavily doped active region and a second P-type heavily doped active region arranged side by side in sequence from the inside to the outside. The invention reduces the effective emission area of ​​the intrinsic SCR, improves the maintaining voltage, and solves the problem that the existing SCR structure is prone to cause latch-up effect.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor technology, and in particular to a high-maintaining-voltage bidirectional thyristor structure. Background Art

[0002] Electrostatic discharge is one of the most common reasons for the failure of integrated circuit products. With the rapid development of semiconductor technology, high-voltage integrated circuits have become an important part of the integrated circuit industry and are widely used in power management, automotive electronics, etc. The harsh working environment of high-voltage integrated circuits has put forward higher design requirements for ESD protection devices, which need to meet the requirements of high voltage and high current resistance, and have a higher maintenance voltage, which is higher than the normal working voltage of the circuit, to fundamentally eliminate the risk of latch up.

[0003] The existing SCR (silicon controlled rectifier) ​​structure has a deep hysteresis characteristic, and its trigger voltage is generally much higher than the process gate oxide breakdown voltage, but it has a very low holding voltage and is prone to latch-up effect, which greatly limits its application in the high-voltage IC field.

[0004] Based on this, a bidirectional thyristor structure with a high holding voltage is needed to solve the problem that the existing SCR structure is prone to cause a latch effect. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a high holding voltage bidirectional thyristor structure to at least solve the problem that the existing SCR structure is prone to cause a latch-up effect.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] The embodiment of the present invention provides a high holding voltage bidirectional thyristor structure, comprising a first P-type epitaxial layer, a second P-type epitaxial layer, and a first N-type well doping type well region stacked between the first P-type epitaxial layer and the second P-type epitaxial layer.

[0008] The first P-type epitaxial layer is provided with a first P-type high-voltage doped well region, a first P-type semiconductor, a first N-type heavily doped active region and a first P-type heavily doped active region arranged side by side in sequence from inside to outside, the first P-type high-voltage doped well region wraps the first P-type semiconductor, and the first P-type semiconductor wraps the first N-type heavily doped active region and the first P-type heavily doped active region;

[0009] The second P-type epitaxial layer is provided with a second P-type high-voltage doped well region, a second P-type semiconductor, a second N-type heavily doped active region and a second P-type heavily doped active region arranged side by side from the inside to the outside, the second P-type high-voltage doped well region wraps the second P-type semiconductor, and the second P-type semiconductor wraps the second N-type heavily doped active region and the second P-type heavily doped active region;

[0010] Among them, the first N-type heavily doped active area, the first P-type semiconductor, the first P-type high-voltage doped type well area, the first P-type epitaxial layer, and the first N-type well-doped type well area constitute a first triode; the second N-type heavily doped active area, the second P-type semiconductor, the second P-type high-voltage doped type well area, the second P-type epitaxial layer, and the first N-type well-doped type well area constitute a second triode; the first P-type heavily doped active area, the first P-type semiconductor, the first P-type high-voltage doped type well area, the first P-type epitaxial layer, the first N-type well-doped type well area, the second P-type epitaxial layer, the second P-type high-voltage doped type well area, the second P-type semiconductor, and the second P-type heavily doped active area constitute a bidirectional third triode.

[0011] Further, the emitter of the first triode is connected to port T1, the emitter of the second triode is connected to port T2, the collectors of the first triode and the second triode are connected and then connected to the base of the third triode, and the two emitters of the third triode are respectively connected to the base of the first triode and the base of the second triode.

[0012] Furthermore, the emitter region of the first transistor includes the first N-type heavily doped active region, and the first N-type heavily doped active region is connected to the port T1.

[0013] Furthermore, the base of the first transistor is connected to the port T1 via a first resistor.

[0014] Furthermore, the emitter region of the second triode includes the second N-type heavily doped active region, and the second N-type heavily doped active region is connected to the port T2.

[0015] Furthermore, the base of the second transistor is connected to the port T2 via a second resistor.

[0016] Furthermore, a diode is formed between the first N-type well-doping type well region and the second P-type epitaxial layer.

[0017] Furthermore, it also includes a shallow trench isolation STI region, which is formed at the top of the first P-type epitaxial layer, the second P-type epitaxial layer and the first N-type well-doped type well region, and isolates the first N-type heavily doped active region, the first P-type heavily doped active region, the second N-type heavily doped active region and the second P-type heavily doped active region, and cooperates with the first P-type semiconductor to surround the first N-type heavily doped active region and the first P-type heavily doped active region, and cooperates with the second P-type semiconductor to surround the second N-type heavily doped active region and the second P-type heavily doped active region.

[0018] Furthermore, it also includes an N-type heavily doped well region, two second N-type well doping type well regions and two third N-type well doping type well regions;

[0019] The N-type heavily doped well region is provided at the bottom of the first P-type epitaxial layer, the first N-type well-doped type well region and the second P-type epitaxial layer, the two second N-type well-doped type well regions are provided at both ends of the N-type heavily doped well region, and are located on the side of the first P-type epitaxial layer and the second P-type epitaxial layer away from the first N-type well-doped type well region, and the two third N-type well-doped type well regions are provided at the top of the two second N-type well-doped type well regions, and are located at the bottom of the shallow trench isolation STI region.

[0020] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0021] A high-maintaining-voltage bidirectional thyristor structure of the present invention, in the process of carriers being transported from the first N-type heavily doped active region at the port T1 end to the port T2, will expand to the second P-type heavily doped active regions on both sides, forming an SCR with stronger electrostatic discharge protection capability, and it will experience a longer path, and the carriers are continuously recombined in this process, and the concentration is continuously reduced, thereby reducing the effective emission area of ​​the intrinsic SCR, and its maintaining voltage is increased accordingly, thereby solving the problem that the existing SCR structure is prone to cause a latch effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A side cross-sectional view of a high holding voltage bidirectional thyristor structure according to an embodiment of the present invention;

[0024] Figure 2 A top view of a high holding voltage bidirectional thyristor structure according to an embodiment of the present invention;

[0025] Figure 3 is a circuit diagram of a first triode, a second triode and a third triode according to an embodiment of the present invention;

[0026] Figure 4 FIG. 4 is an IV diagram of a high holding voltage bidirectional thyristor structure according to an embodiment of the present invention.

[0027] The reference numerals of the embodiments of the present invention are as follows:

[0028] 10, first transistor; 20, second transistor; 30, third transistor; 40, first resistor; 50, second resistor;

[0029] 100, substrate; 101, second N-type well doping type well region; 102, third N-type well doping type well region; 103, first P-type epitaxial layer; 104, first P-type high voltage doping type well region; 105, first P-type semiconductor; 106, first N-type heavily doped active region; 107, first P-type heavily doped active region;

[0030] 203, second P-type epitaxial layer; 204, second P-type high-voltage doping type well region; 205, second P-type semiconductor; 206, second N-type heavily doped active region; 207, second P-type heavily doped active region;

[0031] 301 , N-type heavily doped well region; 302 ˜ 304 , shallow trench isolation STI regions; 305 , first N-type well doping type well region. DETAILED DESCRIPTION

[0032] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0033] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0034] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0035] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0036] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0037] Currently, the most common way to increase the holding voltage is to reduce the emitter injection efficiency to weaken the positive feedback effect of the parasitic transistor. However, these methods sacrifice the robustness of the device in exchange for a high holding voltage, and often increase the process level, sacrifice the layout area, and increase the manufacturing cost.

[0038] A more effective way to increase the holding voltage is to introduce a device shunt path in the SCR structure (silicon controlled rectifier) ​​to weaken the positive feedback effect of the parasitic NPN and PNP transistors, thereby achieving the purpose of increasing the holding voltage. In addition, the high holding voltage solutions currently proposed for single devices are often only effective for medium and low voltage windows, and are far from meeting the ESD (electrostatic discharge) design window requirements in high-voltage integrated circuits.

[0039] Another relatively effective method is the ESD device stacking technology. The stacking structure is composed of multiple ESD protection devices connected in series, and its maintenance voltage is the sum of the maintenance voltages of the multiple ESD protection devices used. This can effectively solve the problem of insufficient maintenance voltage of a single SCR structure. However, the stacking technology also has defects. As the number of stacked devices increases, its trigger voltage also increases, which may exceed the upper limit of the window of the protection device. In addition, due to the stacking of multiple ESD devices, its opening speed is reduced, and it is difficult to respond quickly to fast ESD events to play an effective role.

[0040] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0041] like Figures 1 to 4 As shown, a high-maintenance voltage bidirectional thyristor structure of the present invention can be obtained based on a common size process, such as based on a 180nm BCD (bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor) process. The high-maintenance voltage thyristor device used for ESD protection of high-voltage integrated circuits can meet the actual ESD protection heavy-maintenance voltage design requirements, have extremely high current discharge efficiency, and flexibly adjust the overall current discharge capacity by connecting multiple transistors in parallel, meeting the design requirements of ESD protection of high-voltage integrated circuits above 40V.

[0042] The thyristor structure includes an epitaxial layer, and the epitaxial layer is divided into a first P-type epitaxial layer 103 and a second P-type epitaxial layer 203 according to different distribution areas of the first triode 10 and the second triode 20 .

[0043] The first P-type epitaxial layer 103 is used for depositing semiconductor materials related to the first transistor 10 , and the second P-type epitaxial layer 104 is used for depositing semiconductor materials related to the second transistor 20 .

[0044] The thyristor structure further includes a first N-type well-doping type well region 305 which is located between the first P-type epitaxial layer 103 and the second P-type epitaxial layer 203 and is stacked.

[0045] Specifically, the first P-type epitaxial layer 103 and the second P-type epitaxial layer 203 are both P-type epitaxial layers inherent to the BCD process, and are disposed on the substrate 100 .

[0046] The first N-type well-doping type well region 305 is used to form collectors of the first transistor 10 and the second transistor 20 , and is used to form a base of the third transistor 30 .

[0047] The first P-type epitaxial layer 103 is provided with a first P-type high-voltage doped type well region 104, a first P-type semiconductor 105, a first N-type heavily doped active region 106 and a first P-type heavily doped active region 107 arranged side by side in sequence from the inside to the outside, the first P-type high-voltage doped type well region 104 wraps the first P-type semiconductor 105, and the first P-type semiconductor 105 wraps the first N-type heavily doped active region 106 and the first P-type heavily doped active region 107; the second P-type epitaxial layer 203 is provided with a second P-type high-voltage doped type well region 204, a second P-type semiconductor 205, a second N-type heavily doped active region 206 and a second P-type heavily doped active region 207 arranged side by side in sequence from the inside to the outside, the second P-type high-voltage doped type well region 204 wraps the second P-type semiconductor 205, and the second P-type semiconductor 205 wraps the second N-type heavily doped active region 206 and the second P-type heavily doped active region 207.

[0048] Among them, the first N-type heavily doped active area 106, the first P-type semiconductor 105, the first P-type high-voltage doped type well area 104, the first P-type epitaxial layer 103, and the first N-type well-doped type well area 305 constitute a first transistor 10; the second N-type heavily doped active area 206, the second P-type semiconductor 205, the second P-type high-voltage doped type well area 204, the second P-type epitaxial layer 203, and the first N-type well-doped type well area 305 constitute a second transistor 20; the first P-type heavily doped active area 107, the first P-type semiconductor 105, the first P-type high-voltage doped type well area 104, the first P-type epitaxial layer 103, the first N-type well-doped type well area 305, the second P-type epitaxial layer 203, the second P-type high-voltage doped type well area 204, the second P-type semiconductor 205 and the second P-type heavily doped active area 207 constitute a bidirectional third transistor 30.

[0049] The first N-type well-doping type well region 305 is used to prevent the port T1 and the port T2 from being directly connected, and also serves as a collector in the first transistor 10 and the second transistor 20 .

[0050] Furthermore, the emitter of the first triode 10 is connected to the port T1, the emitter of the second triode 20 is connected to the port T2, the collectors of the first triode 10 and the second triode 20 are connected and then connected to the base of the third triode 30, and the two emitters of the third triode 30 are respectively connected to the base of the first triode 10 and the base of the second triode 20.

[0051] Furthermore, the emitter region of the first transistor 10 includes a first N-type heavily doped active region 106 , and the first N-type heavily doped active region 106 is connected to the port T1 .

[0052] Furthermore, the base of the first transistor 10 is connected to the port T1 through the first resistor 40 .

[0053] Furthermore, the emitter region of the second transistor 20 includes a second N-type heavily doped active region 206 , and the second N-type heavily doped active region 206 is connected to the port T2 .

[0054] Furthermore, the base of the second transistor 20 is connected to the port T2 via the second resistor 50 .

[0055] Furthermore, a diode is formed between the first N-type well-doped type well region 305 and the second P-type epitaxial layer 203, which is used to generate avalanche breakdown and form avalanche current to reduce the potential of the first N-type well-doped type well region 305 when a forward ESD pulse enters from port T1.

[0056] Furthermore, it also includes shallow trench isolation STI regions (302, 303, 304), which are formed at the top of the first P-type epitaxial layer 103, the second P-type epitaxial layer 203 and the first N-type well-doped type well region 305, and isolate the first N-type heavily doped active region 106, the first P-type heavily doped active region 107, the second N-type heavily doped active region 206 and the second P-type heavily doped active region 207, and cooperate with the first P-type semiconductor 105 to surround the first N-type heavily doped active region 106 and the first P-type heavily doped active region 107, and cooperate with the second P-type semiconductor 205 to surround the second N-type heavily doped active region 206 and the second P-type heavily doped active region 207.

[0057] Among them, the shallow trench isolation (STI) region is used to separate different devices or regions on a semiconductor wafer to prevent parasitic effects.

[0058] Furthermore, it also includes an N-type heavily doped well region 301, two second N-type well-doped type well regions 101 and two third N-type well-doped type well regions 102; the N-type heavily doped well region 301 is provided at the bottom of the first P-type epitaxial layer 103 and the second P-type epitaxial layer 203, the two second N-type well-doped type well regions 101 are provided at both ends of the N-type heavily doped well region 301, and are located on the side of the first P-type epitaxial layer 103 and the second P-type epitaxial layer 203 away from the first N-type well-doped type well region 305, and the two third N-type well-doped type well regions 102 are provided at the top of the two second N-type well-doped type well regions 101, and are located at the bottom of the shallow trench isolation STI region.

[0059] The N-type heavily doped well region 301 and the second N-type well doping type well region 101 are used for isolation.

[0060] The first N-type well-doping type well region 305 and the second N-type well-doping type well region 101 are used as the pickup layer of the bottom N-type heavily doped well region 301 to form a wrapping ring with the bottom N-type heavily doped buried layer. In order to ensure the concentration of the first N-type well-doping type well region 305 and the second N-type well-doping type well region 101 and the STI, a third N-type well-doping type well region 102 is added to form isolation to prevent T1 and T2 from being directly turned on.

[0061] The working principle of the present invention is as follows:

[0062] When a positive ESD pulse enters from port T1, the diode formed by the first N-type well-doped type well region 305 and the second P-type epitaxial layer 203 first undergoes avalanche breakdown to form an avalanche current. When the avalanche current flows to port T2, the potential of the first N-type well-doped type well region 305 is reduced, thereby causing the emitter junction of the third transistor 30 to be forward-biased, so that the third transistor 30 is turned on. As the current increases, after a voltage drop of 0.7V is generated on the second resistor 50, the emitter junction of the second transistor 20 is forward-biased, and the second transistor 20 is turned on at this time. Finally, the second transistor 20 and the third transistor 30 form a current positive feedback, thereby constructing a low-resistance SCR discharge path. Similarly, when a negative ESD pulse enters from port T1, the first transistor 10 and the third transistor 30 will form a low-resistance SCR path with current positive feedback.

[0063] In the structure of the present invention, by designing Figure 3 In the plan view, the first N-type heavily doped active area 106 and the first P-type heavily doped active area 107, the second N-type heavily doped active area 206 and the second P-type heavily doped active area 207 form an N, P-type heavily doped block structure, and are wrapped by the first P-type high-voltage doped type well area 104 and the first P-type semiconductor 105, the second P-type high-voltage doped type well area 204 and the second P-type semiconductor 205 P-type well. When the carriers are transported from the first N-type heavily doped active area 106 of the port T1 to the port T2, they will expand to the second P-type heavily doped active area 207 to form an SCR with stronger ESD protection capability, and will experience a longer path. The carriers are constantly recombined in this process, and the concentration is continuously reduced, thereby reducing the effective emission area of ​​the intrinsic SCR, and its holding voltage is increased accordingly.

[0064] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0065] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A high holding voltage bidirectional thyristor structure, comprising a first P-type epitaxial layer and a second P-type epitaxial layer, characterized in that: It also includes a first N-type well-doping type well region stacked between the first P-type epitaxial layer and the second P-type epitaxial layer. The first P-type epitaxial layer is provided with a first P-type high-voltage doped well region, a first P-type semiconductor, a first N-type heavily doped active region and a first P-type heavily doped active region arranged side by side in sequence from inside to outside, the first P-type high-voltage doped well region wraps the first P-type semiconductor, and the first P-type semiconductor wraps the first N-type heavily doped active region and the first P-type heavily doped active region; The second P-type epitaxial layer is provided with a second P-type high-voltage doped well region, a second P-type semiconductor, a second N-type heavily doped active region and a second P-type heavily doped active region arranged side by side from the inside to the outside, the second P-type high-voltage doped well region wraps the second P-type semiconductor, and the second P-type semiconductor wraps the second N-type heavily doped active region and the second P-type heavily doped active region; Among them, the first N-type heavily doped active area, the first P-type semiconductor, the first P-type high-voltage doped type well area, the first P-type epitaxial layer, and the first N-type well-doped type well area constitute a first triode; the second N-type heavily doped active area, the second P-type semiconductor, the second P-type high-voltage doped type well area, the second P-type epitaxial layer, and the first N-type well-doped type well area constitute a second triode; the first P-type heavily doped active area, the first P-type semiconductor, the first P-type high-voltage doped type well area, the first P-type epitaxial layer, the first N-type well-doped type well area, the second P-type epitaxial layer, the second P-type high-voltage doped type well area, the second P-type semiconductor, and the second P-type heavily doped active area constitute a bidirectional third triode.

2. The high sustaining voltage bidirectional thyristor structure according to claim 1, characterized in that: The emitter of the first triode is connected to the port T1, the emitter of the second triode is connected to the port T2, the collectors of the first triode and the second triode are connected and then connected to the base of the third triode, and the two emitters of the third triode are respectively connected to the base of the first triode and the base of the second triode.

3. The high sustaining voltage bidirectional thyristor structure according to claim 2, characterized in that: The emitter region of the first transistor includes the first N-type heavily doped active region, and the first N-type heavily doped active region is connected to the port T1.

4. The high sustaining voltage bidirectional thyristor structure according to claim 3, characterized in that: The base of the first transistor is connected to the port T1 through a first resistor.

5. The high sustaining voltage bidirectional thyristor structure according to claim 4, characterized in that: The emitter region of the second transistor includes the second N-type heavily doped active region, and the second N-type heavily doped active region is connected to the port T2.

6. The high sustaining voltage bidirectional thyristor structure according to claim 5, characterized in that: The base of the second transistor is connected to the port T2 via a second resistor.

7. The high sustaining voltage bidirectional thyristor structure according to claim 1, characterized in that: A diode is formed between the first N-type well-doping type well region and the second P-type epitaxial layer.

8. The high sustaining voltage bidirectional thyristor structure according to any one of claims 1 to 7, characterized in that: It also includes a shallow trench isolation STI region, which is formed at the top of the first P-type epitaxial layer, the second P-type epitaxial layer and the first N-type well-doped type well region, and isolates the first N-type heavily doped active region, the first P-type heavily doped active region, the second N-type heavily doped active region and the second P-type heavily doped active region, and cooperates with the first P-type semiconductor to surround the first N-type heavily doped active region and the first P-type heavily doped active region, and cooperates with the second P-type semiconductor to surround the second N-type heavily doped active region and the second P-type heavily doped active region.

9. The high sustaining voltage bidirectional thyristor structure according to claim 8, characterized in that: It also includes an N-type heavily doped well region, two second N-type well doping type well regions, and two third N-type well doping type well regions; The N-type heavily doped well region is provided at the bottom of the first P-type epitaxial layer, the first N-type well-doped type well region and the second P-type epitaxial layer, the two second N-type well-doped type well regions are provided at both ends of the N-type heavily doped well region, and are located on the side of the first P-type epitaxial layer and the second P-type epitaxial layer away from the first N-type well-doped type well region, and the two third N-type well-doped type well regions are provided at the top of the two second N-type well-doped type well regions, and are located at the bottom of the shallow trench isolation STI region.

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