A bidirectional gate controlled silicon controlled structure

Abstract

The present invention discloses a bidirectional gate-controlled thyristor structure, characterized in that it includes a P-type epitaxial layer, a first N-type well-doped type well region and a first N-type deep well-doped type well region arranged in a stacked manner are formed in the middle of the P-type epitaxial layer to separate the P-type epitaxial layer into a first P-epi and a second P-epi; a first P-type high-voltage doped type well region is formed in the injection region on the first P-epi, a first P-type well-doped type well region is formed in the injection region on the first P-type high-voltage doped type well region, and a first P-type well-doped type well region is provided at the top of the first P-type well-doped type well region along its own length direction with a first P-type heavily doped active region and multiple groups of second P-type heavily doped active regions and a first N-type heavily doped active region arranged in parallel, wherein the first P-type heavily doped active region and multiple groups of second P-type heavily doped active regions and the first N-type heavily doped active region are isolated and arranged. The present invention integrates a gate-controlled structure in a segmented structure, and improves its current discharge capability by controlling the carrier transport path.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a bidirectional gate-controlled thyristor structure. Background Art

[0002] The harsh working environment of high-voltage integrated circuits places higher design requirements on ESD protection devices, which need to withstand high voltage and large current, and have a higher sustaining voltage to fundamentally eliminate the latch-up effect.

[0003] The existing method is the ESD (electrostatic discharge) protection device stacking technology. The stacking structure is composed of multiple ESD protection devices connected in series, and its maintenance voltage is the sum of the maintenance voltages of the multiple ESD protection devices used. This can effectively solve the problem of insufficient maintenance voltage of a single SCR structure. However, the stacking technology also has defects. As the number of stacked devices increases, its trigger voltage also increases and may exceed the window upper limit of the protection device. In addition, due to the stacking of multiple ESD devices, its opening speed is reduced, and it is difficult to respond quickly to fast ESD events to play an effective role.

[0004] Based on this, a new thyristor structure is needed to improve the holding voltage while solving the defects of the existing stacking technology. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a bidirectional gate-controlled thyristor structure to at least solve the defects of the existing ESD (electrostatic discharge) protection device stacking technology.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a bidirectional gate controlled thyristor structure, comprising a P-type epitaxial layer, a first N-type well doping type well region and a first N-type deep well doping type well region arranged in a stacked manner are formed in the middle of the P-type epitaxial layer to separate the P-type epitaxial layer into a first P-epi and a second P-epi; a first P-type high voltage doping type well region is formed in an injection region on the first P-epi, a first P-type well doping type well region is formed in an injection region on the first P-type high voltage doping type well region, a first P-type well doping type well region is formed in a top portion of the first P-type well doping type well region along its length direction, a first P-type heavily doped active region and a plurality of groups of second P-type heavily doped active regions and a first N-type heavily doped active region are arranged in parallel, wherein the first P-type heavily doped active region and the plurality of groups of second The P-type heavily doped active region and the first N-type heavily doped active region are isolated from each other, and the first P-type heavily doped active region and the first N-type heavily doped active region are isolated from each other; a second P-type high-voltage doped type well region is formed in the injection region on the second P-epi, a second P-type well-doped type well region is formed in the injection region on the second P-type high-voltage doped type well region, and a third P-type heavily doped active region and a plurality of groups of fourth P-type heavily doped active regions and a second N-type heavily doped active region are arranged at the top of the second P-type well-doped type well region along its length direction, wherein the third P-type heavily doped active region and the plurality of groups of fourth P-type heavily doped active regions and the second N-type heavily doped active region are isolated from each other, and the fourth P-type heavily doped active region and the second N-type heavily doped active region are isolated from each other.

[0008] Further, the first N-type heavily doped active region, the first P-type well doping type well region, the first P-type high voltage doping type well region, the first P-epi, the first N-type well doping type well region and the first N-type deep well doping type well region constitute a first triode; the second N-type heavily doped active region, the second P-type well doping type well region, the second P-epi, the first N-type well doping type well region and the first N-type deep well doping type well region constitute a second triode; the second P-type heavily doped active region, the second P-type well doping type well region, the second P-epi, the first N-type well doping type well region and the first N-type deep well doping type well region constitute a second triode; The source region, the first P-type heavily doped active region, the first P-type well doping type well region, the first P-type high voltage doping type well region, the first P-epi, the first N-type well doping type well region, the first N-type deep well doping type well region, the second P-epi, the second P-type high voltage doping type well region, the second P-type well doping type well region, the fourth P-type heavily doped active region and the third P-type heavily doped active region constitute a third transistor; wherein the first transistor and the second transistor are NPN transistors, and the third transistor is a bidirectional PNP transistor.

[0009] Furthermore, a third N-type heavily doped active region and a fourth N-type heavily doped active region are arranged at intervals along the length direction of the first N-type well-doping type well region, and the third N-type heavily doped active region and the fourth N-type heavily doped active region are isolated by a shallow trench isolation STI region.

[0010] Furthermore, the first P-type heavily doped active region and multiple groups of second P-type heavily doped active regions and the first N-type heavily doped active region, the first P-type heavily doped active region and the first N-type heavily doped active region, the third P-type heavily doped active region and multiple groups of fourth P-type heavily doped active regions and the second N-type heavily doped active region, and the fourth P-type heavily doped active region and the second N-type heavily doped active region are all isolated by shallow trench isolation (STI) regions.

[0011] Furthermore, the third N-type heavily doped active region and the first P-type heavily doped active region are isolated by a shallow trench isolation (STI) region; the fourth N-type heavily doped active region and the third P-type heavily doped active region are isolated by a shallow trench isolation (STI) region.

[0012] Furthermore, it also includes a first polysilicon gate and a second polysilicon gate; the first polysilicon gate is arranged at the top of the shallow trench isolation STI region between the second P-type heavily doped active region and the first N-type heavily doped active region; the second polysilicon gate is arranged at the top of the shallow trench isolation STI region between the fourth P-type heavily doped active region and the second N-type heavily doped active region.

[0013] Furthermore, it also includes a first port T1 and a second port T2; the first port T1 is respectively connected to the second P-type heavily doped active area, the first N-type heavily doped active area and the first polysilicon gate; the second port T2 is respectively connected to the fourth P-type heavily doped active area, the second N-type heavily doped active area and the second polysilicon gate.

[0014] Furthermore, the bidirectional gate-controlled thyristor structure also includes a deep N-type heavily doped well region, a second N-type deep well doping type well region, and a second N-type well doping type well region; the deep N-type heavily doped well region is arranged at the bottom of the first P-epi, the second P-epi and the first N-type deep well doping type well region; the second N-type deep well doping type well region is arranged around the edge of the deep N-type heavily doped type well region, and surrounds the first P-epi and the second P-epi; the second N-type weill doping type well region is located at the top of the second N-type deep well doping type well region.

[0015] Furthermore, the base of the first transistor is connected to the first port through a first resistor.

[0016] Furthermore, the base of the second transistor is connected to the second port through a second resistor.

[0017] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0018] A bidirectional gate-controlled thyristor structure of the present invention adopts a segmented structure for a high-maintaining voltage SCR device for ESD protection of a high-voltage integrated circuit, and integrates a gate control structure in the segmented structure to improve its current discharge capability by controlling the carrier transport path. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A side cross-sectional view of a bidirectional gate-controlled thyristor structure according to an embodiment of the present invention;

[0021] Figure 2 A top view of a bidirectional gate-controlled thyristor structure according to an embodiment of the present invention;

[0022] Figure 3 is a circuit diagram of a first triode, a second triode and a third triode according to an embodiment of the present invention;

[0023] Figure 4 This is an IV diagram of a bidirectional gate-controlled thyristor structure according to an embodiment of the present invention.

[0024] The accompanying drawings of the present invention are as follows:

[0025] 101, second N-type deep well doping type well region; 102, second N-type well doping type well region; 103, first P-epi; 104, first P-type high voltage doping type well region; 105, first P-type well doping type well region; 106, first P-type heavily doped active region; 107, first N-type heavily doped active region; 108, second P-type heavily doped active region; 109, third N-type heavily doped active region;

[0026] 203, second P-epi; 204, second P-type high voltage doping type well region; 205, second P-type well doping type well region; 206, fourth P-type heavily doped active region; 207, second N-type heavily doped active region; 208, third P-type heavily doped active region; 209, fourth N-type heavily doped active region;

[0027] 301, deep N-type heavily doped well region; 302, shallow trench isolation STI region;

[0028] 401, a first N-type well doping type well region; 402, a first N-type deep well doping type well region; 403, a first polysilicon gate; 404, a second polysilicon gate. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0030] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0031] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0032] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0033] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0034] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0035] like Figures 1 to 4As shown, a bidirectional gate-controlled thyristor structure of the present invention can be applicable to common size processes, such as 130nm process, 180nm BCD process, etc., and adopts a segmented structure to provide a high-maintaining voltage SCR device for ESD protection of high-voltage integrated circuits, and integrates a gate control structure in the segmented structure to control the carrier transport path, thereby improving its current discharge capability.

[0036] Specifically, the bidirectional gate controlled thyristor structure includes a P-type epitaxial layer, and a first N-type well doping type well region 401 and a first N-type deep well doping type well region 402 are stacked and arranged in the middle of the P-type epitaxial layer to separate the P-type epitaxial layer into a first P-epi 103 and a second P-epi 203; the first P-epi A first P-type high-voltage doped well region 104 is formed in the injection region on 103, a first P-type well doped well region 105 is formed in the injection region on the first P-type high-voltage doped well region 104, a first P-type well doped well region 105 is provided at the top of the first P-type well doped well region 105 along its length direction with a first P-type heavily doped active region 106 and a plurality of groups of second P-type heavily doped active regions 108 and a first N-type heavily doped active region 107 arranged in parallel, wherein the first P-type heavily doped active region 106 and the plurality of groups of second P-type heavily doped active regions 108 and the first N-type heavily doped active region 107 are arranged in isolation, and the first P-type heavily doped active region 106 and the first N-type heavily doped active region 107 are arranged in isolation; a second P-epi A second P-type high-voltage doped type well region 204 is formed in the injection region on 203, a second P-type well-doped type well region 205 is formed in the injection region on the second P-type high-voltage doped type well region 204, and a third P-type heavily doped active region 208 and a plurality of groups of fourth P-type heavily doped active regions 206 and a second N-type heavily doped active region 207 are arranged at the top of the second P-type well-doped type well region 205 along its own length direction, wherein the third P-type heavily doped active region 208 and the plurality of groups of fourth P-type heavily doped active regions 206 and the second N-type heavily doped active region 207 are arranged in isolation, and the fourth P-type heavily doped active region 206 and the second N-type heavily doped active region 207 are arranged in isolation.

[0037] The bidirectional gate thyristor structure further includes a substrate 100 , and the substrate 100 is used to form a P-type epitaxial layer.

[0038] The implantation region is a specific region in the single crystal silicon structure where N-type or P-type ions are implanted under a high energy electric field. The N-type or P-type ions are mainly implanted by ion doping implantation.

[0039] Further, the first N-type heavily doped active region 107, the first P-type well doping type well region 105, the first P-type high voltage doping type well region 104, the first P-epi 103, the first N-type well doping type well region 401 and the first N-type deep well doping type well region 402 constitute a first transistor Q1; the second N-type heavily doped active region 207, the second P-type well doping type well region 205, the second P-type high voltage doping type well region 204, the second P-epi 203, the first N-type well doping type well region 401 and the first N-type deep well doping type well region 402 constitute a second transistor Q2; the second P-type heavily doped active region 108, the first P-type heavily doped active region 106, the first P-type well doping type well region 105, the first P-type high voltage doping type well region 104, the first P-epi 103, the first N-type well doping type well region 401, the first N-type deep well doping type well region 402, the second P-epi 203, the second P-type high voltage doping type well region 204, the second P-type well doping type well region 205, the fourth P-type heavily doped active region 206 and the third P-type heavily doped active region 208 constitute a third transistor Q3; wherein, the first transistor Q1 and the second transistor Q2 are NPN transistors, and the third transistor Q3 is a bidirectional PNP transistor.

[0040] The first transistor Q1 and the second transistor Q2 are used to form a conductive path under forward or reverse ESD impact to control the initial current flow. The third transistor Q3 is used to provide a low-resistance SCR discharge path during bidirectional current flow.

[0041] A low-resistance conductive path is established between the first transistor Q1, the second transistor Q2 and the third transistor Q3 of the present invention through positive feedback to enhance the discharge capacity.

[0042] Furthermore, a third N-type heavily doped active region 109 and a fourth N-type heavily doped active region 209 are spaced apart at the top of the first N-type well-doping type well region 401 along its own length direction, and the third N-type heavily doped active region 109 and the fourth N-type heavily doped active region 209 are isolated by a shallow trench isolation STI region 302.

[0043] Furthermore, the first P-type heavily doped active region 106 and multiple groups of second P-type heavily doped active regions 108 and the first N-type heavily doped active region 107, the first P-type heavily doped active region 106 and the first N-type heavily doped active region 107, the third P-type heavily doped active region 208 and multiple groups of fourth P-type heavily doped active regions 206 and the second N-type heavily doped active regions 207, and the fourth P-type heavily doped active region 206 and the second N-type heavily doped active region 207 are all isolated by shallow trench isolation STI regions 302.

[0044] Furthermore, the third N-type heavily doped active region 109 and the first P-type heavily doped active region 106 are isolated by a shallow trench isolation STI region 302 ; the fourth N-type heavily doped active region 209 and the third P-type heavily doped active region 208 are isolated by a shallow trench isolation STI region 302 .

[0045] In the present invention, shallow trench isolation (STI) regions 302 are used for isolation to reduce parasitic effects and improve device performance and reliability.

[0046] Furthermore, it also includes a first polysilicon gate 403 and a second polysilicon gate 404; the first polysilicon gate 403 is arranged at the top of the shallow trench isolation STI region 302 between the second P-type heavily doped active region 108 and the first N-type heavily doped active region 107; the second polysilicon gate 404 is arranged at the top of the shallow trench isolation STI region 302 between the fourth P-type heavily doped active region 206 and the second N-type heavily doped active region 207.

[0047] The first polysilicon gate 403 and the second polysilicon gate 404 of the present invention are used to regulate the transport path of deep-layer carriers, and enhance the electric field to accelerate hole transport, thereby improving the overall current discharge capability.

[0048] Furthermore, it also includes a first port T1 and a second port T2; the first port T1 is respectively connected to the second P-type heavily doped active area 108, the first N-type heavily doped active area 107 and the first polysilicon gate 403; the second port T2 is respectively connected to the fourth P-type heavily doped active area 206, the second N-type heavily doped active area 207 and the second polysilicon gate 404.

[0049] Furthermore, the bidirectional gate-controlled thyristor structure also includes a deep N-type heavily doped well region 301, a second N-type deep well doping type well region 101, and a second N-type well doping type well region 102; the deep N-type heavily doped well region 301 is arranged at the bottom of the first P-epi 103, the second P-epi 203 and the first N-type deep well doping type well region 402; the second N-type deep well doping type well region 101 is arranged around the edge of the deep N-type heavily doped type well region, and surrounds the first P-epi 103 and the second P-epi203; the second N-type weill doping type well region is located at the top of the second N-type deep well doping type well region.

[0050] The first N-type deep well doping type well region 402 and the second N-type deep well doping type well region 101 are used as the pickup layer of the bottom deep N-type heavily doped well region 301 to form a wrapping ring with the bottom deep N-type heavily doped buried layer. In order to ensure the concentration of the first N-type deep well doping type well region 402 and the second N-type deep well doping type well region 101 and the STI, the second N-type well doping type well region 102 is added to form isolation to prevent T1 and T2 from being directly turned on.

[0051] Furthermore, the base of the first transistor Q1 is connected to the first port via the first resistor R1.

[0052] Furthermore, the base of the second transistor Q2 is connected to the second port via the second resistor R2.

[0053] The working principle of the present invention is as follows:

[0054] When a forward ESD pulse enters from the first port T1, the diode formed by the first N-type well doped type well region 401 and the second P-epi203 first undergoes avalanche breakdown to form an avalanche current. In the process of the avalanche current flowing to the right end port, the potential of the deep N-type heavily doped well region 301 is reduced, thereby causing the emitter junction of the third transistor Q3 to be forward-conducted, so that the third transistor Q3 is turned on. As the current increases, when a voltage drop of 0.7V is generated on the second resistor R2, the emitter junction of the second transistor Q2 is forward-biased and turned on. At this time, the second transistor Q2 is turned on. After that, the second transistor Q2 and the third transistor Q3 form a current positive feedback, thereby constructing a low-resistance SCR discharge path. At the same time, the forward ESD pulse applied at the first port makes the first polysilicon gate 403 have the same high potential, which makes the P-type doped region below the first polysilicon gate 403 form a downward electric field, so that holes are transported from a deeper level, thereby improving its carrier transport efficiency. Similarly, when a negative ESD pulse enters from the first port, the first transistor Q1 and the third transistor Q3 will form a low-resistance SCR path of current positive feedback.

[0055] At the same time, a second P-type heavily doped active area 108 and a third P-type heavily doped active area 208 are added between the first port T1 and the second port T2, and a third N-type heavily doped active area 109 and a fourth N-type heavily doped active area 209 are added with N-type heavily doped injection to increase the recombination rate of carriers during transportation, thereby reducing the carrier transportation efficiency and improving the maintenance voltage.

[0056] The present invention utilizes the synergistic effect of multi-layer well regions, transistors and polysilicon gates to achieve bidirectional ESD pulse discharge, and improves the current discharge capability and the maintenance voltage through a positive feedback mechanism and an optimized heavily doped region design. Under common processes, such as the 180nm BCD process, the present invention has a compact structure and is suitable for ESD protection of high-voltage integrated circuits.

[0057] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0058] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A bidirectional gate-controlled thyristor structure, characterized in that: A P-type epitaxial layer is included, wherein a first N-type well-doping type well region and a first N-type deep well-doping type well region are stacked and arranged in the middle of the P-type epitaxial layer, so as to separate the P-type epitaxial layer into a first P-epi and a second P-epi; A first P-type high-voltage doped well region is formed in the injection region on the first P-epi, a first P-type well-doped well region is formed in the injection region on the first P-type high-voltage doped well region, a first P-type heavily doped active region and a plurality of groups of second P-type heavily doped active regions and a first N-type heavily doped active region are arranged at the top of the first P-type well-doped well region along its length direction, wherein the first P-type heavily doped active region and the plurality of groups of second P-type heavily doped active regions and the first N-type heavily doped active region are isolated from each other, and the first P-type heavily doped active region and the first N-type heavily doped active region are isolated from each other; A second P-type high-voltage doped type well region is formed in the injection region on the second P-epi, a second P-type well-doped type well region is formed in the injection region on the second P-type high-voltage doped type well region, and a third P-type heavily doped active region and a plurality of groups of fourth P-type heavily doped active regions and a second N-type heavily doped active region are arranged at the top of the second P-type well-doped type well region along its length direction, wherein the third P-type heavily doped active region and the plurality of groups of fourth P-type heavily doped active regions and the second N-type heavily doped active region are isolated from each other, and the fourth P-type heavily doped active region and the second N-type heavily doped active region are isolated from each other.

2. The bidirectional gate controlled thyristor structure according to claim 1, characterized in that: The first N-type heavily doped active region, the first P-type well doping type well region, the first P-type high voltage doping type well region, the first P-epi, the first N-type well doping type well region and the first N-type deep well doping type well region constitute a first triode; The second N-type heavily doped active region, the second P-type well doping type well region, the second P-type high voltage doping type well region, the second P-epi, the first N-type well doping type well region and the first N-type deep well doping type well region constitute a second triode; The second P-type heavily doped active area, the first P-type heavily doped active area, the first P-type well doping type well area, the first P-type high voltage doping type well area, the first P-epi, the first N-type well doping type well area, the first N-type deep well doping type well area, the second P-epi, the second P-type high voltage doping type well area, the second P-type well doping type well area, the fourth P-type heavily doped active area and the third P-type heavily doped active area constitute a third triode; Among them, the first transistor and the second transistor are NPN transistors, and the third transistor is a bidirectional PNP transistor.

3. The bidirectional gate controlled thyristor structure according to claim 2, characterized in that: A third N-type heavily doped active region and a fourth N-type heavily doped active region are arranged at the top of the first N-type well-doping type well region along its length direction, and the third N-type heavily doped active region and the fourth N-type heavily doped active region are isolated by a shallow trench isolation (STI) region.

4. The bidirectional gate controlled thyristor structure according to claim 3, characterized in that: The first P-type heavily doped active region and the multiple groups of second P-type heavily doped active regions and the first N-type heavily doped active region, the first P-type heavily doped active region and the first N-type heavily doped active region, the third P-type heavily doped active region and the multiple groups of fourth P-type heavily doped active regions and the second N-type heavily doped active regions, and the fourth P-type heavily doped active region and the second N-type heavily doped active region are all isolated by shallow trench isolation (STI) regions.

5. The bidirectional gate controlled thyristor structure according to claim 4, characterized in that: The third N-type heavily doped active region and the first P-type heavily doped active region are isolated by a shallow trench isolation (STI) region; The fourth N-type heavily doped active region and the third P-type heavily doped active region are isolated from each other by a shallow trench isolation (STI) region.

6. The bidirectional gate controlled thyristor structure according to claim 4, characterized in that: Also includes a first polysilicon gate and a second polysilicon gate; The first polysilicon gate is disposed at a top of a shallow trench isolation (STI) region between the second P-type heavily doped active region and the first N-type heavily doped active region; The second polysilicon gate is disposed at a top of a shallow trench isolation (STI) region between the fourth P-type heavily doped active region and the second N-type heavily doped active region.

7. The bidirectional gate controlled thyristor structure according to claim 6, characterized in that: Also includes a first port T1 and a second port T2; The first port T1 is connected to the second P-type heavily doped active area, the first N-type heavily doped active area and the first polysilicon gate respectively; the second port T2 is connected to the fourth P-type heavily doped active area, the second N-type heavily doped active area and the second polysilicon gate respectively.

8. The bidirectional gate controlled thyristor structure according to claim 7, characterized in that: Also includes a deep N-type heavily doped well region, a second N-type deep well doping type well region, and a second N-type well doping type well region; The deep N-type heavily doped well region is disposed at the bottom of the first P-epi, the second P-epi and the first N-type deep well doping type well region; The second N-type deep well doping type well region is arranged around the edge of the deep N-type heavily doped type well region and surrounds the first P-epi and the second P-epi; The second N-type weill doping type well region is located at the top of the second N-type deep well doping type well region.

9. The bidirectional gate controlled thyristor structure according to claim 7, characterized in that: The base of the first transistor is connected to the first port through a first resistor.

10. The bidirectional gate controlled thyristor structure according to claim 9, characterized in that: The base of the second transistor is connected to the second port through a second resistor.

Images