A high temperature resistant bidirectional thyristor structure

Abstract

The present invention discloses a high temperature resistant bidirectional thyristor structure, comprising a P-type epitaxial layer, two first N-type well doping type well regions are formed in the middle of the P-type epitaxial layer, and the two first N-type well doping type well regions are arranged at intervals to separate the P-type epitaxial layer into a first epitaxial layer region, a second epitaxial layer region and a third epitaxial layer region; a first P-type high voltage doping type well region is provided in the injection region on the first epitaxial layer region, a first P-type well doping type well region is provided in the injection region on the first P-type high voltage doping type well region, a first P-type heavily doped active region and a first N-type heavily doped active region are provided at the top of the first P-type well doping type well region, and the first P-type heavily doped active region and the first N-type heavily doped active region are arranged in isolation. The present invention adjusts the ESD discharge path to a deeper level of the chip through the design of slotting in the base region, which is beneficial to its heat dissipation and reduces the current discharge attenuation degree under high temperature.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a high-temperature resistant bidirectional thyristor structure. Background Art

[0002] Electrostatic discharge (ESD) is one of the main reasons for the failure of integrated circuit products. With the development of power semiconductor technology, high-voltage integrated circuits have been widely used in power management and automotive electronics, but their complex working environment has put forward higher requirements for ESD protection devices. Protection devices not only need to be able to withstand high voltage and high current, but also need to have a maintenance voltage higher than the normal operating voltage of the circuit to fundamentally eliminate the risk of latch-up and ensure the stability and reliability of the circuit.

[0003] In the prior art, among many ESD protection devices, the SCR structure is considered to be a powerful choice for on-chip ESD protection due to its extremely high current discharge efficiency. However, due to its deep hysteresis characteristics, the trigger voltage of the traditional SCR structure is usually higher than the breakdown voltage of the process gate oxide layer. At the same time, its maintenance voltage is low, which is easy to cause latch-up effect, limiting its application in the field of high-voltage ICs. In addition, existing ESD protection devices generally face the problem of insufficient high-temperature resistance, and are prone to performance degradation in high-temperature environments, further increasing the difficulty of achieving effective protection for high-voltage ICs under complex working conditions.

[0004] Based on this, a bidirectional thyristor structure with high holding voltage and high temperature resistance is needed. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a high temperature resistant bidirectional thyristor structure to at least solve the problems of low holding voltage and insufficient high temperature resistance of the existing thyristor structure.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a high temperature resistant bidirectional thyristor structure, comprising a P-type epitaxial layer, wherein two first N-type well-doped type well regions are formed in the middle of the P-type epitaxial layer, and the two first N-type well-doped type well regions are arranged at intervals to separate the P-type epitaxial layer into a first epitaxial layer region, a second epitaxial layer region and a third epitaxial layer region, wherein the first epitaxial layer region and the second epitaxial layer region are located on both sides of the two first N-type well-doped type well regions, and the third epitaxial layer region is located between the two first N-type well-doped type well regions;

[0008] A first P-type high-voltage doped well region is provided in the implantation region on the first epitaxial layer region, a first P-type well doped well region is provided in the implantation region on the first P-type high-voltage doped well region, a first P-type heavily doped active region and a first N-type heavily doped active region are provided at the top of the first P-type well doped well region, and the first P-type heavily doped active region and the first N-type heavily doped active region are isolated and arranged;

[0009] A second P-type high-voltage doped type well region is provided in the injection region on the second epitaxial layer region, a second P-type well-doped type well region is provided in the injection region on the second P-type high-voltage doped type well region, a second P-type heavily doped active region and a second N-type heavily doped active region are provided at the top of the second P-type well-doped type well region, and the second P-type heavily doped active region and the second N-type heavily doped active region are isolated and arranged.

[0010] Further, the first N-type heavily doped active region, the first P-type well doping type well region, the first P-type high voltage doping type well region, the first epitaxial layer region and the two first N-type well doping type well regions form a first triode;

[0011] The second N-type heavily doped active region, the second P-type well doping type well region, the second P-type high voltage doping type well region, the second epitaxial layer region and the two first N-type well doping type well regions form a second triode;

[0012] The first P-type heavily doped active region, the first P-type well doping type well region, the first P-type high voltage doping type well region, the first epitaxial layer region, the two first N-type heavily doped active regions, the third epitaxial layer region, the second epitaxial layer region, the second P-type high voltage doping type well region, the second P-type well doping type well region, and the second P-type heavily doped active region form a third triode;

[0013] Wherein, the first transistor and the second transistor are NPN transistors, and the third transistor is a bidirectional PNP transistor.

[0014] Furthermore, it also includes an N-type heavily doped well region, wherein the N-type heavily doped well region is formed at the bottom of the P-type epitaxial layer and the two first N-type well-doping type well regions;

[0015] Both ends of the N-type heavily doped well region are respectively provided with a second N-type well doping type well region.

[0016] Furthermore, the second N-type well doping type well region is formed by stacking two layers of N-type well doping type well regions.

[0017] Further, the first P-type heavily doped active region and the first N-type heavily doped active region are isolated by a shallow trench isolation STI region, and the shallow trench isolation STI region between the first P-type heavily doped active region and the first N-type heavily doped active region extends into the first P-type well doping type well region;

[0018] The second P-type heavily doped active region and the second N-type heavily doped active region are isolated by a shallow trench isolation STI region, and the shallow trench isolation STI region between the second P-type heavily doped active region and the second N-type heavily doped active region extends into the second P-type well-doping type well region.

[0019] Furthermore, a shallow trench isolation (STI) region is included, and the shallow trench isolation (STI) region is provided on top of the two first N-type well-doping type well regions, the P-type epitaxial layer, and the two second N-type well-doping type well regions.

[0020] Furthermore, the two first N-type well doping type well regions are formed by stacking double layers of N-type well doping type well regions.

[0021] Furthermore, it also includes a port T1 and a port T2, the port T1 is connected to the first P-type heavily doped active area and the first N-type heavily doped active area respectively; the port T2 is connected to the first P-type heavily doped active area and the first N-type heavily doped active area respectively.

[0022] Furthermore, the base of the first transistor is connected to the port T1 via a first resistor.

[0023] Furthermore, the base of the second transistor is connected to the port T2 via a second resistor.

[0024] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0025] A high-temperature resistant bidirectional thyristor structure of the present invention can meet the design requirements of high holding voltage in actual ESD protection, and has extremely high current discharge efficiency. The ESD discharge path is adjusted to a deeper level of the chip through the design of slotting in the base area, which is beneficial to its heat dissipation and reduces the degree of current discharge attenuation under high temperature. The overall current discharge capacity can be flexibly adjusted by connecting devices in parallel, thereby meeting the design requirements of ESD protection for high-voltage integrated circuits above 40V. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A side cross-sectional view of a bidirectional gate-controlled thyristor structure according to an embodiment of the present invention;

[0028] Figure 2 A top view of a bidirectional gate-controlled thyristor structure according to an embodiment of the present invention;

[0029] Figure 3 is a circuit diagram of a first triode, a second triode and a third triode according to an embodiment of the present invention;

[0030] Figure 4 This is an IV diagram of a bidirectional gate-controlled thyristor structure according to an embodiment of the present invention.

[0031] The accompanying drawings of the present invention are as follows:

[0032] 101, second N-type well doping type well region; 103, first P-type heavily doped active region; 104, first epitaxial layer region; 105, first P-type well doping type well region; 106, first P-type high voltage doping type well region; 107, first N-type heavily doped active region;

[0033] 203, second P-type heavily doped active region; 204, second epitaxial layer region; 205, second P-type well doping type well region; 206, second P-type high voltage doping type well region; 207, second N-type heavily doped active region; 208, third epitaxial layer region;

[0034] 301 , N-type heavily doped well region; 302 , shallow trench isolation STI region; 303 , first N-type well doping type well region. DETAILED DESCRIPTION

[0035] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0036] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0037] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0038] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0039] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0040] High-voltage circuits often require ESD to maintain good performance at high temperatures (125°C). However, the traditional SCR structure is greatly affected by temperature because its ESD discharge path is a parasitic PNP and NPN feedback structure. The robustness of its current discharge is also affected by temperature.

[0041] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0042] like Figures 1 to 4As shown, a high temperature resistant bidirectional thyristor structure of the present invention comprises a P-type epitaxial layer, two first N-type well doping type well regions 303 are formed in the middle of the P-type epitaxial layer, and the two first N-type well doping type well regions 303 are arranged at intervals to separate the P-type epitaxial layer into a first epitaxial layer region 104, a second epitaxial layer region 204 and a third epitaxial layer region 208, the first epitaxial layer region 104 and the second epitaxial layer region 204 are located on both sides of the two first N-type well doping type well regions 303, and the third epitaxial layer region 208 is located between the two first N-type well doping type well regions 303; a first P-type high voltage doping type well region 106 is provided in the injection region on the first P-type high voltage doping type well region 106, and a third epitaxial layer region 208 is provided in the injection region on the first P-type high voltage doping type well region 106. A P-type well-doped type well region 105, the top of the first P-type well-doped type well region 105 is provided with a first P-type heavily doped active region 103 and a first N-type heavily doped active region 107, and the first P-type heavily doped active region 103 and the first N-type heavily doped active region 107 are isolated and arranged; a second P-type high-voltage doped type well region 206 is provided in the injection region on the second epitaxial layer region 204, a second P-type well-doped type well region 205 is provided in the injection region on the second P-type high-voltage doped type well region 206, and the top of the second P-type well-doped type well region 205 is provided with a second P-type heavily doped active region 203 and a second N-type heavily doped active region 207, and the second P-type heavily doped active region 203 and the second N-type heavily doped active region 207 are isolated and arranged.

[0043] The implantation region is a specific region in the single crystal silicon structure where N-type or P-type ions are implanted under a high energy electric field. The N-type or P-type ions are mainly implanted by ion doping implantation.

[0044] The high temperature resistant bidirectional thyristor structure of the present invention can be applied to common size processes, such as 180nm BCD process, and can be used as a high sustaining voltage thyristor device for ESD protection of high voltage integrated circuits.

[0045] The present application also includes a substrate 100 , on which a P-type epitaxial layer is formed.

[0046] Specifically, the first N-type heavily doped active region 107, the first P-type well doping type well region 105, the first P-type high voltage doping type well region 106, the first epitaxial layer region 104 and the two first N-type well doping type well regions 303 form a first transistor Q1; the second N-type heavily doped active region 207, the second P-type well doping type well region 205, the second P-type high voltage doping type well region 206, the second epitaxial layer region 204 and the two first N-type well doping type well regions 303 forms the second transistor Q2; the first P-type heavily doped active area 103, the first P-type well-doped type well area 105, the first P-type high-voltage doped type well area 106, the first epitaxial layer area 104, the two first N-type heavily doped active areas 107, the third epitaxial layer area 208, the second epitaxial layer area 204, the second P-type high-voltage doped type well area 206, the second P-type well-doped type well area 205, and the second P-type heavily doped active area 203 form the third transistor Q3.

[0047] The first transistor Q1 and the second transistor Q2 are NPN transistors, and the third transistor Q3 is a bidirectional PNP transistor.

[0048] Furthermore, it also includes an N-type heavily doped well region 301, which is formed at the bottom of the P-type epitaxial layer and the two first N-type well-doped type well regions 303; the two ends of the N-type heavily doped well region 301 are respectively provided with a second N-type well-doped type well region 101.

[0049] The N-type heavily doped well region 301 is used to play an isolation role to prevent the first transistor Q1 and the second transistor Q2 from being directly turned on.

[0050] Furthermore, the second N-type well doping type well region 101 is formed by stacking two layers of N-type well doping type well regions.

[0051] Furthermore, the first P-type heavily doped active region 103 and the first N-type heavily doped active region 107 are isolated by a shallow trench isolation STI region 302, and the shallow trench isolation STI region 302 between the first P-type heavily doped active region 103 and the first N-type heavily doped active region 107 extends into the first P-type well-doped type well region 105; the second P-type heavily doped active region 203 and the second N-type heavily doped active region 207 are isolated by a shallow trench isolation STI region 302, and the shallow trench isolation STI region 302 between the second P-type heavily doped active region 203 and the second N-type heavily doped active region 207 extends into the second P-type well-doped type well region 205.

[0052] Furthermore, a shallow trench isolation STI region 302 is included. The shallow trench isolation STI region 302 is provided on the top of the two first N-type well-doping type well regions 303 , the P-type epitaxial layer and the two second N-type well-doping type well regions 101 .

[0053] Furthermore, the two first N-type well doping type well regions 303 are formed by stacking double layers of N-type well doping type well regions.

[0054] Furthermore, it also includes a port T1 and a port T2, the port T1 is connected to the first P-type heavily doped active region 103 and the first N-type heavily doped active region 107 respectively; the port T2 is connected to the first P-type heavily doped active region 103 and the first N-type heavily doped active region 107 respectively.

[0055] Furthermore, the base of the first transistor Q1 is connected to the port T1 via the first resistor R1.

[0056] Furthermore, the base of the second transistor Q2 is connected to the port T2 via the second resistor R2.

[0057] The working principle of the present invention is as follows:

[0058] When a positive ESD pulse enters from port T1, the diode formed by the first N-type well-doped type well region 303 and the second epitaxial layer region 204 first undergoes avalanche breakdown to form an avalanche current. In the process of the avalanche current flowing to port T2, the potential of the N-type heavily doped well region 301 is reduced, thereby causing the emitter junction of the third transistor Q3 to be forward-conducted, so that the third transistor Q3 is turned on. As the current increases, when a voltage drop of 0.7V is generated on the second resistor R2R2, the emitter junction of the second transistor Q2 is forward-biased and turned on. At this time, the second transistor Q2 is turned on. After that, the second transistor Q2 and the third transistor Q3 form current positive feedback, thereby constructing a low-resistance SCR discharge path. Similarly, when a negative ESD pulse enters from port T1, the first transistor Q1 and the third transistor Q3 will form a low-resistance SCR path with current positive feedback.

[0059] The present invention is designed as Figure 3 In the structure of the plan view, a groove structure of a P-type epitaxial layer (third epitaxial layer region 208) is formed in the middle of the two stacked first N-type well-doped type well regions 303 in the base region of the SCR structure, thereby changing the ESD current path to flow through the N-type heavily doped well region 301, which is more conducive to heat dissipation under high temperature conditions, thereby improving its current discharge robustness under high temperature.

[0060] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0061] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A high temperature resistant bidirectional thyristor structure, characterized in that: A P-type epitaxial layer is included, wherein two first N-type well-doping type well regions are formed in the middle of the P-type epitaxial layer, and the two first N-type well-doping type well regions are arranged at intervals to separate the P-type epitaxial layer into a first epitaxial layer region, a second epitaxial layer region and a third epitaxial layer region, wherein the first epitaxial layer region and the second epitaxial layer region are located on both sides of the two first N-type well-doping type well regions, and the third epitaxial layer region is located between the two first N-type well-doping type well regions; A first P-type high-voltage doped well region is provided in the implantation region on the first epitaxial layer region, a first P-type well doped well region is provided in the implantation region on the first P-type high-voltage doped well region, a first P-type heavily doped active region and a first N-type heavily doped active region are provided at the top of the first P-type well doped well region, and the first P-type heavily doped active region and the first N-type heavily doped active region are isolated and arranged; A second P-type high-voltage doped type well region is provided in the injection region on the second epitaxial layer region, a second P-type well-doped type well region is provided in the injection region on the second P-type high-voltage doped type well region, a second P-type heavily doped active region and a second N-type heavily doped active region are provided at the top of the second P-type well-doped type well region, and the second P-type heavily doped active region and the second N-type heavily doped active region are isolated and arranged.

2. The high temperature resistant bidirectional thyristor structure according to claim 1, characterized in that: The first N-type heavily doped active region, the first P-type well doping type well region, the first P-type high voltage doping type well region, the first epitaxial layer region and the two first N-type well doping type well regions form a first triode; The second N-type heavily doped active region, the second P-type well doping type well region, the second P-type high voltage doping type well region, the second epitaxial layer region and the two first N-type well doping type well regions form a second triode; The first P-type heavily doped active region, the first P-type well doping type well region, the first P-type high voltage doping type well region, the first epitaxial layer region, the two first N-type heavily doped active regions, the third epitaxial layer region, the second epitaxial layer region, the second P-type high voltage doping type well region, the second P-type well doping type well region, and the second P-type heavily doped active region form a third triode; Wherein, the first transistor and the second transistor are NPN transistors, and the third transistor is a bidirectional PNP transistor.

3. The high temperature resistant bidirectional thyristor structure according to claim 2, characterized in that: It also includes an N-type heavily doped well region, which is formed at the bottom of the P-type epitaxial layer and the two first N-type well-doping type well regions; Both ends of the N-type heavily doped well region are respectively provided with a second N-type well doping type well region.

4. The high temperature resistant bidirectional thyristor structure according to claim 3, characterized in that: The second N-type well doping type well region is formed by stacking two layers of N-type well doping type well regions.

5. The high temperature resistant bidirectional thyristor structure according to claim 3, characterized in that: The first P-type heavily doped active region and the first N-type heavily doped active region are isolated by a shallow trench isolation (STI) region, and the shallow trench isolation (STI) region between the first P-type heavily doped active region and the first N-type heavily doped active region extends into the first P-type well doping type well region; The second P-type heavily doped active region and the second N-type heavily doped active region are isolated by a shallow trench isolation STI region, and the shallow trench isolation STI region between the second P-type heavily doped active region and the second N-type heavily doped active region extends into the second P-type well-doping type well region.

6. The high temperature resistant bidirectional thyristor structure according to claim 5, characterized in that: It also includes a shallow trench isolation (STI) region, which is provided on top of the two first N-type well-doping type well regions, the P-type epitaxial layer, and the two second N-type well-doping type well regions.

7. The high temperature resistant bidirectional thyristor structure according to claim 1, characterized in that: The two first N-type well doping type well regions are formed by stacking double layers of N-type well doping type well regions.

8. The high temperature resistant bidirectional thyristor structure according to any one of claims 2 to 6, characterized in that: It also includes a port T1 and a port T2, wherein the port T1 is connected to the first P-type heavily doped active region and the first N-type heavily doped active region respectively; and the port T2 is connected to the first P-type heavily doped active region and the first N-type heavily doped active region respectively.

9. The high temperature resistant bidirectional thyristor structure according to claim 8, characterized in that: The base of the first transistor is connected to the port T1 through a first resistor.

10. The thyristor structure according to claim 8, characterized in that: The base of the second transistor is connected to the port T2 via a second resistor.

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