Solar cell and method for manufacturing the same

Abstract

The present invention relates to a solar cell and a method for preparing the same. The solar cell comprises a silicon wafer, the front side of which comprises a first tunneling layer, a second tunneling layer, a first boron-doped polysilicon layer, a third tunneling layer, a second boron-doped polysilicon layer, a passivation layer and an anti-reflection layer stacked in sequence; wherein the first tunneling layer and the third tunneling layer are both silicon dioxide tunneling layers, the second tunneling layer is at least one of an aluminum oxide tunneling layer and a silicon nitride tunneling layer; the front side of the second boron-doped polysilicon layer is a velvet surface. The solar cell provided by the present invention effectively improves the passivation performance and contact performance of the front side of the cell, has excellent cell conversion efficiency, and has broad application prospects.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof. Background Art

[0002] Solar cells are devices that convert light into electrical energy through the photovoltaic effect. As a clean, safe, and convenient renewable energy source, they have been widely used. Tunneling oxide passivation contact (TOPCon) technology is the new solar cell technology with the highest production capacity. It achieves chemical passivation and field effect passivation through the stacking of tunneling oxide layers and doped polysilicon layers. However, in the traditional solar cell structure, there are still a large number of defects and recombination centers on the front side, the passivation effect is poor, and the contact resistance is large, which seriously affects the conversion efficiency of solar cells, thereby limiting the further development and application of TOPCon cells.

[0003] Therefore, there is an urgent need for a solar cell that can reduce defects and recombination centers on the front side of the cell, improve contact resistance, and increase conversion efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a solar cell and a method for preparing the same in view of the above problems. The solar cell provided by the present invention effectively improves the passivation performance and contact performance of the front side of the cell, has excellent cell conversion efficiency, and has broad application prospects.

[0005] The solar cell provided by the present invention comprises a silicon wafer, wherein the front side of the silicon wafer comprises a first tunneling layer, a second tunneling layer, a first boron-doped polysilicon layer, a third tunneling layer, a second boron-doped polysilicon layer, a passivation layer and an anti-reflection layer which are stacked in sequence;

[0006] The first tunneling layer and the third tunneling layer are both silicon dioxide tunneling layers, the second tunneling layer is at least one of an aluminum oxide tunneling layer and a silicon nitride tunneling layer; and the surface of the second boron-doped polysilicon layer close to the passivation layer is a velvet surface.

[0007] In one embodiment, the thickness of the first tunneling layer is greater than the thickness of the third tunneling layer.

[0008] In one embodiment, the thickness of the first tunneling layer is 3 nm to 6 nm, and the thickness of the third tunneling layer is 1 nm to 3 nm.

[0009] In one embodiment, the thickness of the first boron-doped polysilicon layer is less than the thickness of the second boron-doped polysilicon layer.

[0010] In one embodiment, the thickness of the first boron-doped polysilicon layer is 30 nm to 50 nm, and the thickness of the second boron-doped polysilicon layer is 150 nm to 250 nm.

[0011] In one embodiment, the boron doping concentration of the first boron doped polysilicon layer is less than the boron doping concentration of the second boron doped polysilicon layer.

[0012] In one embodiment, the boron doping concentration of the first boron-doped polysilicon layer is 1.5E 19 cm -3 ~2.5E 19 cm -3 The boron doping concentration of the second boron-doped polysilicon layer is 2.5E 19 cm -3 ~4.5E 19 cm -3 .

[0013] In one embodiment, the thickness of the aluminum oxide tunneling layer is 1 nm to 3 nm;

[0014] And / or, the thickness of the silicon nitride tunneling layer is 5 nm to 10 nm.

[0015] The above-mentioned solar cell has a specific structure. First, the first tunneling layer and the first boron-doped polysilicon layer on the front side effectively block the boron element from diffusing into the silicon wafer, which not only ensures the potential difference between the second boron-doped polysilicon layer and the silicon wafer and improves the tunneling effect of the carriers, but also enables the second boron-doped polysilicon layer to have a higher boron doping concentration, effectively improving the ohmic contact of the battery, thereby improving the battery conversion efficiency; second, the second tunneling layer is conducive to the accumulation and transmission of carriers, improving the tunneling effect of carriers, thereby improving the passivation effect of the battery; third, the surface of the second boron-doped polysilicon layer close to the passivation layer forms a velvet surface, which is conducive to improving the light absorption efficiency, while ensuring the passivation performance of the front tunneling layer, thereby improving the battery conversion efficiency.

[0016] Therefore, the solar cell provided by the present invention effectively improves the passivation performance and contact performance of the front side of the solar cell, has excellent cell conversion efficiency, and has broad application prospects.

[0017] The present invention also provides a method for preparing the solar cell as described above, comprising the following steps:

[0018] S1, double-sided polishing of silicon wafer;

[0019] S2, sequentially depositing a first tunneling layer and a second tunneling layer on the front side of the silicon wafer;

[0020] S3, forming a first boron-doped polysilicon layer, a third tunneling layer and a second boron-doped polysilicon layer in sequence on the front side of the silicon wafer;

[0021] S4, wet etching is performed on the back side of the silicon wafer to remove all layers on the back side of the silicon wafer and corrode part of the silicon wafer;

[0022] S5, performing texturing on the front side of the silicon wafer, removing the borosilicate glass layer on the front side, and forming a texturing surface on the surface of the second boron-doped polysilicon layer away from the third tunneling layer;

[0023] S6. A passivation layer and an anti-reflection layer are prepared on both sides of the silicon wafer;

[0024] S7. Prepare a positive electrode and a negative electrode.

[0025] In one of the embodiments, in the wet etching step, all layers on the back side of the silicon wafer are removed, and the silicon wafer having a thickness of 2 μm to 4 μm is etched. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 Schematic diagram of the structure of a solar cell in one embodiment of the present invention.

[0028] Figure numerals: 1, silicon wafer; 21, first tunneling layer; 22, third tunneling layer; 23, fourth tunneling layer; 3, second tunneling layer; 31, aluminum oxide tunneling layer; 32, silicon nitride tunneling layer; 41, first boron-doped polysilicon layer; 42, second boron-doped polysilicon layer; 5, passivation layer; 6, anti-reflection layer; 7, phosphorus-doped polysilicon layer; 8, positive electrode; 9, negative electrode. DETAILED DESCRIPTION

[0029] For ease of understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific implementation methods or embodiments, and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, and the combinations include any two related listed items, any more related listed items, or all related listed items.

[0031] like Figure 1 , which is a schematic diagram of the structure of a solar cell in one embodiment of the present invention, is a TOPCon solar cell, comprising a silicon wafer 1, wherein the front side of the silicon wafer 1 comprises a first tunneling layer 21, an aluminum oxide tunneling layer 31, a silicon nitride tunneling layer 32, a first boron-doped polysilicon layer 41, a third tunneling layer 22, a second boron-doped polysilicon layer 42, a passivation layer 5 and an anti-reflection layer 6 which are stacked in sequence;

[0032] The first tunneling layer 21 and the third tunneling layer 22 are both silicon dioxide tunneling layers, the second tunneling layer 3 is at least one of an aluminum oxide tunneling layer 31 and a silicon nitride tunneling layer 32; and the surface of the second boron-doped polysilicon layer 42 close to the passivation layer 5 is velvet.

[0033] It can be understood that the second tunneling layer 3 of the present invention can be a stack of an aluminum oxide tunneling layer 31 and a silicon nitride tunneling layer 32, or it can be an aluminum oxide tunneling layer 31 or a silicon nitride tunneling layer 32, and the stacking positions of the aluminum oxide tunneling layer 31 and the silicon nitride tunneling layer 32 in the second tunneling layer 3 can be interchanged; the surface of the second boron-doped polysilicon layer 42 close to the passivation layer 5 is the front side of the second boron-doped polysilicon layer 42.

[0034] The above-mentioned solar cell has a specific structure. First, the first tunneling layer 21 and the first boron-doped polysilicon layer 41 on the front side effectively block the boron element from diffusing into the silicon wafer 1, which not only ensures the potential difference between the second boron-doped polysilicon layer 42 and the silicon wafer 1, improves the tunneling effect of the carriers, thereby improving the passivation performance of the battery, but also enables the second boron-doped polysilicon layer 42 to have a higher boron doping concentration, effectively improves the ohmic contact of the battery, and thus improves the battery conversion efficiency; second, the second tunneling layer 3 is conducive to the accumulation and transmission of carriers, improves the tunneling effect of the carriers, thereby improving the passivation effect of the battery; third, the front side of the second boron-doped polysilicon layer 42 forms a velvet surface, which is conducive to improving the light absorption efficiency, while ensuring the passivation performance of the tunneling layer on the front side, thereby improving the battery conversion efficiency.

[0035] Therefore, the solar cell provided by the present invention effectively improves the passivation performance and contact performance of the front side of the solar cell, has excellent cell conversion efficiency, and has broad application prospects.

[0036] It should be noted that the silicon wafer 1 is selected from an N-type silicon wafer or a P-type silicon wafer, preferably an N-type silicon wafer.

[0037] In one embodiment, the thickness of the first tunneling layer 21 is greater than the thickness of the third tunneling layer 22 , which is beneficial to further improve the passivation effect, thereby improving the conversion efficiency of the solar cell.

[0038] Preferably, the thickness of the first tunneling layer 21 is 3nm~6nm, the thickness of the third tunneling layer 22 is 1nm~3nm, the thickness of the first tunneling layer 21 includes but is not limited to any point value among 3.5nm, 3.8nm, 4.2nm, 4.5nm, 4.8nm, 5.3nm, 5.8nm or a range value between any two of them, and the thickness of the third tunneling layer 22 includes but is not limited to any point value among 1.3nm, 1.5nm, 1.8nm, 2nm, 2.3nm, 2.5nm, 2.9nm or a range value between any two of them.

[0039] In one embodiment, the thickness of the first boron-doped polysilicon layer 41 is less than the thickness of the second boron-doped polysilicon layer 42, which is beneficial to further improve the contact resistance, and at the same time, it is beneficial to block the internal diffusion of boron elements and improve the carrier tunneling effect, thereby further improving the passivation effect.

[0040] Preferably, the thickness of the first boron-doped polysilicon layer 41 is 30nm~50nm, and the thickness of the second boron-doped polysilicon layer 42 is 150nm~250nm. The thickness of the first boron-doped polysilicon layer 41 includes but is not limited to any point value among 30nm, 33nm, 35nm, 38nm, 40nm, 43nm, 45nm, 48nm, and 50nm, or a range value between any two of them. The thickness of the second boron-doped polysilicon layer 42 includes but is not limited to any point value among 150nm, 170nm, 180nm, 190nm, 200nm, 220nm, 230nm, 240nm, and 250nm, or a range value between any two of them.

[0041] In one embodiment, the boron doping concentration of the first boron-doped polysilicon layer 41 is less than the boron doping concentration of the second boron-doped polysilicon layer 42, which further improves the contact resistance and is beneficial to increase the potential difference between the second boron-doped polysilicon layer 42 and the silicon wafer 1, thereby improving the carrier tunneling effect and further improving the passivation effect.

[0042] Preferably, the boron doping concentration of the first boron-doped polysilicon layer 41 is 1.5E 19 cm -3 ~2.5E 19 cm -3 The boron doping concentration of the second boron-doped polysilicon layer 42 is 2.5E 19 cm -3 ~4.5E 19 cm -3 .

[0043] In one embodiment, the thickness of the aluminum oxide tunneling layer 31 is 1 nm to 3 nm, including but not limited to any point value among 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, 2.5 nm, 2.8 nm, and 3 nm, or a range value between any two of them. The aluminum oxide tunneling layer 31 carries a negative charge, which further promotes the accumulation and transmission of carriers, improves the carrier tunneling effect, and thus further improves the conversion efficiency of the solar cell.

[0044] In one embodiment, the thickness of the silicon nitride tunneling layer 32 is 5nm to 10nm, including but not limited to any point value among 5nm, 5.2nm, 5.5nm, 5.8nm, 6nm, 7nm, 8nm, 8.5nm, 9nm, and 10nm, or a range value between any two of them. The silicon nitride tunneling layer 32 can effectively block further inward expansion of boron and reduce recombination, thereby further improving the conversion efficiency of the solar cell.

[0045] It should be noted that the present invention has no special restrictions on the material and thickness of the passivation layer 5 and the anti-reflection layer 6. For example, the passivation layer 5 is selected from aluminum oxide, silicon nitride or silicon oxynitride, and the anti-reflection layer 6 is selected from silicon nitride or silicon oxynitride.

[0046] like Figure 1 As shown, in one embodiment of the present invention, the front side of the silicon wafer 1 of the solar cell also includes a positive electrode 8, and the back side of the solar cell includes a fourth tunneling layer 23, a phosphorus-doped polysilicon layer 7, a passivation layer 5, an anti-reflection layer 6 and a negative electrode 9 stacked in sequence.

[0047] In one embodiment, the fourth tunneling layer 23 is selected from a silicon dioxide tunneling layer.

[0048] It should be noted that the present invention has no special restrictions on the thickness of the fourth tunneling layer 23, the thickness of the phosphorus-doped polysilicon layer 7 and the phosphorus doping concentration, and those skilled in the art can make selections according to actual needs; the materials and thicknesses of the passivation layer 5 and the anti-reflection layer 6 on the back side of the silicon wafer 1 and the passivation layer 5 and the anti-reflection layer 6 on the front side can be the same or different, and the present invention has no special restrictions on this.

[0049] It can be understood that the present invention has no special restrictions on the structure of the back side of the solar cell. For example, the back side of the silicon wafer 1 can be a stacked passivation layer 5, an anti-reflection layer 6 and a negative electrode 9, or a cross-finger tunneling passivation structure. The electrode on the back side can be a negative electrode 9, or a positive electrode 8 and a negative electrode 9. That is, the solar cell of the present invention can be a TOPCon solar cell, an IBC solar cell or a TBC solar cell, etc., and the present invention has no special restrictions on this.

[0050] The present invention also provides a method for preparing the solar cell as described above, comprising the following steps:

[0051] S1, silicon wafer 1 is double-sided polished;

[0052] S2, sequentially depositing a first tunneling layer 21 and a second tunneling layer 3 on the front side of the silicon wafer 1;

[0053] S3, forming a first boron-doped polysilicon layer 41, a third tunneling layer 22 and a second boron-doped polysilicon layer 42 in sequence on the front side of the silicon wafer 1;

[0054] S4, wet etching is performed on the back side of the silicon wafer 1 to remove all layers on the back side of the silicon wafer 1 and to corrode part of the silicon wafer 1;

[0055] S5, texturing the front side of the silicon wafer 1, removing the borosilicate glass layer on the front side, and forming a textured surface on the surface of the second boron-doped polysilicon layer 42 away from the third tunneling layer 22;

[0056] S6, a passivation layer 5 and an anti-reflection layer 6 are prepared on both sides of the silicon wafer 1;

[0057] S7. Prepare the positive electrode 8 and the negative electrode 9.

[0058] It can be understood that the surface of the second boron-doped polysilicon layer 42 away from the third tunneling layer 22 is the front side of the second boron-doped polysilicon layer 42 .

[0059] In the above-mentioned preparation method, a stacked structure of a multi-layer tunneling layer and a boron-doped polysilicon layer is formed on the front side of the solar cell silicon wafer 1, and all layers on the back side are removed by wet etching, and part of the silicon wafer 1 is corroded at the same time, effectively ensuring that the passivation performance of the back side of the solar cell is not affected. Subsequently, a velvet surface is formed on the front side of the second boron-doped polysilicon layer 42, which is beneficial to enhancing the passivation effect and contact effect of the solar cell, thereby greatly improving the conversion efficiency of the solar cell.

[0060] In one embodiment, in the wet etching step, all layers on the back side of the silicon wafer 1 are removed, and the silicon wafer 1 with a thickness of 2 μm to 4 μm is etched, further ensuring that the passivation performance of the back side of the solar cell is not affected.

[0061] It can be understood that all the layers on the back side of the silicon wafer 1 include the coated borosilicate glass layer, the second boron-doped polysilicon layer 42, the third tunneling layer 22, the first boron-doped polysilicon layer 41, the second tunneling layer 3, and the first tunneling layer 21. At the same time, a partial thickness of the silicon wafer 1 is corroded, and the silicon wafer 1 is a boron-doped silicon wafer 1, which is beneficial to ensure that the passivation performance of the back structure of the solar cell produced in the subsequent steps is not affected.

[0062] Specifically, before etching, the thickness of the silicon wafer 1 is 130 μm to 170 μm.

[0063] In step S5, the borosilicate glass layer on the front side is removed by front texturing, and a velvet surface is formed on the front side of the second boron-doped polysilicon layer 42, so that the silicon wafer 1, the first tunneling layer 21, the second tunneling layer 3, the first boron-doped polysilicon layer 41, and the back side of the second boron-doped polysilicon layer 42 are all polished surfaces, and the front side of the second boron-doped polysilicon layer 42, the passivation layer 5 and the anti-reflection layer 6 are all velvet surfaces, which is beneficial to improving the passivation performance of the front side of the solar cell, while improving the light absorption efficiency of the front side, thereby greatly improving the conversion efficiency of the solar cell.

[0064] It should be noted that the present invention adopts the existing method to deposit the tunneling layer and the polysilicon layer. For example, the silicon dioxide layer can be prepared by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD) or atomic layer deposition (ALD), the polysilicon layer can be prepared by LPCVD or PECVD, the aluminum oxide layer is prepared by ALD, and the silicon nitride layer is prepared by PECVD. The doped polysilicon layer can be prepared by combining LPCVD with non-in-situ diffusion, or by combining PECVD with high temperature annealing. The present invention does not elaborate on this.

[0065] It can be understood that the present invention has no special restrictions on the method for preparing the film layer on the back side of the silicon wafer 1. For example, when preparing a TOPCon solar cell, that is, when the back side structure of the solar cell silicon wafer 1 is a stacked fourth tunneling layer 23, a phosphorus-doped polysilicon layer 7, a passivation layer 5, an anti-reflection layer 6 and a negative electrode 9, after step S5, the fourth tunneling layer 23 and the phosphorus-doped polysilicon layer 7 are sequentially deposited on the back side of the silicon wafer 1.

[0066] The solar cell and the method for preparing the same will be further described below by the following specific examples. However, those skilled in the art will appreciate that the following examples are only used to illustrate the present invention and should not be considered to limit the scope of the present invention. If no specific conditions are specified in the examples, the conventional conditions or the conditions recommended by the manufacturer are followed. If the manufacturer of the reagents or instruments used is not specified, they are all conventional products that can be purchased commercially.

[0067] Example 1

[0068] Step 1: Double-sided polishing of the silicon wafer is performed using a tank-type alkali polishing process to remove impurities and damaged layers;

[0069] Step 2: depositing a 5 nm first tunneling layer, a 3 nm aluminum oxide tunneling layer, and a 10 nm silicon nitride tunneling layer in sequence on the front side of the silicon wafer obtained in step 1;

[0070] Step 3: Using LPCVD deposition process, a 35nm first polysilicon layer, a 2nm third tunneling layer and a 280nm second polysilicon layer are sequentially deposited on the front side of the silicon wafer obtained in step 2, and a boron diffusion process is performed to form a first boron-doped polysilicon layer (boron diffusion concentration is 2E 19 cm -3 ), so that the second polysilicon layer forms a second boron-doped polysilicon layer (the diffusion concentration of boron is 4E 19 cm -3 );

[0071] Step 4: wet chain etching the back of the silicon wafer obtained in step 3 to remove the borosilicate glass layer, tunneling layer, and boron-doped polysilicon layer coated on the back of the silicon wafer, and etch the silicon wafer with a thickness of 2 μm;

[0072] Step 5: Using LPCVD deposition process, a 2nm third tunneling layer and a 300nm third polysilicon layer are sequentially deposited on the back of the silicon wafer obtained in step 4, and a phosphorus diffusion process is performed to form a phosphorus-doped polysilicon layer (the phosphorus diffusion concentration is 3E 19 cm -3 ).

[0073] Step 6: wet chain texturing the front side of the silicon wafer obtained in step 5 to remove the phosphosilicate glass layer, phosphorus-doped polysilicon layer and borosilicate glass layer on the front side of the silicon wafer, and remove the phosphorus-doped polysilicon layer on the back side of the silicon wafer;

[0074] Step 7: Prepare a 4 nm aluminum oxide passivation layer and an 80 nm silicon nitride anti-reflection layer on both sides of the silicon wafer obtained in step 6;

[0075] Step 8: Prepare a positive electrode on the front side of the silicon wafer obtained in step 7 and a negative electrode on the back side of the silicon wafer by screen printing sintering, light injection and laser assisted sintering processes.

[0076] Example 2

[0077] Step 1: Double-sided polishing of the silicon wafer is performed using a tank-type alkali polishing process to remove impurities and damaged layers;

[0078] Step 2: depositing a 5 nm first tunneling layer, a 1.5 nm aluminum oxide tunneling layer, and a 5 nm silicon nitride tunneling layer in sequence on the front side of the silicon wafer obtained in step 1;

[0079] Step 3: Using LPCVD deposition process, a 35nm first polysilicon layer, a 2nm third tunneling layer and a 280nm second polysilicon layer are sequentially deposited on the front side of the silicon wafer obtained in step 2, and a boron diffusion process is performed to form a first boron-doped polysilicon layer (boron diffusion concentration is 1.8E 19 cm -3), so that the second polysilicon layer forms a second boron-doped polysilicon layer (the diffusion concentration of boron is 3.5E 19 cm -3 );

[0080] Step 4: wet chain etching the back of the silicon wafer obtained in step 3 to remove the borosilicate glass layer, tunneling layer, and boron-doped polysilicon layer coated on the back of the silicon wafer, and etch the silicon wafer with a thickness of 2 μm;

[0081] Step 5: Using LPCVD deposition process, a 1 nm third tunneling layer and a 300 nm third polysilicon layer are sequentially deposited on the back of the silicon wafer obtained in step 4, and a phosphorus diffusion process is performed to form a phosphorus-doped polysilicon layer (the phosphorus diffusion concentration is 3E 19 cm -3 ).

[0082] Step 6: wet chain texturing the front side of the silicon wafer obtained in step 5 to remove the phosphosilicate glass layer, phosphorus-doped polysilicon layer and borosilicate glass layer on the front side of the silicon wafer, and remove the phosphorus-doped polysilicon layer on the back side of the silicon wafer;

[0083] Step 7: Prepare a 4 nm aluminum oxide passivation layer and an 80 nm silicon nitride anti-reflection layer on both sides of the silicon wafer obtained in step 6;

[0084] Step 8: Prepare a positive electrode on the front side of the silicon wafer obtained in step 7 and a negative electrode on the back side of the silicon wafer by screen printing sintering, light injection and laser assisted sintering processes.

[0085] Example 3

[0086] Step 1: Double-sided polishing of the silicon wafer is performed using a tank-type alkali polishing process to remove impurities and damaged layers;

[0087] Step 2, depositing a 2nm first tunneling layer, a 3nm silicon nitride tunneling layer and a 10nm aluminum oxide tunneling layer in sequence on the front side of the silicon wafer obtained in step 1;

[0088] Step 3: Using LPCVD deposition process, a 35nm first polysilicon layer, a 2nm third tunneling layer and a 280nm second polysilicon layer are sequentially deposited on the front side of the silicon wafer obtained in step 2, and a boron diffusion process is performed to form a first boron-doped polysilicon layer (the boron diffusion concentration is 1.9E 19 cm -3 ), so that the second polysilicon layer forms a second boron-doped polysilicon layer (the diffusion concentration of boron is 3.8E 19 cm -3 );

[0089] Step 4: wet chain etching the back of the silicon wafer obtained in step 3 to remove the borosilicate glass layer, tunneling layer, and boron-doped polysilicon layer coated on the back of the silicon wafer, and etch the silicon wafer with a thickness of 2 μm;

[0090] Step 5: Using LPCVD deposition process, a 2nm third tunneling layer and a 300nm third polysilicon layer are sequentially deposited on the back of the silicon wafer obtained in step 4, and a phosphorus diffusion process is performed to form a phosphorus-doped polysilicon layer (the phosphorus diffusion concentration is 3E 17 cm -3 ).

[0091] Step 6: wet chain texturing the front side of the silicon wafer obtained in step 5 to remove the phosphosilicate glass layer, phosphorus-doped polysilicon layer and borosilicate glass layer on the front side of the silicon wafer, and remove the phosphorus-doped polysilicon layer on the back side of the silicon wafer;

[0092] Step 7: Prepare a 4 nm aluminum oxide passivation layer and an 80 nm silicon nitride anti-reflection layer on both sides of the silicon wafer obtained in step 6;

[0093] Step 8: Prepare a positive electrode on the front side of the silicon wafer obtained in step 7 and a negative electrode on the back side of the silicon wafer by screen printing sintering, light injection and laser assisted sintering processes.

[0094] Example 4

[0095] The difference between Example 4 and Example 1 is that in step 2, a 5 nm first tunneling layer and a 3 nm aluminum oxide tunneling layer are deposited in sequence.

[0096] Example 5

[0097] The difference between Example 5 and Example 1 is that in step 2, a 5 nm first tunneling layer and a 10 nm silicon nitride tunneling layer are deposited in sequence.

[0098] Comparative Example 1

[0099] The difference between Comparative Example 1 and Example 1 is that in step 2, only a first tunneling layer of 6 nm is deposited.

[0100] Comparative Example 2

[0101] The difference between Comparative Example 2 and Example 1 is that in step 3, only a first polysilicon layer of 280 nm is deposited.

[0102] Comparative Example 3

[0103] The difference between Comparative Example 3 and Example 1 is that in step 1, the front side of the silicon wafer is textured, so that in the finally obtained solar cell, the front side of the silicon wafer is a textured surface.

[0104] The performance of the solar cells prepared in all the embodiments and comparative examples was tested using a Halm tester to measure the open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF) and conversion efficiency (Eta). All test results are shown in Table 1.

[0105] Table 1

[0106]

[0107]

[0108] According to the results in Table 1, the solar cells prepared in all the embodiments have a high cell conversion efficiency, and the open circuit voltage, short circuit current density, and fill factor are high, while the conversion efficiency, open circuit voltage, short circuit current density, and fill factor of the solar cells in all the comparative examples are significantly lower. Therefore, the solar cell provided by the present invention effectively improves the passivation performance and contact performance of the front side of the cell, has excellent cell conversion efficiency, and has broad application prospects.

[0109] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: The solar cell comprises a silicon wafer, and the front side of the silicon wafer comprises a first tunneling layer, a second tunneling layer, a first boron-doped polysilicon layer, a third tunneling layer, a second boron-doped polysilicon layer, a passivation layer and an anti-reflection layer which are stacked in sequence; The first tunneling layer and the third tunneling layer are both silicon dioxide tunneling layers, the second tunneling layer is at least one of an aluminum oxide tunneling layer and a silicon nitride tunneling layer; and the surface of the second boron-doped polysilicon layer close to the passivation layer is a velvet surface.

2. The solar cell according to claim 1, characterized in that: The thickness of the first tunneling layer is greater than the thickness of the third tunneling layer.

3. The solar cell according to claim 1 or 2, characterized in that: The thickness of the first tunneling layer is 3 nm to 6 nm, and the thickness of the third tunneling layer is 1 nm to 3 nm.

4. The solar cell according to claim 1, characterized in that The thickness of the first boron-doped polysilicon layer is smaller than the thickness of the second boron-doped polysilicon layer.

5. The solar cell according to claim 1 or 4, characterized in that: The thickness of the first boron-doped polysilicon layer is 30 nm to 50 nm, and the thickness of the second boron-doped polysilicon layer is 150 nm to 250 nm.

6. The solar cell according to claim 1, characterized in that The boron doping concentration of the first boron doped polysilicon layer is less than the boron doping concentration of the second boron doped polysilicon layer.

7. The solar cell according to claim 1 or 6, characterized in that: The boron doping concentration of the first boron-doped polysilicon layer is 1.5E 19 cm -3 ~2.5E 19 cm -3 The boron doping concentration of the second boron-doped polysilicon layer is 2.5E 19 cm -3 ~4.5E 19 cm -3 .

8. The solar cell according to claim 1, characterized in that The thickness of the aluminum oxide tunneling layer is 1 nm to 3 nm; And / or, the thickness of the silicon nitride tunneling layer is 5 nm to 10 nm.

9. A method for preparing a solar cell according to any one of claims 1 to 8, characterized in that: The preparation method comprises the following steps: S1, double-sided polishing of silicon wafer; S2, sequentially depositing a first tunneling layer and a second tunneling layer on the front side of the silicon wafer; S3, forming a first boron-doped polysilicon layer, a third tunneling layer and a second boron-doped polysilicon layer in sequence on the front side of the silicon wafer; S4, wet etching is performed on the back side of the silicon wafer to remove all layers on the back side of the silicon wafer and corrode part of the silicon wafer; S5, performing texturing on the front side of the silicon wafer, removing the borosilicate glass layer on the front side, and forming a texturing surface on the surface of the second boron-doped polysilicon layer away from the third tunneling layer; S6. A passivation layer and an anti-reflection layer are prepared on both sides of the silicon wafer; S7. Prepare a positive electrode and a negative electrode.

10. The preparation method according to claim 9, characterized in that: In the wet etching step, all layers on the back side of the silicon wafer are removed, and the silicon wafer having a thickness of 2 μm to 4 μm is etched.

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