Combined passivation back contact battery and preparation method thereof

Abstract

The invention discloses a joint passivation back contact cell and a preparation method thereof. The joint passivation back contact cell comprises a silicon wafer, a third semiconductor layer and an anti-reflection layer which are sequentially arranged on the front surface of the silicon wafer, and a second semiconductor opening region, a first semiconductor opening region and a transition region which are arranged on the back surface of the silicon wafer, the third semiconductor layer is composed of a second intrinsic amorphous silicon layer and a microcrystalline silicon layer which are sequentially deposited on the front face of the silicon wafer, and the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transmission film, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer. The first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer, and an opening is etched in the surface of the transition area to form an insulating groove to isolate the first semiconductor and the second semiconductor. A layer of fullerene film is added to serve as a buffer layer, so that the electronic impedance is reduced, the carrier injection and transmission efficiency is improved, and the cell efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of back contact batteries, and in particular to a combined passivation back contact battery and a preparation method thereof. Background Art

[0002] The existing back contact heterojunction battery includes an N-type monocrystalline silicon wafer, a pyramid velvet surface, an intrinsic amorphous silicon layer, and an anti-reflection layer arranged in sequence on the front of the silicon wafer. An intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal gate line layer are arranged in sequence on the surface of the P region on the back of the silicon wafer. An intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal gate line layer are arranged in sequence on the surface of the N region on the back of the silicon wafer. The P-type amorphous silicon layer is in direct contact with the transparent conductive film layer, and the function of the transparent conductive film layer is to transfer the carriers of the P-type amorphous silicon layer to the electrode. The transparent conductive film (TCO) layer is usually deposited by magnetron sputtering. During the deposition process, the sputtered material has directionality, and the formed film cannot cover the velvet pyramid well, especially the bottom of the pyramid cannot be completely in good contact with the TCO. In addition, the transparent conductive film (TCO) layer is usually ITO, and the work function of ITO is lower than that of P-type silicon. The energy levels between the two are not matched, which makes the series resistance of the battery larger. Summary of the invention

[0003] In view of the above problems, the present invention provides a combined passivated back contact cell and a preparation method thereof, which can effectively reduce the electronic impedance caused by energy band mismatch and improve the carrier injection and transmission efficiency.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: a combined passivation back contact battery, including a silicon wafer, a third semiconductor layer and an anti-reflection layer arranged in sequence on the front side of the silicon wafer, a second semiconductor opening area and a first semiconductor opening area arranged on the back side of the silicon wafer, and a transition area between the second semiconductor opening area and the first semiconductor opening area, wherein the third semiconductor layer is composed of a second intrinsic amorphous silicon layer, a microcrystalline silicon layer, and an anti-reflection layer deposited in sequence on the front side of the silicon wafer, the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transport film, a transparent conductive film, and a metal electrode arranged in sequence on the back side of the silicon wafer, the first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film, and a metal electrode arranged in sequence on the back side of the silicon wafer, the transition area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transport film, and a transparent conductive film arranged in sequence on the back side of the silicon wafer, and an insulating groove is formed by etching an opening in the transparent conductive film on the surface of the transition area.

[0005] A method for preparing the combined passivation back contact battery, the method comprising the following steps:

[0006] S01. Provide polished and cleaned N-type single crystal silicon wafers;

[0007] S02, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; the first semiconductor layer comprises a tunneling oxide layer and an N-type polysilicon layer;

[0008] S03, opening the back side of the silicon wafer obtained in S02 by laser etching to remove the mask layer, the N-type polysilicon layer and the tunnel oxide layer in the second semiconductor opening region;

[0009] S04, performing texturing and cleaning on the silicon wafer obtained in S03, removing the residual mask layer, N-type polysilicon layer and tunneling oxide layer in the second semiconductor opening region, and forming a texturing surface on the silicon wafer;

[0010] S05, depositing a first intrinsic amorphous silicon layer 301 of a second semiconductor layer on the back side of the silicon wafer obtained in S04;

[0011] S06, forming a third semiconductor layer on the front side of the silicon wafer obtained in S05;

[0012] S07, depositing a P-type microcrystalline silicon / amorphous silicon layer 302 of a second semiconductor layer on the back side of the silicon wafer obtained in S06;

[0013] S08, depositing a fullerene transport film on the back side of the silicon wafer obtained in S07;

[0014] S09, depositing an anti-reflection layer on the front side of the silicon wafer obtained in S08;

[0015] S010, opening the back side of the silicon obtained in S09 by laser etching to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning;

[0016] S11, depositing a transparent conductive film on the back side of the silicon wafer obtained in S010;

[0017] S12, etching an opening in the transparent conductive film on the surface of the transition area between the second semiconductor opening area and the first semiconductor opening area on the back side of the silicon wafer obtained in S11 to form an insulating groove, a first semiconductor layer and a second semiconductor layer;

[0018] S13, forming metal electrodes on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S12.

[0019] Furthermore, the tunnel oxide layer is formed by a dry method and has a thickness of 1-2nm; the N-type polysilicon layer is diffused after depositing an intrinsic polysilicon layer by LPCVD and has a thickness of 100-200nm; the mask layer is silicon nitride, formed by PECVD deposition and has a thickness of 60-80nm.

[0020] Furthermore, the first intrinsic amorphous silicon layer is formed by plate-type PECVD deposition and has a thickness of 5-12 nm.

[0021] Furthermore, the third semiconductor layer is formed by depositing a second intrinsic amorphous silicon layer 401 with a thickness of 4-8 nm and a microcrystalline silicon layer with a thickness of 6-20 nm by plate-type PECVD.

[0022] Furthermore, the P-type microcrystalline silicon / amorphous silicon layer is formed by plate-type PECVD deposition and has a thickness of 10-30 nm.

[0023] Furthermore, the fullerene transport film is a C60 film, which is prepared by doping boron atoms using radio frequency plasma assisted evaporation technology, and has a thickness of 10~40nm; the specific method for preparing the C60 film is as follows: 1) pre-evacuating the vacuum chamber to 0.00001~0.0001pa; 2) preparing C60 powder gas by a thermal evaporation device, placing the C60 powder in a quartz boat, the quartz boat heating temperature range is 400~800 degrees, so that the C60 powder is sublimated by heating to form gas; 3) simultaneously introducing a reaction gas diborane mixed gas (2% B2H6 and 98% H2), the gas flow rate of which is precisely controlled by a mass flow meter, and the flow rate range is set to 20~500sccm; 4) C60 powder vapor is mixed with diborane gas, and 13.56 A MHz RF power source excites the mixed gas into a plasma state. During the deposition process, the working pressure is maintained at 0.001Pa~0.01Pa, and the power range is 20~500w, obtaining a C60 film layer with a thickness of 10-40nm.

[0024] Furthermore, the C60 film is treated by a combination of heating and light: a. Annealing process, using a vacuum annealing furnace to set the annealing temperature to 150~200 degrees, and the duration is 20~50 minutes for film layer heating treatment; b. Light process treatment, using a white light source, the light irradiance is 1000~4000W / m2, the treatment time is 20~500s, and the temperature is 80~150 degrees.

[0025] Furthermore, the transparent conductive film is doped with an indium oxide system or a tin oxide system and is formed by PVD deposition with a thickness of 50-150 nm.

[0026] It can be seen from the above description of the present invention that, compared with the prior art, the present invention has the following advantages:

[0027] 1. The present invention adds a fullerene film between the P-type microcrystalline silicon / amorphous silicon layer and the transparent conductive film (ITO): the energy level structure of the film is regulated by chemical doping, surface treatment, structural design and other methods, so that its work function is between the work functions of P-type silicon and ITO, and appropriate energy band bending is performed between the P-type silicon and ITO materials to form a P-type silicon-fullerene film-ITO structure gradient energy band, which is beneficial to reduce the obstruction of charge carriers at the interface. This energy band matching helps to improve the charge transfer efficiency and improve the device performance;

[0028] 2. Fullerene film uses plasma-assisted evaporation technology. Due to the low excitation energy, the energy of its deposited atoms is small, which can reduce particle deposition damage. It can act as a sputtering buffer layer before the deposition of the ITO film, reducing the sputtering damage to the NP layer caused by the sputtering deposition of the ITO film, which helps to improve the open circuit voltage (Voc) of the device. The directionality of the deposited material is lower than that of the sputtering deposition method, and can form a better film smoothness and uniformity. The uniformity of coverage on the P-type silicon surface is improved, which improves the problem of poor contact between the bottom of the silicon wafer velvet pyramid and ITO, reduces the series resistance, and is also beneficial to improve FF, so that the battery efficiency is improved.

[0029] 3. The internal structure of the film is treated by combining heating and light, and a synergistic effect is produced by the heating and light treatment, so that the structure and performance of the film are doubly optimized, the structural adjustment inside the film is promoted, defects are reduced and the carrier mobility is increased, which not only improves the carrier transport performance of the film layer but also ensures the stability of the film structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0031] Figure 1 It is a schematic cross-sectional structure diagram of a combined passivation back contact battery of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] Example

[0034] refer to Figure 1A combined passivation back contact cell comprises a silicon wafer 101, a third semiconductor layer C and an anti-reflection layer 501 sequentially arranged on the front side of the silicon wafer 101, a second semiconductor opening region B and a first semiconductor opening region A and a transition region D between the second semiconductor opening region B and the first semiconductor opening region A arranged on the back side of the silicon wafer 101, the third semiconductor layer C is composed of a second intrinsic amorphous silicon layer 401 and a microcrystalline silicon layer 402 deposited sequentially on the front side of the silicon wafer, the second semiconductor opening region B is composed of a first intrinsic amorphous silicon layer 301, a P-type microcrystalline silicon / amorphous silicon layer 302, a fullerene conductive layer 303 and a P-type microcrystalline silicon / amorphous silicon layer 304 arranged sequentially on the back side of the silicon wafer, and a transition region D between the second semiconductor opening region B and the first semiconductor opening region A arranged on the back side of the silicon wafer. The first semiconductor opening area A is composed of a tunneling oxide layer 201, an N-type polysilicon layer 202, a transparent conductive film 701, and a metal electrode 801, and the transition area D is composed of a tunneling oxide layer 201, an N-type polysilicon layer 202, a first intrinsic amorphous silicon layer 301, a P-type microcrystalline silicon / amorphous silicon layer 302, a fullerene transport film 601, and a transparent conductive film 701, and the surface of the transition area D is etched to form an insulating groove 901.

[0035] A method for preparing the combined passivation back contact battery according to claim 1, the method comprising the following steps:

[0036] S01. Provide polished and cleaned N-type single crystal silicon wafers;

[0037] S02, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; the first semiconductor layer comprises a tunneling oxide layer and an N-type polysilicon layer;

[0038] S03, opening the back side of the silicon wafer obtained in S02 by laser etching to remove the mask layer, the N-type polysilicon layer and the tunnel oxide layer in the second semiconductor opening region;

[0039] S04, performing texturing and cleaning on the silicon wafer obtained in S03, removing the residual mask layer, N-type polysilicon layer and tunneling oxide layer in the second semiconductor opening region, and forming a texturing surface on the silicon wafer;

[0040] S05, depositing a first intrinsic amorphous silicon layer of a second semiconductor layer on the back side of the silicon wafer obtained in S04;

[0041] S06, forming a third semiconductor layer on the front side of the silicon wafer obtained in S05;

[0042] S07, depositing a P-type microcrystalline silicon / amorphous silicon layer 302 of a second semiconductor layer on the back side of the silicon wafer obtained in S06;

[0043] S08, depositing a fullerene transport film on the back side of the silicon wafer obtained in S07;

[0044] S09, depositing an anti-reflection layer on the front side of the silicon wafer obtained in S08;

[0045] S010, opening the back side of the silicon obtained in S09 by laser etching to form a first semiconductor opening area spaced apart from the second semiconductor + C60 film opening area, and then cleaning;

[0046] S11, depositing a transparent conductive film on the back side of the silicon wafer obtained in S010;

[0047] S12, etching an opening in the transparent conductive film on the surface of the transition area between the second semiconductor and fullerene transport film opening area and the first semiconductor opening area on the back side of the silicon wafer obtained in S11 to form an insulating groove to isolate the first semiconductor layer from the second semiconductor layer;

[0048] S13, forming metal electrodes on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S12.

[0049] The tunnel oxide layer 201 is formed by a dry process and has a thickness of 1-2 nm. The N-type polysilicon layer 202 is formed by LPCVD deposition of an intrinsic polysilicon layer followed by diffusion and has a thickness of 100-200 nm. The mask layer 301 is silicon nitride and is formed by PECVD deposition and has a thickness of 60-80 nm.

[0050] The first intrinsic amorphous silicon layer 301 is formed by plate-type PECVD deposition with a thickness of 5-12nm, the P-type microcrystalline silicon / amorphous silicon layer 302 is formed by plate-type PECVD deposition with a thickness of 10-30nm, and the third semiconductor layer is formed by plate-type PECVD deposition of a second intrinsic amorphous silicon layer 401 with a thickness of 4-8nm and a microcrystalline silicon layer 402 with a thickness of 6-20nm.

[0051] The fullerene transport film 601 is a C60 film, which is made by doping boron atoms using radio frequency plasma assisted evaporation technology, and has a thickness of 10-40 nm. The specific method for preparing the C60 film is as follows: 1) pre-evacuating the vacuum chamber to 0.00001-0.0001 pa; 2) preparing C60 powder gas by a thermal evaporation device, placing the C60 powder in a quartz boat, and heating the quartz boat at a temperature range of 400-800 degrees, so that the C60 powder is sublimated by heating to form gas; 3) simultaneously introducing a reaction gas diborane mixed gas (2% B2H6 and 98% H2), and its gas flow rate is precisely controlled by a mass flow meter, and the flow rate range is set to 20-500 sccm; 4) C60 powder vapor is mixed with diborane gas, and 13.56 A MHz RF power source excites the mixed gas into a plasma state. During the deposition process, the working pressure is maintained at 0.001Pa~0.01Pa, and the power range is 20~500w, obtaining a C60 film layer with a thickness of 10-40nm.

[0052] The C60 film is treated by a combination of heating and light: a. Annealing process, using a vacuum annealing furnace to set the annealing temperature to 150~200 degrees, and the duration is 20~50 minutes to perform film layer heating treatment; b. Light process treatment, using a white light source, the light irradiance is 1000~4000W / m2, the treatment time is 20~500s, and the temperature is 80~150 degrees.

[0053] The transparent conductive film 701 is doped with an indium oxide system or a tin oxide system and is deposited by PVD and has a thickness of 50-150 nm.

[0054] The present invention adds a fullerene film between the P-type microcrystalline silicon / amorphous silicon layer and the transparent conductive film (ITO): the energy level structure of the film is regulated by chemical doping, surface treatment, structural design and other methods, so that its work function is between the work functions of P-type silicon and ITO, and appropriate energy band bending is performed between the P-type silicon and ITO materials to form a P-type silicon-fullerene film-ITO structure gradient energy band, which is beneficial to reducing the obstruction of charge carriers at the interface. This energy band matching helps to improve the charge transfer efficiency and enhance the device performance;

[0055] Fullerene film uses plasma-assisted evaporation technology. Due to the low excitation energy, the energy of its deposited atoms is small, which can reduce particle deposition damage and act as a sputtering buffer layer before ITO film deposition, reducing the sputtering damage to the NP layer caused by sputtering deposition of ITO film, which helps to improve the open circuit voltage (Voc) of the device. The directionality of the deposited material is lower than that of the sputtering deposition method, and can form a better film smoothness and uniformity, improve the uniformity of coverage on the P-type silicon surface, improve the problem of poor contact between the bottom of the silicon wafer velvet pyramid and ITO, reduce the series resistance, and also help to improve FF, so that the battery efficiency is improved.

[0056] The internal structure of the film is treated by combining heating and light, and a synergistic effect is produced by the combination of heating and light treatment, so that the structure and performance of the film are doubly optimized, the structural adjustment inside the film is promoted, defects are reduced and the carrier mobility is increased, which not only improves the carrier transport performance of the film layer but also ensures the stability of the film structure.

[0057] Taking the C60 film in the implementation case as an example, the FTIR spectrum of the film was tested. The characteristic peaks of C60 in the treated film (527, 576, 1183 and 1428 cm -1 ) intensity is relatively weakened, indicating that more C60 molecules may be doped, promoting the diffusion of boron atoms in the film, improving the uniformity of doping distribution, reducing defects and increasing the mobility of carriers, improving the lower carrier transport performance of C60 film and enhancing stability.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A combined passivation back contact cell, characterized in that: The invention comprises a silicon wafer, a third semiconductor layer and an anti-reflection layer arranged in sequence on the front side of the silicon wafer, a second semiconductor opening area and a first semiconductor opening area arranged on the back side of the silicon wafer, and a transition area between the second semiconductor opening area and the first semiconductor opening area, wherein the third semiconductor layer is composed of a second intrinsic amorphous silicon layer, a microcrystalline silicon layer, and an anti-reflection layer deposited in sequence on the front side of the silicon wafer, the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transport film, a transparent conductive film, and a metal electrode arranged in sequence on the back side of the silicon wafer, the first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film, and a metal electrode arranged in sequence on the back side of the silicon wafer, the transition area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transport film, and a transparent conductive film arranged in sequence on the back side of the silicon wafer, and an insulating groove is formed by etching an opening in the transparent conductive film on the surface of the transition area.

2. A method for preparing the combined passivation back contact battery according to claim 1, characterized in that: The method comprises the following steps: S01. Provide polished and cleaned N-type single crystal silicon wafers; S02, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; the first semiconductor layer comprises a tunneling oxide layer and an N-type polysilicon layer; S03, opening the back side of the silicon wafer obtained in S02 by laser etching to remove the mask layer, the N-type polysilicon layer and the tunnel oxide layer in the second semiconductor opening region; S04, performing texturing and cleaning on the silicon wafer obtained in S03, removing the residual mask layer, N-type polysilicon layer and tunneling oxide layer in the second semiconductor opening region, and forming a texturing surface on the silicon wafer; S05, depositing a first intrinsic amorphous silicon layer 301 of a second semiconductor layer on the back side of the silicon wafer obtained in S04; S06, forming a third semiconductor layer on the front side of the silicon wafer obtained in S05; S07, depositing a P-type microcrystalline silicon / amorphous silicon layer 302 of a second semiconductor layer on the back side of the silicon wafer obtained in S06; S08, depositing a fullerene transport film on the back side of the silicon wafer obtained in S07; S09, depositing an anti-reflection layer on the front side of the silicon wafer obtained in S08; S010, opening the back side of the silicon obtained in S09 by laser etching to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning; S11, depositing a transparent conductive film on the back side of the silicon wafer obtained in S010; S12, etching an opening in the transparent conductive film on the surface of the transition area between the second semiconductor opening area and the first semiconductor opening area on the back side of the silicon wafer obtained in S11 to form an insulating groove to isolate the first semiconductor from the second semiconductor; S13, forming metal electrodes on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S12.

3. The method for preparing a combined passivation back contact battery according to claim 2, characterized in that: The tunnel oxide layer is formed by a dry method and has a thickness of 1-2nm; the N-type polysilicon layer is diffused after depositing an intrinsic polysilicon layer by LPCVD and has a thickness of 100-200nm; the mask layer is silicon nitride, formed by PECVD deposition and has a thickness of 60-80nm.

4. The method for preparing a combined passivation back contact battery according to claim 2, characterized in that: The first intrinsic amorphous silicon layer is formed by plate-type PECVD deposition and has a thickness of 5-12 nm.

5. The method for preparing a combined passivation back contact battery according to claim 2, characterized in that: The third semiconductor layer is deposited by plate-type PECVD to form a second intrinsic amorphous silicon layer 401 with a thickness of 4-8 nm and a microcrystalline silicon layer with a thickness of 6-20 nm.

6. The method for preparing a combined passivation back contact battery according to claim 2, characterized in that: The P-type microcrystalline silicon / amorphous silicon layer is formed by plate-type PECVD deposition and has a thickness of 10-30 nm.

7. The method for preparing a combined passivation back contact battery according to claim 2, characterized in that: The fullerene transport film is a C60 film, which is prepared by doping boron atoms using radio frequency plasma assisted evaporation technology, and has a thickness of 10-40 nm. The specific method for preparing the C60 film is as follows: 1) pre-evacuating the vacuum chamber to 0.00001-0.0001 pa; 2) preparing C60 powder gas by a thermal evaporation device, placing the C60 powder in a quartz boat, and heating the quartz boat at a temperature range of 400-800 degrees, so that the C60 powder is sublimated by heating to form gas; 3) simultaneously introducing a reaction gas diborane mixed gas (2% B2H6 and 98% H2), and its gas flow rate is precisely controlled by a mass flow meter, and the flow rate range is set to 20-500 sccm; 4) C60 powder vapor is mixed with diborane gas, and 13.56 A MHz RF power source excites the mixed gas into a plasma state. During the deposition process, the working pressure is maintained at 0.001Pa~0.01Pa, and the power range is 20~500w, obtaining a C60 film layer with a thickness of 10-40nm.

8. A method for preparing a combined passivation back contact battery according to claim 7, characterized in that: The C60 film is treated by a combination of heating and light: a. Annealing process, using a vacuum annealing furnace to set the annealing temperature to 150~200 degrees, and the duration is 20~50 minutes to perform film layer heating treatment; b. Light process treatment, using a white light source, the light irradiance is 1000~4000W / m2, the treatment time is 20~500s, and the temperature is 80~150 degrees.

9. The method for preparing a combined passivation back contact battery according to claim 2, characterized in that: The transparent conductive film is doped with an indium oxide system or a tin oxide system and is formed by deposition via PVD and has a thickness of 50-150 nm.

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