Solar cell, photovoltaic module and method for preparing solar cell

Abstract

The present application relates to a solar cell, a photovoltaic module and a method for preparing a solar cell. The solar cell includes a semiconductor substrate having a first surface and a second surface arranged opposite to each other; a tunneling layer arranged on the first surface; a first passivation layer arranged on a side of the tunneling layer away from the semiconductor substrate; and a conductive structure arranged on a side of the first passivation layer away from the semiconductor substrate, the first passivation layer is provided with a through hole penetrating the first passivation layer, and the conductive structure is in ohmic contact with the tunneling layer by means of the through hole. Therefore, the solar cell, photovoltaic module and method for preparing a solar cell provided in the present application can improve the conversion efficiency of the solar cell.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell, a photovoltaic module and a method for preparing a solar cell. Background Art

[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that convert sunlight directly into electrical energy. As they are green and environmentally friendly products that do not cause environmental pollution, and solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] In the related technology, the tunnel oxide passivation contact cell is a solar cell technology with tunnel oxide passivation contact based on the principle of selective carriers. It has an N-type silicon substrate cell structure. By preparing an ultra-thin silicon oxide tunneling layer on the back of the cell and depositing a doped polysilicon layer, a passivation contact structure is formed, which effectively reduces surface recombination and metal contact recombination, thereby improving the conversion efficiency of the cell.

[0004] However, the conversion efficiency of the above-mentioned tunnel oxide layer passivation contact cell needs to be improved. Summary of the invention

[0005] Based on this, it is necessary to provide a solar cell, a photovoltaic module and a method for preparing a solar cell, which can improve the conversion efficiency of the solar cell.

[0006] In a first aspect, an embodiment of the present application provides a solar cell, comprising:

[0007] A semiconductor substrate having a first surface and a second surface arranged opposite to each other;

[0008] A tunneling layer, disposed on the first surface;

[0009] A first passivation layer is disposed on a side of the tunneling layer away from the semiconductor substrate; and

[0010] The conductive structure is arranged on the side of the first passivation layer away from the semiconductor substrate. The first passivation layer is provided with a through hole penetrating the first passivation layer. The conductive structure is in ohmic contact with the tunneling layer via the through hole.

[0011] The solar cell provided in the embodiment of the present application can improve the passivation effect of the first passivation layer by directly contacting the first passivation layer with the tunneling layer, which is beneficial to improving the conversion efficiency of the solar cell.

[0012] In one of the embodiments, an outer contour of an orthographic projection of the tunnel layer on the semiconductor substrate coincides with an outer contour of an orthographic projection of the first passivation layer on the semiconductor substrate.

[0013] In one embodiment, the first passivation layer includes at least two sub-passivation layers, and the at least two sub-passivation layers are stacked along the thickness direction of the semiconductor substrate;

[0014] The at least two sub-passivation layers include a first sub-passivation layer and a second sub-passivation layer, and the first sub-passivation layer is disposed between the second sub-passivation layer and the semiconductor substrate;

[0015] The material of the first sub-passivation layer includes oxide, and the material of the second sub-passivation layer includes nitride.

[0016] In one embodiment, the material of the first sub-passivation layer includes aluminum oxide, and the material of the second sub-passivation layer includes silicon nitride.

[0017] In one embodiment, the thickness of the first sub-passivation layer is in the range of 3 nm to 5 nm;

[0018] and / or, the thickness of the second sub-passivation layer is in the range of 100 nm to 120 nm;

[0019] And / or, the tunneling layer has a thickness in the range of 1.5 nm to 3 nm.

[0020] In one embodiment, the conductive structure includes a conductive layer and a first electrode, the conductive layer is located on a side of the first passivation layer away from the semiconductor substrate, and the first electrode is located on a side of the conductive layer away from the semiconductor substrate;

[0021] The first passivation layer is provided with a through hole penetrating the first passivation layer, and a portion of the conductive layer is provided in the through hole and in contact with the tunneling layer;

[0022] The energy band barrier between the conductive layer and the first electrode and the energy band barrier between the conductive layer and the semiconductor substrate are both smaller than the energy band barrier between the first electrode and the semiconductor substrate.

[0023] In one embodiment, there are a plurality of first electrodes and through holes, and they are arranged at intervals along a first direction, and the first direction is perpendicular to the thickness direction of the semiconductor substrate;

[0024] The plurality of through holes are arranged corresponding to the plurality of first electrodes, and the orthographic projections of the first electrodes on the semiconductor substrate overlap with the orthographic projections of the corresponding through holes on the semiconductor substrate.

[0025] In one of the embodiments, the orthographic projection of the through hole on the semiconductor substrate is located within the orthographic projection of the corresponding first electrode on the semiconductor substrate;

[0026] and / or, the material of the conductive layer includes a transparent conductive oxide;

[0027] and / or, the material of the conductive layer includes indium tin oxide;

[0028] and / or, the material of the first electrode includes silver;

[0029] And / or, a size of the through hole along the first direction ranges from 5 μm to 20 μm.

[0030] In a second aspect, an embodiment of the present application provides a photovoltaic module, comprising the solar cell in the above-mentioned first aspect.

[0031] The photovoltaic module provided in the embodiment of the present application includes a solar cell. The first passivation layer is in direct contact with the tunneling layer, which can improve the passivation effect of the first passivation layer and is beneficial to improving the conversion efficiency of the solar cell.

[0032] In a third aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising:

[0033] Providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface arranged opposite to each other;

[0034] forming a tunneling layer on the first surface;

[0035] forming a first passivation layer on a side of the tunneling layer facing away from the semiconductor substrate;

[0036] Performing patterning on the first passivation layer to form a through hole penetrating the first passivation layer;

[0037] A conductive structure is formed on the side of the first passivation layer away from the semiconductor substrate; a portion of the conductive structure is arranged in the through hole and contacts the tunneling layer.

[0038] The method for preparing a solar cell provided in the embodiment of the present application can improve the passivation effect of the first passivation layer by directly contacting the first passivation layer with the tunneling layer, which is beneficial to improving the conversion efficiency of the solar cell.

[0039] In one embodiment, after forming the tunneling layer on the first surface and before forming the first passivation layer on the side of the tunneling layer facing away from the semiconductor substrate, the method includes:

[0040] forming a doped polysilicon layer on a side of the tunneling layer facing away from the semiconductor substrate;

[0041] performing annealing treatment on the semiconductor substrate;

[0042] The doped polysilicon layer is removed.

[0043] In one embodiment, the thickness of the doped polysilicon layer is in the range of 80 nm to 150 nm.

[0044] In one embodiment, forming a first passivation layer on a side of the tunneling layer facing away from the semiconductor substrate includes:

[0045] forming a first sub-passivation layer on a side of the tunneling layer away from the semiconductor substrate; the material of the first sub-passivation layer includes aluminum oxide;

[0046] A second sub-passivation layer is formed on a side of the first sub-passivation layer facing away from the semiconductor substrate; the material of the second sub-passivation layer includes silicon nitride.

[0047] In one embodiment, forming a conductive structure on a side of the first passivation layer facing away from the semiconductor substrate includes:

[0048] A conductive layer is formed on a side of the first passivation layer facing away from the semiconductor substrate; a portion of the conductive layer is disposed in the through hole and in contact with the tunneling layer;

[0049] A first electrode is formed on the side of the conductive layer away from the semiconductor substrate; the energy band barrier between the conductive layer and the first electrode and the energy band barrier between the conductive layer and the semiconductor substrate are both smaller than the energy band barrier between the first electrode and the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of the structure of a solar cell provided in an embodiment of the present application.

[0051] Figure 2 A schematic diagram of the process of preparing a solar cell provided in an embodiment of the present application.

[0052] Figure 3 A schematic diagram of the structure after providing a semiconductor substrate is provided in an embodiment of the present application.

[0053] Figure 4 A schematic diagram of the structure after forming a tunneling layer provided in an embodiment of the present application.

[0054] Figure 5 A schematic diagram of the structure after forming a doped polysilicon layer provided in an embodiment of the present application.

[0055] Figure 6 A schematic diagram of the structure after forming the first electrode provided in an embodiment of the present application.

[0056] Description of reference numerals:

[0057] 100, solar cell; 110, first passivation layer; 110a, sub-passivation layer; 111, first sub-passivation layer; 112, second sub-passivation layer; 113, through hole; 120, second passivation layer; 123, third sub-passivation layer; 124, fourth sub-passivation layer; 130, tunneling layer; 104, conductive structure; 140, conductive layer; 151, first electrode; 152, second electrode; 160, semiconductor substrate; 161, first surface; 162, second surface; 170, doped polysilicon layer; 180, emitter. DETAILED DESCRIPTION

[0058] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0059] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0060] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0061] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0062] In the related art, a tunneling oxide layer passivated contact cell includes an N-type silicon substrate, a silicon oxide tunneling layer and a doped polysilicon layer are arranged on the side of the N-type silicon substrate close to the backlight surface of the cell, and the silicon oxide tunneling layer is located between the doped polysilicon layer and the N-type silicon substrate.

[0063] However, the doped polysilicon layer is in direct contact with the silicon oxide tunneling layer, and its passivation effect is poor. In addition, due to the large parasitic absorption of sunlight by the doped polysilicon layer, a large energy loss is caused, resulting in a low conversion efficiency of the solar cell.

[0064] To solve the above problems, the embodiments of the present application provide a solar cell, a photovoltaic module and a method for preparing a solar cell, which can improve the conversion efficiency of the solar cell.

[0065] The following will be combined Figure 1-Figure 6 The solar cell, photovoltaic module and method for preparing the solar cell provided in the embodiments of the present application are described.

[0066] The embodiment of the present application provides a solar cell 100 , and the solar cell 100 may be a tunnel oxide passivating contact cell (TOPCON for short) or the like.

[0067] See also Figure 1 The solar cell 100 includes a semiconductor substrate 160, which can provide support for the film layers to be formed subsequently. The semiconductor substrate 160 can be used to receive incident light and generate photogenerated carriers.

[0068] For example, see Figure 1 , the semiconductor substrate 160 may have a thickness along the thickness direction of the semiconductor substrate 160 (ie Figure 1 The solar cell 100 includes a first surface 161 and a second surface 162 that are arranged opposite to each other in a direction Z, and at least one of the first surface 161 and the second surface 162 can be used to receive sunlight. The embodiment of the present application is described by taking the second surface 162 being used to receive sunlight as an example, that is, the second surface 162 is close to the light-facing surface of the solar cell 100, and the first surface 161 is close to the backlight surface of the solar cell 100.

[0069] For example, the semiconductor substrate 160 may be a silicon substrate, and the material of the silicon substrate may include at least one of single crystal silicon and polycrystalline silicon. The present application embodiment is described by taking single crystal silicon as an example.

[0070] Exemplarily, the doping type of the semiconductor substrate 160 may be N-type doping, which may be achieved by doping N-type ions, and the N-type ions may include at least one of phosphorus, arsenic, and antimony. Alternatively, the doping type of the semiconductor substrate 160 may be P-type doping, which may be achieved by doping P-type ions, and the P-type ions may include at least one of aluminum and boron. The embodiment of the present application is described by taking the doping type of the semiconductor substrate 160 as N-type doping as an example.

[0071] In some embodiments, at least one of the first surface 161 and the second surface 162 may have a velvet structure. The velvet structure may be a pyramid velvet, an etched pit velvet, etc. The velvet structure has a lower reflectivity to incident light, and thus has a higher absorption rate to incident light, so that the photoelectric conversion efficiency of the solar cell 100 is higher.

[0072] See also Figure 1 The solar cell 100 includes a tunneling layer 130, which is disposed on the first surface 161. The majority carriers (electrons) can pass through the tunneling layer 130 through the tunneling effect, and the tunneling layer 130 can also block the minority carriers (holes), thereby realizing the selective collection of carriers, preventing the recombination of electrons and holes, reducing the surface recombination rate, and increasing the open circuit voltage.

[0073] Exemplarily, the material of the tunneling layer 130 may be a dielectric material, such as at least one of silicon oxide, magnesium fluoride, silicon oxide, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide.

[0074] Exemplarily, the thickness of the tunneling layer 130 ranges from 1.5 nm to 3 nm, so that the tunneling layer 130 can be prevented from being too thin less than 1.5 nm, so as to improve the tunneling effect of the tunneling layer 130. In addition, by setting the thickness of the tunneling layer 130 to not more than 3 nm, the thickness of the tunneling layer 130 is small, and the energy band barrier between the tunneling layer 130 and the semiconductor substrate 160 can be ignored, which is beneficial to the transmission of carriers. For example, the thickness of the tunneling layer 130 can be 1.5 nm, 2 nm, 2.5 nm, 3 nm, or any value between 1.5 nm and 3 nm.

[0075] See also Figure 1 The solar cell 100 includes a first passivation layer 110 disposed on the first surface 161. The first passivation layer 110 is disposed on the side of the tunneling layer 130 away from the semiconductor substrate 160. The first passivation layer 110 is in direct contact with the tunneling layer 130, which can improve the passivation effect of the first passivation layer 110 and is beneficial to improving the conversion efficiency of the solar cell 100.

[0076] In some embodiments, the outer contour of the orthographic projection of the tunneling layer 130 on the semiconductor substrate 160 coincides with the outer contour of the orthographic projection of the first passivation layer 110 on the semiconductor substrate 160, the tunneling layer 130 can be set as a whole layer, and the first passivation layer 110 can also be set as a whole layer, so that the setting area of ​​the tunneling layer 130 and the first passivation layer 110 is larger, which is beneficial to improving the tunneling effect of the tunneling layer 130 and improving the passivation effect of the first passivation layer 110.

[0077] In some embodiments, see Figure 1The first passivation layer 110 includes a plurality of sub-passivation layers 110a (i.e., at least two), and the plurality of sub-passivation layers 110a are arranged along the thickness direction of the semiconductor substrate 160. For example, the materials of two adjacent sub-passivation layers 110a are different, which is beneficial to improving the passivation effect of the passivation layer. The plurality of sub-passivation layers 110a include a first sub-passivation layer 111 and a second sub-passivation layer 112, and the first sub-passivation layer 111 is located between the second sub-passivation layer 112 and the semiconductor substrate 160.

[0078] Exemplarily, the material of the first sub-passivation layer 111 includes an oxide, for example, the material of the first sub-passivation layer 111 includes aluminum oxide, and the surface of the aluminum oxide film facing the semiconductor substrate 160 has a high fixed negative charge density, and these negative charges can generate a built-in electric field, which can repel electrons (minority carriers) from approaching the first surface 161 of the semiconductor substrate 160, thereby reducing the recombination of electrons on the surface, showing good field passivation characteristics. In addition, the first sub-passivation layer 111 can be in direct contact with the tunneling layer 130, which can improve the passivation effect of the first passivation layer 110, which is conducive to increasing the open circuit voltage and improving the efficiency of the solar cell 100.

[0079] Exemplarily, the material of the second sub-passivation layer 112 includes nitride, for example, the material of the second sub-passivation layer 112 includes silicon nitride. The silicon nitride film can play a hydrogen passivation role. The silicon nitride film contains a large amount of hydrogen. These hydrogen atoms can diffuse to the first surface 161 of the semiconductor substrate 160, and combine with the dangling bonds of the first surface 161 to form a stable Si-H bond, thereby reducing the number of dangling bonds of the first surface 161 of the semiconductor substrate 160, reducing the defects of the first surface 161 of the semiconductor substrate 160, reducing the interface state density, and reducing the surface recombination of carriers. In addition, the passivation effect of silicon nitride is good, which can improve the passivation effect of the first passivation layer 110, which is conducive to improving the open circuit voltage and improving the efficiency of the solar cell 100.

[0080] Exemplarily, the thickness of the first sub-passivation layer 111 ranges from 3 nm to 5 nm, so that the thickness of the first sub-passivation layer 111 can be prevented from being too thin, which is beneficial to improving the passivation effect of the first sub-passivation layer 111. In addition, the thickness of the first sub-passivation layer 111 can be prevented from being too thick, so that the first sub-passivation layer 111 can be prevented from blocking the transmission of sunlight, and the photoelectric conversion efficiency under weak light intensity can be prevented from being reduced to produce a weak light dark film phenomenon. For example, the thickness of the first sub-passivation layer 111 can be 3 nm, 4 nm, 5 nm, or any value between 3 nm and 5 nm.

[0081] Exemplarily, the thickness of the second sub-passivation layer 112 ranges from 100 nm to 120 nm, so that the thickness of the second sub-passivation layer 112 can be prevented from being too thin, which is beneficial to improving the passivation effect of the second sub-passivation layer 112. In addition, the thickness of the second sub-passivation layer 112 can be prevented from being too thick, which is beneficial to the thinness of the solar cell 100. For example, the thickness of the second sub-passivation layer 112 can be 100 nm, 110 nm, 120 nm, or any value between 100 nm and 120 nm.

[0082] In some embodiments, the solar cell 100 includes a first electrode 151 located on the first surface 161. The first electrode 151 may be located on a side of the first passivation layer 110 away from the semiconductor substrate 160. The first electrode 151 may collect and transmit photogenerated carriers, thereby realizing solar energy conversion.

[0083] For example, the material of the first electrode 151 may include metal materials such as silver, copper, titanium, iron, and gold.

[0084] The present application embodiment is described by taking silver as the material of the first electrode 151. The energy band barrier between silver and the semiconductor substrate 160 is large, resulting in energy level mismatch between silver and the semiconductor substrate 160, and carriers are not easily transferred from the semiconductor substrate 160 to the first electrode 151, making it difficult to extract the carriers.

[0085] In some embodiments, the solar cell 100 includes a conductive structure 104, which is disposed on a side of the first passivation layer 110 facing away from the semiconductor substrate 160, and a portion of the conductive structure 104 is disposed in the through hole 113 so that the conductive structure 104 contacts the tunneling layer 130 via the through hole 113, thereby conducting carriers.

[0086] In some embodiments, the conductive structure 104 may include a conductive layer 140, which is located between the first passivation layer 110 and the first electrode 151. The first passivation layer 110 is provided with a through hole 113 that penetrates the first passivation layer 110. Part of the conductive layer 140 is arranged in the through hole 113, and the conductive layer 140 contacts the tunneling layer 130 after passing through the through hole 113. The energy band barrier between the conductive layer 140 and the first electrode 151 is smaller than the energy band barrier between the first electrode 151 and the semiconductor substrate 160, and the energy band barrier between the conductive layer 140 and the semiconductor substrate 160 is smaller than the energy band barrier between the first electrode 151 and the semiconductor substrate 160, so that the energy levels between the conductive layer 140 and the first electrode 151 are matched, and the energy levels between the conductive layer 140 and the semiconductor substrate 160 are matched, so that carriers are easily transferred from the semiconductor substrate 160 to the conductive layer 140, and also easily transferred from the conductive layer 140 to the first electrode 151, so as to reduce the difficulty of carrier extraction, and thus improve the efficiency of the solar cell 100. That is, the energy level matching between the semiconductor substrate 160 and the first electrode 151 is achieved by adding the conductive layer 140.

[0087] Exemplarily, the material of the conductive layer 140 includes a transparent conductive oxide, for example, may include at least one of indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium aluminum zinc oxide (GAZO), tin oxide (SnO2), antimony tin oxide (ATO), fluorine tin oxide (FTO), indium cerium oxide (ICO), and indium aluminum oxide (IWO).

[0088] It should be noted that the conductive structure 104 may only include the first electrode 151 without the conductive layer 140. Alternatively, the first electrode 151 and the conductive layer 140 may be provided at the same time.

[0089] For example, see Figure 1 , the solar cell 100 may have a first direction X, a second direction and a third direction Z, and the first direction X, the second direction and the third direction Z are all different. The first direction X, the second direction and the third direction Z may be perpendicular to each other. For example, the third direction Z may be the thickness direction of the semiconductor substrate 160, and the first direction X and the second direction may be any two different directions perpendicular to the thickness direction of the semiconductor substrate 160. The first direction X may be the width direction of the solar cell 100, and the second direction may be the length direction of the solar cell 100. The length, width and thickness in the embodiments of the present application are merely for the convenience of description and do not imply any limitation on the size. For example, the width may be greater than, equal to or less than the length. The direction of the solar cell 100 may be consistent with the direction of the film layer such as the semiconductor substrate 160.

[0090] In some embodiments, see Figure 1There are a plurality of first electrodes 151 and a plurality of through holes 113, and the plurality of first electrodes 151 are arranged at intervals along the first direction X, and the plurality of through holes 113 are arranged at intervals along the first direction X. The plurality of through holes 113 are arranged corresponding to the plurality of first electrodes 151, and the orthographic projection of the first electrode 151 on the semiconductor substrate 160 overlaps with the orthographic projection of the corresponding through hole 113 on the semiconductor substrate 160, so that the through hole 113 and the corresponding first electrode 151 are at least partially arranged opposite to each other in the thickness direction of the semiconductor substrate 160, so that the transmission path of the carriers between the semiconductor substrate 160 and the first electrode 151 is shorter, which is beneficial to the transmission of the carriers.

[0091] Among them, in the embodiment of the present application, the corresponding arrangement of A and B may refer to: one A is corresponding to at least one B, or one B is corresponding to at least one A. The embodiment of the present application is described by taking the corresponding arrangement of one A and one B as an example. For example, the corresponding arrangement of multiple through holes 113 and multiple first electrodes 151 may refer to: one through hole 113 and at least one first electrode 151 are correspondingly arranged, or one first electrode 151 is correspondingly arranged with at least one through hole 113. The embodiment of the present application is described by taking the corresponding arrangement of one through hole 113 and one first electrode 151 as an example.

[0092] In some embodiments, see Figure 1 The orthographic projection of the through hole 113 on the semiconductor substrate 160 is located within the orthographic projection of the corresponding first electrode 151 on the semiconductor substrate 160, and the area of ​​the through hole 113 is set to be smaller, thereby reducing the damage of the through hole 113 to the first passivation layer 110, thereby reducing the adverse effect of the through hole 113 on the passivation effect of the first passivation layer 110.

[0093] Exemplarily, the size of the through hole 113 along the first direction X ranges from 5 μm to 20 μm, so that the size of the through hole 113 along the first direction X can be prevented from being too small, which is beneficial to improving the transmission of carriers. In addition, the size of the through hole 113 along the first direction X can be prevented from being too large, which is beneficial to reducing the adverse effect of the through hole 113 on the passivation effect of the first passivation layer 110. For example, the size of the through hole 113 along the first direction X can be 5 μm, 10 μm, 15 μm, 20 μm, or any value between 5 μm and 20 μm.

[0094] In some embodiments, see Figure 1 The solar cell 100 includes an emitter 180, which is disposed on the second surface 162 of the semiconductor substrate 160. The emitter 180 may be a boron emitter. For example, the emitter 180 may be formed by performing a boron diffusion process on the second surface 162 of the semiconductor substrate 160. The emitter 180 and the semiconductor substrate 160 may form a PN junction to achieve conversion of light energy into electrical energy.

[0095] In some embodiments, the solar cell 100 includes a second passivation layer 120 disposed on the second surface 162, and the second passivation layer 120 may include a third sub-passivation layer 123, and the third sub-passivation layer 123 is located on the side of the emitter 180 away from the semiconductor substrate 160. The second passivation layer 120 may include a fourth sub-passivation layer 124, and the fourth sub-passivation layer 124 is located on the side of the third sub-passivation layer 123 away from the semiconductor substrate 160.

[0096] Exemplarily, the material of the third sub-passivation layer 123 includes aluminum oxide, and its principle is similar to that of the first sub-passivation layer 111 , which will not be described in detail.

[0097] Exemplarily, the material of the fourth sub-passivation layer 124 includes silicon nitride, and its principle is similar to that of the second sub-passivation layer 112 , which will not be described in detail.

[0098] In some embodiments, the solar cell 100 includes a second electrode 152 located on the second surface 162, the second electrode 152 is located on the side of the second passivation layer 120 away from the semiconductor substrate 160, and the second electrode 152 can pass through the second passivation layer 120 and contact the emitter 180. The second electrode 152 can collect and transmit photogenerated carriers, thereby realizing the conversion of solar energy into electrical energy.

[0099] For example, the material of the second electrode 152 may include metal materials such as silver, copper, titanium, iron, and gold.

[0100] The photovoltaic module provided in the embodiments of the present application is described below.

[0101] The embodiment of the present application further provides a photovoltaic module, which may include the solar cell 100 in the above embodiment. There may be at least one solar cell 100 in the photovoltaic module. The embodiment of the present application is described by taking the case where there are multiple solar cells 100 in the photovoltaic module as an example, and the multiple solar cells 100 together constitute a battery string layer.

[0102] In some embodiments, the photovoltaic module may include a first encapsulation member and a second encapsulation member located on both sides of the battery string layer, and the first encapsulation member and the second encapsulation member encapsulate the battery string layer to protect the battery string layer. The first encapsulation member and the second encapsulation member may include an encapsulation adhesive layer and a cover plate, the encapsulation adhesive layer is located on the side of the cover plate facing the battery string layer, the cover plate can protect the battery string layer, and the encapsulation adhesive layer can be used to connect the cover plate and the battery string layer.

[0103] The following is an explanation of a method for preparing the solar cell 100 provided in an embodiment of the present application.

[0104] The present application embodiment provides a method for preparing a solar cell 100, which can be used to prepare the solar cell 100 in the above embodiment. Figure 2, the preparation method may include:

[0105] S100: providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface that are opposite to each other.

[0106] First, see Figure 3 , providing a semiconductor substrate 160. The semiconductor substrate 160 has a first surface 161 and a second surface 162 that are opposite to each other.

[0107] For example, at least one of the first surface 161 and the second surface 162 of the semiconductor substrate 160 may be textured to form a textured structure. Taking the second surface 162 of the semiconductor substrate 160 as an example, at least a portion of the second surface 162 may be textured.

[0108] For example, the velvet structure can be prepared by wet chemical etching, for example, an alkaline solution can be used for velvet preparation, such as a NaOH solution, or chemical etching, laser etching, mechanical method, plasma etching, etc. can be used to prepare the velvet structure.

[0109] Exemplarily, the thickness of the semiconductor substrate 160 may be in a range of 120 μm-150 μm.

[0110] S200: forming a tunneling layer on the first surface.

[0111] See also Figure 4 After providing the semiconductor substrate 160 , the process may include depositing a tunneling layer 130 on the first surface 161 .

[0112] Exemplarily, the deposition process may include an atomic layer deposition process (atomic layer deposition, referred to as ALD), a physical vapor deposition process (physical vapor deposition, referred to as PVD) or a chemical vapor deposition process (chemical vapor deposition, referred to as CVD), etc. Other structural layers in the embodiments of the present disclosure may also be formed by deposition, which will not be described in detail.

[0113] For example, the tunneling layer 130 may be formed using a plasma enhanced chemical vapor deposition (PECVD) process.

[0114] S300: forming a first passivation layer on a side of the tunneling layer facing away from the semiconductor substrate.

[0115] See also Figure 6After forming the tunneling layer 130 on the first surface 161 , it may include forming a first passivation layer 110 on the side of the tunneling layer 130 away from the semiconductor substrate 160 . The first passivation layer 110 may be in contact with the tunneling layer 130 , which may improve the passivation effect of the first passivation layer 110 , thereby facilitating improving the conversion efficiency of the solar cell 100 .

[0116] In some embodiments, see Figure 5 After forming the tunneling layer 130 on the first surface 161, before forming the first passivation layer 110 on the side of the tunneling layer 130 facing away from the semiconductor substrate 160, it may include forming a doped polysilicon layer 170 on the side of the tunneling layer 130 facing away from the semiconductor substrate 160. In this way, during the preparation process of the solar cell 100, the doped polysilicon layer 170 can attract impurities in the semiconductor substrate 160 and impurities introduced during the process into the doped polysilicon layer 170, thereby reducing impurities and defects in the semiconductor substrate 160.

[0117] For example, the doping type of the doped polysilicon layer 170 may be N-type doping.

[0118] Exemplarily, after forming the doped polysilicon layer 170, before forming the first passivation layer 110 on the side of the tunneling layer 130 away from the semiconductor substrate 160, the semiconductor substrate 160 may be annealed. In this way, under high temperature process conditions, the doped polysilicon layer 170 is conducive to attracting impurities in the semiconductor substrate 160 into the doped polysilicon layer 170.

[0119] Exemplarily, after the semiconductor substrate 160 is annealed, before the first passivation layer 110 is formed on the side of the tunneling layer 130 away from the semiconductor substrate 160, the doped polysilicon layer 170 may be removed, so that the final solar cell 100 product does not have the doped polysilicon layer 170, avoiding the parasitic absorption of light by polysilicon, thereby facilitating the improvement of the conversion efficiency of the solar cell 100. In this way, the embodiment of the present application forms the doped polysilicon layer 170 first to maintain the doping effect of the doped polysilicon layer 170 on the semiconductor substrate 160, and then removes the doped polysilicon layer 170 after the annealing process to remove the parasitic absorption of light by the doped polysilicon layer 170.

[0120] For example, the doped polysilicon layer 170 may be removed by chemical etching.

[0121] Exemplarily, the thickness of the doped polysilicon layer 170 ranges from 80 nm to 150 nm, thereby preventing the doped polysilicon layer 170 from being too thin, which is beneficial to improving the gettering effect of the doped polysilicon layer 170. In addition, it can also prevent the doped polysilicon layer 170 from being too thick, which results in a long preparation time and removal time. For example, the thickness of the doped polysilicon layer 170 can be 80 nm, 100 nm, 120 nm, 140 nm, 150 nm, or any value between 80 nm and 150 nm.

[0122] In some embodiments, see Figure 6 Forming the first passivation layer 110 on the side of the tunneling layer 130 away from the semiconductor substrate 160 may include forming a first sub-passivation layer 111 on the side of the tunneling layer 130 away from the semiconductor substrate 160. Then, forming a second sub-passivation layer 112 on the side of the first sub-passivation layer 111 away from the semiconductor substrate 160.

[0123] Exemplarily, for example, the material of the first sub-passivation layer 111 includes aluminum oxide, and the material of the second sub-passivation layer 112 includes silicon nitride. The principle has been described and will not be repeated here. In addition, since aluminum oxide and silicon nitride both have good passivation effects, after removing the doped polysilicon layer 170, aluminum oxide and nitride can be directly passivated, thereby improving the passivation effect of the first passivation layer 110, which is beneficial to increase the open circuit voltage.

[0124] S400: performing patterning on the first passivation layer to form a through hole penetrating the first passivation layer.

[0125] In some embodiments, see Figure 6 After forming the first passivation layer 110 on the side of the tunneling layer 130 facing away from the semiconductor substrate 160 , the method may include patterning the first passivation layer 110 to form a through hole 113 in the first passivation layer 110 .

[0126] For example, the through hole 113 may be formed in the first passivation layer 110 by laser etching, and the through hole 113 exposes the tunneling layer 130 .

[0127] For example, the through hole 113 may only penetrate the first passivation layer 110 and not extend into the tunneling layer 130 . Alternatively, the through hole 113 may extend into the tunneling layer 130 , or the through hole 113 may penetrate the tunneling layer 130 .

[0128] S500: forming a conductive structure on a side of the first passivation layer facing away from the semiconductor substrate; the conductive structure is in ohmic contact with the tunneling layer via a through hole.

[0129] In some embodiments, after patterning the first passivation layer 110 , a conductive structure 104 may be formed on a side of the first passivation layer 110 facing away from the semiconductor substrate 160 ; a portion of the conductive structure 104 is disposed in the through hole 113 so that the conductive structure 104 contacts the tunneling layer 130 .

[0130] For example, see Figure 6 , forming a conductive structure 104 on a side of the first passivation layer 110 away from the semiconductor substrate 160, which may include forming a conductive layer 140 on a side of the first passivation layer 110 away from the semiconductor substrate 160, a portion of the conductive layer 140 is disposed in the through hole 113, and the conductive layer 140 contacts the tunneling layer 130 through the through hole 113. Then, forming a first electrode 151 on a side of the conductive layer 140 away from the semiconductor substrate 160, the energy band barrier between the conductive layer 140 and the first electrode 151, and the energy band barrier between the conductive layer 140 and the semiconductor substrate 160 are both smaller than the energy band barrier between the first electrode 151 and the semiconductor substrate 160, so that the conductive layer 140 and the semiconductor substrate 160, and the conductive layer 140 and the first electrode 151 can form a good contact, have a good energy level matching, so that the energy level matching between the first electrode 151 and the semiconductor substrate 160 is achieved through the conductive layer 140, which is beneficial to the carrier extraction and improves the efficiency of the solar cell 100. The principle has been explained and will not be repeated here.

[0131] Exemplarily, the conductive layer 140 may be prepared by magnetron sputtering.

[0132] For example, the thickness of the conductive layer 140 may be 80 nm.

[0133] In some embodiments, forming the first electrode 151 on the side of the conductive layer 140 away from the semiconductor substrate 160 may include forming a first initial electrode on the side of the conductive layer 140 away from the semiconductor substrate 160. For example, the first initial electrode may be formed by screen printing of low-temperature silver paste. Then, the first initial electrode is subjected to low-temperature sintering to form the first electrode 151. For example, the temperature of the low-temperature sintering may be 400°C. Since the conductive layer 140 is provided, a low-temperature sintering method may be adopted, and the temperature of the low-temperature sintering is relatively low, which is conducive to reducing the damage of the sintering to the solar cell 100.

[0134] Exemplarily, the preparation process of the first electrode 151 may also include laser transfer, electroplating or thermal evaporation.

[0135] in, Figure 4-Figure 6 Only the film layers on the first surface 161 of the semiconductor substrate 160 are shown, and the film layers on the second surface 162 are not shown. The embodiment of the present application does not limit the order of the film layers on the first surface 161 and the film layers on the second surface 162.

[0136] In some embodiments, see Figure 1 The method for preparing the solar cell 100 may further include forming an emitter 180 on the second surface 162 .

[0137] For example, a boron diffusion process may be performed on the second surface 162 of the semiconductor substrate 160 to form the emitter 180 .

[0138] In some embodiments, see Figure 1 After forming the emitter 180 , the method may include sequentially forming a third sub-passivation layer 123 and a fourth sub-passivation layer 124 on a side of the emitter 180 facing away from the semiconductor substrate 160 .

[0139] In some embodiments, see Figure 1 After forming the fourth sub-passivation layer 124 , the method may include forming a second electrode 152 on a side of the fourth sub-passivation layer 124 away from the semiconductor substrate 160 , wherein the second electrode 152 penetrates the third sub-passivation layer 123 and the fourth sub-passivation layer 124 , and the second electrode 152 contacts the emitter 180 .

[0140] Exemplarily, the second electrode 152 may also be inserted into the emitter 180 , so that the contact area between the second electrode 152 and the emitter 180 may be increased.

[0141] For example, the second initial electrode may be formed by screen printing, and the second initial electrode may be sintered at a high temperature and laser-assisted sintered to form the second electrode 152 .

[0142] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface arranged opposite to each other; A tunneling layer, disposed on the first surface; A first passivation layer is disposed on a side of the tunneling layer away from the semiconductor substrate; as well as The conductive structure is arranged on a side of the first passivation layer away from the semiconductor substrate. The first passivation layer is provided with a through hole penetrating the first passivation layer. The conductive structure is in ohmic contact with the tunneling layer via the through hole.

2. The solar cell according to claim 1, characterized in that The first passivation layer includes at least two sub-passivation layers, and the at least two sub-passivation layers are stacked along the thickness direction of the semiconductor substrate; The at least two sub-passivation layers include a first sub-passivation layer and a second sub-passivation layer, wherein the first sub-passivation layer is disposed between the second sub-passivation layer and the semiconductor substrate; A material of the first sub-passivation layer includes oxide, and a material of the second sub-passivation layer includes nitride.

3. The solar cell according to claim 2, characterized in that: The material of the first sub-passivation layer includes aluminum oxide, and the material of the second sub-passivation layer includes silicon nitride.

4. The solar cell according to claim 2 or 3, characterized in that: The thickness of the first sub-passivation layer is in the range of 3nm-5nm; And / or, the thickness of the second sub-passivation layer is in the range of 100 nm to 120 nm; And / or, the tunneling layer has a thickness ranging from 1.5 nm to 3 nm.

5. The solar cell according to any one of claims 1 to 3, characterized in that: The conductive structure comprises a conductive layer and a first electrode, wherein the conductive layer is located on a side of the first passivation layer away from the semiconductor substrate, and the first electrode is located on a side of the conductive layer away from the semiconductor substrate; A portion of the conductive layer is disposed in the through hole and contacts the tunneling layer; The energy band barrier between the conductive layer and the first electrode and the energy band barrier between the conductive layer and the semiconductor substrate are both smaller than the energy band barrier between the first electrode and the semiconductor substrate.

6. The solar cell according to claim 5, characterized in that There are a plurality of the first electrodes and the through holes, and the first electrodes and the through holes are arranged at intervals along a first direction, and the first direction is perpendicular to the thickness direction of the semiconductor substrate; The plurality of through holes are arranged corresponding to the plurality of first electrodes, and the orthographic projections of the first electrodes on the semiconductor substrate overlap with the orthographic projections of the corresponding through holes on the semiconductor substrate.

7. The solar cell according to claim 6, characterized in that: The orthographic projection of the through hole on the semiconductor substrate is located within the orthographic projection of the corresponding first electrode on the semiconductor substrate; And / or, the material of the conductive layer includes a transparent conductive oxide; And / or, the material of the conductive layer includes indium tin oxide; And / or, the material of the first electrode includes silver; And / or, a size of the through hole along the first direction ranges from 5 μm to 20 μm.

8. The solar cell according to any one of claims 1 to 3, characterized in that: An outer contour of an orthographic projection of the tunneling layer on the semiconductor substrate coincides with an outer contour of an orthographic projection of the first passivation layer on the semiconductor substrate.

9. A photovoltaic module, characterized in that: A solar cell comprising any one of claims 1 to 8.

10. A method for preparing a solar cell, characterized in that: include: providing a semiconductor substrate; The semiconductor substrate has a first surface and a second surface arranged opposite to each other; forming a tunneling layer on the first surface; forming a first passivation layer on a side of the tunneling layer facing away from the semiconductor substrate; performing patterning on the first passivation layer to form a through hole penetrating the first passivation layer; forming a conductive structure on a side of the first passivation layer facing away from the semiconductor substrate; The conductive structure is in ohmic contact with the tunneling layer via the through hole.

11. The method for preparing a solar cell according to claim 10, characterized in that: After forming the tunneling layer on the first surface and before forming the first passivation layer on the side of the tunneling layer facing away from the semiconductor substrate, the method comprises: forming a doped polysilicon layer on a side of the tunneling layer facing away from the semiconductor substrate; performing annealing treatment on the semiconductor substrate; The doped polysilicon layer is removed.

12. The method for preparing a solar cell according to claim 11, characterized in that: The thickness of the doped polysilicon layer is in the range of 80nm-150nm.

13. The method for preparing a solar cell according to any one of claims 10 to 12, characterized in that: The step of forming a first passivation layer on a side of the tunneling layer away from the semiconductor substrate comprises: forming a first sub-passivation layer on a side of the tunneling layer away from the semiconductor substrate; the material of the first sub-passivation layer includes aluminum oxide; A second sub-passivation layer is formed on a side of the first sub-passivation layer away from the semiconductor substrate; the material of the second sub-passivation layer includes silicon nitride.

14. The method for preparing a solar cell according to any one of claims 10 to 12, characterized in that: The forming of a conductive structure on a side of the first passivation layer away from the semiconductor substrate comprises: forming a conductive layer on a side of the first passivation layer away from the semiconductor substrate; a portion of the conductive layer is disposed in the through hole and in contact with the tunneling layer; A first electrode is formed on a side of the conductive layer away from the semiconductor substrate; the energy band barrier between the conductive layer and the first electrode and the energy band barrier between the conductive layer and the semiconductor substrate are both smaller than the energy band barrier between the first electrode and the semiconductor substrate.

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