Back contact battery and preparation method of back contact battery

Abstract

The invention relates to a back contact battery and a preparation method of the back contact battery. The back contact battery comprises a substrate, a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, a second doped semiconductor layer, a first electrode and a second electrode. In the thickness direction of the substrate, the substrate is provided with a front face and a back face which are oppositely arranged, and the back face comprises first areas and second areas which are alternately arranged. And the first tunneling layer, the first doped semiconductor layer, the second tunneling layer and the second doped semiconductor layer are stacked on the first region of the back surface along the direction far away from the substrate. The first electrode is electrically connected with the second doped semiconductor layer, and the second electrode is arranged in the second area and electrically connected with the substrate. Therefore, the probability of short circuit can be reduced while an additional grooving process for separating the first region from the second region can be omitted, so that the manufacturing efficiency and reliability of the back contact battery can be improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a method for preparing the back-contact cell. Background Art

[0002] The electrodes of the back contact cell are arranged on the back side of the back contact cell, so that the front side of the back contact cell is not blocked by the electrodes, thereby increasing the area of ​​the back contact cell absorbing sunlight, thereby improving the conversion efficiency of the back contact cell.

[0003] In the related art, the preparation process of the back contact battery generally includes: separating the P region and the N region on the back side of the back contact battery through a grooving process (the P region refers to the area on the back side of the back contact battery for setting the P-type doping layer, and the N region refers to the area on the back side of the back contact battery for setting the N-type doping layer) to reduce the probability of a short circuit. Summary of the invention

[0004] Based on this, it is necessary to provide a back contact battery and a method for preparing the back contact battery in order to address the above technical problems, so as to improve the manufacturing efficiency of the back contact battery.

[0005] According to a first aspect of the present application, there is provided a back contact battery, comprising:

[0006] A substrate, wherein along a thickness direction of the substrate, the substrate has a front side and a back side that are arranged opposite to each other, and the back side includes first areas and second areas that are arranged alternately;

[0007] A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on the first region of the back side in a direction away from the substrate; wherein the first doped semiconductor layer has the same conductivity type as the second doped semiconductor layer and is opposite to the conductivity type of the substrate;

[0008] A first electrode electrically connected to the second doped semiconductor layer; and

[0009] The second electrode is disposed in the second region and is electrically connected to the substrate.

[0010] In one embodiment, the second area of ​​the back surface has a first velvet structure, and the first velvet structure includes a plurality of first pyramid structures;

[0011] Along the direction from the front side to the back side, the height of the first pyramid structure is 2 μm-5 μm;

[0012] Along a direction perpendicular to the front surface and pointing toward the back surface, a size of the first pyramid structure is 1 μm-5 μm.

[0013] In one embodiment, the front surface has a second velvet structure, and the second velvet structure includes a plurality of second pyramid structures;

[0014] Along the direction from the front side to the back side, the height of the second pyramid structure is 1 μm-3 μm;

[0015] Along a direction perpendicular to the front surface and pointing toward the back surface, a size of the second pyramid structure is 1 μm-5 μm.

[0016] In one embodiment, the sheet resistance of the second doped semiconductor layer is 100Ω / □-300Ω / □; and / or

[0017] The sheet resistance of the first doped semiconductor layer is 100Ω / □-300Ω / □; and / or

[0018] The thickness of the first doped semiconductor layer is 20nm-100nm; and / or

[0019] The thickness of the second doped semiconductor layer is 100 nm-250 nm; and / or

[0020] The thickness of the first tunneling layer is 1 nm-4 nm; and / or

[0021] The thickness of the second tunneling layer is 1 nm-4 nm.

[0022] In one embodiment, the flatness of the first region is less than the flatness of the second region; and / or

[0023] The second area of ​​the back side has a first velvet structure, the first velvet structure includes a plurality of first pyramid structures; the first area of ​​the back side has a polished structure, the polished structure includes a plurality of tower base structures, and the height of the first pyramid structure is greater than the height of the tower base structure in the direction from the front side to the back side; and / or

[0024] The area of ​​the first region is S1, and the area of ​​the second region is S2, wherein S1 and S2 have the same unit, and S2 satisfies the following condition: S2 / (S1+S2)=a, where a is 30%-70%.

[0025] According to a second aspect of the present application, a method for preparing a back contact battery is provided, comprising:

[0026] Providing a substrate, wherein along a thickness direction of the substrate, the substrate has a front side and a back side that are arranged opposite to each other, and the back side includes first areas and second areas that are arranged alternately;

[0027] A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on the first region of the back side of the substrate in a direction away from the substrate; wherein the first doped semiconductor layer has the same conductivity type as the second doped semiconductor layer and is opposite to the conductivity type of the substrate;

[0028] A first electrode electrically connected to the second doped semiconductor layer and a second electrode disposed on the second region and electrically connected to the substrate are formed.

[0029] In one embodiment, forming a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer in a stacked manner on the first region of the back side of the substrate in a direction away from the substrate specifically includes:

[0030] forming a first initial tunneling layer, a first initial semiconductor layer, a second initial tunneling layer, and a second initial semiconductor layer stacked on the first region of the back side of the substrate in a direction away from the substrate;

[0031] forming a doping source layer on a side of the second initial semiconductor layer away from the second initial tunneling layer;

[0032] Diffusing the doping element in the doping source layer into the first initial semiconductor layer and the second initial semiconductor layer, so that the first initial semiconductor layer is transformed into a first initial doped semiconductor layer, and the second initial semiconductor layer is transformed into a second initial doped semiconductor layer;

[0033] Using a laser to pattern the doping source layer in a first preset pattern to remove a portion of the doping source layer corresponding to the second region;

[0034] Removing the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer, and a portion of the second initial doped semiconductor layer corresponding to the second region to form a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer stacked on the first region of the back side of the substrate;

[0035] The doping source layer is removed.

[0036] In one embodiment, in the step of patterning the doping source layer with a laser in a first preset pattern to remove the portion of the doping source layer corresponding to the second region, the process parameters of the laser treatment include: a laser wavelength of 300nm-1000nm; an energy density of the laser of 103W / cm 2 -106W / cm 2, laser line width is 80μm-1500μm; and / or

[0037] The removing of the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer and the portion of the second initial doped semiconductor layer corresponding to the second region specifically includes: using a first etching solution to remove the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer and the portion of the second initial doped semiconductor layer corresponding to the second region; wherein the first etching solution includes an alkali and a polishing additive; the volume of the alkali is 20L-40L, and the volume of the polishing additive is 2L-5L; the temperature of the first etching solution is 60°C-80°C; and the processing time of the first etching solution is 100s-300s.

[0038] In one embodiment, before patterning the doping source layer with a laser in a first preset pattern to remove the portion of the doping source layer corresponding to the second region, the method further includes: forming a protective layer on a side of the doping source layer away from the second initial doped semiconductor layer;

[0039] The method of patterning the doping source layer with a first preset pattern using a laser to remove a portion of the doping source layer corresponding to the second region specifically includes: patterning the doping source layer and the protective layer with a first preset pattern using a laser to remove a portion of the doping source layer corresponding to the second region, and a portion of the protective layer corresponding to the second region.

[0040] In one embodiment, before forming the first electrode electrically connected to the second doped semiconductor layer and the second electrode provided on the second region and electrically connected to the substrate, after forming the first tunneling layer, the first doped semiconductor layer, the second tunneling layer and the second doped semiconductor layer stacked on the first region on the back side of the substrate in a direction away from the substrate, the method further includes:

[0041] Performing a velvet treatment on the second region and the front surface to form a first velvet structure on the second region and a second velvet structure on the front surface; wherein the first velvet structure includes a plurality of first pyramid structures; and the second velvet structure includes a plurality of second pyramid structures;

[0042] Along the direction away from the substrate, a first passivation layer and a first anti-reflection layer are stacked on the side of the second doped semiconductor layer away from the second tunneling layer and on the first velvet structure, and a second passivation layer and a second anti-reflection layer are stacked on the second velvet structure.

[0043] In the technical solution of the present application, a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on a first region on the back side of a substrate. On the one hand, compared with a thicker tunneling layer, in the present application, the thickness of the first tunneling layer or the second tunneling layer in the two tunneling layers can be designed to be thinner, so that the first tunneling layer and the second tunneling layer can jointly play an anti-tunneling role and a passivation role at the same time, thereby enhancing the passivation performance and carrier transport of the back contact battery, thereby improving the electrical properties of the back contact battery such as open circuit voltage and fill factor. On the other hand, compared with a thicker doped semiconductor layer, the present invention Two thinner doped semiconductor layers can be designed in the application, which is beneficial to increase the doping concentration of the first doped semiconductor layer and the second doped semiconductor layer, and further helps to improve the electrical performance of the back contact battery; in addition, the first tunneling layer, the first doped semiconductor layer, the second tunneling layer and the second doped semiconductor layer are stacked on the first area on the back side of the substrate, and a height difference can be formed between the first electrode and the second electrode, and the first electrode and the second electrode can be electrically isolated by the first tunneling layer, which eliminates the need to separate the first area and the second area through an additional grooving process, and can also reduce the probability of short circuit, thereby improving the manufacturing efficiency and reliability of the back contact battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic structural diagram of a back contact battery in one embodiment of the present application is shown.

[0045] Figure 2 A schematic diagram (partial structural diagram) of the process of manufacturing a back-contact battery in one embodiment of the present application is shown.

[0046] Figure 3 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 2 process schematic following the process schematic shown).

[0047] Figure 4 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 3 process schematic following the process schematic shown).

[0048] Figure 5 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 4 process schematic following the process schematic shown).

[0049] Figure 6 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 5 process schematic following the process schematic shown).

[0050] Figure 7 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 6 process schematic following the process schematic shown).

[0051] Figure 8 A schematic diagram of the process of manufacturing a back-contact battery in an embodiment of the present application (schematic diagram of the overall structure) is shown.

[0052] Fig. 9 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 8 process schematic following the process schematic shown).

[0053] Fig.10 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Fig. 9 process schematic following the process schematic shown).

[0054] Fig.11 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Fig.10 process schematic following the process schematic shown).

[0055] Figure numerals: 100, substrate; 101, front side; 102, back side; 1021, first region; 1022, second region; 103, first pyramid structure; 104, second pyramid structure; 105, side; 210, first tunneling layer; 310, first doped semiconductor layer; 220, second tunneling layer; 320, second doped semiconductor layer; 211, first initial tunneling layer; 311, first initial semiconductor layer; 312, first initial doped semiconductor layer; 221, second initial tunneling layer; 321, second initial semiconductor layer; 322, second initial doped semiconductor layer; 400, doping source layer; 500, protective layer; 610, first passivation layer; 620, second passivation layer; 710, first anti-reflection layer; 720, second anti-reflection layer; 810, first electrode; 820, second electrode. DETAILED DESCRIPTION

[0056] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0057] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0058] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0059] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0060] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0061] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0062] Figure 1 A schematic structural diagram of a back contact battery in one embodiment of the present application is shown.

[0063] See also Figure 1 An embodiment of the present application provides a back-contact battery, including a substrate 100 , a first tunneling layer 210 , a first doped semiconductor layer 310 , a second tunneling layer 220 , a second doped semiconductor layer 320 , a first electrode 810 , and a second electrode 820 .

[0064] Along the thickness direction of the substrate 100, the substrate 100 has a front side 101 and a back side 102 arranged in opposite directions, the back side 102 includes a first region 1021 and a second region 1022 arranged alternately, the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220 and the second doped semiconductor layer 320 are stacked on the first region 1021 of the back side 102 in a direction away from the substrate 100; wherein the first doped semiconductor layer 310 and the second doped semiconductor layer 320 have the same conductivity type and are opposite to the conductivity type of the substrate 100. The first electrode 810 is electrically connected to the second doped semiconductor layer 320, and the second electrode 820 is arranged in the second region 1022 and is electrically connected to the substrate 100.

[0065] The substrate 100 is used to receive incident light and generate photogenerated carriers.

[0066] The conductivity type of the substrate 100 may be one of P-type and N-type, and the conductivity type of the first doped semiconductor layer 310 and the second doped semiconductor layer 320 may be the other of P-type and N-type. For example, the conductivity type of the substrate 100 is N-type, and the conductivity type of the first doped semiconductor layer 310 and the second doped semiconductor layer 320 is P-type.

[0067] The front surface 101 of the substrate 100 may be a pyramid-shaped velvet surface, so that the reflectivity of the front surface 101 of the substrate 100 to the incident light is small, thereby the light absorption utilization rate is large. Alternatively, the front surface 101 of the substrate 100 may be a non-pyramid-shaped velvet surface, such as a stacked step morphology. No specific limitation is made here.

[0068] It is possible that at least a portion of the back surface 102 of the substrate 100 is provided as a pyramid-shaped suede surface. It is also possible that the back surface 102 of the substrate 100 is provided as a non-pyramid-shaped suede surface. No specific limitation is made here.

[0069] The materials of the first tunnel layer 210 and the second tunnel layer 220 may be dielectric materials, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or magnesium fluoride.

[0070] The material of the first doped semiconductor layer 310 and the second doped semiconductor layer 320 may be at least one of amorphous silicon, silicon carbide, microcrystalline silicon, or polycrystalline silicon.

[0071] The material of the first electrode 810 and the second electrode 820 may be silver, copper, nickel or aluminum.

[0072] In the technical solution of the present application, a first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220 and a second doped semiconductor layer 320 are stacked on the first region 1021 of the back side 102 of the substrate 100. On the one hand, compared with a thicker tunneling layer, in the present application, the thickness of the first tunneling layer 210 or the second tunneling layer 220 in the two tunneling layers can be designed to be thinner, so that the first tunneling layer 210 and the second tunneling layer 220 can play an anti-tunneling role together and play a passivation role at the same time, thereby enhancing the passivation performance and carrier transport of the back contact battery, thereby improving the electrical properties of the back contact battery such as open circuit voltage and fill factor. On the other hand, compared with a thicker doped semiconductor layer, two tunneling layers can be designed in the present application. A thinner doped semiconductor layer is beneficial for increasing the doping concentration of the first doped semiconductor layer 310 and the second doped semiconductor layer 320, thereby helping to improve the electrical performance of the back contact battery; in addition, the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220 and the second doped semiconductor layer 320 are stacked on the first region 1021 of the back side 102 of the substrate 100, so that a height difference can be formed between the first electrode 810 and the second electrode 820, and the first electrode 810 and the second electrode 820 can be electrically isolated by the first tunneling layer 210, which eliminates the need to separate the first region 1021 and the second region 1022 through an additional grooving process, and can also reduce the probability of a short circuit, thereby improving the manufacturing efficiency and reliability of the back contact battery.

[0073] It should be noted that the second electrode 820 is in contact with the substrate 100, that is, the second electrode 820 is directly electrically connected to the substrate 100, and no conductive layer is provided between the second electrode 820 and the substrate 100, thereby eliminating the step of additionally forming a conductive layer of the opposite conductive type to the first doped semiconductor layer 310, and also eliminating the step of removing the portion of the conductive layer on the first region 1021, thereby eliminating the high-temperature doping process and mask process corresponding to the conductive layer, thereby facilitating the improvement of the reliability and manufacturing efficiency of the back contact battery. It is also convenient to subsequently form a velvet structure on the second region 1022 of the back side 102, thereby improving the absorption utilization rate of the back side 102 of the substrate 100 to light, and also improving the contact effect of the electrode slurry to a certain extent, thereby enabling the second electrode 820 to form a better ohmic contact.

[0074] In some embodiments, the second region 1022 of the back surface 102 has a first textured structure, and the first textured structure includes a plurality of first pyramid structures 103 .

[0075] Thus, by using a plurality of first pyramid structures 103, the reflectivity of the second region 1022 of the back side 102 of the substrate 100 to the incident light can be reduced, thereby increasing the light absorption utilization rate. In addition, the velvet structure can also improve the contact effect of the electrode slurry to a certain extent, thereby enabling the second electrode 820 to form a better ohmic contact.

[0076] In some embodiments, the height of the first pyramid structure 103 along the direction from the front surface 101 to the back surface 102 is 2 μm-5 μm, and the size of the first pyramid structure 103 along the direction perpendicular to the front surface 101 and toward the back surface 102 is 1 μm-5 μm.

[0077] For example, the height of the first pyramid structure 103 is 2 μm, 3 μm, 4 μm or 5 μm along the direction from the front surface 101 to the back surface 102. The size of the first pyramid structure 103 is 1 μm, 2 μm, 3 μm, 4 μm or 5 μm along the direction perpendicular to the front surface 101 to the back surface 102.

[0078] Setting the height of the first pyramid structure 103 within an appropriate range and setting the size of the first pyramid structure 103 in a direction perpendicular to the front side 101 and pointing toward the back side 102 within an appropriate range is beneficial to improving the light absorption efficiency of the second area 1022 of the back side 102 of the substrate 100 and also enables the second electrode 820 to form a better ohmic contact.

[0079] In some embodiments, the front surface 101 has a second velvet structure including a plurality of second pyramid structures 104 .

[0080] In this way, by using a plurality of second pyramid structures 104 , the reflectivity of the front surface 101 of the substrate 100 to the incident light can be reduced, thereby increasing the light absorption utilization rate.

[0081] In some embodiments, the height of the second pyramid structure 104 along the direction from the front surface 101 to the back surface 102 is 1 μm-3 μm, and the size of the second pyramid structure 104 along the direction perpendicular to the front surface 101 and toward the back surface 102 is 1 μm-5 μm.

[0082] For example, the height of the second pyramid structure 104 is 1 μm, 2 μm or 3 μm along the direction from the front surface 101 to the back surface 102 . The size of the second pyramid structure 104 is 1 μm, 2 μm, 3 μm, 4 μm or 5 μm along the direction perpendicular to the front surface 101 to the back surface 102 .

[0083] Setting the height of the second pyramid structure 104 within a suitable range and setting the size of the second pyramid structure 104 in a direction perpendicular to the front side 101 and pointing toward the back side 102 within a suitable range is beneficial to improving the light absorption utilization rate of the front side 101 of the substrate 100 .

[0084] In some embodiments, the sheet resistance of the second doped semiconductor layer 320 is 100Ω / □-300Ω / □.

[0085] For example, the sheet resistance of the second doped semiconductor layer 320 is 100Ω / □, 200Ω / □ or 300Ω / □.

[0086] In some embodiments, the sheet resistance of the first doped semiconductor layer 310 is 100Ω / □-300Ω / □.

[0087] For example, the sheet resistance of the first doped semiconductor layer 310 is 100Ω / □, 200Ω / □ or 300Ω / □.

[0088] The square resistance of the doped region is related to the doping concentration. The greater the doping concentration, the smaller the square resistance, and the smaller the doping concentration, the larger the square resistance. If the square resistance of the first doped semiconductor layer 310 is too large or the square resistance of the second doped semiconductor layer 320 is too large, the doping concentration of the second doped semiconductor layer 320 is too small or the doping concentration of the second doped semiconductor layer 320 is too small, which will cause the overall recombination of the back contact battery to be large and the open circuit voltage of the back contact battery to be low; if the square resistance of the first doped semiconductor layer 310 is too small or the square resistance of the second doped semiconductor layer 320 is too small, the recombination generated by the first doped semiconductor layer 310 or the second doped semiconductor layer 320 is large, so that the recombination of the back contact battery is large, which will also cause the open circuit voltage of the back contact battery to be low. Therefore, the square resistance of the first doped semiconductor layer 310 and the square resistance of the second doped semiconductor layer 320 both need to be selected in a suitable range. For example, when the square resistance of the first doped semiconductor layer 310 is 100Ω / □-300Ω / □ and the square resistance of the second doped semiconductor layer 320 is 100Ω / □-300Ω / □, the overall recombination of the back contact battery can be effectively reduced, thereby increasing the open circuit voltage of the back contact battery, and further improving the performance of the back contact battery.

[0089] In some embodiments, the thickness of the first doped semiconductor layer 310 is 20 nm-100 nm.

[0090] In some embodiments, the second doped semiconductor layer 320 has a thickness of 100 nm-250 nm.

[0091] Setting the thickness of the first doped semiconductor layer 310 within a suitable range, and setting the thickness of the second doped semiconductor layer 320 within a suitable range, for example, setting the thickness of the first doped semiconductor layer 310 to 20nm-100nm, and setting the thickness of the second doped semiconductor layer 320 to 100nm-250nm, is beneficial for doping the corresponding doping elements into the first doped semiconductor layer 310 and the second doped semiconductor layer 320, which is beneficial for increasing the doping concentration of the first doped semiconductor layer 310 and the second doped semiconductor layer 320, and further beneficial for improving the electrical performance of the back contact battery.

[0092] In some embodiments, the thickness of the first tunneling layer 210 is 1 nm-4 nm.

[0093] In some embodiments, the thickness of the second tunneling layer 220 is 1 nm-4 nm.

[0094] The thickness of the first tunneling layer 210 is set within an appropriate range, and the thickness of the second tunneling layer 220 is set within an appropriate range, for example, the thickness of the first tunneling layer 210 is 1nm-4nm, and the thickness of the second tunneling layer 220 is 1nm-4nm, so that the first tunneling layer 210 and the second tunneling layer 220 can jointly play an anti-tunneling role and a passivation role at the same time, thereby enhancing the passivation performance and carrier transport of the back contact battery, thereby improving the electrical properties of the back contact battery such as open circuit voltage and fill factor.

[0095] In some embodiments, the flatness of the first region 1021 is less than the flatness of the second region 1022 .

[0096] In some embodiments, the second area 1022 of the back side 102 has a first velvet structure, the first velvet structure includes a plurality of first pyramid structures 103, the first area 1021 of the back side 102 has a polishing structure, the polishing structure includes a plurality of tower base structures (not shown in the figure), and the height of the first pyramid structure 103 is greater than the height of the tower base structure along the direction from the front side 101 to the back side 102.

[0097] For example, the height of the base structure is less than or equal to one quarter of the height of the first pyramid structure 103 .

[0098] It can be understood that, compared with the first velvet structure including a plurality of first pyramid structures 103, the polished structure is smoother, so that the first tunneling layer 210 located on the first region 1021 of the back side 102 of the substrate 100 can have a higher density and uniformity, so that the first tunneling layer 210 has a good passivation effect on the back side 102 of the substrate 100. In addition, the first pyramid structure 103 can also make the second region 1022 of the back side 102 of the substrate 100 have a lower reflectivity to the incident light, thereby having a higher absorption and utilization rate of the light.

[0099] In some embodiments, the area of ​​the first region 1021 is S1, and the area of ​​the second region 1022 is S2, wherein S1 and S2 have the same unit, and S2 satisfies the following condition: S2 / (S1+S2)=a, and a is 30%-70%.

[0100] Setting a to 30%-70% can make the back contact battery have lower reflectivity, reduce current loss, improve bifaciality, and balance the negative effects such as passivation loss and PN junction area loss caused by the suede structure.

[0101] Please refer to Figure 2-Figure 7 , an embodiment of the present application provides a method for preparing a back contact battery, comprising:

[0102] S10, providing a substrate 100. In the thickness direction of the substrate 100, the substrate 100 has a front side 101 and a back side 102 which are arranged opposite to each other, and the back side 102 includes first regions 1021 and second regions 1022 which are arranged alternately.

[0103] S20, in a direction away from the substrate 100, a first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, and a second doped semiconductor layer 320 are stacked on the first region 1021 of the back side 102 of the substrate 100. The first doped semiconductor layer 310 and the second doped semiconductor layer 320 have the same conductivity type, and are opposite to the conductivity type of the substrate 100.

[0104] Optionally, step S20 of forming a stacked first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, and a second doped semiconductor layer 320 on the first region 1021 of the back side 102 of the substrate 100 in a direction away from the substrate 100 specifically includes:

[0105] S21 , forming a first initial tunneling layer 211 , a first initial semiconductor layer 311 , a second initial tunneling layer 221 , and a second initial semiconductor layer 321 in a stacked manner on the first region 1021 of the back side 102 of the substrate 100 in a direction away from the substrate 100 .

[0106] S22, such as Figure 2 As shown, a doping source layer 400 is formed on a side of the second preliminary semiconductor layer 321 away from the second preliminary tunneling layer 221 .

[0107] The doping source layer 400 may include a P-type or N-type doping element. For example, the doping source layer 400 includes a P-type doping element.

[0108] S23 , diffusing the doping elements in the doping source layer 400 into the first initial semiconductor layer 311 and the second initial semiconductor layer 321 , so that the first initial semiconductor layer 311 is transformed into the first initial doped semiconductor layer 312 , and the second initial semiconductor layer 321 is transformed into the second initial doped semiconductor layer 322 .

[0109] It should be noted that, due to process reasons, some doping elements diffuse into the substrate 100 , but this does not affect the conductivity type of the substrate 100 .

[0110] S24, such as Figure 4 As shown, the doping source layer 400 is patterned with a laser in a first preset pattern to remove the portion of the doping source layer 400 corresponding to the second region 1022 , that is, the portion of the doping source layer 400 corresponding to the first region 1021 is retained.

[0111] S25, such as Figure 5 As shown, the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221 and the second initial doped semiconductor layer 322 corresponding to the second area 1022 are removed to form a stacked first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220 and a second doped semiconductor layer 320 on the first area 1021 of the back side 102 of the substrate 100.

[0112] S26 , removing the doping source layer 400 .

[0113] In the present application, laser grooving technology is used to remove the portion of the doping source layer 400 corresponding to the second region 1022, and the portion of the doping source layer 400 corresponding to the first region 1021 can be used to protect the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220 and the second doped semiconductor layer 320 stacked in layers, thereby abandoning the complicated mask process and achieving a better film opening effect.

[0114] S30, such as Figure 1 As shown, a first electrode 810 electrically connected to the second doped semiconductor layer 320 and a second electrode 820 disposed in the second region 1022 and electrically connected to the substrate 100 are formed.

[0115] In some embodiments, in step S24 of patterning the doping source layer 400 with a laser in a first preset pattern to remove the portion of the doping source layer 400 corresponding to the second region 1022, the process parameters of the laser processing include: the wavelength of the laser is 300nm-1000nm; the energy density of the laser is 103W / cm 2 -106W / cm 2 , the laser line width is 80μm-1500μm.

[0116] For example, the wavelength of the laser is 300 nm, 500 nm, 700 nm, 900 nm or 1000 nm, and the energy density of the laser is 103 W / cm 2 、104W / cm 2 、105W / cm 2 or 106W / cm 2 , the laser line width is 80μm, 100μm, 200μm, 400μm, 600μm, 1000μm, 1200μm, 1400μm or 1500μm.

[0117] The process parameters of the laser treatment are set to include: the wavelength of the laser is 300nm-1000nm; the energy density of the laser is 103W / cm 2 -106W / cm 2The laser line width is 80μm-1500μm, which is conducive to improving the accuracy of laser grooving technology and thus achieving better film opening effect.

[0118] In some embodiments, step S25 of removing the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221, and the second initial doped semiconductor layer 322 corresponding to the second region 1022 specifically includes: using a first etching solution to remove the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221, and the second initial doped semiconductor layer 322 corresponding to the second region 1022. The first etching solution includes an alkali and a polishing additive; the volume of the alkali in the first etching solution is 20L-40L, the volume of the polishing additive in the first etching solution is 2L-5L, the temperature of the first etching solution is 60°C-80°C, and the processing time of the first etching solution is 100s-300s.

[0119] For example, the volume of alkali in the first etching solution is 20L, 30L or 40L, the volume of the polishing additive in the first etching solution is 2L, 3L, 4L or 5L, the temperature of the first etching solution is 60°C, 70°C or 80°C, and the processing time of the first etching solution is 100s, 200s or 300s.

[0120] Laser grooving technology combined with wet etching technology is used to remove the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221 and the second initial doped semiconductor layer 322 corresponding to the second area 1022, thereby abandoning the complicated mask process, improving the manufacturing efficiency of the back contact battery preparation method, and achieving a better film opening effect.

[0121] In some embodiments, Figure 3 As shown, before step S24 of patterning the doping source layer 400 with a first preset pattern using a laser to remove the portion of the doping source layer 400 corresponding to the second region 1022, the method for preparing a back-contact battery also includes: forming a protective layer 500 on the side of the doping source layer 400 away from the second initial doped semiconductor layer 322.

[0122] The step S24 of patterning the doping source layer 400 with a first preset pattern using a laser to remove a portion of the doping source layer 400 corresponding to the second region 1022 specifically includes: patterning the doping source layer 400 and the protective layer 500 with a first preset pattern using a laser to remove a portion of the doping source layer 400 corresponding to the second region 1022 and a portion of the protective layer 500 corresponding to the second region 1022 (such as Figure 4 as shown).

[0123] The portion of the doping source layer 400 corresponding to the first region 1021 and the portion of the protective layer 500 corresponding to the first region 1021 can be used to protect the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220 and the second doped semiconductor layer 320 stacked in layers, thereby abandoning the complicated mask process, improving the manufacturing efficiency of the back contact battery preparation method, and achieving a better film opening effect.

[0124] It should be noted that, before step S26 of removing the doping source layer 400 , the method for preparing a back contact battery further includes: removing the protective layer 500 .

[0125] In some embodiments, before step S30 of forming the first electrode 810 electrically connected to the second doped semiconductor layer 320 and the second electrode 820 disposed on the second region 1022 and electrically connected to the substrate 100, after step S20 of forming the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220, and the second doped semiconductor layer 320 stacked on the first region 1021 of the back side 102 of the substrate 100 in a direction away from the substrate 100, the method for preparing a back contact battery further includes:

[0126] like Figure 6 As shown, the second area 1022 and the front side 101 are subjected to a velvet treatment to form a first velvet structure on the second area 1022 and a second velvet structure on the front side 101 ; wherein the first velvet structure includes a plurality of first pyramid structures 103 , and the second velvet structure includes a plurality of second pyramid structures 104 .

[0127] Optionally, the texturing treatment of the second area 1022 and the front side 101 specifically includes: using a second etching solution to perform texturing treatment on the second area 1022 and the front side 101, wherein the second etching solution includes an alkali and an additive, the volume of the alkali of the second etching solution is 20L-40L, the volume of the additive of the second etching solution is 2L-5L, the temperature of the second etching solution is 60℃-80℃, and the processing time of the second etching solution is 300s-800s.

[0128] For example, the volume of the alkali in the second etching solution is 20L, 30L or 40L, the volume of the additive in the second etching solution is 2L, 3L, 4L or 5L, the temperature of the second etching solution is 60°C, 70°C or 80°C, and the processing time of the second etching solution is 300s, 400s, 500s, 600s, 700s or 800s.

[0129] In this way, along the direction from the front side 101 to the back side 102, the height of the first pyramid structure 103 can be 2μm-5μm, and the height of the second pyramid structure 104 can be 1μm-3μm. In addition, along the direction perpendicular to the front side 101 to the back side 102, the sizes of the first pyramid structure 103 and the second pyramid structure 104 can be 1μm-5μm, so that the reflectivity of the second region 1022 can reach 8%-10%.

[0130] like Figure 7 As shown, in the direction away from the substrate 100, a first passivation layer 610 and a first anti-reflection layer 710 are stacked on the side of the second doped semiconductor layer 320 away from the second tunneling layer 220 and on the first velvet structure, and a second passivation layer 620 and a second anti-reflection layer 720 are stacked on the second velvet structure.

[0131] The first anti-reflection layer 710 and the second anti-reflection layer 720 can be formed by physical vapor deposition or plasma enhanced chemical vapor deposition (PECVD). The material of the first anti-reflection layer 710 and the second anti-reflection layer 720 can be silicon nitride (SiN x ), silicon oxynitride (SiON x ) and silicon oxide (SiO x ) layer, can utilize the first anti-reflection layer 710 and the second anti-reflection layer 720 to improve the light absorption efficiency of the substrate 100, enhance the light utilization rate, and help to improve the short-circuit current of the back contact battery, thereby improving the photoelectric conversion efficiency of the back contact battery, and also help to improve the isolation effect between the back contact battery and the outside world.

[0132] The first passivation layer 610 may be formed on the side of the second doped semiconductor layer 320 away from the second tunneling layer 220 and on the first texture structure by atomic layer deposition, and the second passivation layer 620 may be formed on the second texture structure by atomic layer deposition.

[0133] The material of the first passivation layer 610 and the second passivation layer 620 can be aluminum oxide (AlO x ).

[0134] By using the first passivation layer 610 and the second passivation layer 620 , the passivation performance of the back contact cell can be improved.

[0135] In some embodiments, please refer to Figure 8-Figure 11 , the preparation method of the back contact battery comprises:

[0136] S110 , providing a substrate 100 , wherein the substrate 100 is an N-type silicon substrate.

[0137] S120, performing double-sided polishing on the substrate 100, and using an existing polishing liquid (a combination of alkali and additives) to perform double-sided polishing on the substrate 100.

[0138] S210 , forming a first initial tunneling layer 211 , a first initial semiconductor layer 311 , a second initial tunneling layer 221 , and a second initial semiconductor layer 321 which are stacked on the substrate 100 in a direction away from the substrate 100 .

[0139] S220, such as Figure 8 As shown, a doping source layer 400 is formed on a side of the second initial semiconductor layer 321 away from the second initial tunneling layer 221. The doping source layer 400 may be a borosilicate glass layer.

[0140] S230 , diffusing the doping elements in the doping source layer 400 into the first initial semiconductor layer 311 and the second initial semiconductor layer 321 , so that the first initial semiconductor layer 311 is transformed into the first initial doped semiconductor layer 312 , and the second initial semiconductor layer 321 is transformed into the second initial doped semiconductor layer 322 .

[0141] S240, such as Fig. 9 As shown, a protective layer 500 is formed on a side of the doping source layer 400 away from the second initial doped semiconductor layer 322. Optionally, a tubular or chain oxidation process may be used to form the protective layer 500 on a side of the doping source layer 400 away from the second initial doped semiconductor layer 322, and the thickness of the protective layer 500 may be 100nm-200nm, and the material of the protective layer 500 may be silicon oxide.

[0142] S250, such as Fig.10 As shown, the doping source layer 400 and the protective layer 500 are patterned with a laser in a first preset pattern to remove a portion of the doping source layer 400 corresponding to the second region 1022 and a portion of the protective layer 500 corresponding to the second region 1022 .

[0143] S260 , using hydrofluoric acid (HF) to remove the doping source layer 400 and the protective layer 500 extending around the front surface 101 and the side surface 105 . The side surface 105 refers to the surface of the substrate 100 that is connected between the front surface 101 and the back surface 102 .

[0144] S270, such as Fig.11 As shown, a first etching solution is used to remove the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221 and the second initial doped semiconductor layer 322 corresponding to the second area 1022 to form a stacked first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220 and a second doped semiconductor layer 320 on the first area 1021 of the back side 102 of the substrate 100.

[0145] S310, using a second etching solution to perform a texturing treatment on the second area 1022 and the front side 101 to form a first texturing structure on the second area 1022 and a second texturing structure on the front side 101; wherein the first texturing structure includes a plurality of first pyramid structures 103, and the second texturing structure includes a plurality of second pyramid structures 104.

[0146] S320, using hydrofluoric acid (HF) to remove the doping source layer 400 and the protective layer 500. In this process, the hydrofluoric acid (HF) will not wash away the substrate 100 and the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220 and the second doped semiconductor layer 320 stacked on the substrate 100.

[0147] S330, along the direction away from the substrate 100, a first passivation layer 610 and a first anti-reflection layer 710 are stacked on the side of the second doped semiconductor layer 320 away from the second tunneling layer 220 and on the first velvet structure, and a second passivation layer 620 and a second anti-reflection layer 720 are stacked on the second velvet structure.

[0148] S400 , forming a first electrode 810 electrically connected to the second doped semiconductor layer 320 , and a second electrode 820 disposed in the second region 1022 and electrically connected to the substrate 100 .

[0149] The first electrode 810 and the second electrode 820 may be formed by screen printing, and the first electrode 810 and the second electrode 820 may be sintered at a high temperature of 700° C. to 800° C. to form a good ohmic contact.

[0150] The back contact cell of the present application is compatible with the advantages of Topcon and BC cells. At the same time, the second area 1022 of the back side 102 and the front side 101 are designed as a velvet structure, which can reduce the reflectivity of the back side 102, thereby improving the double-sidedness of the back contact cell. Compared with the polished structure, the velvet structure is more conducive to the contact of the metal paste, and the second electrode 820 can form a better ohmic contact, thereby improving the contact and increasing the fill factor.

[0151] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0152] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A back contact battery, characterized in that: include: A substrate, wherein along a thickness direction of the substrate, the substrate has a front side and a back side that are arranged opposite to each other, and the back side includes first areas and second areas that are arranged alternately; A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on the first region of the back side in a direction away from the substrate; wherein the first doped semiconductor layer has the same conductivity type as the second doped semiconductor layer and is opposite to the conductivity type of the substrate; A first electrode electrically connected to the second doped semiconductor layer; and The second electrode is disposed in the second region and is electrically connected to the substrate.

2. The back contact cell according to claim 1, characterized in that: The second area of ​​the back surface has a first velvet structure, wherein the first velvet structure includes a plurality of first pyramid structures; Along the direction from the front side to the back side, the height of the first pyramid structure is 2 μm-5 μm; Along a direction perpendicular to the front surface and pointing toward the back surface, a size of the first pyramid structure is 1 μm-5 μm.

3. The back contact cell according to claim 1, characterized in that: The front side has a second velvet structure, and the second velvet structure includes a plurality of second pyramid structures; Along the direction from the front side to the back side, the height of the second pyramid structure is 1 μm-3 μm; Along a direction perpendicular to the front surface and pointing toward the back surface, a size of the second pyramid structure is 1 μm-5 μm.

4. The back contact cell according to claim 1, characterized in that: The sheet resistance of the second doped semiconductor layer is 100Ω / □-300Ω / □; and / or The sheet resistance of the first doped semiconductor layer is 100Ω / □-300Ω / □; and / or The thickness of the first doped semiconductor layer is 20nm-100nm; and / or The thickness of the second doped semiconductor layer is 100 nm-250 nm; and / or The thickness of the first tunneling layer is 1 nm-4 nm; and / or The thickness of the second tunneling layer is 1 nm-4 nm.

5. The back contact cell according to claim 1, characterized in that: The flatness of the first region is less than the flatness of the second region; and / or The second area of ​​the back side has a first velvet structure, the first velvet structure includes a plurality of first pyramid structures; the first area of ​​the back side has a polished structure, the polished structure includes a plurality of tower base structures, and the height of the first pyramid structure is greater than the height of the tower base structure in the direction from the front side to the back side; and / or The area of ​​the first region is S1, and the area of ​​the second region is S2, wherein S1 and S2 have the same unit, and S2 satisfies the following condition: S2 / (S1+S2)=a, where a is 30%-70%.

6. A method for preparing a back contact battery, characterized in that: include: Providing a substrate, wherein along a thickness direction of the substrate, the substrate has a front side and a back side that are arranged opposite to each other, and the back side includes first areas and second areas that are arranged alternately; A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on the first region of the back side of the substrate in a direction away from the substrate; wherein the first doped semiconductor layer has the same conductivity type as the second doped semiconductor layer and is opposite to the conductivity type of the substrate; A first electrode electrically connected to the second doped semiconductor layer and a second electrode disposed on the second region and electrically connected to the substrate are formed.

7. The method for preparing a back contact battery according to claim 6, characterized in that: The forming of a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer stacked on the first region of the back side of the substrate in a direction away from the substrate specifically includes: forming a first initial tunneling layer, a first initial semiconductor layer, a second initial tunneling layer, and a second initial semiconductor layer stacked on the first region of the back side of the substrate in a direction away from the substrate; forming a doping source layer on a side of the second initial semiconductor layer away from the second initial tunneling layer; Diffusion of the doping element in the doping source layer into the first initial semiconductor layer and the second initial semiconductor layer, so that the first initial semiconductor layer is transformed into a first initial doped semiconductor layer, and the second initial semiconductor layer is transformed into a second initial doped semiconductor layer; Using a laser to pattern the doping source layer in a first preset pattern to remove a portion of the doping source layer corresponding to the second region; Removing the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer, and a portion of the second initial doped semiconductor layer corresponding to the second region to form a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer stacked on the first region of the back side of the substrate; The doping source layer is removed.

8. The method for preparing a back contact battery according to claim 7, characterized in that: In the step of patterning the doping source layer with a laser in a first preset pattern to remove the portion of the doping source layer corresponding to the second region, the process parameters of the laser treatment include: a laser wavelength of 300nm-1000nm; an energy density of the laser of 103W / cm 2 -106W / cm 2 , laser line width is 80μm-1500μm; and / or The removing of the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer and the portion of the second initial doped semiconductor layer corresponding to the second region specifically includes: using a first etching solution to remove the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer and the portion of the second initial doped semiconductor layer corresponding to the second region; wherein the first etching solution includes an alkali and a polishing additive; the volume of the alkali is 20L-40L, and the volume of the polishing additive is 2L-5L; the temperature of the first etching solution is 60°C-80°C; and the processing time of the first etching solution is 100s-300s.

9. The method for preparing a back contact battery according to claim 7, characterized in that: Before patterning the doping source layer with a laser in a first preset pattern to remove the portion of the doping source layer corresponding to the second region, the method further includes: forming a protective layer on a side of the doping source layer away from the second initial doped semiconductor layer; The method of patterning the doping source layer with a first preset pattern using a laser to remove a portion of the doping source layer corresponding to the second region specifically includes: patterning the doping source layer and the protective layer with a first preset pattern using a laser to remove a portion of the doping source layer corresponding to the second region, and a portion of the protective layer corresponding to the second region.

10. The method for preparing a back contact battery according to claim 6, characterized in that: Before forming the first electrode electrically connected to the second doped semiconductor layer and the second electrode provided on the second region and electrically connected to the substrate, after forming the first tunneling layer, the first doped semiconductor layer, the second tunneling layer and the second doped semiconductor layer stacked on the first region on the back side of the substrate in a direction away from the substrate, the method further includes: Performing a velvet treatment on the second region and the front surface to form a first velvet structure on the second region and a second velvet structure on the front surface; wherein the first velvet structure includes a plurality of first pyramid structures; and the second velvet structure includes a plurality of second pyramid structures; Along the direction away from the substrate, a first passivation layer and a first anti-reflection layer are stacked on the side of the second doped semiconductor layer away from the second tunneling layer and on the first velvet structure, and a second passivation layer and a second anti-reflection layer are stacked on the second velvet structure.

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