Back-contact battery and method for preparing back-contact battery

Abstract

The present application relates to a back-contact battery and a method for manufacturing the back-contact battery. The back-contact battery includes a substrate, a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, a second doped semiconductor layer, a first electrode, and a second electrode. Along the thickness direction of the substrate, the substrate has a front surface and a back surface that are opposite to each other, and the back surface includes alternately arranged first regions and second regions. The first tunneling layer, the first doped semiconductor layer, the second tunneling layer, and the second doped semiconductor layer are stacked on the first region of the back surface in a direction away from the substrate. The first electrode is electrically connected to the second doped semiconductor layer, and the second electrode is disposed in the second region and is electrically connected to the substrate. It is possible to omit the step of separating the first region and the second region by an additional grooving process, and at the same time, the probability of short circuit can be reduced, thereby improving the manufacturing efficiency and reliability of the back-contact battery.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular, to a back-contact battery and a method for manufacturing the back-contact battery. Background Art

[0002] The electrodes of the back-contact battery are disposed on the back surface of the back-contact battery, so that there is no electrode shielding on the front surface of the back-contact battery, thereby increasing the area of the back-contact battery that absorbs sunlight, and further improving the conversion efficiency of the back-contact battery.

[0003] In related technologies, the manufacturing process of the back-contact battery generally includes: separating the P region and the N region on the back surface of the back-contact battery through a grooving process (the P region refers to the region on the back surface of the back-contact battery for setting the P-type doping layer, and the N region refers to the region on the back surface of the back-contact battery for setting the N-type doping layer), so as to reduce the probability of short circuit. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a back-contact battery and a method for manufacturing the back-contact battery, which can improve the manufacturing efficiency of the back-contact battery.

[0005] According to the first aspect of the present application, a back-contact battery is provided, including:

[0006] A substrate, along the thickness direction of the substrate, the substrate has a front surface and a back surface arranged opposite to each other, and the back surface includes an alternately arranged first region and second region;

[0007] A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer, which are stacked on the first region of the back surface along a direction away from the substrate; wherein, the first doped semiconductor layer and the second doped semiconductor layer have the same conduction type and are opposite to the conduction type of the substrate;

[0008] A first electrode, electrically connected to the second doped semiconductor layer; and

[0009] A second electrode, disposed on the second region and electrically connected to the substrate.

[0010] In one embodiment, the second region of the back surface has a first textured structure, and the first textured structure includes a plurality of first pyramid structures;

[0011] Along the direction from the front surface to the back surface, the height of the first pyramid structure is 2 μm - 5 μm;

[0012] Along the direction perpendicular to the direction from the front surface to the back surface, the size of the first pyramid structure is 1 μm - 5 μm.

[0013] In one embodiment, the front surface has a second suede structure, and the second suede structure includes a plurality of second pyramid structures;

[0014] In the direction from the front surface to the back surface, the height of the second pyramid structure is 1 μm - 3 μm;

[0015] In the direction perpendicular to the front surface and pointing to the back surface, the size of the second pyramid structure is 1 μm - 5 μm.

[0016] In one embodiment, the sheet resistance of the second doped semiconductor layer is 100 Ω / sq - 300 Ω / sq; and / or

[0017] the sheet resistance of the first doped semiconductor layer is 100 Ω / sq - 300 Ω / sq; and / or

[0018] the thickness of the first doped semiconductor layer is 20 nm - 100 nm; and / or

[0019] the thickness of the second doped semiconductor layer is 100 nm - 250 nm; and / or

[0020] the thickness of the first tunneling layer is 1 nm - 4 nm; and / or

[0021] the thickness of the second tunneling layer is 1 nm - 4 nm.

[0022] In one embodiment, compared with the second region, the first region is flatter; and / or

[0023] The second region of the back surface has a first suede structure, and the first suede structure includes a plurality of first pyramid structures; the first region of the back surface has a polishing structure, and the polishing structure includes a plurality of base structures. In the direction from the front surface to the back surface, the height of the first pyramid structure is greater than the height of the base structure; and / or

[0024] The area of the first region is S1, and the area of the second region is S2. Wherein, S1 and S2 have the same unit, and S2 satisfies the following condition: S2 / (S1 + S2) = a, and a is 30% - 70%.

[0025] According to the second aspect of the present application, there is provided a method for manufacturing a back contact battery, including:

[0026] Providing a substrate, in the thickness direction of the substrate, the substrate has a front surface and a back surface arranged opposite to each other, and the back surface includes an alternately arranged first region and a second region;

[0027] Stack a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer in sequence on the first region of the back surface of the substrate in a direction away from the substrate; wherein, the first doped semiconductor layer and the second doped semiconductor layer have the same conductivity type, and have a conductivity type opposite to that of the substrate.

[0028] Form a first electrode electrically connected to the second doped semiconductor layer, and a second electrode disposed on the second region and electrically connected to the substrate.

[0029] In one embodiment, the step of stacking a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer in sequence on the first region of the back surface of the substrate in a direction away from the substrate specifically includes:

[0030] Stack a first initial tunneling layer, a first initial semiconductor layer, a second initial tunneling layer, and a second initial semiconductor layer in sequence on the first region of the back surface of the substrate in a direction away from the substrate.

[0031] Form a doping source layer on a side of the second initial semiconductor layer away from the second initial tunneling layer.

[0032] Diffuse doping elements in the doping source layer into the first initial semiconductor layer and the second initial semiconductor layer, so that the first initial semiconductor layer is transformed into a first initially doped semiconductor layer, and the second initial semiconductor layer is transformed into a second initially doped semiconductor layer.

[0033] Use a laser to pattern the doping source layer with a first preset pattern to remove a portion of the doping source layer corresponding to the second region.

[0034] Remove portions of the first initial tunneling layer, the first initially doped semiconductor layer, the second initial tunneling layer, and the second initially doped semiconductor layer corresponding to the second region, so as to form a stacked first tunneling layer, first doped semiconductor layer, second tunneling layer, and second doped semiconductor layer on the first region of the back surface of the substrate.

[0035] Remove the doping source layer.

[0036] In one embodiment, in the step of using a laser to pattern the doping source layer with a first preset pattern to remove a portion of the doping source layer corresponding to the second region, the process parameters of the laser treatment include: the wavelength of the laser is 300 nm - 1000 nm; the energy density of the laser is 103 W / cm 2 -106 W / cm 2, the laser line width is 80 μm - 1500 μm; and / or

[0037] Removing the portions of the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer, and the second initial doped semiconductor layer corresponding to the second region specifically includes: using a first etching solution to remove the portions of the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer, and the second initial doped semiconductor layer corresponding to the second region; wherein, the first etching solution includes an alkali and a polishing additive; the volume of the alkali is 20 L - 40 L, the volume of the polishing additive is 2 L - 5 L; the temperature of the first etching solution is 60°C - 80°C; the processing time of the first etching solution is 100 s - 300 s.

[0038] In one embodiment, before using the laser to pattern the doping source layer with a first preset pattern to remove the portion of the doping source layer corresponding to the second region, it further includes: forming a protective layer on the side of the doping source layer facing away from the second initial doped semiconductor layer;

[0039] Using the laser to pattern the doping source layer with a first preset pattern to remove the portion of the doping source layer corresponding to the second region specifically includes: using the laser to pattern the doping source layer and the protective layer with a first preset pattern to remove the portion of the doping source layer corresponding to the second region and the portion of the protective layer corresponding to the second region.

[0040] In one embodiment, before forming the first electrode electrically connected to the second doped semiconductor layer and the second electrode disposed on the second region and electrically connected to the substrate, after forming the first tunneling layer, the first doped semiconductor layer, the second tunneling layer, and the second doped semiconductor layer stacked on the first region of the back surface of the substrate in a direction away from the substrate, it further includes:

[0041] Texturing the second region and the front surface to form a first textured surface structure on the second region and a second textured surface structure on the front surface; wherein, the first textured surface structure includes a plurality of first pyramid structures; the second textured surface structure includes a plurality of second pyramid structures;

[0042] In a direction away from the substrate, a first passivation layer and a first antireflection layer are formed stacked on the side of the second doped semiconductor layer facing away from the second tunneling layer and the first textured surface structure, and a second passivation layer and a second antireflection layer are formed stacked on the second textured surface structure.

[0043] In the technical solution of the present application, a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on a first region on the back surface of the substrate. On the one hand, compared with a relatively thick tunneling layer, in the present application, on the basis that the thickness of the first tunneling layer or the second tunneling layer in the two tunneling layers can be designed to be thinner, the two tunneling layers, namely the first tunneling layer and the second tunneling layer, can jointly play a role in preventing tunneling and can also play a passivation role at the same time, thereby enhancing the passivation performance and carrier transport of the back contact battery, and thus improving the electrical performance of the back contact battery such as open circuit voltage and fill factor, etc.; on the other hand, compared with a relatively thick doped semiconductor layer, in the present application, two relatively thin doped semiconductor layers can be designed, which is beneficial to increasing the doping concentration of the first doped semiconductor layer and the second doped semiconductor layer, and further beneficial to improving the electrical performance of the back contact battery; in addition, by stacking the first tunneling layer, the first doped semiconductor layer, the second tunneling layer, and the second doped semiconductor layer on the first region on the back surface of the substrate, a height difference can also be formed between the first electrode and the second electrode, and the first electrode and the second electrode can be electrically isolated through the first tunneling layer. While eliminating the need to separate the first region and the second region through an additional grooving process, the probability of short circuit can also be reduced, and thus the manufacturing efficiency and reliability of the back contact battery can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 FIG. shows a schematic structural diagram of a back contact battery in an embodiment of the present application.

[0045] Figure 2 FIG. shows a schematic process diagram (partial structural diagram) of a manufacturing method of a back contact battery in an embodiment of the present application.

[0046] Figure 3 FIG. shows a schematic process diagram of a manufacturing method of a back contact battery in an embodiment of the present application (a process diagram after the process shown in Figure 2 ).

[0047] Figure 4 FIG. shows a schematic process diagram of a manufacturing method of a back contact battery in an embodiment of the present application (a process diagram after the process shown in Figure 3 ).

[0048] Figure 5 FIG. shows a schematic process diagram of a manufacturing method of a back contact battery in an embodiment of the present application (a process diagram after the process shown in Figure 4 ).

[0049] Figure 6 FIG. shows a schematic process diagram of a manufacturing method of a back contact battery in an embodiment of the present application (a process diagram after the process shown in Figure 5 ).

[0050] Figure 7 Shows a process schematic diagram of the manufacturing method of a back-contact battery in an embodiment of the present application (a process schematic diagram after the Figure 6 shown process schematic diagram).

[0051] Figure 8 Shows a process schematic diagram of the manufacturing method of a back-contact battery in an embodiment of the present application (overall structure schematic diagram).

[0052] Figure 9 Shows a process schematic diagram of the manufacturing method of a back-contact battery in an embodiment of the present application (a process schematic diagram after the Figure 8 shown process schematic diagram).

[0053] Figure 10 Shows a process schematic diagram of the manufacturing method of a back-contact battery in an embodiment of the present application (a process schematic diagram after the Figure 9 shown process schematic diagram).

[0054] Figure 11 Shows a process schematic diagram of the manufacturing method of a back-contact battery in an embodiment of the present application (a process schematic diagram after the Figure 10 shown process schematic diagram).

[0055] Reference numerals: 100, substrate; 101, front surface; 102, back surface; 1021, first region; 1022, second region; 103, first pyramid structure; 104, second pyramid structure; 105, side surface; 210, first tunneling layer; 310, first doped semiconductor layer; 220, second tunneling layer; 320, second doped semiconductor layer; 211, first initial tunneling layer; 311, first initial semiconductor layer; 312, first initial doped semiconductor layer; 221, second initial tunneling layer; 321, second initial semiconductor layer; 322, second initial doped semiconductor layer; 400, doping source layer; 500, protective layer; 610, first passivation layer; 620, second passivation layer; 710, first antireflection layer; 720, second antireflection layer; 810, first electrode; 820, second electrode. Detailed implementation manners

[0056] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe in detail the specific implementation manners of the present application with reference to the accompanying drawings. Many specific details are set forth in the following description in order to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0057] In the description of the present application, it should be understood that if there are terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., the orientation or positional relationship indicated by these terms is based on the orientation or positional relationship shown in the drawings. These are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0058] In addition, if there are terms such as "first" and "second", these terms are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, if there is a term "plurality", the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0059] In the present application, unless otherwise clearly specified and limited, if there are terms such as "installed", "connected", "joined", "fixed", etc., these terms should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0060] In the present application, unless otherwise clearly specified and limited, if there is a description such as a first feature being "on" or "under" a second feature, etc., its meaning may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0061] It should be noted that if an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there can also be an intermediate element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intermediate element at the same time. If present, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are only for the purpose of illustration and do not represent the only implementation.

[0062] Figure 1 The structural schematic diagram of a back contact battery in an embodiment of the present application is shown.

[0063] Please refer to Figure 1 , an embodiment of the present application provides a back contact battery, including a substrate 100, a first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, a second doped semiconductor layer 320, a first electrode 810 and a second electrode 820.

[0064] Along the thickness direction of the substrate 100, the substrate 100 has a front surface 101 and a back surface 102 arranged opposite to each other. The back surface 102 includes an alternating first region 1021 and a second region 1022. The first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220 and the second doped semiconductor layer 320 are stacked on the first region 1021 of the back surface 102 in a direction away from the substrate 100; wherein, the first doped semiconductor layer 310 and the second doped semiconductor layer 320 have the same conductivity type and are opposite to the conductivity type of the substrate 100. The first electrode 810 is electrically connected to the second doped semiconductor layer 320, and the second electrode 820 is disposed in the second region 1022 and is electrically connected to the substrate 100.

[0065] The substrate 100 is used to receive incident light and generate photo-generated carriers.

[0066] It can be that the conductivity type of the substrate 100 is one of P-type and N-type, and the conductivity type of the first doped semiconductor layer 310 and the second doped semiconductor layer 320 is the other of P-type and N-type. Exemplarily, the conductivity type of the substrate 100 is N-type, and the conductivity type of the first doped semiconductor layer 310 and the second doped semiconductor layer 320 is P-type.

[0067] It can be that the front surface 101 of the substrate 100 is set as a pyramid-shaped textured surface, so that the reflectivity of the front surface 101 of the substrate 100 to incident light is small, and thus the absorption and utilization rate of light is large. It can also be that the front surface 101 of the substrate 100 is set as a non-pyramid-shaped textured surface, such as a stacked step morphology. No specific limitation is made here.

[0068] It may be that at least part of the back surface 102 of the substrate 100 is provided as a pyramidal matte surface. Alternatively, the back surface 102 of the substrate 100 may be provided as a non-pyramidal matte surface. There is no specific limitation here.

[0069] The materials of the first tunneling layer 210 and the second tunneling layer 220 may be dielectric materials, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or magnesium fluoride.

[0070] The materials of the first doped semiconductor layer 310 and the second doped semiconductor layer 320 may be at least one of amorphous silicon, silicon carbide, microcrystalline silicon, or polycrystalline silicon.

[0071] The materials of the first electrode 810 and the second electrode 820 may be silver, copper, nickel, or aluminum.

[0072] In the technical solution of this application, the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220, and the second doped semiconductor layer 320 are stacked on the first region 1021 of the back surface 102 of the substrate 100. On the one hand, compared with a thicker tunneling layer, in this application, on the basis that the thickness of the first tunneling layer 210 or the second tunneling layer 220 in the two tunneling layers can be designed thinner, the two tunneling layers, namely the first tunneling layer 210 and the second tunneling layer 220, can jointly play a role in preventing tunneling and can also play a passivation role at the same time, thereby enhancing the passivation performance and carrier transport of the back contact battery, and thus improving the electrical performance of the back contact battery such as open circuit voltage and fill factor, etc.; on the other hand, compared with a thicker doped semiconductor layer, in this application, two thinner doped semiconductor layers can be designed, which is beneficial to increasing the doping concentration of the first doped semiconductor layer 310 and the second doped semiconductor layer 320, and further beneficial to improving the electrical performance of the back contact battery; in addition, by stacking the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220, and the second doped semiconductor layer 320 on the first region 1021 of the back surface 102 of the substrate 100, a height difference can also be formed between the first electrode 810 and the second electrode 820, and the first electrode 810 and the second electrode 820 can be electrically isolated through the first tunneling layer 210. While eliminating the need to separate the first region 1021 and the second region 1022 through an additional grooving process, the probability of short circuit can also be reduced, and thus the manufacturing efficiency and reliability of the back contact battery can be improved.

[0073] It should be noted that the second electrode 820 is in contact with the substrate 100. That is to say, the second electrode 820 is directly electrically connected to the substrate 100, and no conductive layer is provided between the second electrode 820 and the substrate 100. This omits the step of additionally forming a conductive layer with a conductivity type opposite to that of the first doped semiconductor layer 310, and also omits the step of removing the portion of the conductive layer on the first region 1021. The high-temperature doping process and the mask process corresponding to the conductive layer can be omitted, which is conducive to improving the reliability and manufacturing efficiency of the back-contact battery. It is also convenient to form a textured structure on the second region 1022 of the back surface 102 subsequently, which can improve the light absorption utilization rate of the back surface 102 of the substrate 100, and can also improve the contact effect of the electrode paste to a certain extent, so that the second electrode 820 can form a better ohmic contact.

[0074] In some embodiments, the second region 1022 of the back surface 102 has a first textured structure, and the first textured structure includes a plurality of first pyramid structures 103.

[0075] In this way, by using the plurality of first pyramid structures 103, the reflectivity of the second region 1022 of the back surface 102 of the substrate 100 to incident light can be made smaller, so that the light absorption utilization rate is larger. In addition, the textured structure can also improve the contact effect of the electrode paste to a certain extent, so that the second electrode 820 can form a better ohmic contact.

[0076] In some embodiments, along the direction from the front surface 101 to the back surface 102, the height of the first pyramid structure 103 is 2 μm - 5 μm, and along the direction perpendicular to the direction from the front surface 101 to the back surface 102, the size of the first pyramid structure 103 is 1 μm - 5 μm.

[0077] Exemplarily, along the direction from the front surface 101 to the back surface 102, the height of the first pyramid structure 103 is 2 μm, 3 μm, 4 μm or 5 μm. Along the direction perpendicular to the direction from the front surface 101 to the back surface 102, the size of the first pyramid structure 103 is 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0078] Setting the height of the first pyramid structure 103 within a suitable range and setting the size of the first pyramid structure 103 along the direction perpendicular to the direction from the front surface 101 to the back surface 102 within a suitable range are conducive to improving the light absorption utilization rate of the second region 1022 of the back surface 102 of the substrate 100, and can also enable the second electrode 820 to form a better ohmic contact.

[0079] In some embodiments, the front surface 101 has a second textured structure, and the second textured structure includes a plurality of second pyramid structures 104.

[0080] Thus, by using multiple second pyramid structures 104, the reflectivity of the front surface 101 of the substrate 100 to incident light can be made smaller, so that the absorption and utilization rate of light is larger.

[0081] In some embodiments, along the direction from the front surface 101 to the back surface 102, the height of the second pyramid structure 104 is 1 μm - 3 μm, and along the direction perpendicular to the front surface 101 and pointing to the back surface 102, the size of the second pyramid structure 104 is 1 μm - 5 μm.

[0082] Exemplarily, along the direction from the front surface 101 to the back surface 102, the height of the second pyramid structure 104 is 1 μm, 2 μm or 3 μm. Along the direction perpendicular to the front surface 101 and pointing to the back surface 102, the size of the second pyramid structure 104 is 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0083] Setting the height of the second pyramid structure 104 within a suitable range and setting the size of the second pyramid structure 104 along the direction perpendicular to the front surface 101 and pointing to the back surface 102 within a suitable range are beneficial to improving the absorption and utilization rate of light by the front surface 101 of the substrate 100.

[0084] In some embodiments, the sheet resistance of the second doped semiconductor layer 320 is 100 Ω / sq - 300 Ω / sq.

[0085] Exemplarily, the sheet resistance of the second doped semiconductor layer 320 is 100 Ω / sq, 200 Ω / sq or 300 Ω / sq.

[0086] In some embodiments, the sheet resistance of the first doped semiconductor layer 310 is 100 Ω / sq - 300 Ω / sq.

[0087] Exemplarily, the sheet resistance of the first doped semiconductor layer 310 is 100 Ω / sq, 200 Ω / sq or 300 Ω / sq.

[0088] The sheet resistance of the doped region is related to the doping concentration. The greater the doping concentration, the smaller the sheet resistance; the smaller the doping concentration, the greater the sheet resistance. If the sheet resistance of the first doped semiconductor layer 310 is too large or the sheet resistance of the second doped semiconductor layer 320 is too large, it means that the doping concentration of the second doped semiconductor layer 320 is too small or the doping concentration of the second doped semiconductor layer 320 is too small, which will lead to a large overall recombination of the back-contact battery and a low open-circuit voltage of the back-contact battery. If the sheet resistance of the first doped semiconductor layer 310 is too small or the sheet resistance of the second doped semiconductor layer 320 is too small, the recombination generated by the first doped semiconductor layer 310 or the second doped semiconductor layer 320 is large, resulting in a large recombination of the back-contact battery and also causing a low open-circuit voltage of the back-contact battery. Therefore, the sheet resistance of the first doped semiconductor layer 310 and the sheet resistance of the second doped semiconductor layer 320 both need to be selected within a suitable range. For example, when the sheet resistance of the first doped semiconductor layer 310 is 100 Ω / sq - 300 Ω / sq and the sheet resistance of the second doped semiconductor layer 320 is 100 Ω / sq - 300 Ω / sq, the overall recombination of the back-contact battery can be effectively reduced, thereby increasing the open-circuit voltage of the back-contact battery and further improving the performance of the back-contact battery.

[0089] In some embodiments, the thickness of the first doped semiconductor layer 310 is 20 nm - 100 nm.

[0090] In some embodiments, the thickness of the second doped semiconductor layer 320 is 100 nm - 250 nm.

[0091] Setting the thickness of the first doped semiconductor layer 310 within a suitable range and setting the thickness of the second doped semiconductor layer 320 within a suitable range, for example, setting the thickness of the first doped semiconductor layer 310 to be 20 nm - 100 nm and setting the thickness of the second doped semiconductor layer 320 to be 100 nm - 250 nm, is beneficial for the corresponding doping elements to be incorporated into the first doped semiconductor layer 310 and the second doped semiconductor layer 320, which is conducive to increasing the doping concentration of the first doped semiconductor layer 310 and the second doped semiconductor layer 320, and further conducive to improving the electrical performance of the back-contact battery.

[0092] In some embodiments, the thickness of the first tunneling layer 210 is 1 nm - 4 nm.

[0093] In some embodiments, the thickness of the second tunneling layer 220 is 1 nm - 4 nm.

[0094] Set the thickness of the first tunneling layer 210 within an appropriate range, and set the thickness of the second tunneling layer 220 within an appropriate range. For example, the thickness of the first tunneling layer 210 is 1 nm - 4 nm, and for example, the thickness of the second tunneling layer 220 is 1 nm - 4 nm. Enable the two tunneling layers, namely the first tunneling layer 210 and the second tunneling layer 220, to jointly play a role in preventing tunneling and at the same time play a passivation role, thereby enhancing the passivation performance and carrier transport of the back contact battery, and thus improving the electrical performance of the back contact battery such as open-circuit voltage and fill factor, etc.

[0095] In some embodiments, the first region 1021 is flatter than the second region 1022.

[0096] In some embodiments, the second region 1022 of the back surface 102 has a first textured structure, the first textured structure includes a plurality of first pyramid structures 103, the first region 1021 of the back surface 102 has a polished structure, the polished structure includes a plurality of tower base structures (not shown in the figure), and along the direction from the front surface 101 to the back surface 102, the height of the first pyramid structure 103 is greater than the height of the tower base structure.

[0097] Exemplarily, the height of the tower base structure is less than or equal to one-fourth of the height of the first pyramid structure 103.

[0098] It can be understood that compared with the first textured structure including a plurality of first pyramid structures 103, the polished structure is flatter. In this way, the first tunneling layer 210 on the first region 1021 of the back surface 102 of the substrate 100 can have higher density and uniformity, so that the first tunneling layer 210 has a good passivation effect on the back surface 102 of the substrate 100. In addition, the first pyramid structure 103 can also make the reflectivity of the second region 1022 of the back surface 102 of the substrate 100 to incident light smaller, so that the absorption and utilization rate of light is larger.

[0099] In some embodiments, the area of the first region 1021 is S1, and the area of the second region 1022 is S2, where S1 and S2 have the same unit, and S2 satisfies the following condition: S2 / (S1 + S2) = a, and a is 30% - 70%.

[0100] Setting a to 30% - 70% can enable the back contact battery to obtain a lower reflectivity, reduce current loss, improve the bifaciality, and at the same time balance the negative effects such as passivation loss and PN junction area loss brought by the textured structure.

[0101] Please refer to Figures 2 - 7 , an embodiment of the present application provides a method for manufacturing a back contact battery, including:

[0102] S10. Provide a substrate 100. Among them, along the thickness direction of the substrate 100, the substrate 100 has a front surface 101 and a back surface 102 which are arranged opposite to each other, and the back surface 102 includes alternately arranged first regions 1021 and second regions 1022.

[0103] S20. Along the direction away from the substrate 100, form a first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, and a second doped semiconductor layer 320 which are stacked on the first region 1021 of the back surface 102 of the substrate 100. Among them, the first doped semiconductor layer 310 and the second doped semiconductor layer 320 have the same conductivity type, and are opposite to the conductivity type of the substrate 100.

[0104] Optionally, the step S20 of forming a first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, and a second doped semiconductor layer 320 which are stacked on the first region 1021 of the back surface 102 of the substrate 100 along the direction away from the substrate 100 specifically includes:

[0105] S21. Along the direction away from the substrate 100, form a first initial tunneling layer 211, a first initial semiconductor layer 311, a second initial tunneling layer 221, and a second initial semiconductor layer 321 which are stacked on the first region 1021 of the back surface 102 of the substrate 100.

[0106] S22. As Figure 2 shown, form a doping source layer 400 on the side of the second initial semiconductor layer 321 away from the second initial tunneling layer 221.

[0107] The doping source layer 400 may include a P-type or N-type doping element. Exemplarily, the doping source layer 400 has a P-type doping element.

[0108] S23. Make the doping element in the doping source layer 400 diffuse into the first initial semiconductor layer 311 and the second initial semiconductor layer 321, so that the first initial semiconductor layer 311 is transformed into a first initial doped semiconductor layer 312, and the second initial semiconductor layer 321 is transformed into a second initial doped semiconductor layer 322.

[0109] It should be noted that due to process reasons, there is a part of the doping element diffusing into the substrate 100, but it does not affect the conductivity type of the substrate 100.

[0110] S24. As Figure 4 shown, use a laser to pattern the doping source layer 400 with a first preset pattern to remove the part of the doping source layer 400 corresponding to the second region 1022, that is, retain the part of the doping source layer 400 corresponding to the first region 1021.

[0111] S25. AsFigure 5 As shown, the portions of the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221, and the second initial doped semiconductor layer 322 corresponding to the second region 1022 are removed to form, on the first region 1021 of the back surface 102 of the substrate 100, a first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, and a second doped semiconductor layer 320 that are stacked.

[0112] S26. Remove the doped source layer 400.

[0113] In this application, the laser grooving technique is used to remove the portion of the doped source layer 400 corresponding to the second region 1022. The portion of the doped source layer 400 corresponding to the first region 1021 can be utilized to protect the stacked first tunneling layer 210, first doped semiconductor layer 310, second tunneling layer 220, and second doped semiconductor layer 320, eliminating the complicated mask process and achieving a better film opening effect.

[0114] S30. As Figure 1 shown, form a first electrode 810 electrically connected to the second doped semiconductor layer 320, and a second electrode 820 disposed in the second region 1022 and electrically connected to the substrate 100.

[0115] In some embodiments, in step S24 of patterning the doped source layer 400 with a laser in a first preset pattern to remove the portion of the doped source layer 400 corresponding to the second region 1022, the process parameters of the laser treatment include: the wavelength of the laser is 300 nm - 1000 nm; the energy density of the laser is 103 W / cm 2 -106 W / cm 2 , and the laser line width is 80 μm - 1500 μm.

[0116] Exemplarily, the wavelength of the laser is 300 nm, 500 nm, 700 nm, 900 nm, or 1000 nm, the energy density of the laser is 103 W / cm 2 , 104 W / cm 2 , 105 W / cm 2 or 106 W / cm 2 , and the laser line width is 80 μm, 100 μm, 200 μm, 400 μm, 600 μm, 1000 μm, 1200 μm, 1400 μm, or 1500 μm.

[0117] Set the process parameters of the laser treatment to include: the wavelength of the laser is 300 nm - 1000 nm; the energy density of the laser is 103 W / cm 2 -106 W / cm 2, the laser line width is 80 μm - 1500 μm, which is beneficial to improving the accuracy of the laser grooving technique, and thus a better film opening effect can be achieved.

[0118] In some embodiments, the step S25 of removing the portions of the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221, and the second initial doped semiconductor layer 322 corresponding to the second region 1022 specifically includes: using a first etching solution to remove the portions of the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221, and the second initial doped semiconductor layer 322 corresponding to the second region 1022. Among them, the first etching solution includes an alkali and a polishing additive; the volume of the alkali in the first etching solution is 20 L - 40 L, the volume of the polishing additive in the first etching solution is 2 L - 5 L, the temperature of the first etching solution is 60°C - 80°C, and the treatment time of the first etching solution is 100 s - 300 s.

[0119] Exemplarily, the volume of the alkali in the first etching solution is 20 L, 30 L, or 40 L, the volume of the polishing additive in the first etching solution is 2 L, 3 L, 4 L, or 5 L, the temperature of the first etching solution is 60°C, 70°C, or 80°C, and the treatment time of the first etching solution is 100 s, 200 s, or 300 s.

[0120] Using the laser grooving technique in combination with the wet etching technique to remove the portions of the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221, and the second initial doped semiconductor layer 322 corresponding to the second region 1022 abandons the complicated mask process, can improve the manufacturing efficiency of the preparation method of the back contact battery, and at the same time can also achieve a better film opening effect.

[0121] In some embodiments, as Figure 3 shown, before the step S24 of patterning the doping source layer 400 with a first preset pattern by using a laser to remove the portion of the doping source layer 400 corresponding to the second region 1022, the preparation method of the back contact battery further includes: forming a protective layer 500 on the side of the doping source layer 400 facing away from the second initial doped semiconductor layer 322.

[0122] The step S24 of patterning the doping source layer 400 with a first preset pattern by using a laser to remove the portion of the doping source layer 400 corresponding to the second region 1022 specifically includes: patterning the doping source layer 400 and the protective layer 500 with a first preset pattern by using a laser to remove the portion of the doping source layer 400 corresponding to the second region 1022 and the portion of the protective layer 500 corresponding to the second region 1022 (as Figure 4 shown).

[0123] The first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220, and the second doped semiconductor layer 320, which are formed by laminating the part of the doping source layer 400 corresponding to the first region 1021 and the part of the protective layer 500 corresponding to the first region 1021, eliminate the complicated masking process, improve the manufacturing efficiency of the manufacturing method of the back-contact battery, and achieve a better film-opening effect at the same time.

[0124] It should be noted that before the step S26 of removing the doping source layer 400, the manufacturing method of the back-contact battery further includes: removing the protective layer 500.

[0125] In some embodiments, before the step S30 of forming the first electrode 810 electrically connected to the second doped semiconductor layer 320 and the second electrode 820 disposed on the second region 1022 and electrically connected to the substrate 100, after the step S20 of forming the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220, and the second doped semiconductor layer 320 which are laminated on the first region 1021 of the back surface 102 of the substrate 100 in a direction away from the substrate 100, the manufacturing method of the back-contact battery further includes:

[0126] As Figure 6 shown, the second region 1022 and the front surface 101 are subjected to texturing treatment to form a first textured surface structure on the second region 1022 and a second textured surface structure on the front surface 101; wherein, the first textured surface structure includes a plurality of first pyramid structures 103, and the second textured surface structure includes a plurality of second pyramid structures 104.

[0127] Optionally, the texturing treatment of the second region 1022 and the front surface 101 specifically includes: using a second etching solution to perform texturing treatment on the second region 1022 and the front surface 101, wherein the second etching solution includes an alkali and an additive, the volume of the alkali in the second etching solution is 20L - 40L, the volume of the additive in the second etching solution is 2L - 5L, the temperature of the second etching solution is 60°C - 80°C, and the treatment time of the second etching solution is 300s - 800s.

[0128] Exemplarily, the volume of the alkali in the second etching solution is 20L, 30L, or 40L, the volume of the additive in the second etching solution is 2L, 3L, 4L, or 5L, the temperature of the second etching solution is 60°C, 70°C, or 80°C, and the treatment time of the second etching solution is 300s, 400s, 500s, 600s, 700s, or 800s.

[0129] Thus, along the direction from the front surface 101 to the back surface 102, the height of the first pyramid structure 103 can be 2 μm - 5 μm, and the height of the second pyramid structure 104 can be 1 μm - 3 μm. Also, along the direction perpendicular to the front surface 101 and pointing to the back surface 102, the sizes of the first pyramid structure 103 and the second pyramid structure 104 can be 1 μm - 5 μm, and the reflectivity of the second region 1022 can reach 8% - 10%.

[0130] As Figure 7 shown, along the direction away from the substrate 100, a first passivation layer 610 and a first antireflection layer 710 are formed in a stacked manner on the side of the second doped semiconductor layer 320 facing away from the second tunneling layer 220 and on the first textured structure, and a second passivation layer 620 and a second antireflection layer 720 are formed in a stacked manner on the second textured structure.

[0131] The first antireflection layer 710 and the second antireflection layer 720 can be formed by physical vapor deposition or plasma enhanced chemical vapor deposition (abbreviated as PECVD). The materials of the first antireflection layer 710 and the second antireflection layer 720 can be one or a combination of film layers such as silicon nitride (SiN x ), silicon oxynitride (SiON x ), and silicon oxide (SiO x ). The first antireflection layer 710 and the second antireflection layer 720 can be used to improve the light absorption efficiency of the substrate 100, enhance the utilization rate of light, and are beneficial to increasing the short - circuit current of the back - contact battery, thereby improving the photoelectric conversion efficiency of the back - contact battery. They are also beneficial to improving the isolation effect between the back - contact battery and the outside.

[0132] The first passivation layer 610 can be formed on the side of the second doped semiconductor layer 320 facing away from the second tunneling layer 220 and on the first textured structure by atomic layer deposition, and the second passivation layer 620 can also be formed on the second textured structure by atomic layer deposition.

[0133] The materials of the first passivation layer 610 and the second passivation layer 620 can be aluminum oxide (AlO x ).

[0134] By using the first passivation layer 610 and the second passivation layer 620, the passivation performance of the back - contact battery can be improved.

[0135] In some embodiments, please refer to Figures 8 - 11 . The preparation method of the back - contact battery includes:

[0136] S110. Provide a substrate 100, and the substrate 100 is an N - type silicon substrate.

[0137] S120. Double-side polish the substrate 100. An existing polishing solution (a combination of an alkali and an additive) can be used to double-side polish the substrate 100.

[0138] S210. Along a direction away from the substrate 100, form a first initial tunneling layer 211, a first initial semiconductor layer 311, a second initial tunneling layer 221, and a second initial semiconductor layer 321 that are stacked on the substrate 100.

[0139] S220. As Figure 8 shown, form a doped source layer 400 on a side of the second initial semiconductor layer 321 away from the second initial tunneling layer 221. The doped source layer 400 can be a borosilicate glass layer.

[0140] S230. Diffuse the doping element in the doped source layer 400 into the first initial semiconductor layer 311 and the second initial semiconductor layer 321, so that the first initial semiconductor layer 311 is converted into a first initial doped semiconductor layer 312, and the second initial semiconductor layer 321 is converted into a second initial doped semiconductor layer 322.

[0141] S240. As Figure 9 shown, form a protective layer 500 on a side of the doped source layer 400 away from the second initial doped semiconductor layer 322. Optionally, the protective layer 500 can be formed on a side of the doped source layer 400 away from the second initial doped semiconductor layer 322 by using a tube-type or chain-type oxidation process. The thickness of the protective layer 500 can be 100 nm - 200 nm, and the material of the protective layer 500 can be silicon oxide.

[0142] S250. As Figure 10 shown, pattern the doped source layer 400 and the protective layer 500 with a first preset pattern by using a laser, so as to remove the part of the doped source layer 400 corresponding to the second region 1022, and the part of the protective layer 500 corresponding to the second region 1022.

[0143] S260. Use hydrofluoric acid (HF) to remove the doped source layer 400 and the protective layer 500 that are diffusely extended on the front surface 101 and the side surface 105. The side surface 105 refers to the surface on the substrate 100 that is connected between the front surface 101 and the back surface 102.

[0144] S270. As Figure 11 shown, use a first etching solution to remove the parts of the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221, and the second initial doped semiconductor layer 322 corresponding to the second region 1022, so as to form a first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, and a second doped semiconductor layer 320 that are stacked on the first region 1021 of the back surface 102 of the substrate 100.

[0145] S310. Use a second etching solution to perform texturing on the second region 1022 and the front surface 101 to form a first textured surface structure on the second region 1022 and a second textured surface structure on the front surface 101. Among them, the first textured surface structure includes a plurality of first pyramid structures 103, and the second textured surface structure includes a plurality of second pyramid structures 104.

[0146] S320. Use hydrofluoric acid (HF) to remove the doping source layer 400 and the protective layer 500. During this process, the hydrofluoric acid (HF) will not wash away the substrate 100 and the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220, and the second doped semiconductor layer 320 stacked on the substrate 100.

[0147] S330. Along the direction away from the substrate 100, form a stacked first passivation layer 610 and a first antireflection layer 710 on the side of the second doped semiconductor layer 320 facing away from the second tunneling layer 220 and on the first textured surface structure, and form a stacked second passivation layer 620 and a second antireflection layer 720 on the second textured surface structure.

[0148] S400. Form a first electrode 810 electrically connected to the second doped semiconductor layer 320, and a second electrode 820 disposed in the second region 1022 and electrically connected to the substrate 100.

[0149] The first electrode 810 and the second electrode 820 can be formed by screen printing, and the first electrode 810 and the second electrode 820 are sintered at a high temperature of 700°C - 800°C to form a good ohmic contact.

[0150] The back-contact battery of the present application combines the advantages of Topcon and BC batteries. At the same time, the second region 1022 of the back surface 102 and the front surface 101 are designed as textured surface structures, which can reduce the reflectivity of the back surface 102, thereby improving the bifaciality of the back-contact battery. Moreover, the textured surface structure is more conducive to the contact of metal paste than the polished structure, which can enable the second electrode 820 to form a better ohmic contact, thereby improving the contact and filling factor.

[0151] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0152] The above-described embodiments merely represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a back-contact battery, characterized in that, Comprising: Providing a substrate, along the thickness direction of the substrate, the substrate has a front surface and a back surface disposed opposite to each other, and the back surface includes alternately arranged first regions and second regions; Forming, along a direction away from the substrate, a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer stacked on the first region of the back surface of the substrate; wherein, the first doped semiconductor layer and the second doped semiconductor layer have the same conductivity type and are opposite to the conductivity type of the substrate; Forming a first electrode electrically connected to the second doped semiconductor layer, and a second electrode disposed on the second region and electrically connected to the substrate; Wherein, the forming, along a direction away from the substrate, a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer stacked on the first region of the back surface of the substrate specifically includes: Forming, along a direction away from the substrate, a first initial tunneling layer, a first initial semiconductor layer, a second initial tunneling layer, and a second initial semiconductor layer stacked on the first region of the back surface of the substrate; Forming a doping source layer on a side of the second initial semiconductor layer away from the second initial tunneling layer; Diffusing doping elements in the doping source layer into the first initial semiconductor layer and the second initial semiconductor layer, so that the first initial semiconductor layer is converted into a first initially doped semiconductor layer, and the second initial semiconductor layer is converted into a second initially doped semiconductor layer; Patterning the doping source layer with a first preset pattern by using a laser to remove a portion of the doping source layer corresponding to the second region; Removing portions of the first initial tunneling layer, the first initially doped semiconductor layer, the second initial tunneling layer, and the second initially doped semiconductor layer corresponding to the second region to form a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer stacked on the first region of the back surface of the substrate; Removing the doping source layer.

2. The preparation method of the back-contact battery according to claim 1, wherein The doping source layer includes a P-type or N-type doping element.

3. The preparation method of the back-contact battery according to claim 1, characterized in that, In the step of patterning the doping source layer with a laser in a first preset pattern to remove a part of the doping source layer corresponding to the second region, the process parameters of the laser treatment include: the wavelength of the laser is 300 nm - 1000 nm; the energy density of the laser is 103 W / cm 2 - 106 W / cm 2 , the laser line width is 80 μm - 1500 μm; and / or The removing portions of the first initial tunneling layer, the first initially doped semiconductor layer, the second initial tunneling layer, and the second initially doped semiconductor layer corresponding to the second region specifically includes: removing portions of the first initial tunneling layer, the first initially doped semiconductor layer, the second initial tunneling layer, and the second initially doped semiconductor layer corresponding to the second region by using a first etching solution; wherein, the first etching solution includes an alkali and a polishing additive; the volume of the alkali is 20L - 40L, the volume of the polishing additive is 2L - 5L; the temperature of the first etching solution is 60°C - 80°C; the processing time of the first etching solution is 100s - 300s.

4. The preparation method of the back-contact battery according to claim 1, characterized in that, Before the patterning the doping source layer with a first preset pattern by using a laser to remove a portion of the doping source layer corresponding to the second region, it further includes: forming a protective layer on a side of the doping source layer away from the second initially doped semiconductor layer; Performing patterning on the doping source layer with a laser in a first preset pattern to remove a portion of the doping source layer corresponding to the second region specifically includes: performing patterning on the doping source layer and the protective layer with a laser in a first preset pattern to remove a portion of the doping source layer corresponding to the second region and a portion of the protective layer corresponding to the second region.

5. The preparation method of the back contact battery according to claim 1, characterized in that, Before forming the first electrode electrically connected to the second doped semiconductor layer and the second electrode disposed on the second region and electrically connected to the substrate, after forming a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer stacked on the first region of the back surface of the substrate in a direction away from the substrate, it further includes: Performing texturing on the second region and the front surface to form a first textured surface structure on the second region and a second textured surface structure on the front surface; wherein, the first textured surface structure includes a plurality of first pyramid structures; the second textured surface structure includes a plurality of second pyramid structures; Forming a first passivation layer and a first antireflection layer stacked on one side of the second doped semiconductor layer facing away from the second tunneling layer and the first textured surface structure, and forming a second passivation layer and a second antireflection layer stacked on the second textured surface structure.

6. A back-contact battery, characterized in that, The back contact battery is prepared by the preparation method of the back contact battery according to any one of claims 1-5, and the back contact battery includes: A substrate, in the thickness direction of the substrate, the substrate has a front surface and a back surface disposed opposite to each other, and the back surface includes alternately arranged first regions and second regions; A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer, stacked on the first region of the back surface in a direction away from the substrate; wherein, the first doped semiconductor layer and the second doped semiconductor layer have the same conductivity type and are opposite to the conductivity type of the substrate; A first electrode, electrically connected to the second doped semiconductor layer; and A second electrode, disposed on the second region and electrically connected to the substrate.

7. The back-contact battery according to claim 6, characterized in that, The second region of the back surface has a first textured surface structure, and the first textured surface structure includes a plurality of first pyramid structures; In the direction from the front surface to the back surface, the height of the first pyramid structure is 2 μm - 5 μm; In the direction perpendicular to the direction from the front surface to the back surface, the size of the first pyramid structure is 1 μm - 5 μm.

8. The back-contact battery according to claim 6, wherein, The front surface has a second textured surface structure, and the second textured surface structure includes a plurality of second pyramid structures; In the direction from the front surface to the back surface, the height of the second pyramid structure is 1 μm - 3 μm; In the direction perpendicular to the direction from the front surface to the back surface, the size of the second pyramid structure is 1 μm - 5 μm.

9. The back contact battery according to claim 6, wherein The sheet resistance of the second doped semiconductor layer is 100 Ω / sq - 300 Ω / sq; and / or The sheet resistance of the first doped semiconductor layer is 100 Ω / sq - 300 Ω / sq; and / or The thickness of the first doped semiconductor layer is 20 nm - 100 nm; and / or The thickness of the second doped semiconductor layer is 100 nm - 250 nm; and / or The thickness of the first tunneling layer is 1 nm - 4 nm; and / or The thickness of the second tunneling layer is 1 nm - 4 nm.

10. The back-contact battery according to claim 6, characterized in that, The first region is flatter than the second region; and / or The second region on the back surface has a first textured structure, the first textured structure includes a plurality of first pyramid structures; the first region on the back surface has a polished structure, the polished structure includes a plurality of base structures, along the direction from the front surface to the back surface, the height of the first pyramid structure is greater than the height of the base structure; and / or The area of the first region is S1, and the area of the second region is S2, where S1 and S2 have the same unit, and S2 satisfies the following condition: S2 / (S1 + S2) = a, and a is 30% - 70%.

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