Synthesizing voltage signals

Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for injecting a synthesized voltage signal. One of the methods includes initiating, by a processing core, a transition from execution in a low power state to execution in a high power state. The device injects the synthesized voltage signal into a voltage feedback line of the power manager to cause the power manager to react earlier to the transition by increasing the current supplied to the processing core. The power manager uses the synthesized voltage signal to increase the current supplied to the processing core after the processing core transitions from the low power state to the high power state.

Description

Background Art

[0001] This specification relates to power management of computing devices.

[0002] Computing devices, particularly battery-powered computing devices such as mobile phones, laptops, and tablet computers, employ many strategies to provide high computing performance with long battery life. To this end, such devices reduce power consumption when computing demand is low. For example, some devices attempt to save power by entering a high-power state when there is computing work to be done and then entering a low-power state when the computing work is completed.

[0003] The power efficiency of entering and exiting these differential power states is highly dependent on how quickly the device can transition between states. However, there are real physical limits on how quickly a device can enter a high power state. One reason for this is that there are typically physical electronic components (e.g., inductors) arranged between the current regulator and the computing core that impose physical limits on how quickly the current can be increased.

[0004] Because of this physical limitation on increasing current, the device can employ mitigation strategies to ensure that the computational workload ramp-up does not cause an unacceptable voltage drop that could crash or malfunction the device before the current is fully increased. The device can employ several strategies to help control such undesirable consequences.

[0005] One example is a voltage drop detector that monitors the core voltage of a device. When the voltage drops below a certain threshold, for example due to a ramp-up in computing workload, the system slows down the clock frequency to prevent the voltage from dropping too much. However, slowing down the clock frequency has the disadvantage of reducing the computing power of the device because the device then operates more slowly.

[0006] Another example is architectural mitigation, which uses a mapping between expected voltage drops and instruction types or sequences. If an upcoming instruction sequence has an unexpected expected voltage drop, the system may execute instructions more slowly. This approach also has the undesirable feature that computing power is throttled to prevent unsafe voltage drops. Summary of the invention

[0007] This specification describes how a system can use a synthetic voltage signal to improve the power performance of a computing device having a power manager that uses a voltage feedback signal to control the increase of current. Injecting the synthetic voltage signal into the voltage feedback signal has the following effect: the power manager can react to power consumption spikes more quickly while reducing the adverse effects of frequency mitigation measures on computing performance.

[0008] Particular embodiments of the subject matter described in this specification can be implemented to achieve one or more of the following advantages. Using a synthetic voltage signal improves computing performance and power efficiency of a computing device in a number of ways. First, the synthetic voltage signal allows the computing device to transition from a low power state to a high power state more quickly, which improves computing performance of the device. The synthetic voltage signal also reduces the adverse effects of frequency throttling. Using a synthetic voltage signal generated by a processing core also allows these performance and efficiency improvements to be achieved without redesigning or modifying a power manager.

[0009] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a diagram illustrating an example system that uses architectural mitigation.

[0011] Figure 1B is a diagram illustrating an example system that uses clock frequency throttling mitigation.

[0012] Figure 2A It illustrates how the composite voltage signal can make the voltage recover faster.

[0013] Figure 2B It illustrates how the synthesized voltage signal can make the frequency recovery faster.

[0014] Figure 3 It illustrates how the power manager reacts with architectural mitigation but without a synthetic voltage signal.

[0015] Figure 4 The faster reaction time of the power manager when using the synthetic voltage signal is illustrated.

[0016] Figure 5 It is illustrated how a synthetic voltage signal can be used to compensate for both architectural mitigation and frequency mitigation in the same system.

[0017] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0018] This specification describes how a system can use a synthetic voltage signal to improve the power performance of a computing device having a power manager that uses a voltage feedback signal to control the increase of current. Injecting the synthetic voltage signal into the voltage feedback signal has the following effect: the power manager can react to power consumption spikes more quickly while reducing the adverse effects of frequency mitigation measures on computing performance.

[0019] Figure 1Ais a diagram illustrating an example system 100a that uses architectural mitigation. System 100a is an example of a system that can use a synthetic voltage signal to improve power performance.

[0020] System 100a includes a power manager 110 and an application processor 120 having a computing core 130. System 100a may be part of any suitable mobile or stationary computing device. For example, the system may be part of a mobile phone, a wearable device, a tablet computer, a laptop computer, a desktop computer, or a server. Computing core 130 may be any suitable computing device that executes instructions.

[0021] Power manager 110 may be any suitable power manager that uses voltage feedback to regulate the current supplied to computing core 130. For example, power manager 110 may be a buck converter. Power manager 110 uses voltage feedback line 112 to receive a voltage feedback signal “Vout_sns” in order to adjust the amount of current being supplied to application processor 120.

[0022] To generate the voltage feedback signal, system 100a uses series resistor 127 in conjunction with controlled current source 129, which draws current across series resistor 127. Changes in the current being consumed by computing core 130 due to the current being present before series resistor 127 cause corresponding changes in the voltage drop across resistor 127. These voltages are converted to voltage feedback signals after being fed through voltage buffer 131.

[0023] The system 100a has at least two computing modes—a low power mode and a high power mode. When transitioning from the low power mode to the high power mode, the power manager 110 may detect a voltage drop from a voltage feedback signal received on the voltage feedback line 112 .

[0024] Figure 1A An inset graph 105 is included that illustrates the behavior of components due to architectural mitigation of the current supplied by the power manager 110 .

[0025] The x-axis of the inset graph 105 is time, and the y-axis is the current at two locations 111 and 114 of the device. Thus, the inset graph 105 illustrates the relationship between: 1) the current consumed by the computing core 130 at the location 114 where power is supplied to the computing core, and 2) the current supplied by the power manager 110, which is called the "buck current" and is measured at point 111 just outside the buck inductor 113.

[0026] The current consumed to transition from a low power state to a high power state without any mitigation is illustrated by dashed line 102. Although as explained above, this may not actually be an option as doing so may cause an unsafe voltage drop.

[0027] The current consumed under architectural mitigation when transitioning from a low power state to a high power state is illustrated by dashed line 104. When the computing core 130 performs this mitigation, the current consumed steps up twice over time, as represented by dashed line 104.

[0028] Finally, the current supplied by the power manager 110 during the transition with architectural mitigation is illustrated by solid line 106. Because the power manager 110 cannot see what the computing core 130 is doing, the power manager 110 relies on the voltage feedback signal to begin increasing power. In this example, the power manager 110 senses the voltage drop only after the first step increase in current consumption illustrated by dashed line 104. The power manager 110 then steadily increases the current until a steady state is reached after the computer device performs a second step increase in its current consumption.

[0029] The computing core 130 has functional circuitry for implementing architectural mitigation. The effect of architectural mitigation is that the computing core 130 will execute instructions more slowly during the transition period from low power to high power until the power manager has a chance to fully increase the available current. In some implementations, the components that implement architectural mitigation do not actually measure the current being supplied by the power manager 110. Instead, these components use calculations or lookup tables, or some combination of calculations and lookup tables, to calculate an estimate of how much current each instruction or sequence of instructions is expected to consume when executed.

[0030] Compute core 130 has a digital power estimator 132 that calculates an estimate of the power consumed for a particular instruction or sequence of instructions. A di / dt instruction throttling module 134 can then use the digital power estimate generated by digital power estimator 132 to control how quickly instructions should be executed or throttled.

[0031] The di / dt digital-to-analog converter (DAC) 136 can calculate the difference between the amount of power expected to be consumed and the amount of power being supplied to the computing core 130. For example, the architecture mitigation can inject three NOP instructions for each actual payload instruction. Then, a power cost prediction will be performed with respect to only the actual payload and with respect to the included NOP instructions. NOP, for example, can have a power cost of 1 unit, while the payload instruction can have a power cost of 10 units. These costs can be summed over an instruction window (e.g., 5, 50, or 100 instructions), and the difference between the cost sums will represent an increment. Then an increment signal can be calculated based on a comparison between the unthrottled power cost and the throttled power cost, possibly as well as a pre-calculated scaling factor.

[0032] The system 100a can then use the calculated increment 133 to alter the controlled current source 129 in a manner that generates a proportional voltage shift across the series resistor 127. For example, the increment can be used to reduce the current of the controlled current source 129 to drop the voltage across the series resistor 127 so as to effectively subtract from the voltage feedback signal on the voltage feedback signal line 112. This effectively generates a composite voltage signal that is fed into the voltage feedback signal line 112. In some implementations, the computing core 130 can use a programmable GM amplifier to inject the increment signal 133 as a current to affect the operation of the controlled current source 129.

[0033] Figure 1A Another inset graph 115 is included that illustrates the shape of the composite voltage signal. In the inset graph 115, the x-axis is time and the y-axis is voltage. As the computing core 130 enters a high power state, there is a drop in voltage at location 116 before the current reaches the computing core 130. Therefore, in order to cause the power manager 110 to react faster, a composite voltage signal 117 is fed onto the voltage feedback line 112.

[0034] In some implementations, the computing core generates a composite voltage signal 117 that matches the trajectory 116 of the expected drop in voltage. In other words, the composite voltage signal has a shape designed to match the physical characteristics of the system, and therefore substantially matches the expected drop in voltage. As shown in the inset graph 115, while the shape is substantially similar, the composite voltage signal has an artificially lower amplitude. In effect, the composite voltage signal conveys information to the power manager 100 that the state of the power being supplied is worse than the state of the actual power, which in turn stimulates the power manager 110 to react earlier and more aggressively than it would otherwise.

[0035] Figure 1Bis a diagram illustrating an example system 100b that uses clock frequency throttling mitigation. System 100b has many similarities to system 100a, but system 100b uses a frequency locked loop (FLL) module 138 to throttle the clock frequency of computing core 130b until power regulator 110 can increase current to computing core 130b.

[0036] However, in this case, the system uses the frequency-reduced value calculated by FLL 138 to generate an incremental signal 135 that affects controlled current source 129 and thus produces a synthetic voltage signal. Computation core 130b can, for example, use a programmable GM amplifier to inject an incremental signal calculated from the frequency-reduced value and, optionally, a scaling factor.

[0037] Figure 2A Illustrated is how the composite voltage signal 204 enables the voltage to recover faster.At a transition point 210, which may be, for example, a transition from a low power state to a high power state, the voltage of the computing core drops due to consuming more power.

[0038] At transition point 210, the system may inject a composite voltage signal 204 that causes the resulting regulated voltage 206 to recover faster than the normal voltage 202 would have without the composite voltage signal. As described above, this is because the composite error signal causes the power manager to react earlier and potentially more aggressively.

[0039] Figure 2B 2. How the synthesized voltage signal can cause the frequency to recover faster is illustrated. At transition point 211, the computing core may implement frequency throttling due to increased power demand. Thus, the frequency mitigation technique causes the frequency to drop. Without the synthesized voltage signal, the core frequency 212 recovers slower than the core frequency 214 when the synthesized voltage signal is used.

[0040] Figure 3 It illustrates how the power manager reacts with architectural mitigation but without a synthetic voltage signal.

[0041] exist Figure 3 In FIG. 3 , there are three graphs on the same time axis. The top graph 310 illustrates how the current consumption of the core changes due to power-up, and how the power manager ramps up the current supply to meet the increasing demand.

[0042] At 1 microsecond, the core initiates entry into a high power state. This causes a first spike 312 in the current consumption of the core and a corresponding first voltage drop 322 .

[0043] To avoid unsafe voltage drops, the core's architectural mitigation subsystem throttles the instructions being executed in order to allow the power manager to catch up to the amount of current that the power manager is supplying.

[0044] The power manager uses the voltage feedback signal to detect the first voltage drop 322 and will respond by increasing the supply of current. However, due to inherent delays due to physical components and wire lengths, the power manager is unable to respond with an increase in current until 1.025 microseconds, at which point the current increases steadily.

[0045] When the supplied current eventually matches the current consumption, architectural mitigation is disabled, resulting in a second current spike 314 at 1.05 microseconds and a corresponding second voltage drop 324 .

[0046] The power manager again senses the second voltage drop 324, but takes time to respond, and in doing so, steadily increases the supply of current until sufficient to meet the current demand of the high power state.

[0047] As shown in the middle graph 320 , the voltage in the core has two falling events 322 and 324 corresponding to the current spikes 312 and 314 , respectively.

[0048] And although the buck power manager is able to increase current supply to match current consumption before about 1.12 microseconds, it takes longer than that for the voltage of the core to return to the voltage before the first current spike 312. Overall, the peak voltage deviation is 60 mV relative to the voltage before entering the high power state.

[0049] As shown in the bottom graph 330 , even with architectural mitigations, the FLL clock frequency reduction system still requires a 15% reduction in frequency to keep the voltage at a safe state.

[0050] Figure 4 The faster reaction time of the power manager when using a synthetic voltage signal is illustrated. In this example, the computing core uses architectural mitigation to slow down the execution frequency, resulting in two current spikes 512 and 514 .

[0051] As shown in the top graph 410, once the first current spike 412 is detected, the system generates a resultant voltage signal 426 and feeds the resultant voltage signal 426 into the power manager.

[0052] Therefore, the power manager initiates a more aggressive current increase that continues even after the architectural mitigation is eliminated just before the second spike 414 .

[0053] Therefore, with Figure 3The power manager can achieve a current supply that exceeds the current consumption of the core in a high power state more quickly than in the illustrated example. When using the synthetic voltage signal, the power manager achieves the target current with fewer step ups than the power manager would have without the synthetic voltage signal. In this example, the power manager uses only one step up increase in less than 0.5 microseconds. Figure 3 The example in requires two current increases and takes more than 1 microsecond.

[0054] As shown in the bottom graph 420, the core voltage 424 does have two voltage drops 422 and 424 corresponding to the first peak 412 and the second peak 414, respectively, but the voltage drops 422 and 424 are smaller than Figure 3 Illustrated are voltage drops 322 and 324 that occur without using a composite voltage signal.

[0055] Additionally, the FLL clock frequency reduction is also smaller, resulting in only a 6% frequency reduction and only 40mV peak voltage deviation.

[0056] Figure 5 This example illustrates how a synthetic voltage signal can be used to compensate for both architectural mitigation and frequency mitigation in the same system. In this example, the compute core first uses architectural mitigation. Then, while the voltage is still low, the system uses frequency throttling to further mitigate the increased power demand. Figure 3 to Figure 4 Similarly, architectural mitigation results in two current spikes 512 and 514 .

[0057] like Figure 5 As shown, the initial transition to the high power state causes a first current spike 512 as the computing core implements architectural relief.

[0058] The system may then generate a trajectory matched composite voltage signal 526 so that the power manager can more aggressively increase the current supplied to the processing core.

[0059] When the current supplied by the power manager catches up with the current consumed by the processing core, there is a second current spike 514. At this point, the processing core may inject a second synthesized voltage signal 528 to try to compensate for frequency throttling, for example, as implemented by the FLL system.

[0060] Therefore, the current supplied by the power manager is Figure 4 In other words, the power manager has less oscillations between local high and low current values ​​when the synthetic voltage signal is also used to compensate for frequency throttling.

[0061] Therefore, less overall frequency throttling is required and the peak voltage deviation is lower. Figure 5 As shown, the frequency reduction rate is only 4.5%, and the peak voltage deviation is Figure 4 40mV and Figure 3 It is only 30mV compared to 60mV in the circuit.

[0062] Embodiments of the subject matter and functional operations described in this specification may be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium, for execution by a data processing device or for controlling the operation of a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. Alternatively or in addition, program instructions may be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical, optical, or electromagnetic signal), which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device.

[0063] The term "data processing equipment" refers to data processing hardware, and includes all kinds of equipment, devices and machines for processing data, including, for example, a programmable processor, a computer or a plurality of processors or computers. The equipment may also be or further include a dedicated logic circuit system, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, the equipment may also optionally include code for creating an execution environment for a computer program, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0064] A computer program, which may also be referred to or described as a program, software, software application, app, module, software module, script or code, may be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages); and it may be deployed in any form, including as a standalone program or as a module, component, subroutine or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines or code portions). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a data communications network.

[0065] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by a dedicated logic circuit system such as an FPGA or ASIC, or by a combination of a dedicated logic circuit system and one or more programmed computers.

[0066] A computer suitable for executing a computer program may be based on a general or special purpose microprocessor or both, or any other kind of central processing unit. Typically, the central processing unit will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a central processing unit for fulfilling or executing instructions and one or more memory devices for storing instructions and data. The central processing unit and the memory may be supplemented by or incorporated into a dedicated logic circuit system. Typically, the computer will also include one or more mass storage devices for storing data, such as a magnetic disk, a magneto-optical disk, or an optical disk, or will be operatively coupled to receive data from or transfer data to the one or more mass storage devices, or both. However, the computer does not have to have such a device. In addition, the computer may be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0067] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0068] In addition to the embodiments described above, the following embodiments are also innovative:

[0069] Embodiment 1 is a device, comprising: a processing core configured to initiate a transition from executing in a low power state to executing in a high power state; and a power manager configured to increase current supplied to the processing core when the processing core transitions from the low power state to the high power state, Wherein the apparatus is configured to inject a composite voltage signal into a voltage feedback line of the power manager to cause the power manager to react to the transition earlier by increasing the current supplied to the processing core according to the composite voltage signal.

[0070] Embodiment 2 is the apparatus of embodiment 1, wherein the apparatus is configured to generate the synthetic voltage signal to compensate for architectural voltage mitigation that limits how quickly instructions can be executed when the processing core transitions to the high power state.

[0071] Embodiment 3 is the apparatus of embodiment 2, wherein the composite voltage signal has a trajectory that matches an expected voltage drop due to transitioning to the high power state.

[0072] Embodiment 4 is an apparatus as described in any one of embodiments 1 to 3, wherein the apparatus is configured to generate the synthetic voltage signal to compensate for frequency throttling mitigation, which limits the clock frequency of the processing core when the processing core transitions to the high power state.

[0073] Embodiment 5 is the apparatus of embodiment 4, wherein the apparatus is configured to generate different synthetic voltage signals to compensate for frequency throttling mitigation and to compensate for architecture mitigation.

[0074] Embodiment 6 is the apparatus of any one of embodiments 1 to 5, wherein injecting the synthetic voltage signal causes the power manager to increase the current supplied to the processing core with fewer step increases than would be required in the absence of the synthetic voltage signal.

[0075] Embodiment 7 is the apparatus of any one of embodiments 1 to 6, wherein injecting the synthetic voltage signal reduces the amount of clock frequency throttling on the processing core when transitioning to the high power state.

[0076] Embodiment 8 is the apparatus of any one of embodiments 1 to 7, wherein injecting the synthetic voltage signal causes the core frequency of the processing core to return to a voltage level from the low power state faster than without the synthetic voltage signal.

[0077] Embodiment 9 is a method performed by a device having a processing core and a power manager, comprising: A transition from executing in a low power state to executing in a high power state is initiated by a processing core; injecting, by the device, a composite voltage signal into a voltage feedback line of the power manager to cause the power manager to react earlier to the transition by increasing current supplied to the processing core; and After the processing core transitions from the low power state to the high power state, the current supplied to the processing core is increased by the power manager according to the composite voltage signal.

[0078] Embodiment 10 is the method of embodiment 9, wherein the apparatus is configured to generate the synthetic voltage signal to compensate for architectural voltage mitigation that limits how quickly instructions can be executed when the processing core transitions to the high power state.

[0079] Embodiment 11 is the method of embodiment 10, wherein the composite voltage signal has a trajectory that matches an expected voltage drop due to transitioning to the high power state.

[0080] Embodiment 12 is an apparatus as described in any of embodiments 9 to 10, wherein the apparatus is configured to generate the synthetic voltage signal to compensate for frequency throttling mitigation that limits the clock frequency of the processing core when the processing core transitions to the high power state.

[0081] Embodiment 13 is the apparatus of embodiment 12, wherein the apparatus is configured to generate different synthetic voltage signals to compensate for frequency throttling mitigation and to compensate for architectural mitigation.

[0082] Embodiment 14 is the method of any one of embodiments 9 to 13, wherein injecting the synthetic voltage signal causes the power manager to increase the current supplied to the processing core with fewer step increases than would be required in the absence of the synthetic voltage signal.

[0083] Embodiment 15 is the method of any one of embodiments 9 to 14, wherein injecting the synthetic voltage signal reduces the amount of clock frequency throttling on the processing core when transitioning to the high power state.

[0084] Embodiment 16 is the method of any one of embodiments 9 to 15, wherein injecting the synthetic voltage signal causes the core frequency of the processing core to return to a voltage level from the low power state faster than without the synthetic voltage signal.

[0085] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but should be interpreted as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve a variant of a sub-combination or a sub-combination.

[0086] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed to achieve the desired results. In certain contexts, multitasking and parallel processing can be advantageous. In addition, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0087] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions set forth in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequential order shown to achieve the desired results. In some implementations, multitasking and parallel processing can be advantageous.

Claims

1. A device comprising: a processing core configured to initiate a transition from executing in a low power state to executing in a high power state; as well as a power manager configured to increase current supplied to the processing core when the processing core transitions from the low power state to the high power state, Wherein the apparatus is configured to inject a composite voltage signal into a voltage feedback line of the power manager to cause the power manager to react earlier to the transition by increasing the current supplied to the processing core in accordance with the composite voltage signal.

2. The apparatus of claim 1, wherein the apparatus is configured to generate the synthetic voltage signal to compensate for architectural voltage mitigation that limits how quickly instructions can be executed when the processing core transitions to the high power state.

3. The apparatus of claim 2, wherein the composite voltage signal has a trajectory that matches an expected voltage drop due to transitioning to the high power state.

4. The apparatus of any one of claims 1 to 3, wherein the apparatus is configured to generate the synthetic voltage signal to compensate for a frequency throttling mitigation that limits a clock frequency of the processing core when the processing core transitions to the high power state.

5. The apparatus of claim 4, wherein the apparatus is configured to generate different synthetic voltage signals to compensate for frequency throttling mitigation and to compensate for architectural mitigation.

6. The apparatus of any one of claims 1 to 5, wherein injecting the synthetic voltage signal causes the power manager to increase the current supplied to the processing core with fewer step increases than would be required in the absence of the synthetic voltage signal.

7. The apparatus of any one of claims 1 to 6, wherein injecting the synthetic voltage signal reduces an amount of clock frequency throttling on the processing core when transitioning to the high power state.

8. The apparatus of any one of claims 1 to 7, wherein injecting the synthetic voltage signal causes the core frequency of the processing core to return to a voltage level from the low power state faster than would otherwise occur without the synthetic voltage signal.

9. A method performed by a device having a processing core and a power manager, comprising: A transition from executing in a low power state to executing in a high power state is initiated by a processing core; injecting, by the device, a composite voltage signal into a voltage feedback line of the power manager to cause the power manager to react earlier to the transition by increasing current supplied to the processing core; as well as The current supplied to the processing core is increased by the power manager according to the composite voltage signal after the processing core transitions from the low power state to the high power state.

10. The method of claim 9, wherein the apparatus is configured to generate the synthetic voltage signal to compensate for architectural voltage mitigation that limits how quickly instructions can be executed when the processing core transitions to the high power state.

11. The method of claim 10, wherein the composite voltage signal has a trajectory that matches an expected voltage drop due to transitioning to the high power state.

12. The method of any one of claims 9 to 10, wherein the apparatus is configured to generate the synthetic voltage signal to compensate for a frequency throttling mitigation that limits a clock frequency of the processing core when the processing core transitions to the high power state.

13. The method of claim 12, wherein the apparatus is configured to generate different synthetic voltage signals to compensate for frequency throttling mitigation and to compensate for architectural mitigation.

14. The method of any one of claims 9 to 13, wherein injecting the composite voltage signal causes the power manager to increase the current supplied to the processing core with fewer step increases than would be required in the absence of the composite voltage signal.

15. The method of any one of claims 9 to 14, wherein injecting the synthetic voltage signal reduces the amount of clock frequency throttling on the processing core when transitioning to the high power state.

16. The method of any one of claims 9 to 15, wherein injecting the synthetic voltage signal causes the core frequency of the processing core to return to a voltage level from the low power state more quickly than would otherwise occur without the use of the synthetic voltage signal.

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