Process reset processing method, processor, storage medium and program product

Abstract

The invention provides a process reset processing method, a processor, a storage medium and a program product, and relates to the technical field of chip design, the method is applied to the processor comprising at least one processing core, and the processing core comprises a gateway module and a process management module. The method comprises the following steps: under the condition that a gateway module receives a first task request from a process management module, based on a process identifier carried by the first task request, determining a latest count value of a counter associated with the process management module, the counter is used for recording the accumulated number of times that the process borne by the process management module is triggered to reset; and in response to determining that the first count value carried by the first task request is inconsistent with the newest count value of the counter, executing an operation related to process reset on the first task request. The method can ensure that a single process can be effectively terminated, and process-level resetting is realized.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and in particular to a process reset processing method, processor, storage medium and program product. Background Technology

[0002] In the design of Graphics Processing Units (GPUs), there is a need to terminate (kill) a single process without interfering with other processes. A process is the smallest unit of processor resource allocation, each process has its own independent resources, and is isolated from other processes. However, current methods for terminating a single process sometimes fail to terminate it effectively, thus affecting system reliability. Therefore, how to effectively terminate a single process without interfering with other processes has become a pressing technical problem to be solved. Summary of the Invention

[0003] This disclosure provides a process reset processing method, a processor, a storage medium, and a program product.

[0004] In a first aspect, embodiments of this disclosure propose a process reset processing method applied to a processor including at least one processing core, the processing core including a gateway module and a process management module. The method includes: when the gateway module receives a first task request originating from the process management module, determining the latest count value of a counter associated with the process management module based on a process identifier carried in the first task request, wherein the counter is used to record the cumulative number of times a process carried by the process management module has been triggered to reset; and in response to determining that the first count value carried in the first task request is inconsistent with the latest count value of the counter, performing operations related to process reset on the first task request.

[0005] In some optional implementations of the embodiments of this disclosure, the above-mentioned operation related to process reset on the first task request includes: in response to determining that the first task request belongs to a request that requires a response, performing an operation to return an empty response corresponding to the first task request; or, in response to determining that the first task request belongs to a request that does not require a response, performing an operation to discard the first task request.

[0006] In some optional implementations of the embodiments of this disclosure, the above-mentioned processing core further includes a first hardware module, and the above-mentioned process reset processing method further includes: when the first hardware module receives a second task request from the process management module, determining the current count value of the counter carried by the second task request as the identifier value of a field associated with the first hardware module; determining the identifier value of the field as the first count value carried by the first task request, and sending the first task request to the gateway module, wherein the first task request is associated with the second task request.

[0007] In some optional implementations of the embodiments of this disclosure, the process reset processing method further includes: when the gateway module receives a task response, determining the latest count value of the counter based on the process identifier carried in the task response; and in response to determining that the second count value carried in the task response is inconsistent with the latest count value of the counter, performing the operation of discarding the task response.

[0008] In some optional implementations of the embodiments of this disclosure, the above process reset processing method further includes: when the gateway module receives a notification that the process has been triggered to reset, for a third task request that the gateway module has received but has not processed, in response to determining that the process identifier carried by the third task request is consistent with the process identifier, performing an operation to return an empty response corresponding to the third task request, and deleting the third task request.

[0009] In some optional implementations of the embodiments of this disclosure, the first task request, the second task request, and the third task request include memory access requests.

[0010] In some optional implementations of the embodiments of this disclosure, the above-mentioned determination of the latest count value of the counter associated with the process management module based on the process identifier carried in the first task request includes: in response to determining that the target process indicated by the process identifier carried in the first task request is consistent with the process carried by the process management module, sending a query request to the process management module and receiving the latest count value of the counter issued by the process management module based on the query request; or, obtaining the latest count value of the counter stored associated with the process identifier carried in the first task request from the count value statistics list, wherein the count values ​​in the count value statistics list are issued to the gateway module by the process management module through a preset signal.

[0011] In some optional implementations of the embodiments of this disclosure, the above process reset processing method further includes: when the process is triggered to reset, redirecting the instruction execution sequence of the thread associated with the process to the termination program, and executing the termination program.

[0012] In some optional implementations of the embodiments of this disclosure, the above process reset processing method further includes: determining that the process reset is completed when the in-transit instructions in the execution sequence are cleared and all task requests for pending responses issued by the process management module are returned.

[0013] In some optional implementations of the embodiments of this disclosure, the process reset processing method further includes: in response to receiving a trigger command to reset the process, incrementing the current count value of the counter by 1 to obtain the latest count value of the counter.

[0014] In some optional implementations of the embodiments of this disclosure, the above process reset processing method further includes: in response to determining that the process reset has not been completed, carrying the current count value of the counter in the task request issued by the process management module; or, in response to determining that the process reset has been completed, carrying the latest count value of the counter in the task request issued by the process management module.

[0015] Secondly, embodiments of this disclosure provide a processor including at least one processing core, wherein the processing core includes a gateway module and a process management module associated with a counter, the counter being used to record the cumulative number of times a process carried by the process management module has been triggered to reset; and the gateway module is configured to: upon receiving a first task request originating from the process management module, determine a latest count value of the counter based on a process identifier carried in the first task request, and in response to determining that the first count value carried in the first task request is inconsistent with the latest count value of the counter, perform an operation related to process reset on the first task request.

[0016] In some optional implementations of the embodiments of this disclosure, the gateway module is further configured to: in response to determining that the first task request belongs to a request that requires a response, perform an operation to return an empty response corresponding to the first task request; or, in response to determining that the first task request belongs to a request that does not require a response, perform an operation to discard the first task request.

[0017] In some optional implementations of the embodiments of this disclosure, the above-mentioned processing core further includes a first hardware module associated with a field. The first hardware module is configured to: upon receiving a second task request from the process management module, determine the current count value of the counter carried by the second task request as the identifier value of the field; determine the identifier value of the field as the first count value carried by the first task request, and send the first task request to the gateway module, wherein the first task request is associated with the second task request.

[0018] In some optional implementations of the embodiments of this disclosure, the gateway module is further configured to: upon receiving a task response, determine the latest count value of the counter based on the process identifier carried in the task response; and in response to determining that the second count value carried in the task response is inconsistent with the latest count value of the counter, perform an operation to discard the task response.

[0019] In some optional implementations of the embodiments of this disclosure, the gateway module is further configured to: upon receiving a notification that a process has been triggered to reset, in response to determining that the process identifier carried by the third task request is consistent with the process identifier, perform an operation to return an empty response corresponding to the third task request and delete the third task request.

[0020] In some optional implementations of the embodiments of this disclosure, the first task request, the second task request, and the third task request include memory access requests.

[0021] In some optional implementations of the embodiments of this disclosure, the gateway module is further configured to: in response to determining that the target process indicated by the process identifier carried in the first task request is consistent with the process carried by the process management module, send a query request to the process management module and receive the latest count value of the counter issued by the process management module based on the query request; or, obtain the latest count value of the counter stored in association with the process identifier carried in the first task request from the count value statistics list, wherein the count value in the count value statistics list is issued to the gateway module by the process management module through a preset signal.

[0022] In some optional implementations of the embodiments of this disclosure, the processing core further includes a second hardware module, which is configured to: redirect the instruction execution sequence of the thread associated with the process to a termination program and execute the termination program when the process is triggered to reset.

[0023] In some optional implementations of the embodiments of this disclosure, the process management module is configured to determine that the reset is complete when the in-transit instructions in the execution sequence are cleared and all task requests awaiting return responses are returned.

[0024] In some optional implementations of the embodiments of this disclosure, the process management module is further configured to: in response to receiving a trigger command to reset the process, increment the current count value of the counter by 1 to obtain the latest count value of the counter.

[0025] In some optional implementations of the embodiments of this disclosure, the process management module is further configured to: in response to determining that the reset is not completed, carry the current count value of the counter in the issued task request; or, in response to determining that the reset is completed, carry the latest count value of the counter in the issued task request.

[0026] Thirdly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that, when executed by a processor, can implement the process reset processing method described in any implementation of the first aspect.

[0027] Fourthly, embodiments of this disclosure provide a computer program product including a computer program that, when executed by a processor, can implement the process reset processing method as described in any implementation of the first aspect.

[0028] According to the solution provided in this disclosure, for any task request (i.e., a first task request) received by the gateway module from the process management module, the latest count value of the counter associated with the process management module carrying the process indicated by the process identifier is determined based on the process identifier carried by the first task request. This latest count value is then compared in real time with the first count value carried by the first task request. If the two count values ​​are found to be inconsistent, the suspended task request can be accurately and timely identified, and operations related to process reset can be performed on it. This ensures that the single process can be effectively terminated, achieving process-level reset, thereby improving system throughput, reliability, availability, and maintainability.

[0029] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0030] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating a process reset method provided in an embodiment of this disclosure; Figure 2 A flowchart illustrating another process reset method provided in this embodiment of the disclosure; Figure 3 This is a schematic diagram of a system in an application scenario provided by an embodiment of the present disclosure; Figure 4 A flowchart of a process reset processing method in an application scenario provided by an embodiment of this disclosure; Figure 5A schematic diagram of the structure of a processor provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of an electronic device suitable for a process reset processing method, provided in an embodiment of this disclosure. Detailed Implementation

[0031] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0032] In the design of Graphics Processing Units (GPUs), there is a need to terminate (kill) a single process without interfering with other processes. A process is the smallest unit of processor resource allocation, each process has its own independent resources, and is isolated from other processes. However, current methods for terminating a single process sometimes fail to terminate it effectively, thus affecting system reliability.

[0033] Therefore, how to effectively terminate a single process without interfering with other processes has become a pressing technical problem.

[0034] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a process reset method provided in an embodiment of the present disclosure. This process reset method can be executed by a processor, meaning it can be applied to a processor including at least one processing core. Each processing core may include, but is not limited to, a gateway module and a process management module. The number of gateway modules and process management modules in each processing core can be one or more, without specific limitation. When there are multiple process management modules, different process management modules can share the same gateway module. A process management module can be understood as a hardware module capable of hosting an independent process, used to manage that process. For example, it manages the termination of the currently hosted process, receives new processes, receives commands issued by the driver, issues tasks to downstream modules, and maintains counter values. The process reset method's corresponding flow 100 may include the following steps: Step 101: When the gateway module receives the first task request from the process management module, it determines the latest count value of the counter associated with the process management module based on the process identifier carried in the first task request. The counter is used to record the cumulative number of times the process carried by the process management module has been triggered to reset.

[0035] In this embodiment, each processing core of the processor includes a process management module associated with a corresponding counter. This can be understood as each process management module independently maintaining its own counter, meaning there is a one-to-one correspondence between the process management module and the counter. The counter can be located within the process management module or connected via a communication mechanism (e.g., sending a request to increment or decrement the counter). The counter records the cumulative number of times the process carried by its corresponding process management module has been triggered for reset. The process management module can simultaneously issue a process identifier when issuing a task. Thus, when the gateway module in the processing core receives a first task request from the corresponding process management module, it can accurately determine the latest count value of the counter maintained by the process management module carrying the process identifier in the first task request. The first task request can refer to any task request received by or arriving at the gateway module, not a specific one, and it can originate from an upstream hardware module adjacent to the gateway module.

[0036] In some optional implementations of the embodiments of this disclosure, the first task request originating from the process management module can be understood as the first task request being directly issued to the gateway module by the process management module. Alternatively, it can be understood as the first task request being triggered by the task issued by the process management module, which then triggers a corresponding downstream hardware module to generate and issue the request to the gateway module; no specific limitation is made here. That is to say, the upstream hardware module adjacent to the gateway module can be the process management module or other hardware modules downstream of the process management module.

[0037] In some optional implementations of the embodiments of this disclosure, the processing core may include any number of first hardware modules, with no topological limitation, in addition to the process management module and the gateway module. The process reset processing method may further include: when the first hardware module receives a second task request from the process management module, determining the current count value of the counter carried in the second task request as the identifier value of a field associated with the first hardware module; determining the identifier value of the field as the first count value carried in the first task request, and sending a first task request to the gateway module, wherein the first task request is associated with the second task request. In some optional implementations of the embodiments of this disclosure, the first hardware module may be a module adjacent to the gateway module.

[0038] In this embodiment, a corresponding field can be added to the first hardware module in the processing core to identify the current count value of the associated counter issued along with the task issued by the process management module. This counter value issued by the process management module is then transparently transmitted during task processing communication, ensuring accurate and reliable identification when the task request reaches the gateway module. In some optional implementations of this disclosure, the association between the first task request and the second task request can be understood as both carrying the same counter value. Optionally, the first task request and the second task request can be identical, or the first task request can be determined based on the second task request or generated through the task distribution corresponding to the second task request.

[0039] In some optional implementations of this disclosure, the width of the field associated with the first hardware module can be greater than or equal to the counting width of the counter associated with the process management module. For example, if the counting width of the counter associated with the process management module, used to identify its count value, is 2 bits, then the width of the field associated with the first hardware module can be 2 bits, or it can be any other number of bits larger than 2 bits. This can be flexibly set according to specific needs to effectively control the bandwidth occupied.

[0040] In some optional implementations of the embodiments of this disclosure, the second task request originating from the process management module can be understood as the second task request being directly issued to the first hardware module by the process management module. Alternatively, it can be understood as the second task request being triggered by the task issued by the process management module, which in turn triggers other downstream hardware modules to generate and issue the request to the first hardware module; no specific limitation is made here.

[0041] In some optional implementations of the embodiments of this disclosure, the first task request and the second task request may include, but are not limited to, memory access requests. Optionally, the memory access request may refer to the operation instruction issued by the processing core to other external registers or memory (such as static random access memory (SRAM), dynamic random access memory (DRAM), etc.) outside the processing core in order to read or write data; of course, it may also refer to the operation instruction for reading or writing data issued by the issuing end of the memory access request to the memory within the processing core.

[0042] In some optional implementations of the embodiments of this disclosure, the step 101 above, which determines the latest count value of the counter associated with the process management module based on the process identifier carried in the first task request, can be implemented as one of the following: (1) In response to determining that the target process indicated by the process identifier carried in the first task request is consistent with the process carried by the process management module, a query request is sent to the process management module, and the latest count value of the counter issued by the process management module based on the query request is received.

[0043] In this implementation, the network module can determine the process management module carrying the target process indicated by the process identifier carried in the received first task request. The network module can then proactively obtain the latest count value of the counter associated with the process management module by sending a query request to that module. Specifically, the process management module can respond to the query request and send the latest count value of its associated counter to the network management module. For example, the process management module can send the latest count value of its associated counter to the gateway module via a pulse signal.

[0044] (2) Obtain the latest count value of the counter associated with the process identifier carried in the first task request from the count value statistics list. The count value in the count value statistics list is sent to the gateway module by the process management module through a preset signal.

[0045] In this implementation, a local counter value statistics list can be maintained in the gateway module to store the correspondence between the identifiers of processes carried by the process management module and the latest count values ​​of counters associated with the process management module. Thus, the gateway module can conveniently retrieve the latest count value of the counter associated with the process identifier from this counter value statistics list based on the process identifier carried in the received first task request. The latest count value of the counter stored in the counter value statistics list can be actively sent to the gateway module by the process management module via a preset signal, and maintained by the gateway module. This preset signal includes, but is not limited to, level signals or pulse signals. For example, in response to a process carried by the process management module being triggered to reset, the latest count value of its associated counter can be sent to the gateway module via a pulse signal for recording; or in response to an update of the count value of the counter associated with the process management module, the latest count value of the counter can be communicated to the gateway module via a level signal, thereby updating the count value stored in the counter value statistics list at the gateway module that is associated with the identifier of the process carried by the process management module.

[0046] In some optional implementations of the embodiments of this disclosure, the above-mentioned count value statistics list may store the correspondence between the identifiers of processes carried by different process management modules and the latest count values ​​of the counters associated with each process management module.

[0047] Step 102: In response to determining that the first count value carried by the first task request is inconsistent with the latest count value of the counter, perform an operation related to process reset on the first task request.

[0048] In this embodiment, in addition to carrying the corresponding process identifier, the first task request may also carry the first count value of the associated counter issued by the process management module when issuing the task, and this first count value is transparently transmitted to the gateway module. Thus, for each task request arriving at the gateway module, the count value carried in the task request can be compared with the latest count value of the counter associated with the process management module corresponding to the task request, regardless of whether the process carried by the process management module has been triggered to reset, to accurately identify whether the corresponding task request is a task request suspended due to congestion or error. Optionally, if it is determined that the first count value carried in the first task request received by the gateway module is inconsistent with the latest count value of the counter associated with the process management module, the first task request can be determined to be a suspended task request, and operations related to process reset can be performed on it.

[0049] According to the process reset processing method provided in the embodiments of this disclosure, for any task request (i.e., a first task request) received by the gateway module from the process management module, the latest count value of the counter associated with the process management module carrying the process identifier is determined based on the process identifier carried by the first task request. The latest count value is then compared in real time with the first count value carried by the first task request. When the two count values ​​are found to be inconsistent, the suspended task request can be accurately and timely identified, and operations related to process reset can be performed on it. This ensures that the single process can be effectively terminated, thereby achieving process-level reset. Moreover, compared to the method of emptying the pipeline and performing a single-process soft reset by jumping to the killing program at the instruction level, this method avoids the situation where the killing program also depends on the completion of the preceding in-process instructions, but the killing program cannot be completed in time due to the pending task requests of the preceding in-process instructions, thus preventing the corresponding process from being truly terminated. Therefore, the process reset processing method of this disclosure can effectively terminate a single process at a controllable cost without affecting the operation of other processes, avoiding a full processor (or full chip) shutdown, including all processes. This effectively controls the scope of process reset and ensures the reliability, availability, and maintainability of the system.

[0050] In some optional implementations of the embodiments of this disclosure, in response to determining that the first count value carried by the first task request is consistent with the latest count value of the counter associated with the process management module, the task processing flow corresponding to the first task request can be executed, including but not limited to forwarding the first task request to downstream hardware modules.

[0051] Please refer to Figure 2 , Figure 2 This is a flowchart of another process reset processing method provided in an embodiment of this disclosure. This process reset processing method can be executed by a processor, meaning it can be applied to a processor including at least one processing core. Each processing core may include, but is not limited to, a gateway module and a process management module. The number of gateway modules and process management modules in each processing core can be one or more, without specific limitation. When there are multiple process management modules, different process management modules can share the same gateway module. A process management module can be understood as a hardware module capable of carrying an independent process, used to manage that process. For example, it manages the termination of the currently carried process, receives new processes, receives commands issued by the driver, issues tasks to downstream modules, and maintains counter values. The process reset processing method's corresponding flow 200 may include the following steps: Step 201: When the gateway module receives the first task request from the process management module, it determines the latest count value of the counter associated with the process management module based on the process identifier carried in the first task request. The counter is used to record the cumulative number of times the process carried by the process management module has been triggered to reset.

[0052] Step 202: In response to determining that the first count value carried by the first task request is inconsistent with the latest count value of the counter, perform an operation related to process reset on the first task request.

[0053] Steps 201-202 above and as follows Figure 1 The steps 101-102 shown are the same. For the same parts, please refer to the corresponding parts of the previous embodiment. They will not be repeated here.

[0054] Step 203: When the gateway module receives a task response, it determines the latest count value of the counter based on the process identifier carried in the task response.

[0055] In this embodiment, the gateway module can also receive task responses corresponding to its issued task requests from its downstream modules. For any task response received by the gateway module, the latest count value of the counter maintained by the process management module corresponding to the process indicated by the process identifier can be accurately determined based on the process identifier carried in the task response. Here, "task response" can refer to any task response received by the gateway module or reaching the gateway module, rather than a specific one.

[0056] In some optional implementations of the embodiments of this disclosure, the step of determining the latest count value of the counter associated with the process management module based on the process identifier carried in the task response can refer to the relevant description of determining the latest count value of the counter based on the process identifier carried in the first task request, and will not be repeated here.

[0057] Step 204: In response to the determination that the second count value carried by the task response is inconsistent with the latest count value of the counter, the task response is discarded.

[0058] In this embodiment, in addition to carrying the corresponding process identifier, the task response may also carry a second count value of the associated counter, which is simultaneously issued by the process management module when the task is issued. This second count value originates from the corresponding task request. Thus, for each task response arriving at the gateway module, the count value carried in the task response can be compared with the latest count value of the counter associated with the corresponding process management module, regardless of whether the process carried by the process management module has been triggered to reset. This accurately identifies whether the corresponding task response is a return for an overdue task request or a response in transit before the process management module is reset. Optionally, if it is determined that the second count value carried in the task response received by the gateway module is inconsistent with the latest count value of the counter associated with the process management module, the task response can be determined to be a return for an overdue task request. For example, the overdue task request may include a request that was not promptly responded to before the process carried by the process management module was reset, and thus, the task response can be discarded.

[0059] According to the process reset processing method provided in this disclosure, for any task response received by the gateway module, the latest count value of the counter associated with the process management module carrying the process indicated by the process identifier is determined based on the process identifier carried by the task response. This latest count value is then compared in real time with a second count value carried by the task response. If the two count values ​​are found to be inconsistent, the system can accurately and promptly return expired task requests and discard the task response. This prevents newly started processes from entering an uncertain state or the response data related to the newly started process from being overwritten by the return of expired task requests after the reset. Furthermore, compared to a single-process hard reset method that adds traversal and clearing logic for task requests to the hardware module associated with the process, this avoids increasing the complexity of processor design, effectively controlling area overhead and verification workload. Thus, the process reset processing method of this disclosure can effectively terminate a single process at a controllable cost and avoid interference from the return of expired task requests from terminated processes to newly started tasks by the process management module, preventing corresponding uncertain states and data loss. This effectively ensures the reliability, availability, and maintainability of the system.

[0060] In some optional implementations of the embodiments of this disclosure, in response to determining that the second count value carried by the task response is consistent with the latest count value of the counter associated with the process management module, the task processing flow corresponding to the task response can be executed, including but not limited to returning the task response to the upstream hardware module.

[0061] The above disclosure Figure 1 or Figure 2 In some optional implementations of the corresponding embodiments, in this process reset processing method, in response to receiving a trigger command to reset the process, the current count value of the counter associated with the process management module can be incremented by 1 to obtain the latest count value of the counter. Thus, by driving the trigger command to reset the process hosted by the process management module, triggering the update of the value of the counter associated with the process management module, it is possible to simply and efficiently identify whether the process is in a reset state. The reset of the process hosted by the process management module can be triggered by the corresponding driver program.

[0062] The above disclosure Figure 1 or Figure 2 In some optional implementations of the corresponding embodiments, the operation related to process reset in step 102 or step 202 above may include, but is not limited to, one of the following: (1) In response to determining that the first task request belongs to a request that requires a response, perform the operation of returning a dummy response corresponding to the first task request; for example, a dummy response may refer to a completion-type response that does not carry a payload and is used to terminate the waiting of the peer (i.e., the receiver of the dummy response). In this way, the problem of blocked pending task requests can be effectively solved, thereby effectively terminating the process.

[0063] (2) In response to determining that the first task request is a type of request that does not require a response, the operation of discarding the first task request is performed.

[0064] In this embodiment, by performing an operation of returning an empty response or discarding the suspended task request, overdue in-transit transactions can be accurately intercepted, ensuring cache consistency and bus integrity when the process management module processes tasks.

[0065] Based on any of the above embodiments of this disclosure, the above process reset processing method may optionally include the following: when the gateway module receives a notification that a process has been triggered to reset, for a third task request that the gateway module has received but has not processed, in response to determining that the process identifier carried by the third task request is consistent with the process identifier, an operation is performed to return an empty response corresponding to the third task request, and the third task request is deleted.

[0066] In this embodiment, when a process carried by the process management module is triggered to reset, a notification of the reset can be sent to the gateway module. At this time, all task requests that the gateway module has received but not yet processed, i.e., third task requests, can be traversed to identify the third task requests whose process identifiers match the identifier of the currently reset process carried by the process management module. A forced return operation is then performed on the part of the third task requests that are in transit for the reset process, i.e., an empty response is returned corresponding to that part of the third task requests. This ensures that all task requests issued by the reset process that require a response but have not yet been returned are effectively returned, thereby ensuring that the process can be effectively terminated. After the forced return operation is completed, the third task request is deleted to release the occupied resources in a timely manner and improve resource utilization.

[0067] In some optional implementations of the embodiments of this disclosure, the aforementioned third task request may include, but is not limited to, a memory access request. Optionally, the memory access request may refer to the operation instruction issued by the processing core to other external registers or memories (such as static random access memory (SRAM), dynamic random access memory (DRAM), etc.) outside the processing core in order to read or write data; of course, it may also refer to the operation instruction for reading or writing data issued by the issuing end of the memory access request to the memory within the processing core.

[0068] Based on any of the above embodiments of this disclosure, the process reset processing method may optionally include the following: when a process is triggered to reset, redirecting the instruction execution sequence of the thread associated with the process to a termination program and executing the termination program.

[0069] In this embodiment, when the process carried by the process management module is triggered to reset, in order to effectively terminate the process, in addition to processing the task requests that have been sent to the gateway module or have arrived in real time in relation to the process reset, it is also necessary to terminate the in-transit instructions to be executed in the instruction sequence of the thread associated with the process. Optionally, the in-transit instruction stream of the thread can be drained by redirecting the instruction execution sequence of each thread to the termination program and executing the termination program to stop the continued execution of the original program in the instruction execution sequence, so as to ensure that the process can be effectively terminated. Specifically, redirecting the instruction execution sequence of the thread associated with the process that will be triggered to reset to a termination procedure can be understood as inserting the termination procedure into the corresponding position in the instruction execution sequence. For example, it can be positioned before the in-transit instruction that is about to be executed when the process is triggered to reset. By executing the termination procedure, the execution of the in-transit instruction that is about to be executed and other in-transit instructions that are to be executed afterward can be truncated. In-transit instructions can be understood as instructions that have not yet been sent to the gateway module with the corresponding task request. The end of this part of the in-transit instructions does not depend on other preceding in-transit instructions. In this way, the process can be accurately and efficiently terminated by redirecting to the termination procedure.

[0070] Based on any of the above embodiments of this disclosure, the above process reset processing method may optionally include the following: when the in-transit instructions in the execution sequence are cleared and all task requests for pending responses issued by the process management module are returned, it is determined that the process reset is completed.

[0071] In this embodiment, a process can be considered to have been effectively terminated and its reset completed if and only if all tasks issued by the process management module are returned and the execution queue is cleared.

[0072] In some optional implementations of the embodiments of this disclosure, the above process reset processing method may further include the following: in response to determining that the process reset is not completed, carrying the current count value of the counter in the task request issued by the process management module; or, in response to determining that the process reset is completed, carrying the latest count value of the counter in the task request issued by the process management module.

[0073] In this embodiment, when a process carried by the process management module is triggered to reset but does not complete the reset, the incomplete task requests sent downstream still carry the old count value before the latest count value is updated, i.e., the current count value before the counter is incremented by 1. Correspondingly, when the process carried by the process management module is reset and is reactivated to process new tasks in response to new commands, the latest count value of the counter associated with the process management module, which is updated based on the current count value when the process is triggered to reset, can be carried in the task requests corresponding to the new task, so as to achieve a fast and safe reset of a single process.

[0074] It should be noted that when multiple processes managed by the core processing module are simultaneously triggered to reset, the process reset processing method described in any of the above embodiments of this disclosure can be applied to each process that is triggered to reset and is managed by the corresponding process management module. In this way, parallel reset of multiple processes can be supported without interference between them, thereby improving system reliability.

[0075] To enhance understanding, this disclosure also provides a specific implementation scheme based on a particular application scenario. Please refer to the example below. Figure 3 The system 300 shown and Figure 4 The process shown is 400.

[0076] by Figure 3 Taking a single hardware process module 311 (corresponding to the process management module in the above embodiment) in the processing core 31 of the processor (such as a GPU) as an example, the hardware process module 311 records all the tasks it issues, and the downstream hardware modules (such as...) Figure 3 The modules A, B, C, X, Y, Z, etc. shown (the topology formed by these modules is not specifically limited here, including the first hardware module in the above embodiment) will generate one or more threads for each task to complete the target task. The generated threads will prepare and issue instructions in the thread instruction issuing module 312 to complete the target task. The number of thread instruction issuing modules 312 in the processing core 31 can be N, where N can be an integer greater than or equal to 1.

[0077] In this embodiment, each hardware process module 311 can independently maintain an epoch counter (corresponding to the counter in the above embodiment, also called an identifier counter). This counter can correspond to the reset cycle identifier of the process carried by the hardware process module 311, and is used to record the cumulative number of times the process carried by the hardware process module 311 has been triggered to reset. Furthermore, an epoch identifier field (corresponding to the field in the above embodiment) can be added to the interface of each hardware module in the pipeline of the processor's processing core 31 for judging the validity of requests and responses. The bit width of the epoch identifier field can be the same as the counting width of the epoch counter, for example, both being 2 bits. Thus, by introducing a new epoch counter and epoch field, independent reset of the process carried by each hardware process module 311 in the GPU can be achieved. Each hardware process module 311 needs to send its current epoch value (corresponding to the counter values ​​in the above embodiment) when issuing a task or request, and the epoch value must also be transparently transmitted with the request or task during communication between the various hardware modules.

[0078] In this embodiment, the processing logic for filtering, discarding, and returning an empty response of the epoch value and process identifier (ID) can also be implemented in a suitable port module 313 (corresponding to the gateway module in the above embodiment), such as... Figure 3 As shown, the port module 313 can be set in the middle of the processing core 31, such as setting P units near the hardware process module 311, or it can be set at the edge of the processing core 31, such as setting K units near the external module 32. The values ​​of P and K can be integers greater than or equal to 1.

[0079] In this embodiment, regardless of whether a reset occurs, i.e. whether the process carried by the hardware process module 311 is triggered to reset, the port module 313 will compare the epoch value carried in the received upstream request and downstream response with the latest epoch value corresponding to the process.

[0080] Specifically, if the epoch value (corresponding to the first or second task request in the above embodiments, and originating from an upstream module adjacent to port module 313) carried by the upstream request is the same as the latest epoch value (corresponding to the latest count value in the above embodiments) obtained by querying the process ID carried by the upstream request, then the request is forwarded downstream normally. If they are different, port module 313 can determine whether to return a dummy response based on the request type, and then discard the request without forwarding it to the downstream module (such as the external module 32 mentioned above): if the request needs to return, a dummy response is returned upstream and the request is discarded; if no return is needed, the request is discarded directly. In this way, suspended requests are accurately identified at the hardware level, and the problem of instruction blocking is solved by using dummy responses, fundamentally solving the problem of incomplete process killing, accurately intercepting outdated in-transit transactions, and ensuring cache consistency and bus integrity.

[0081] Specifically, if the epoch value (corresponding to the second count value in the above embodiment) carried by the downstream response (corresponding to the task response in the above embodiment) is the same as the latest epoch value (corresponding to the latest count value in the above embodiment) obtained by querying the process ID carried by the downstream response, then the port module 313 returns the response normally; if they are different, the port module 313 can directly discard the response. In this way, the interference of the return of the request in transit from the terminated process on the newly started task on the hardware process module 311 can be eliminated, avoiding uncertain states and data loss.

[0082] In this embodiment, when the system software or user detects that the process they belong to needs to be terminated, they can notify the hardware process module 311 through the communication mechanism between the driver 30 and the processing core 31, triggering a reset of the process currently being carried by the hardware process module 311 (see reference). Figure 4 (Step 401 in process 400 shown). At this time, the hardware process module 311 increments its maintained epoch counter by 1 (see step 401 in process 400). Figure 4 In step 402 of the process 400 shown, the epoch value incremented by 1 corresponds to the latest count value in the above embodiment, and the epoch value carried by the issued task or request (corresponding to the current count value in the above embodiment) remains unchanged. Optionally, the hardware process module 311 can simultaneously notify all port modules 313 of the reset occurrence via a pulse signal and inform them of the latest epoch value of the epoch count value corresponding to the hardware process module 311, so as to maintain the latest epoch value corresponding to the process at the port module 313, which facilitates querying based on the process ID.

[0083] In this embodiment, when the process carried by the hardware process module 311 is triggered to reset, a forced return of the in-transit request of the triggered reset process can also be executed (see [reference]). Figure 4 In step 403 of the flowchart 400 shown, optionally, the process that is triggered to reset can notify all its corresponding threads through a level broadcast signal (such as a high-level broadcast signal or a low-level broadcast signal) to redirect its instruction stream to a predefined killing program to clear all in-transit instructions and requests; in some other optional implementations of the embodiments of this disclosure, it can also notify all its corresponding threads through a pulse signal to redirect its instruction stream to a predefined killing program, and so on. The port module 313 can traverse and search for the incomplete requests (corresponding to the third task requests, outstanding requests in the above embodiments) belonging to the process that is triggered to reset, and determine whether the process ID of each incomplete request matches the process ID of the process that was reset. If they match, it means that the incomplete request belongs to the process that was reset, and the port module 313 can return a dummy response, then delete the request and release the related resources.

[0084] In this embodiment, when the process carried by the hardware process module 311 is triggered to reset, the thread of the reset process can also be redirected to the killing program (see [reference]). Figure 4 In step 404 of the process 400 shown, optionally, the instruction streams of each thread of the process (corresponding to the instruction execution sequence in the above embodiment) can be redirected to a dedicated killing program to drain the instructions in transit in each pipeline and execute the killing program instead of continuing to execute the original program.

[0085] In this embodiment, it is also necessary to determine whether the reset is complete (see...). Figure 4 In step 404 of the illustrated process 400, optionally, the reset is considered complete if and only if all tasks issued by the hardware process module 311 return and the execution queue is cleared. The process reset is complete after all tasks issued by the hardware process module 311 have returned. At this time, the processing core 31 can notify the driver 30 to perform subsequent processing, such as executing a new task. The hardware process module 311 can then respond to the new command or be reactivated.

[0086] It should be noted that, after the driver 30 triggers the reset of the hardware process module 311 but before the reset is complete, when the hardware process module 311 sends unfinished tasks downstream, it still uses the old epoch value before the epoch counter increments by 1. However, once the process currently carried by the hardware process module 311 has completed its reset, the hardware process module 311 will use the new epoch value after the epoch counter increments by 1 when executing newly issued tasks by the driver 30.

[0087] This disclosure provides a process-level reset mechanism that can safely and cost-effectively terminate a single process, avoiding a full chip shutdown and eliminating the need to reset the entire chip. It operates only on a single process, identifying and discarding expired in-transit requests of the process to be terminated through hardware means without globally resetting all processes or affecting the operation of other processes. This avoids the costly overhead of a global reset, and the scope of process reset is controllable, preventing the system (e.g., multi-tenant systems, such as device virtualization) from entering an uncontrollable state. Thus, at a controllable cost, it achieves rapid and safe termination of a single process while ensuring the continuous operation of other processes, effectively terminating the single process (including clearing all in-transit instructions and requests), ensuring that related hardware modules return to an idle state, improving the reliability of process reset, thereby guaranteeing system reliability, availability, and maintainability, increasing system throughput, and supporting multiple processes to be reset in parallel without interference, further enhancing system reliability. This reset mechanism also exhibits strong compatibility.

[0088] Further reference Figure 5 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of a processor, which is similar to... Figure 1 Corresponding to the method embodiments shown, this processor can be specifically applied to various chip products.

[0089] like Figure 5 As shown, the processor 500 of this embodiment may include at least one processing core 501, wherein the processing core 501 includes a gateway module 5012 and a process management module 5011 associated with a counter, the counter being used to record the cumulative number of times a process carried by the process management module 5011 has been triggered to reset; and the gateway module 5012 is configured to: upon receiving a first task request from the process management module 5011, determine the latest count value of the counter based on the process identifier carried in the first task request, and in response to determining that the first count value carried in the first task request is inconsistent with the latest count value of the counter, perform an operation related to process reset on the first task request.

[0090] In this embodiment, the specific processing of the gateway module 5012 in the processor 500 and the resulting technical effects can be referred to respectively. Figure 1 The relevant descriptions of steps 101-102 in the corresponding embodiments will not be repeated here.

[0091] In some optional implementations of the embodiments of this disclosure, the gateway module 5012 is further configured to: in response to determining that the first task request belongs to a request that requires a response, perform an operation to return an empty response corresponding to the first task request; or, in response to determining that the first task request belongs to a request that does not require a response, perform an operation to discard the first task request.

[0092] In some optional implementations of the embodiments of this disclosure, the processing core 501 may further include a first hardware module (not shown in the figure) associated with a field. The first hardware module is configured to: upon receiving a second task request from the process management module 5011, determine the current count value of the counter carried by the second task request as the identifier value of the field; determine the identifier value of the field as the first count value carried by the first task request, and send the first task request to the gateway module 5012, wherein the first task request is associated with the second task request.

[0093] In some optional implementations of the embodiments of this disclosure, the gateway module 5012 is further configured to: upon receiving a task response, determine the latest count value of the counter based on the process identifier carried in the task response; and in response to determining that the second count value carried in the task response is inconsistent with the latest count value of the counter, perform an operation to discard the task response.

[0094] In some optional implementations of the embodiments of this disclosure, the gateway module 5012 is further configured to: upon receiving a notification that a process has been triggered to reset, for a received but unprocessed third task request, in response to determining that the process identifier carried by the third task request is consistent with the process identifier, perform an operation to return an empty response corresponding to the third task request, and delete the third task request.

[0095] In some optional implementations of the embodiments of this disclosure, the first task request, the second task request, and the third task request include memory access requests.

[0096] In some optional implementations of the embodiments of this disclosure, the gateway module 5012 is further configured to: in response to determining that the target process indicated by the process identifier carried in the first task request is consistent with the process carried by the process management module 5011, send a query request to the process management module 5011 and receive the latest count value of the counter issued by the process management module 5011 based on the query request; or, obtain the latest count value of the counter stored in association with the process identifier carried in the first task request from the count value statistics list, wherein the count value in the count value statistics list is issued to the gateway module 5012 by the process management module 5011 through a preset signal.

[0097] In some optional implementations of the embodiments of this disclosure, the processing core 501 may further include a second hardware module (not shown in the figure), which is configured to redirect the instruction execution sequence of the thread associated with the process to a termination program and execute the termination program when the process is triggered to reset.

[0098] In some optional implementations of the embodiments of this disclosure, the process management module 5011 is configured to determine that the reset is complete when the in-transit instructions in the execution sequence are cleared and all task requests awaiting return responses are returned.

[0099] In some optional implementations of the embodiments of this disclosure, the process management module 5011 is further configured to: in response to receiving a trigger command to reset the process, increment the current count value of the counter by 1 to obtain the latest count value of the counter.

[0100] In some optional implementations of the embodiments of this disclosure, the process management module 5011 is further configured to: in response to determining that the reset is not completed, carry the current count value of the counter in the issued task request; or, in response to determining that the reset is completed, carry the latest count value of the counter in the issued task request.

[0101] This embodiment exists as a processor embodiment corresponding to the above method embodiment. For any task request (i.e., the first task request) received by the gateway module from the process management module, the latest count value of the counter associated with the process management module carrying the process identifier is determined based on the process identifier carried by the first task request. The latest count value is then compared with the first count value carried by the first task request in real time. If the two count values ​​are found to be inconsistent, the suspended task request can be accurately and timely identified, and operations related to process reset can be performed on it. This ensures that the single process can be effectively terminated, achieving process-level reset, thereby improving system throughput, reliability, availability, and maintainability.

[0102] According to embodiments of this disclosure, this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions that, when executed by a processor, can implement the process reset processing method described in any of the above embodiments.

[0103] According to embodiments of this disclosure, this disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, can implement the process reset processing method described in any of the above embodiments.

[0104] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device 600 includes one or more processors 601, a communication interface 602, and a memory 603. The processors 601, communication interface 602, and memory 603 are interconnected via a bus 604. Optionally, the electronic device 600 may further include an input / output interface 605, which is connected to input / output devices for receiving user-set parameters, etc. The electronic device 600 can be used to implement some or all of the functions of the device embodiments or system embodiments of the present disclosure described above; the processor 601 can also be used to implement some or all of the operation steps of the method embodiments of the present disclosure described above. For example, the specific implementation of various operations performed by the electronic device 600 can be referred to the specific details in the above embodiments, such as the processor 601 being used to execute some or all of the steps or operations in the above method embodiments.

[0105] It should be understood that, Figure 6 The electronic device 600 may include one or more processors 601, and the multiple processors 601 may collaboratively provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or an arbitrary connection mode; or the multiple processors 601 may form a processor sequence or a processor array; or the multiple processors 601 may be divided into a main processor and an auxiliary processor; or the multiple processors 601 may have different architectures, such as adopting a heterogeneous computing architecture. Furthermore, Figure 6 The structural and functional descriptions of the electronic device 600 shown are exemplary and non-limiting. In some exemplary embodiments, the electronic device 600 may include... Figure 6 The diagram shows more or fewer components, or combinations of some components, or splitting of some components, or different arrangements of components.

[0106] The processor 601 can have various specific implementations. For example, the processor 601 may include one or more combinations of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a tensor processing unit (TPU), or a data processing unit (DPU), etc., and this disclosure does not impose specific limitations. The processor 601 can also be a single-core processor or a multi-core processor. The processor 601 can be a combination of a CPU and hardware chips. The aforementioned hardware chips can be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The aforementioned PLDs can be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof. The processor 601 can also be implemented using logic devices with built-in processing logic, such as FPGAs or digital signal processors (DSPs). The communication interface 602 can be a wired interface or a wireless interface, used to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless LAN interface, etc.

[0107] Memory 603 may be non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 603 may also be volatile memory, which may be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as SRAM, DRAM, synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The memory 603 can also be used to store program code and data so that the processor 601 can call the program code stored in the memory 603 to execute some or all of the operation steps in the above method embodiments, or to execute the corresponding functions in the above device embodiments.

[0108] Bus 604 can be a Peripheral Component Interconnect Express (PCIe) bus, or an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. Bus 604 can be divided into address bus, data bus, control bus, etc. In addition to the data bus, bus 604 can also include a power bus, control bus, and status signal bus. However, for clarity, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0109] The methods and devices provided in this disclosure are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, embodiments, implementation methods, examples, or methods of implementation can be referred to mutually, and repeated details will not be repeated. This disclosure also provides a system comprising multiple computing devices, the structure of each computing device being comparable to the structure of the computing devices described above. The functions or operations achievable by this system can be referenced to the specific implementation steps in the above method embodiments and / or the specific functions described in the above processor embodiments, and will not be repeated here.

[0110] According to the technical solution of this disclosure embodiment, for any task request (i.e., a first task request) received by the gateway module from the process management module, the latest count value of the counter associated with the process management module carrying the process indicated by the process identifier is determined based on the process identifier carried by the first task request. The latest count value is then compared with the first count value carried by the first task request in real time. When the two count values ​​are found to be inconsistent, the suspended task request can be accurately and timely identified, and operations related to process reset can be performed on it. This ensures that the single process can be effectively terminated, achieving process-level reset, thereby improving system throughput, reliability, availability, and maintainability.

[0111] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. This disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this disclosure can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. A computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the flow or function according to embodiments of this disclosure is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0112] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0113] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. The steps in the methods of the embodiments of this disclosure can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this disclosure can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this disclosure fall within the scope of this disclosure and its equivalents, then this disclosure also intends to include these modifications and variations.

[0114] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0115] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A process reset method, applied to a processor including at least one processing core, the processing core including a gateway module and a process management module, the method comprising: When the gateway module receives a first task request from the process management module, it determines the latest count value of the counter associated with the process management module based on the process identifier carried by the first task request, wherein the counter is used to record the cumulative number of times the process carried by the process management module has been triggered to reset; In response to determining that the first count value carried by the first task request is inconsistent with the latest count value of the counter, an operation related to process reset is performed on the first task request.

2. The method according to claim 1, wherein, The operation related to process reset in response to the first task request includes: In response to determining that the first task request is a request that requires a response, perform the operation of returning an empty response corresponding to the first task request; or... In response to determining that the first task request is a type of request that does not require a response, the operation of discarding the first task request is performed.

3. The method according to claim 1, wherein, The processing core further includes a first hardware module, and the method further includes: When the first hardware module receives a second task request from the process management module, the current count value of the counter carried in the second task request is determined as the identifier value of the field associated with the first hardware module. The identifier value of the field is determined as the first count value carried by the first task request, and the first task request is sent to the gateway module, wherein the first task request is associated with the second task request.

4. The method according to claim 1, wherein, The method further includes: When the gateway module receives a task response, it determines the latest count value of the counter based on the process identifier carried in the task response. In response to determining that the second count value carried by the task response is inconsistent with the latest count value of the counter, the task response is discarded.

5. The method according to claim 1, wherein, The method further includes: When the gateway module receives a notification that the process has been triggered to reset, in response to determining that the process identifier carried by the third task request matches the process identifier, the gateway module performs an operation to return an empty response corresponding to the third task request and deletes the third task request.

6. The method according to claim 4, wherein, The first task request, the second task request, and the third task request all include memory access requests.

7. The method according to claim 1, wherein, The step of determining the latest count value of the counter associated with the process management module based on the process identifier carried in the first task request includes: In response to determining that the target process indicated by the process identifier carried in the first task request is consistent with the process carried by the process management module, a query request is sent to the process management module, and the latest count value of the counter issued by the process management module based on the query request is received; or, The latest count value of the counter associated with the process identifier carried in the first task request is obtained from the count value statistics list, wherein the count value in the count value statistics list is sent to the gateway module by the process management module through a preset signal.

8. The method according to any one of claims 1 to 7, wherein, The method further includes: If the process is triggered to reset, the instruction execution sequence of the thread associated with the process is redirected to the termination procedure, and the termination procedure is executed.

9. The method according to claim 8, wherein, The method further includes: When all in-transit instructions in the execution sequence are cleared and all task requests for pending responses issued by the process management module are returned, the process reset is determined to be complete.

10. The method according to claim 9, wherein, The method further includes: In response to receiving a trigger command to reset the process, the current count value of the counter is incremented by 1 to obtain the latest count value of the counter.

11. The method according to claim 9, wherein, The method further includes: In response to determining that the process reset has not been completed, the current count value of the counter is included in the task request issued by the process management module; or, In response to determining that the process has been reset, the latest count value of the counter is carried in the task request issued by the process management module.

12. A processor comprising at least one processing core, wherein, The core processing module includes a gateway module and a process management module associated with a counter. The counter is used to record the cumulative number of times the process carried by the process management module is triggered to reset. as well as The gateway module is configured to: upon receiving a first task request originating from the process management module, determine the latest count value of the counter based on the process identifier carried in the first task request, and in response to determining that the first count value carried in the first task request is inconsistent with the latest count value of the counter, perform an operation related to process reset on the first task request.

13. The processor according to claim 12, wherein, The processing core also includes a first hardware module associated with fields, the first hardware module being configured as follows: Upon receiving a second task request from the process management module, the current count value of the counter carried in the second task request is determined as the identifier value of the field. The identifier value of the field is determined as the first count value carried by the first task request, and the first task request is sent to the gateway module, wherein the first task request is associated with the second task request.

14. The processor according to claim 12, wherein, The gateway module is also configured to: Upon receiving a task response, the latest count value of the counter is determined based on the process identifier carried in the task response; In response to determining that the second count value carried by the task response is inconsistent with the latest count value of the counter, the task response is discarded.

15. The processor according to claim 12, wherein, The gateway module is also configured to: Upon receiving a notification that the process has been triggered to reset, in response to a received but unprocessed third task request, if the process identifier carried by the third task request matches the identifier of the process, an operation is performed to return an empty response corresponding to the third task request, and the third task request is deleted.

16. The processor according to any one of claims 12 to 15, wherein, The processing core also includes a second hardware module, which is configured as follows: If the process is triggered to reset, the instruction execution sequence of the thread associated with the process is redirected to the termination procedure, and the termination procedure is executed.

17. The processor of claim 16, wherein, The process management module is configured as follows: The reset is determined to be complete when all in-transit instructions in the execution sequence are cleared and all task requests awaiting a response are returned.

18. The processor of claim 17, wherein, The process management module is also configured as follows: In response to determining that the reset is incomplete, the current count value of the counter is included in the issued task request; or, In response to determining that the reset is complete, the latest count value of the counter is carried in the issued task request.

19. A non-transitory computer-readable storage medium storing computer instructions, wherein, When the computer instructions are executed by the processor, they implement the process reset processing method according to any one of claims 1-11.

20. A computer program product comprising a computer program, wherein, When the computer program is executed by the processor, it implements the process reset processing method according to any one of claims 1-11.

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