Method and apparatus for controlling a prediction unit

Abstract

Aspects of the present disclosure relate to an apparatus including a prediction circuit having a plurality of prediction units, the plurality of prediction units including a plurality of types of prediction units. Each prediction unit is configured to perform a prediction of a corresponding type with respect to an operation to be performed by the apparatus. The shared prediction resource circuitry includes a shared prediction resource configurable to perform the type of prediction. The resource allocation circuitry is configured to determine an allocation of the shared prediction resource to one or more prediction units of the plurality of prediction units, and allocate the shared prediction resource in accordance with the determination.

Description

Background Art

[0001] The present technology relates to the field of prediction units associated with processing circuits. Such prediction units are used to predict upcoming processing to be performed by the processing circuits. This can significantly improve the performance of the processing circuits. For example, a prefetcher can predict instruction addresses or data addresses and fetch such instructions or data from a storage device before the processing flow reaches a point where the corresponding instructions and / or data are explicitly requested. The prefetched instructions and / or data are thus ready to be accessed, for example by being held in a short-term storage device (such as a cache) that is faster to access than a long-term but slower-access storage device (such as a memory). This improves performance because the prefetched instructions and / or data can be quickly accessed when requested without incurring the delay associated with fetching them from a long-term storage device.

[0002] Other types of prediction units may also be used, such as branch predictors that predict the outcome of branch instructions. In some systems, many types of predictors are used simultaneously.

[0003] Although predictors can significantly improve processing performance, they also incur overhead in terms of processing resources and power consumption. This effect is magnified when multiple types of predictors are implemented simultaneously. Therefore, there is a need for a way to increase the level of predictive functionality that can be provided while reducing its overall resource usage. Summary of the invention

[0004] At least some examples provide an apparatus comprising:

[0005] prediction circuitry comprising a plurality of prediction units, the plurality of prediction units comprising a plurality of types of prediction units, each prediction unit configured to perform a corresponding type of prediction regarding an operation to be performed by the apparatus;

[0006] shared prediction resource circuitry comprising a shared prediction resource configurable to perform predictions of the type described; and

[0007] A resource allocation circuit, the resource allocation circuit being configured to:

[0008] determining allocation of the shared prediction resource to one or more prediction units among the plurality of prediction units; and

[0009] The shared prediction resource is allocated based on the determination.

[0010] Another example provides a method comprising:

[0011] performing a plurality of types of predictions regarding operations to be performed, each type of prediction being performed by a corresponding prediction unit;

[0012] determining an allocation of a shared prediction resource to one or more prediction units of the plurality of prediction units, the shared prediction resource being configurable to perform each of the types of prediction; and

[0013] The shared prediction resource is allocated based on the determination.

[0014] Another example provides a non-transitory computer readable medium for storing a computer readable code for manufacturing an apparatus, the apparatus comprising:

[0015] prediction circuitry comprising a plurality of prediction units, the plurality of prediction units comprising a plurality of types of prediction units, each prediction unit configured to perform a corresponding type of prediction regarding an operation to be performed by the apparatus;

[0016] shared prediction resource circuitry comprising a shared prediction resource configurable to perform predictions of the type described; and

[0017] A resource allocation circuit, the resource allocation circuit being configured to:

[0018] determining allocation of the shared prediction resource to one or more prediction units among the plurality of prediction units; and

[0019] The shared prediction resource is allocated based on the determination.

[0020] Another example provides a computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising:

[0021] prediction logic implementing a plurality of prediction units, the plurality of prediction units comprising a plurality of types of prediction units, each prediction unit configured to perform a corresponding type of prediction regarding an operation to be performed within the instruction execution environment;

[0022] shared prediction resource logic comprising a shared prediction resource configurable to perform predictions of the type described; and

[0023] Resource allocation logic, which is configured to:

[0024] determining allocation of the shared prediction resource to one or more prediction units among the plurality of prediction units; and

[0025] The shared prediction resource is allocated based on the determination.

[0026] Further aspects, features and advantages of the present technology will be apparent from the following description of examples read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 An apparatus according to an example is schematically depicted.

[0028] FIG. 2A to FIG. 2C An example resource allocation to prediction units is depicted.

[0029] Figure 3A and Figure 3B An example method is depicted.

[0030] Figure 4 An example method is illustrated.

[0031] Figure 5 Systems according to examples are depicted.

[0032] Figure 6 An example method is shown.

[0033] Figure 7 An example method is shown.

[0034] Figure 8 Computer readable media according to examples are depicted.

[0035] Fig. 9 An example implementation by way of a simulator is depicted. DETAILED DESCRIPTION

[0036] In one example, a device (e.g., a processing device such as a central processing unit or a graphics processing unit) includes a prediction circuit having a plurality of prediction units. The prediction units are of various types, such that the prediction circuit includes multiple types of prediction units, each prediction unit being configured to perform a corresponding type of prediction about an operation to be performed by the device. The operations may be instructions, such as program instructions and / or hardware signals that direct the device to perform a processing action.

[0037] Those skilled in the art will appreciate that various types of prediction units may be implemented in this example. A non-limiting list of such prediction unit types is:

[0038] - a branch predictor, which predicts the outcome of branch instructions;

[0039] -Data prefetchers, which predict the data that subsequent instructions will act on;

[0040] - an instruction prefetcher, which predicts future instructions;

[0041] - A load or store coalescing predictor that predicts opportunities to group or coalesce accesses to the same memory granule in order to maximize utilization of available memory bandwidth;

[0042] - a congestion predictor that identifies bottlenecks in data transmission between functional units and / or processing units of the device to allow data to be re-routed accordingly;

[0043] - an execution cluster predictor that identifies which functional units are best suited to execute a particular instruction,

[0044] In order to improve efficiency and speed up the forwarding of results;

[0045] - an address conflict predictor, which predicts whether a data hazard will occur when a load overtakes a store during out-of-order instruction execution. That is, when loads are executed out of program order relative to stores, there is a possibility that a newer load from a given address will overtake an older store to the same address (causing a fault), and the address conflict predictor attempts to determine the likelihood of this sequence of events;

[0046] - A snoop predictor that predicts the likelihood of a memory consistency violation.

[0047] The apparatus also includes a shared prediction resource circuit, which includes a shared prediction resource that can be configured to perform the above-mentioned type of prediction. The shared resource is shared between the processing units and can be allocated to one or more such processing units at any given time. The shared prediction resource may include one or more storage units or memory units, such as registers and / or static random access memory (SRAM). The shared prediction resource may also include one or more processing resource units, such as lookup tables. These lookup tables can be general lookup tables that can be configured for use with multiple prediction unit types. The shared prediction resource may also include interconnection resources.

[0048] The device also includes a resource allocation circuit that can control the allocation of shared resources to the prediction units. The resource allocation circuit is therefore configured to determine the allocation of shared prediction resources to one or more prediction units in the plurality of prediction units. This allocation can be determined for the purpose of maximizing the overall performance improvement of the device (e.g., expressed as overall operation throughput). After determining the allocation, the resource allocation circuit allocates the shared prediction resources according to the determination.

[0049] This example therefore provides improved prediction performance by flexibly allocating shared prediction resources to multiple predictors, and thus improves overall processing performance. This is achieved at a lower resource cost than would be incurred without using shared prediction resources: in a comparative example in which all prediction resources are associated only with a specific prediction unit, a significantly larger overall increase in prediction resources would be required in order to give a similar overall performance improvement. This is because, for example, when a given predictor is not in use (or when the predictor is not operating at full capacity), the resources of the predictor will be idle. In contrast, this example allows such idle resources to be reallocated to different prediction units. This example also allows resources to be allocated to the prediction units to which they will be most efficiently utilized. For example, as described in more detail below, different prediction units may have different degrees of impact on overall processing performance depending on the nature of the instruction region currently being processed. This example allows processing resources to be flexibly allocated to the prediction units that are most efficient at a given time, thereby maximizing the performance improvement of a given amount of resources.

[0050] In an example, the resource allocation circuit performs the above determination by evaluating the current sensitivity of one or more given prediction units to changes in the shared prediction resources allocated to the one or more given prediction units. The resource allocation circuit then determines an updated allocation based on the determination. This provides an efficient way to allocate shared resources to the prediction units that will benefit most from the additional resources: if resources are allocated to the prediction units that are currently most sensitive to the provision of additional resources, the overall impact on processing performance can be higher.

[0051] For example, the resource allocation circuitry may determine that one or more prediction units in a given prediction unit are sensitive to changes in the allocated shared prediction resources relative to one or more prediction units in other prediction units. The resource allocation circuitry may then preferentially allocate the shared prediction resources to the relatively sensitive prediction units. This effectively allocates the shared resources to the units that will gain the most benefit.

[0052] In some examples, the resource allocation circuit is configured to perform a feedback loop that includes repeatedly performing the above-described determination of updated allocations. For example, the allocation of shared resources between prediction units may be adjusted, and changes in overall performance may be evaluated. By repeatedly performing these steps, prediction units that are relatively sensitive to the provision of shared resources may be identified. The shared resources may then be allocated to the prediction units that can obtain the greatest benefit and result in the greatest improvement in overall performance.

[0053] As an example of such a feedback loop, the shared prediction resources allocated to one or more predictors may be modified. The change in prediction performance associated with the modification may be evaluated. Further modifications to the shared prediction resource allocation may then be performed based on the results of the evaluation.

[0054] As described above, the sensitivity of a given prediction unit to changes in shared prediction resources can be assessed by measuring the prediction performance associated with at least the given prediction unit. This may in particular be an assessment of the prediction accuracy of that prediction unit: assessing all prediction units in this way may provide a fine-grained assessment of per-prediction unit performance. Alternatively, prediction performance may be measured by measuring the overall rate at which instructions are processed by the device. This allows resources to be allocated to the prediction units that will result in the greatest improvement in overall processing performance, without the need to track the performance of each individual prediction unit individually. As a result, overall performance (which may be more important than the performance of individual prediction units in determining the optimal resource allocation) is efficiently maximized.

[0055] Alternatively or additionally, the improvement in predicted performance may be determined by an increase in data processing throughput, an increase in processing performance, and / or an increase in the rate at which instructions are executed. These all provide an effective way to quantify the overall performance improvement associated with a given allocation of shared resources.

[0056] In an example, the above-mentioned prediction performance can be quantified by one or more prediction performance values ​​maintained by or accessible to the resource allocation circuit. For example, such a value can express the total rate of instruction processing, or a count of the number of instructions processed in a given time period. These provide an effective way to track prediction performance.

[0057] In some such examples, the resource allocation circuitry is configured to detect that processing of an operation has entered a new phase, such as a new code region. This may be determined, for example, based on a hint within the operation (e.g., a sequence of processing instructions may include a hint that a new code region will be entered) and / or a change in an address space identifier. In response to entering the new code region, the resource allocation circuitry may reset at least one of the predicted performance values ​​to a default value. In this way, the predicted performance may be measured specifically within a given region.

[0058] The resource allocation circuit may be configured to store a given determined shared prediction resource allocation associated with a given code region. For example, this may be an allocation that has been determined to provide a beneficial increase in the overall performance of the code region. The resource allocation circuit may then allocate shared prediction resources according to the stored allocation in response to determining that processing of the operation has re-entered the given code region. In this way, previously determined shared resource allocations may be stored for one or more code regions in preparation for reuse when re-entering the given code region. This may improve overall performance relative to a comparison device in which performance is always determined instantly without reference to previous results. In some examples, the previously stored allocation is treated as an initial allocation for the newly re-entered code region, after which an iterative process of refining the allocation is performed as described above.

[0059] In some examples, an arbitrary allocation of shared resources to prediction unit combinations may be performed. In other examples, the resource allocation circuit is configured to maintain a plurality of predefined shared prediction resource allocations. Such resource allocation circuitry may then perform said determination of the allocation by selecting one of the predefined shared prediction resource allocations. This may reduce the processing overhead associated with the allocation of shared resources by effectively having a plurality of preset configurations from which to choose. This is at the expense of reduced flexibility in the number of possible combinations of shared resource allocations.

[0060] In one example, resource allocation is configured to allocate shared prediction resources to a first prediction unit in chunks of a first size, and to allocate shared prediction resources to a second prediction unit in chunks of a second size. This allows the allocation to take into account different requirements of different prediction units. For example, a first prediction unit may utilize SRAM chunks of size N, while a second prediction unit may utilize SRAM chunks of size 2N. By allocating shared SRAM to a first prediction unit in chunks of size N, and to a second prediction unit in chunks of size 2N, the shared SRAM may be efficiently allocated such that no prediction unit is left with unusable resources (as might occur, for example, if the second prediction unit were allocated SRAM chunks of size N).

[0061] Examples of the present disclosure will now be described with reference to the accompanying drawings.

[0062] Figure 1 An apparatus 100 according to an example of the present disclosure is schematically shown. The apparatus comprises a plurality of prediction units 105a, 105b, 105c, 105d. Each of these prediction units makes a different type of prediction about a processing operation (e.g., instruction) being executed. For example, unit 105a may be a branch predictor that predicts the outcome of a branch instruction, and unit 105b may be a data prefetcher that predicts data before it is requested in an instruction.

[0063] The prediction units 105a-d receive prediction inputs. These inputs include information about the processing of the operation, and the prediction units 105a-d make their predictions based on this information. For example, the data prefetcher 105b may receive the data address requested by the instruction, so that the prefetcher 105b may attempt to detect a pattern of data accesses and extrapolate the pattern into the future to make predictions about future data accesses.

[0064] Based on the prediction outputs, the prediction units 105a-d make predictions and output corresponding prediction outputs.

[0065] Each prediction unit 105a-d may have its own dedicated prediction resources for its individual use. Prediction units 105a-d also have access to shared prediction resources 110. Resource allocator 115 controls the allocation of these shared resources to prediction units 105a-105d with the goal of improving overall system performance.

[0066] The sensitivity of overall system performance to a given resource allocation depends on the processing conditions at a given time. As an example, during the processing of code that includes a high density of branch instructions (e.g., software such as games that involve a high degree of user input), the branch predictor will likely be particularly sensitive to changes in resource allocation. Therefore, an increase in resources will be expected to result in a significant improvement in overall system performance. Conversely, if the current code area has a low density of branch instructions, the sensitivity will be low: even if an increase in resources will improve the performance of the branch predictor, the low density of branch instructions means that this will not have a large impact on overall system performance.

[0067] Thus, in general, while the accuracy of prediction units 105a-d generally increases as more resources are allocated to them, the impact of improving the accuracy of each predictor on overall system performance may not be equal. For example, improving the accuracy of unit 105a by 10% may require 50% more resources and only improve performance by 2%, while improving the accuracy of prediction unit 105b by 10% may require 20% more resources and improve performance by 8%. In this case, it is advantageous to sacrifice the resources allocated to unit 105a in favor of increasing the resources allocated to prediction unit 105b. The performance improvement numbers observed as a result of changes to the predictor circuits are rarely static and vary not only between applications but also between stages of an application.

[0068] FIG. 2A to FIG. 2C Three potential allocations of the shared prediction resource 110 to the prediction units 105a-d are illustrated.

[0069] Figure 2A A configuration is shown in which the shared resource 110 is shared equally between prediction units 105a-d: a first quarter 110a of the shared resource 110 is allocated to unit 105a, a second quarter 110b is allocated to unit 105b, a third quarter 110c is allocated to unit 105c, and a fourth quarter 110d is allocated to unit 105d. This allocation may be a default allocation that is implemented when the resource allocator 115 has no reason to prioritize a particular prediction unit 105a-105d. For example, this allocation may be used when no particular prediction unit 105a-105d would benefit disproportionately from the additional resources.

[0070] Figure 2BA configuration is shown in which all 110a of the shared resource 110a is allocated to prediction unit 105a and none of the shared resource is allocated to units 105b-d. This allocation may be used, for example, when processing conditions are such that an increase in the resources allocated to prediction unit 105a (relative to units 105b-d) would result in a disproportionately large improvement in overall system performance. Thus, allocating all 110a of the shared resource 110 to unit 105a results in higher overall system performance than would be observed if the shared resource 110 were allocated more evenly.

[0071] Figure 2C A hybrid configuration is shown in which a relatively large portion 110a of shared resources 110 is allocated to prediction unit 105a, no shared resources 110 are allocated to unit 105b, a small portion 110c is allocated to unit 105c, and a medium portion 110d is allocated to portion 105d. This allocation may be implemented, for example, because resource allocator 115 has determined that this is the best configuration for maximizing overall system performance. For example, processing conditions may be such that prediction unit 105a gains a relatively large benefit from increased resources, but there are diminishing returns beyond a certain point, such that sharing some of shared resources 110 with units 105c and 105d may achieve better performance, such as with the use of Figure 2B The configuration is opposite.

[0072] In one example, to determine the best allocation of shared resources 110 to prediction units 105a-105d, resource allocator 115 utilizes a runtime learning engine (RLE) that finds the relationship between changes in resources allocated to each prediction unit 105a-105d and corresponding changes in overall processing performance. By finding such performance gradients for each prediction unit 105a-105d at a given time, resource allocator 115 can then allocate more resources 110 to prediction units with high performance gradients and allocate fewer resources to prediction units with low performance gradients.

[0073] Figure 3A and Figure 3B A particular manner in which the resource allocator 115 may evaluate the performance impact of changes in the allocation of the shared resources 110 to the prediction units 105a-d is shown.

[0074] exist Figure 3A , the method starts by modifying 305 the allocation of a shared resource. For example, this may be a perturbation of a previous allocation.

[0075] Then, at a later time, resource allocator 115 evaluates 310 the performance changes due to the allocation modification.

[0076] Flow then returns to block 305 and the process is iteratively repeated.Over time, the resource allocator 115 learns which prediction units 105a-d have a particularly large impact on overall processing performance and can optimize allocations accordingly.

[0077] Figure 3B Shows Figure 3A A more detailed example of the method is given in Figure 3B In the modification step 305, the amount of resources allocated to the first group of units is increased 305a, and the amount of resources allocated to the second group of units is decreased 305b. Then, the evaluation step 310 includes an evaluation 310a of the extent to which the performance has been improved or degraded since the allocation modification 310.

[0078] In some examples, the process can be repeated for each epoch or stage of the program. An epoch or stage is a time period of reasonable size during which it can be assumed that the behavior of the program is relatively more deterministic. They can be, for example, different code regions, which can be identified by hint instructions provided by the programmer or compiler. It is usually more difficult to find a deterministic relationship between the change in resource allocation and the overall performance over a very long period, and on the other hand, very short periods may not enable the collection of enough data to determine the performance gradient. Performance tracking can be reset at the end of a given stage / epoch / region. The length of the stage / epoch / region can be optimized over time by the resource allocator 115 in the same manner as the allocation value itself.

[0079] Figure 4 Depicted are example methods by which performance may be tracked across multiple code regions and used to inform allocation of shared resources across multiple code regions.

[0080] The method begins at block 405 when a new code region is entered.

[0081] At block 410, resource allocator 415 determines whether it has previously stored a shared resource allocation for the code region (e.g., in a previous iteration of the code region). If so, the previously stored allocation is loaded at block 415a. Otherwise, a default allocation is loaded at block 415b. For example, the default allocation may be an equal allocation to each prediction unit 405a-d (e.g., Figure 2A ).

[0082] At block 420, overall processing performance is tracked over a period of time, and performance changes are evaluated at block 425. At step 430, a determination is made as to whether the end of the region has been reached. If not, the allocation is modified at block 435 based on the evaluated performance (e.g., as described above with respect to Figure 3A and Figure 3BFlow then returns to block 420, and resource allocator 115 continues to track performance.

[0083] If the end of the region has been reached, the stored allocation is updated at block 440. For example, the currently determined best allocation may replace the previously stored allocation, ready for reuse if the same code region is re-entered. Performance may thus be optimized over time.

[0084] The flow returns to block 405 where a new code region is entered.

[0085] Figure 5 A system according to an example is depicted, which may implement the method described above.

[0086] The system comprises a processor 505 which executes processing instructions retrieved from a memory 507. These instructions define the processing of data, which are also retrieved from the memory 507. The processor comprises prediction units 510a, 510b, 510c which are arranged in a manner similar to Figure 1 Each prediction unit 510a-c has its own baseline prediction resources that are sufficient to provide a baseline level of performance. The prediction units 510a-c also have access to shared prediction resources 515 that function in the same manner as the shared resources 110 described above.

[0087] Performance counters 520 are maintained that track the processing and / or prediction performance of the processor 505 and the prediction units 510a-c. For example, one of these counters may be a count of the number or rate of processing instructions executed in the current code region.

[0088] Performance counters 520 are read by a runtime learning engine (RLE) 525 which determines over time performance gradients 530 associated with predictors 510a-c. RLE 525 thus learns which prediction units 510a-c should be preferentially allocated shared resources 515 in order to optimize overall processing performance.

[0089] RLE 525 passes this learned information to mapper 535. Based on the learned information and configuration information from configuration storage 540 (which may, for example, define the size of the functional blocks to which shared resources 515 may be allocated), mapper 535 directs the allocation of shared resources 515 to each prediction unit 510a-c.

[0090] Figure 5 The system can therefore be Figure 1 The apparatus functions in the same manner as , where the RLE 525 and the mapper 535 correspond to the resource allocator 115.

[0091] Figure 6 Depicted is a method according to an example, which may be performed by Figure 5 system implementation.

[0092] At block 605, a new epoch (eg, code region or phase) is started. Then, at block 610, performance counters 520 are reset to their default values ​​(eg, zero).

[0093] At block 615 , allocation of the shared resource 515 to the prediction units 510 a - c is selectively adjusted.

[0094] At block 620, an estimate is made of the change in performance as a result of the selective adjustment. For example, this may be based on tracking process performance over a period of time.

[0095] At block 625 , a performance gradient 530 is calculated for each prediction unit 510 a - c .

[0096] At block 630 , the prediction unit with the highest performance gradient 530 is selected.

[0097] At block 635 , the mapper 535 allocates more of the shared resources 515 to the selected prediction unit (and reduces allocations to other prediction units).

[0098] At block 640, the system operates with this allocation for the remainder of the epoch. Flow then returns to block 605 and enters a new epoch.

[0099] Figure 6 The method thus provides an effective way to improve system performance by allocating shared resources to where they are most useful.

[0100] Figure 7 Describes a method according to an example, which can be, for example, Figure 1 Implementation of the device.

[0101] At block 705, multiple types of predictions are performed regarding instructions to be executed. Each type of prediction is performed by a corresponding prediction unit 105a-d.

[0102] At block 710, an allocation of the shared prediction resource 110 to one or more prediction units of the plurality of prediction units 105a-d is determined. The shared prediction resource 110 can be configured to perform each of the types of predictions.

[0103] At block 715 , the shared prediction resource 110 is allocated based on the determination.

[0104] The concepts described herein may be embodied in computer readable code for making devices embodying the described concepts. For example, the computer readable code may be used at one or more stages of the semiconductor design and fabrication process, including the electronic design automation (EDA) stage, to fabricate integrated circuits including devices embodying the concepts. The computer readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0105] For example, computer readable code for making an apparatus embodying the concepts described herein may be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register transfer level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define an HDL representation of one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. The computer readable code may provide definitions of concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of the concepts that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0106] Additionally or alternatively, the computer readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer readable representations of integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representation to generate definitions for making devices embodying the present invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer readable code to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing concepts before making integrated circuits, or the FPGA may be deployed directly in a product.

[0107] The computer readable code may include a mixture of code representations for making a device, such as a mixture including one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and fabrication process to make a device embodying the invention. Alternatively or additionally, concepts may be defined in a combination of a computer readable definition used in a semiconductor design and fabrication process to make a device and computer readable code defining instructions to be executed by the defined device once fabricated.

[0108] Such computer readable code may be provided in any known transient computer readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer readable medium such as a semiconductor, magnetic disk, or optical disk. An integrated circuit fabricated using the computer readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept individually or collectively.

[0109] Figure 8 Such a computer readable medium 805 is schematically depicted, and includes a method for manufacturing a device as described above (e.g., Figure 1 or Figure 5 810 of a device having a plurality of components (shown in FIG. 8 ).

[0110] Fig. 9 The simulator that can be used is illustrated. Although the previously described embodiments implement the present invention in terms of the apparatus and method for operating the specific processing hardware supporting the technology involved, an instruction execution environment according to the embodiments described herein can also be provided, which is implemented by using a computer program. Such computer programs are generally referred to as simulators, to a certain extent because such computer programs provide a software-based specific implementation of the hardware architecture. The types of simulator computer programs include emulators, virtual machines, models and binary converters, which include dynamic binary converters. Typically, the simulator is specifically implemented and can be run on a host processor 905, which optionally runs a host operating system 910 and supports simulator programs 915. In some arrangements, there may be multiple simulation layers between the hardware and the provided instruction execution environment and / or a plurality of different instruction execution environments provided on the same host processor. Historically, a powerful processor is required to provide a simulator that is executed at a reasonable speed, but this method may be reasonable in certain circumstances, such as when it is desired to run another processor local code for compatibility or reuse reasons. For example, the simulator is specifically implemented to provide additional functions that the host processor hardware does not support to the instruction execution environment, or to provide an instruction execution environment that is generally associated with different hardware architectures. An overview of simulation is given in: "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0111] To the extent that embodiments have been previously described with reference to specific hardware constructs or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructs or features. For example, specific circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. In arrangements where one or more of the hardware elements referenced in previously described embodiments are present on host hardware (e.g., host processor 905), some simulated embodiments may utilize host hardware, where appropriate.

[0112] The simulator program 915 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 920 (which may include an application, an operating system, and a hypervisor) that is the same as the interface of the hardware architecture modeled by the simulator program 915. Thus, the simulator program 915 may be used to execute program instructions of the target code 920 from within the instruction execution environment so that a host computer 905 that does not actually have the hardware features of the device 2 discussed above can emulate these features.

[0113] Therefore, an apparatus and method are provided for improving the performance of a processing apparatus, in particular a processing apparatus having multiple prediction units.

[0114] As will be seen from the above description, the techniques described herein provide many significant benefits. Specifically, resource allocation may be optimized to maximize overall processing performance.

[0115] In this application, the words "configured to..." are used to mean that elements of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way in order to provide the defined operation.

[0116] Although exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be effected therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims

1. A device, comprising: prediction circuitry comprising a plurality of prediction units, the plurality of prediction units comprising a plurality of types of prediction units, each prediction unit configured to perform a corresponding type of prediction regarding an operation to be performed by the apparatus; shared prediction resource circuitry comprising a shared prediction resource configurable to perform said type of prediction; and A resource allocation circuit, wherein the resource allocation circuit is configured to: determining allocation of the shared prediction resource to one or more prediction units among the plurality of prediction units; and The shared prediction resource is allocated according to the determination.

2. The apparatus according to claim 1, wherein the plurality of types of prediction units include at least two of the following: Branch predictor; Data prefetcher; Instruction prefetcher; Load or store merge predictors; Congestion predictor; Execute the cluster predictor; address conflict predictor; and Peep the predictor.

3. The apparatus according to claim 1 or claim 2, wherein the resource allocation circuit is configured to perform the determination by: evaluating a current sensitivity of one or more given prediction units to a change in a shared prediction resource allocated to the one or more given prediction units; and An updated allocation is determined based on the evaluation.

4. The apparatus of claim 3, wherein the resource allocation circuit is configured to determine the updated allocation by: determining that one or more of the given prediction units are sensitive to a change in the allocated shared prediction resources relative to one or more of the other prediction units; and Additional shared prediction resources are preferentially allocated to the relatively sensitive prediction units.

5. The apparatus of claim 4, wherein the resource allocation circuit is configured to perform a feedback loop comprising repeatedly performing the determination of an updated allocation.

6. The apparatus of claim 5, wherein the feedback loop comprises iteratively: modifying the shared prediction resource allocated to one or more of the predictors; evaluating a change in predicted performance associated with the modification; and Further modification of the shared predicted resource allocation is performed based on the evaluation.

7. The apparatus of any one of claims 3 to 6, wherein the assessing the sensitivity of a given prediction unit to changes in a shared prediction resource comprises measuring a prediction performance associated with at least the given prediction unit.

8. The apparatus of claim 7, wherein measuring prediction performance comprises measuring an overall rate at which instructions are processed by the apparatus.

9. An apparatus according to claim 7 or claim 8, wherein the resource allocation circuit is configured to determine the improvement in predicted performance in response to measuring at least one of: Increased data processing throughput; Improved processing performance; and The rate at which instructions are processed increases.

10. The apparatus of claim 7, wherein measuring prediction performance comprises tracking prediction accuracy of the given prediction unit.

11. The apparatus of any one of claims 3 to 10, wherein the resource allocation circuit is configured to measure the predicted performance by maintaining at least one predicted performance value.

12. The apparatus according to claim 11, wherein the resource allocation circuit is configured to: detecting that processing of the operation has entered a new code region; and In response to detecting the new code region, at least one of the predicted performance values ​​is reset to a default value.

13. The apparatus of claim 12, wherein the resource allocation circuit is configured to detect the new code region based on at least one of: Prompts within said operations; and Change of address space identifier.

14. The apparatus according to claim 12 or claim 13, wherein the resource allocation circuit is configured to: storing a given determined shared predicted resource allocation associated with a given code region; and In response to determining that processing of the operation has re-entered the given code region, the shared prediction resource is allocated according to the stored allocation.

15. An apparatus according to any preceding claim, wherein the resource allocation circuit is configured to: maintaining a plurality of predefined shared forecast resource allocations; and Said determination of an allocation is performed by selecting one of said predefined shared predicted resource allocations.

16. An apparatus according to any preceding claim, wherein the resource allocation circuit is configured to: allocating the shared prediction resource to a first prediction unit among the plurality of prediction units in chunks of a first size; and The shared prediction resource is allocated to a second prediction unit of the plurality of prediction units in chunks of a second size, the second size being different from the first size.

17. An apparatus according to any preceding claim, wherein the shared prediction resource circuit comprises at least one of: one or more storage units; and One or more processing resource units.

18. The apparatus of claim 16, wherein: The one or more storage units include one or more memory units; and / or The one or more processing resource units include at least one general purpose lookup table unit, each of the general purpose lookup table units being configurable for use by each of the plurality of prediction units.

19. A method comprising: performing a plurality of types of predictions regarding operations to be performed, each type of prediction being performed by a corresponding prediction unit; determining an allocation of a shared prediction resource to one or more prediction units of the plurality of prediction units, the shared prediction resource being configurable to perform each of the types of prediction; as well as The shared prediction resource is allocated according to the determination.

20. A non-transitory computer readable medium storing a computer readable code for manufacturing an apparatus, the apparatus comprising: prediction circuitry comprising a plurality of prediction units, the plurality of prediction units comprising a plurality of types of prediction units, each prediction unit configured to perform a corresponding type of prediction regarding an operation to be performed by the apparatus; shared prediction resource circuitry comprising a shared prediction resource configurable to perform said type of prediction; and A resource allocation circuit, wherein the resource allocation circuit is configured to: determining allocation of the shared prediction resource to one or more prediction units among the plurality of prediction units; and The shared prediction resource is allocated according to the determination.

21. A computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising: prediction logic implementing a plurality of prediction units, the plurality of prediction units comprising a plurality of types of prediction units, each prediction unit configured to perform a corresponding type of prediction regarding an operation to be performed within the instruction execution environment; shared prediction resource logic, the shared prediction resource logic comprising a shared prediction resource configurable to perform the type of prediction; and Resource allocation logic, the resource allocation logic being configured to: determining allocation of the shared prediction resource to one or more prediction units among the plurality of prediction units; and The shared prediction resource is allocated according to the determination.

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