Array substrate, manufacturing method and display device

Abstract

The invention provides an array substrate, a manufacturing method and a display device. The array substrate comprises a driving circuit arranged on a substrate body, and the driving circuit comprises a pull-up node control circuit, a first pull-down node control circuit and an output circuit. The pull-up node control circuit controls the potential of a pull-up node (PU); the first pull-down node control circuit is used for controlling first control voltage to be written into a first pull-down node (PD1); the output circuit is used for controlling a driving signal output end to output a driving signal under the control of the potential of the pull-up node (PU); the array substrate further comprises a first conductive part arranged on the substrate; the first conductive portion is electrically connected to a first control voltage line (VDDO). The conversion between the 17T1C drive circuit and the 21T1C drive circuit can be realized only by adding one mask, so that the product compatibility is effectively improved, and meanwhile, the mask cost is saved.

Description

Array substrate, manufacturing method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method and a display device. Background Art

[0002] In the related art, when switching between a 17T1C driving circuit and a 21T1C driving circuit, since the structure of the 17T1C driving circuit is different from that of the 21T1C driving circuit, a large number of masks need to be changed, resulting in high mask costs when improving product compatibility.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising a driving circuit disposed on a base substrate, the driving circuit comprising a pull-up node control circuit, a first pull-down node control circuit, and an output circuit;

[0005] The pull-up node control circuit is electrically connected to the pull-up node and is used to control the potential of the pull-up node;

[0006] The first pull-down node control circuit is electrically connected to the first control voltage line and the first pull-down node respectively, and is used to control the first control voltage provided by the first control voltage line to be written into the first pull-down node;

[0007] The output circuit is electrically connected to the pull-up node and the drive signal output terminal respectively, and is used to control the drive signal output terminal to output the drive signal under the control of the potential of the pull-up node;

[0008] The array substrate further includes a first conductive portion provided on the base substrate;

[0009] The first conductive portion is electrically connected to the first control voltage line.

[0010] Optionally, the shortest distance between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first control voltage line on the substrate is greater than or equal to 4 um and less than or equal to 12 um.

[0011] Optionally, the first conductive portion is composed of a first gate pattern; or, the first conductive portion is composed of a first gate pattern and a first active pattern;

[0012] The first gate pattern is electrically connected to a first control voltage line.

[0013] Optionally, the first pull-down node control circuit includes a second transistor;

[0014] A gate of the second transistor is electrically connected to the first connection structure, a first electrode of the second transistor is electrically connected to the first control voltage line, and a second electrode of the second transistor is electrically connected to the first pull-down node.

[0015] Optionally, the first connection structure is electrically connected to the first control voltage line.

[0016] Optionally, the first pull-down node control circuit is further configured to write a first voltage signal provided by a first voltage line into the first pull-down node;

[0017] The array substrate further includes a second conductive portion provided on the base substrate;

[0018] The second conductive portion is electrically connected to the pull-up node.

[0019] Optionally, the second conductive portion is composed of a third gate pattern; or, the second conductive portion is composed of a third gate pattern and a third active pattern;

[0020] The third gate pattern is electrically connected to the pull-up node.

[0021] Optionally, the shortest distance between an orthographic projection of the second conductive portion on the substrate and an orthographic projection of the first control voltage line on the substrate is greater than or equal to 4 μm;

[0022] The shortest distance between an orthographic projection of the second conductive portion on the base substrate and an orthographic projection of the first voltage line on the base substrate is greater than or equal to 4 um and less than or equal to 12 um.

[0023] Optionally, the first pull-down node control circuit includes a fourth transistor;

[0024] A gate of the fourth transistor is electrically connected to the pull-up node, a first electrode of the fourth transistor is electrically connected to the first pull-down node, and a second electrode of the fourth transistor is electrically connected to the first voltage line.

[0025] Optionally, the driving circuit further includes a second pull-down node control circuit;

[0026] The second pull-down node control circuit is electrically connected to the second control voltage line and the second pull-down node respectively, and is used to control the writing of the second control voltage provided by the second control voltage line into the second pull-down node;

[0027] The array substrate further includes a third conductive portion provided on the base substrate;

[0028] The third conductive portion is electrically connected to the second control voltage line.

[0029] Optionally, the third conductive portion is composed of a fifth gate pattern; or, the third conductive portion is composed of a fifth gate pattern and a fifth active pattern.

[0030] Optionally, the shortest distance between an orthographic projection of the third conductive portion on the substrate and an orthographic projection of the second control voltage line on the substrate is greater than or equal to 4 um and less than or equal to 12 um.

[0031] Optionally, the second pull-down node control circuit includes a sixth transistor;

[0032] A gate of the sixth transistor is electrically connected to the second connection structure, a first electrode of the sixth transistor is electrically connected to the second control voltage line, and a second electrode of the sixth transistor is electrically connected to the second pull-down node.

[0033] Optionally, the second connection structure is electrically connected to a second control voltage line.

[0034] Optionally, the second pull-down node control circuit is further configured to write the first voltage signal provided by the first voltage line into the second pull-down node;

[0035] The array substrate further includes a fourth conductive portion provided on the base substrate;

[0036] The fourth conductive portion is electrically connected to the pull-up node.

[0037] Optionally, the fourth conductive portion is composed of the seventh gate pattern; or, the fourth conductive portion is composed of the seventh gate pattern and the seventh active pattern;

[0038] The seventh gate pattern is electrically connected to the pull-up node.

[0039] Optionally, the shortest distance between the orthographic projection of the fourth conductive portion on the substrate and the orthographic projection of the second control voltage line on the substrate is greater than or equal to 4um, and the shortest distance between the orthographic projection of the fourth conductive portion on the substrate and the orthographic projection of the first voltage line on the substrate is greater than or equal to 4um and less than or equal to 12um.

[0040] Optionally, the second pull-down node control circuit includes an eighth transistor;

[0041] A gate of the eighth transistor is electrically connected to the pull-up node, a first electrode of the eighth transistor is electrically connected to the second pull-down node, and a second electrode of the eighth transistor is electrically connected to the first voltage line.

[0042] Optionally, the array substrate further includes a first source-drain metal pattern and a third source-drain metal pattern provided on the base substrate;

[0043] The first source-drain metal pattern includes a first electrode of the first transistor and a second electrode of the first transistor;

[0044] A first electrode of the first transistor is electrically connected to the first control voltage line, and a second electrode of the first transistor is electrically connected to the first connection structure;

[0045] An orthographic projection of at least a portion of the first electrode of the first transistor on the substrate overlaps with an orthographic projection of the first conductive portion on the substrate, and an orthographic projection of at least a portion of the second electrode of the first transistor on the substrate overlaps with an orthographic projection of the first conductive portion on the substrate;

[0046] The third source-drain metal pattern includes a first electrode of a third transistor and a second electrode of the third transistor;

[0047] A first electrode of the third transistor is electrically connected to the first connection structure, and a second electrode of the third transistor is electrically connected to the first voltage line;

[0048] The orthographic projection of at least part of the first electrode of the third transistor on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the third transistor on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate.

[0049] Optionally, the array substrate further includes a fifth source-drain metal pattern provided on the base substrate; the array substrate further includes a seventh source-drain metal pattern provided on the base substrate;

[0050] The fifth source-drain metal pattern includes a first electrode of a fifth transistor and a second electrode of the fifth transistor;

[0051] A first electrode of the fifth transistor is electrically connected to the second control voltage line, and a second electrode of the fifth transistor is electrically connected to the second connection structure;

[0052] An orthographic projection of at least a portion of the first electrode of the fifth transistor on the substrate overlaps with an orthographic projection of the third conductive portion on the substrate, and an orthographic projection of at least a portion of the second electrode of the fifth transistor on the substrate overlaps with an orthographic projection of the third conductive portion on the substrate;

[0053] The seventh source-drain metal pattern includes a first electrode of a seventh transistor and a second electrode of the seventh transistor;

[0054] A first electrode of the seventh transistor is electrically connected to the second connection structure, and a second electrode of the seventh transistor is electrically connected to the first voltage line;

[0055] The orthographic projection of at least part of the first electrode of the seventh transistor on the substrate overlaps with the orthographic projection of the fourth conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the seventh transistor on the substrate overlaps with the orthographic projection of the fourth conductive portion on the substrate.

[0056] Optionally, the pull-up node control circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0057] The gate of the ninth transistor is electrically connected to the first input terminal, the first electrode of the ninth transistor is electrically connected to the second input terminal, and the second electrode of the ninth transistor is electrically connected to the pull-up node;

[0058] The gate of the tenth transistor is electrically connected to the reset terminal, the first electrode of the tenth transistor is electrically connected to the pull-up node, and the second electrode of the tenth transistor is electrically connected to the first voltage line;

[0059] The gate of the eleventh transistor is electrically connected to the starting voltage line, the first electrode of the eleventh transistor is electrically connected to the pull-up node, and the second electrode of the eleventh transistor is electrically connected to the first voltage line;

[0060] The gate of the twelfth transistor is electrically connected to the first pull-down node, the first electrode of the twelfth transistor is electrically connected to the pull-up node, and the second electrode of the twelfth transistor is electrically connected to the first voltage line;

[0061] A gate of the thirteenth transistor is electrically connected to the second pull-down node, a first electrode of the twelfth transistor is electrically connected to the pull-up node, and a second electrode of the twelfth transistor is electrically connected to the first voltage line.

[0062] Optionally, the driving circuit further includes a first pull-down reset circuit and a second pull-down reset circuit; the first pull-down reset circuit includes a fourteenth transistor; the second pull-down reset circuit includes a fifteenth transistor;

[0063] The gate of the fourteenth transistor is electrically connected to the first input terminal, the first electrode of the fourteenth transistor is electrically connected to the first pull-down node, and the second electrode of the fourteenth transistor is electrically connected to the first voltage line;

[0064] A gate of the fifteenth transistor is electrically connected to the first input terminal, a first electrode of the fifteenth transistor is electrically connected to the second pull-down node, and a second electrode of the fourteenth transistor is electrically connected to the first voltage line.

[0065] Optionally, the output circuit includes a sixteenth transistor; a gate of the sixteenth transistor is electrically connected to the pull-up node, a first electrode of the sixteenth transistor is electrically connected to the clock signal line, and a second electrode of the sixteenth transistor is electrically connected to the drive signal output terminal;

[0066] The first electrode of the ninth transistor includes N first electrode portions, and the second electrode of the ninth transistor includes N second electrode portions;

[0067] The first electrode of the sixteenth transistor includes M first electrode portions, and the second electrode of the sixteenth transistor includes M second electrode portions;

[0068] The nth first electrode portion of the ninth transistor and the nth second electrode portion of the ninth transistor are provided in the nth first source-drain region;

[0069] The m-th first electrode portion of the sixteenth transistor and the m-th second electrode portion of the sixteenth transistor are provided in the m-th second source-drain region;

[0070] N and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M.

[0071] Optionally, the active pattern included in the transistor in the driving circuit includes at least one strip-shaped active pattern portion; or,

[0072] The transistor in the driving circuit includes an active pattern that is a block-shaped active pattern.

[0073] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing an array substrate, for manufacturing the above-mentioned array substrate, the method for manufacturing the array substrate comprising:

[0074] Fabricating a pull-up node control circuit, a first pull-down node control circuit, and an output circuit on a base substrate;

[0075] A first conductive portion and a first control voltage line are manufactured on a base substrate, and the first conductive portion is configured to be electrically connected to the first control voltage line.

[0076] Optionally, the step of manufacturing a first conductive portion and a first control voltage line on the base substrate and setting the first conductive portion to be electrically connected to the first control voltage line includes:

[0077] Fabricating a first metal layer on a base substrate, and patterning the first metal layer to form a first gate pattern, wherein the first gate pattern includes the first conductive portion;

[0078] forming a second metal layer on a side of the first metal layer away from the base substrate, and performing a patterning process on the second metal layer using a first mask to form a first control voltage line;

[0079] The first gate pattern is set to be electrically connected to the first control voltage line, and the first conductive portion and the second metal layer do not overlap in a direction perpendicular to the base substrate.

[0080] Optionally, the step of manufacturing a first conductive portion and a first control voltage line on the base substrate and setting the first conductive portion to be electrically connected to the first control voltage line includes:

[0081] Fabricating a first metal layer on a base substrate, and patterning the first metal layer to form a first gate pattern, wherein the first gate pattern includes the first conductive portion;

[0082] A second metal layer is formed on a side of the first metal layer away from the base substrate, and a second mask is used to perform a composition process on the second metal layer to form a first control voltage line, and a first electrode of the first transistor and a second electrode of the first transistor are formed, wherein the orthographic projection of the first electrode on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the second electrode on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate.

[0083] Optionally, the method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes: forming a conductive layer on a side of the second metal layer away from the base substrate, and patterning the conductive layer to form a first connection structure;

[0084] Setting a first electrode of the first transistor to be electrically connected to a first control voltage line, and setting a second electrode of the first transistor to be electrically connected to the first connection structure;

[0085] The orthographic projection of at least part of the first electrode of the first transistor on the substrate is set to overlap with the orthographic projection of the first conductive part on the substrate, and the orthographic projection of at least part of the second electrode of the first transistor on the substrate is set to overlap with the orthographic projection of the first conductive part on the substrate.

[0086] Optionally, the method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0087] performing a patterning process on the first metal layer to form a third gate pattern included in the second conductive portion;

[0088] The third gate pattern is disposed to be electrically connected to the pull-up node.

[0089] Optionally, the method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0090] performing a patterning process on the second metal layer to form a first voltage line, a first electrode of the third transistor, and a second electrode of the third transistor;

[0091] Disposing a first electrode of the third transistor to be electrically connected to the first connection structure, and disposing a second electrode of the third transistor to be electrically connected to the first voltage line;

[0092] The orthographic projection of at least part of the first electrode of the third transistor on the substrate is set to overlap with the orthographic projection of the second conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the third transistor on the substrate is set to overlap with the orthographic projection of the second conductive portion on the substrate.

[0093] Optionally, the method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0094] performing a patterning process on the first metal layer to form a fifth gate pattern included in the third conductive portion;

[0095] performing a patterning process on the second metal layer to form a second control voltage line;

[0096] The fifth gate pattern is configured to be electrically connected to the second control voltage line.

[0097] Optionally, the method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0098] performing a patterning process on the second metal layer to form a first electrode of a fifth transistor and a second electrode of the fifth transistor;

[0099] performing a patterning process on the first conductive portion to form a second connection structure;

[0100] Disposing a first electrode of the fifth transistor to be electrically connected to the second control voltage line, and disposing a second electrode of the fifth transistor to be electrically connected to the second connection structure;

[0101] The orthographic projection of at least part of the first electrode of the fifth transistor on the substrate is set to overlap with the orthographic projection of the third conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the fifth transistor on the substrate is set to overlap with the orthographic projection of the third conductive portion on the substrate.

[0102] Optionally, the method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0103] performing a patterning process on the first metal layer to form a seventh gate pattern included in the fourth conductive portion;

[0104] The seventh gate pattern is configured to be electrically connected to the pull-up node.

[0105] Optionally, the method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0106] performing a patterning process on the second metal layer to form a first voltage line, a first electrode of the seventh transistor, and a second electrode of the seventh transistor;

[0107] Disposing a first electrode of the seventh transistor to be electrically connected to the second connection structure, and disposing a second electrode of the seventh transistor to be electrically connected to the first voltage line;

[0108] The orthographic projection of at least part of the first electrode of the seventh transistor on the substrate is set to overlap with the orthographic projection of the fourth conductive part on the substrate, and the orthographic projection of at least part of the second electrode of the seventh transistor on the substrate is set to overlap with the orthographic projection of the fourth conductive part on the substrate.

[0109] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0110] FIG1 is a circuit diagram of at least one embodiment of a 17T1C drive circuit;

[0111] FIG2 is a circuit diagram of at least one embodiment of a 21T1C drive circuit;

[0112] 3A and 3B are layout diagrams of the first circuit portion of the 17T1C driving circuit shown in FIG1 ;

[0113] 4A and 4B are layout diagrams of the first circuit portion of the 21T1C driving circuit shown in FIG2 ;

[0114] FIG5 is a layout diagram of the gate metal layer in FIG3A ;

[0115] FIG6 is a layout diagram of the semiconductor layer in FIG3A;

[0116] 7A and 7B are layout diagrams of the source / drain metal layer in FIG. 3A ;

[0117] FIG8 is a layout diagram of the conductive layer in FIG3A;

[0118] 9A and 9B are layout diagrams of the source / drain metal layer in FIG. 4A ;

[0119] 10 is a layout diagram of the second circuit portion of the 17T1C drive circuit shown in FIG1 , FIG10 is a layout diagram of the second circuit portion of the 21T1C drive circuit shown in FIG2 ;

[0120] FIG11 is a layout diagram of the gate metal layer in FIG10 ;

[0121] FIG12 is a layout diagram of the semiconductor layer in FIG10;

[0122] 13A and 13B are layout diagrams of the source / drain metal layer in FIG10;

[0123] FIG14 is a layout diagram of the conductive layer in FIG10;

[0124] 15 is a layout diagram of the third circuit portion of the 17T1C drive circuit shown in FIG1 , and FIG15 is a layout diagram of the second circuit portion of the 21T1C drive circuit shown in FIG2 ;

[0125] FIG16 is a layout diagram of the gate metal layer in FIG15 ;

[0126] FIG17 is a layout diagram of the semiconductor layer in FIG15;

[0127] 18A and 18B are layout diagrams of the source / drain metal layer in FIG. 15 ;

[0128] FIG19 is a layout diagram of the conductive layer in FIG15;

[0129] 20 is a layout diagram of the fourth circuit portion of the 17T1C drive circuit shown in FIG1 , and FIG20 is a layout diagram of the fourth circuit portion of the 21T1C drive circuit shown in FIG2 ;

[0130] FIG21 is a layout diagram of the gate metal layer in FIG20;

[0131] FIG22 is a layout diagram of the semiconductor layer in FIG20;

[0132] 23A and 23B are layout diagrams of the source / drain metal layer in FIG. 20 ;

[0133] FIG24 is a layout diagram of the conductive layer in FIG20;

[0134] FIG25 is a layout diagram of the fifth circuit section in the 17T1C driving circuit shown in FIG1 , and FIG25 is a layout diagram of the fifth circuit section in the 21T1C driving circuit shown in FIG2 ;

[0135] FIG26 is a layout diagram of the gate metal layer in FIG25;

[0136] FIG27 is a layout diagram of the semiconductor layer in FIG25;

[0137] 28A and 28B are layout diagrams of the source / drain metal layer in FIG. 25 ;

[0138] FIG29 is a layout diagram of the conductive layer in FIG25;

[0139] FIG30 is a layout diagram of the sixth circuit section in the 17T1C drive circuit shown in FIG1 , and FIG30 is a layout diagram of the sixth circuit section in the 21T1C drive circuit shown in FIG2 ;

[0140] FIG31 is a layout diagram of the gate metal layer in FIG30;

[0141] FIG32 is a layout diagram of the semiconductor layer in FIG30;

[0142] 33A, 33B and 33C are layout diagrams of the source / drain metal layer in FIG30;

[0143] FIG34 is a layout diagram of the seventh circuit section in the 17T1C driving circuit shown in FIG1 , and FIG34 is a layout diagram of the seventh circuit section in the 21T1C driving circuit shown in FIG2 ;

[0144] FIG35 is a layout diagram of the gate metal layer in FIG34;

[0145] FIG36 is a layout diagram of the source / drain metal layer in FIG34 ;

[0146] FIG37 is a layout diagram of the conductive layer in FIG34;

[0147] FIG38 is a layout diagram of the eighth circuit section in the 17T1C driving circuit shown in FIG1 , and FIG38 is a layout diagram of the eighth circuit section in the 21T1C driving circuit shown in FIG2 ;

[0148] FIG39 is a layout diagram of the gate metal layer in FIG38;

[0149] FIG40 is a layout diagram of the semiconductor layer in FIG38;

[0150] 41A and 41B are layout diagrams of the source / drain metal layer in FIG. 38 ;

[0151] 42A and 42B are layout diagrams of the ninth circuit section in the 17T1C driving circuit shown in FIG1 , and FIG42A and 42B are layout diagrams of the ninth circuit section in the 21T1C driving circuit shown in FIG2 ;

[0152] FIG43 is a layout diagram of the first circuit unit U1 in FIG42A;

[0153] FIG44 is a layout diagram of the gate metal layer in FIG43;

[0154] FIG45 is a layout diagram of the semiconductor layer in FIG43;

[0155] FIG46 is a layout diagram of the source / drain metal layer in FIG43;

[0156] FIG47 is a layout diagram of the second circuit unit U2 in FIG42A;

[0157] FIG48 is a layout diagram of the gate metal layer in FIG47;

[0158] FIG49 is a layout diagram of the semiconductor layer in FIG47;

[0159] FIG50 is a layout diagram of the source / drain metal layer in FIG47;

[0160] FIG51 is a layout diagram of the conductive layer in FIG47.

[0161] FIG52 is a layout diagram of the first circuit portion of the 21T1C driving circuit shown in FIG2 when the transistors in the 21T1C driving circuit shown in FIG2 are a-Si (amorphous silicon) transistors;

[0162] FIG53 is a layout diagram of the semiconductor layer in FIG52;

[0163] FIG54 is a circuit diagram of at least one embodiment of a 15T1C driver circuit;

[0164] FIG55 is a circuit diagram of at least one embodiment of a 19T1C driver circuit;

[0165] FIG56 is a layout diagram of the tenth transistor when the tenth transistor is an oxide transistor;

[0166] FIG57 is a layout diagram of the gate metal layer in FIG56;

[0167] FIG58 is a layout diagram of the semiconductor layer in FIG56;

[0168] FIG59 is a layout diagram of the source / drain metal layer in FIG56 ;

[0169] FIG60 is a layout diagram of the tenth transistor when the tenth transistor is an amorphous silicon transistor;

[0170] FIG61 is a layout diagram of the semiconductor layer in FIG60;

[0171] FIG62 is a layout diagram of the source / drain metal layer in FIG60 ;

[0172] FIG63 is a combined diagram of the layout diagram of the first portion of the 17T1C driving circuit shown in FIG3A and the layout diagram of the second portion of the driving circuit shown in FIG10 ;

[0173] FIG64 is a combined diagram of the layout diagram of the first circuit portion of the 21T1C driving circuit shown in FIG4A and the layout diagram of the second circuit portion of the driving circuit shown in FIG10 ;

[0174] FIG65 is a structural diagram of at least one embodiment of a drive module;

[0175] FIG66 is a timing diagram illustrating the operation of at least one embodiment of the driving module shown in FIG65 . DETAILED DESCRIPTION

[0176] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. The embodiments of the present disclosure can be used alone or in combination with each other, and are not limited here.

[0177] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0178] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain, and the second electrode may be a source; or, the first electrode may be a source, and the second electrode may be a drain.

[0179] The array substrate according to the embodiment of the present disclosure includes a driving circuit provided on a base substrate, wherein the driving circuit includes a pull-up node control circuit, a first pull-down node control circuit and an output circuit;

[0180] The pull-up node control circuit is electrically connected to the pull-up node and is used to control the potential of the pull-up node;

[0181] The first pull-down node control circuit is electrically connected to the first control voltage line and the first pull-down node respectively, and is used to control the first control voltage provided by the first control voltage line to be written into the first pull-down node;

[0182] The output circuit is electrically connected to the pull-up node and the drive signal output terminal respectively, and is used to control the drive signal output terminal to output the drive signal under the control of the potential of the pull-up node;

[0183] The array substrate further includes a first conductive portion provided on the base substrate;

[0184] The first conductive portion is electrically connected to the first control voltage line.

[0185] In at least one embodiment of the present disclosure, the first conductive portion may include a first gate pattern. In the 17T1C driving circuit, only the first conductive portion is provided without the first transistor. In the 21T1C driving circuit, the first transistor is provided. In at least one embodiment of the present disclosure, conversion between the 17T1C driving circuit and the 21T1C driving circuit can be achieved by simply adding a mask (the mask may be a mask used when forming the source and drain metal layers), thereby effectively improving product compatibility while saving mask costs.

[0186] In at least one embodiment of the present disclosure, the first conductive portion may be a metal structure. In this case, the impedance of the driving circuit may be reduced by providing the first conductive portion.

[0187] In at least one embodiment of the present disclosure, the shortest distance between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first control voltage line on the substrate is greater than or equal to 4 um and less than or equal to 12 um, so as to facilitate wiring, facilitate electrical connection between the first control voltage line and the first conductive portion, and facilitate maintenance.

[0188] In a specific implementation, the shortest distance between the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first control voltage line on the substrate is greater than or equal to 4um to facilitate maintenance; the shortest distance between the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first control voltage line on the substrate is less than or equal to 12um to facilitate wiring and facilitate electrical connection between the first control voltage line and the first conductive part.

[0189] As shown in FIG1 , at least one embodiment of a 17T1C driver circuit may include a pull-up node control circuit, a first pull-down node control circuit, an output circuit, a second pull-down node control circuit, a first pull-down reset circuit, a second pull-down reset circuit, and a carry output circuit;

[0190] The first pull-down node control circuit includes a second transistor M2 and a fourth transistor M4;

[0191] The gate of the second transistor M2 is electrically connected to the first control voltage line VDDO, the first electrode of the second transistor M2 is electrically connected to the first control voltage line VDDO, and the second electrode of the second transistor M2 is electrically connected to the first pull-down node PD1;

[0192] A gate of the fourth transistor M4 is electrically connected to the pull-up node PU, a first electrode of the fourth transistor M4 is electrically connected to the first pull-down node PD1, and a second electrode of the fourth transistor M4 is electrically connected to the first voltage line LVGL;

[0193] The second pull-down node control circuit includes a sixth transistor M6 and an eighth transistor M8;

[0194] The gate of the sixth transistor M6 is electrically connected to the second control voltage line VDDE, the first electrode of the sixth transistor M6 is electrically connected to the second control voltage line VDDE, and the second electrode of the sixth transistor M6 is electrically connected to the second pull-down node PD2;

[0195] The gate of the eighth transistor M8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor M8 is electrically connected to the second pull-down node PD2, and the second electrode of the eighth transistor M8 is electrically connected to the first voltage line LVGL;

[0196] The pull-up node control circuit includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13;

[0197] The gate of the ninth transistor M9 is electrically connected to the first input terminal I1, the first electrode of the ninth transistor M9 is electrically connected to the first input terminal I1, and the second electrode of the ninth transistor M9 is electrically connected to the pull-up node PU;

[0198] The gate of the tenth transistor M10 is electrically connected to the reset terminal RST, the first electrode of the tenth transistor M10 is electrically connected to the pull-up node PU, and the second electrode of the tenth transistor M10 is electrically connected to the first voltage line LVGL;

[0199] The gate of the eleventh transistor M11 is electrically connected to the start voltage line STV, the first electrode of the eleventh transistor M11 is electrically connected to the pull-up node PU, and the second electrode of the eleventh transistor M11 is electrically connected to the first voltage line LVGL;

[0200] The gate of the twelfth transistor M12 is electrically connected to the first pull-down node PD1, the first electrode of the twelfth transistor M12 is electrically connected to the pull-up node PU, and the second electrode of the twelfth transistor M12 is electrically connected to the first voltage line LVGL;

[0201] The gate of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, the first electrode of the thirteenth transistor M13 is electrically connected to the pull-up node PU, and the second electrode of the thirteenth transistor is electrically connected to the first voltage line LVGL;

[0202] The first pull-down reset circuit includes a fourteenth transistor M14; the second pull-down reset circuit includes a fifteenth transistor M15;

[0203] A gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, a first electrode of the fourteenth transistor M14 is electrically connected to the first pull-down node PD1, and a second electrode of the fourteenth transistor M14 is electrically connected to the first voltage line LVBL;

[0204] A gate of the fifteenth transistor M15 is electrically connected to the first input terminal I1, a first electrode of the fifteenth transistor M15 is electrically connected to the second pull-down node PD2, and a second electrode of the fifteenth transistor M15 is electrically connected to the first voltage line LVGL;

[0205] The output circuit includes a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18 and a first capacitor C1;

[0206] The gate of the sixteenth transistor M16 is electrically connected to the pull-up node PU, the first electrode of the sixteenth transistor M16 is electrically connected to the clock signal line CLK, and the second electrode of the sixteenth transistor M16 is electrically connected to the driving signal output terminal O1;

[0207] The gate of the seventeenth transistor M17 is electrically connected to the first pull-down node PD1, the first electrode of the seventeenth transistor M17 is electrically connected to the driving signal output terminal O1, and the second electrode of the seventeenth transistor M17 is electrically connected to the second voltage line VGL;

[0208] The gate of the eighteenth transistor M18 is electrically connected to the second pull-down node PD2, the first electrode of the eighteenth transistor M18 is electrically connected to the driving signal output terminal O1, and the second electrode of the eighteenth transistor M18 is electrically connected to the second voltage line VGL;

[0209] The first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the driving signal output terminal O1;

[0210] The carry output circuit includes a nineteenth transistor M19, a twentieth transistor M20 and a twenty-first transistor M21;

[0211] The gate of the nineteenth transistor M19 is electrically connected to the pull-up node PU, the first electrode of the nineteenth transistor M19 is electrically connected to the clock signal line CLK, and the second electrode of the nineteenth transistor M19 is electrically connected to the carry signal output terminal CR;

[0212] A gate of the 20th transistor M20 is electrically connected to the first pull-down node PD1, a first electrode of the 20th transistor M20 is electrically connected to the carry signal output terminal CR, and a second electrode of the 20th transistor M20 is electrically connected to the first voltage line LVGL;

[0213] A gate of the 21st transistor M21 is electrically connected to the second pull-down node PD2 , a first electrode of the 21st transistor M21 is electrically connected to the carry signal output terminal CR, and a second electrode of the 21st transistor M21 is electrically connected to the first voltage line LVGL.

[0214] In at least one embodiment of the present disclosure, the first electrode of the ninth transistor may also be electrically connected to the second input terminal; the first input terminal may be the same input terminal as the second input terminal, or the first input terminal may be different from the second input terminal.

[0215] Optionally, the first voltage line LVGL can be a first low voltage line, the second voltage line VGL can be a second low voltage line, the first low voltage signal provided by the first voltage line LVGL can be the same as the second low voltage signal provided by the second voltage line VGL, or, the first low voltage signal provided by the first voltage line LVGL can be different from the second low voltage signal provided by the second voltage line VGL, and the voltage value of the first low voltage signal is less than the voltage value of the second low voltage signal.

[0216] As shown in FIG2 , at least one embodiment of a 21T1C driver circuit may include a pull-up node control circuit, a first pull-down node control circuit, an output circuit, a second pull-down node control circuit, a first pull-down reset circuit, a second pull-down reset circuit, and a carry output circuit;

[0217] The first pull-down node control circuit includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;

[0218] The gate of the first transistor M1 and the first electrode of the first transistor M1 are both electrically connected to the first control voltage line VDDO, and the second electrode of the first transistor M1 is electrically connected to the first pull-down control node PDCN1;

[0219] The gate of the second transistor M2 is electrically connected to the first pull-down control node PDCN1, the first electrode of the second transistor M2 is electrically connected to the first control voltage line VDDO, and the second electrode of the second transistor M2 is electrically connected to the first pull-down node PD1;

[0220] A gate of the third transistor M3 is electrically connected to the pull-up node PU, a first electrode of the third transistor M3 is electrically connected to the first pull-down control node PDCN1, and a second electrode of the third transistor M3 is electrically connected to the first voltage line LVGL;

[0221] A gate of the fourth transistor M2 is electrically connected to the pull-up node PU, a first electrode of the fourth transistor M4 is electrically connected to the first pull-down node PD1, and a second electrode of the fourth transistor M4 is electrically connected to the first voltage line LVGL;

[0222] The second pull-down node control circuit includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8;

[0223] The gate of the fifth transistor M5 and the first electrode of the fifth transistor M5 are both electrically connected to the second control voltage line VDDE, and the second electrode of the fifth transistor M5 is electrically connected to the second pull-down control node PDCN2;

[0224] The gate of the sixth transistor M6 is electrically connected to the second pull-down control node PDCN2, the first electrode of the sixth transistor M6 is electrically connected to the second control voltage line VDDE, and the second electrode of the sixth transistor M6 is electrically connected to the second pull-down node PD2;

[0225] The gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the first electrode of the seventh transistor M7 is electrically connected to the second pull-down control node PDCN2, and the second electrode of the seventh transistor M7 is electrically connected to the first voltage line LVGL;

[0226] The gate of the eighth transistor M8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor M8 is electrically connected to the second pull-down node PD2, and the second electrode of the eighth transistor M8 is electrically connected to the first voltage line LVGL;

[0227] The pull-up node control circuit includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13;

[0228] The gate of the ninth transistor M9 is electrically connected to the first input terminal I1, the first electrode of the ninth transistor M9 is electrically connected to the first input terminal I1, and the second electrode of the ninth transistor M9 is electrically connected to the pull-up node PU;

[0229] The gate of the tenth transistor M10 is electrically connected to the reset terminal RST, the first electrode of the tenth transistor M10 is electrically connected to the pull-up node PU, and the second electrode of the tenth transistor M10 is electrically connected to the first voltage line LVGL;

[0230] The gate of the eleventh transistor M11 is electrically connected to the start voltage line STV. Optionally, a plurality of cascaded gate driving circuits are provided in the non-display area of ​​the display panel, and at least some or all of the gate driving circuits are electrically connected to the start voltage line STV for performing a total reset function, that is, resetting the gate driving circuits between adjacent frames. The first electrode of the eleventh transistor M11 is electrically connected to the pull-up node PU, and the second electrode of the eleventh transistor M11 is electrically connected to the first voltage line LVGL.

[0231] The gate of the twelfth transistor M12 is electrically connected to the first pull-down node PD1, the first electrode of the twelfth transistor M12 is electrically connected to the pull-up node PU, and the second electrode of the twelfth transistor M12 is electrically connected to the first voltage line LVGL;

[0232] The gate of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, the first electrode of the thirteenth transistor M13 is electrically connected to the pull-up node PU, and the second electrode of the thirteenth transistor is electrically connected to the first voltage line LVGL;

[0233] The first pull-down reset circuit includes a fourteenth transistor M14; the second pull-down reset circuit includes a fifteenth transistor M15;

[0234] A gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, a first electrode of the fourteenth transistor M14 is electrically connected to the first pull-down node PD1, and a second electrode of the fourteenth transistor M14 is electrically connected to the first voltage line LVGL;

[0235] A gate of the fifteenth transistor M15 is electrically connected to the first input terminal I1, a first electrode of the fifteenth transistor M15 is electrically connected to the second pull-down node PD2, and a second electrode of the fifteenth transistor M15 is electrically connected to the first voltage line LVGL;

[0236] The output circuit includes a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18 and a first capacitor C1;

[0237] The gate of the sixteenth transistor M16 is electrically connected to the pull-up node PU, the first electrode of the sixteenth transistor M16 is electrically connected to the clock signal line CLK, and the second electrode of the sixteenth transistor M16 is electrically connected to the driving signal output terminal O1;

[0238] The gate of the seventeenth transistor M17 is electrically connected to the first pull-down node PD1, the first electrode of the seventeenth transistor M17 is electrically connected to the driving signal output terminal O1, and the second electrode of the seventeenth transistor M17 is electrically connected to the second voltage line VGL;

[0239] The gate of the eighteenth transistor M18 is electrically connected to the second pull-down node PD2, the first electrode of the eighteenth transistor M18 is electrically connected to the driving signal output terminal O1, and the second electrode of the eighteenth transistor M18 is electrically connected to the second voltage line VGL;

[0240] The first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the driving signal output terminal O1;

[0241] The carry output circuit includes a nineteenth transistor M19, a twentieth transistor M20 and a twenty-first transistor M21;

[0242] The gate of the nineteenth transistor M19 is electrically connected to the pull-up node PU, the first electrode of the nineteenth transistor M19 is electrically connected to the clock signal line CLK, and the second electrode of the nineteenth transistor M19 is electrically connected to the carry signal output terminal CR;

[0243] A gate of the 20th transistor M20 is electrically connected to the first pull-down node PD1, a first electrode of the 20th transistor M20 is electrically connected to the carry signal output terminal CR, and a second electrode of the 20th transistor M20 is electrically connected to the first voltage line LVGL;

[0244] A gate of the 21st transistor M21 is electrically connected to the second pull-down node PD2 , a first electrode of the 21st transistor M21 is electrically connected to the carry signal output terminal CR, and a second electrode of the 21st transistor M21 is electrically connected to the first voltage line LVGL.

[0245] In at least one embodiment of the present disclosure, the pull-up node control circuit may also include only a ninth transistor and a tenth transistor to control the potential of the pull-up node under the control of an input signal provided by the input terminal and a reset signal provided by the reset terminal. Optionally, the first conductive portion is composed of a first gate pattern; or, the first conductive portion is composed of a first gate pattern and a first active pattern;

[0246] The first gate pattern is electrically connected to a first control voltage line.

[0247] 3A and 3B are layout diagrams of the first circuit portion of the 17T1C driving circuit shown in FIG1 ;

[0248] 4A and 4B are layout diagrams of the first circuit portion of the 21T1C driving circuit shown in FIG2 ;

[0249] 5 is a layout diagram of the gate metal layer in FIG. 3A , FIG. 6 is a layout diagram of the semiconductor layer in FIG. 3A , FIG. 7A and FIG. 7B are layout diagrams of the source / drain metal layer in FIG. 3A , and FIG. 8 is a layout diagram of the conductive layer in FIG. 3A ;

[0250] 9A and 9B are layout diagrams of the source / drain metal layer in FIG. 4A .

[0251] The layout diagram of the gate metal layer in FIG. 4A is shown in FIG. 5 , the layout diagram of the semiconductor layer in FIG. 4A is shown in FIG. 6 , and the conductive layer in FIG. 4A is shown in FIG. 8 .

[0252] Optionally, the first pull-down node control circuit includes a second transistor;

[0253] A gate of the second transistor is electrically connected to the first connection structure, a first electrode of the second transistor is electrically connected to a first control voltage line, and a second electrode of the second transistor is electrically connected to the first pull-down node.

[0254] In at least one embodiment of the present disclosure, the first connection structure is electrically connected to a first control voltage line.

[0255] As shown in FIG5 , the pattern labeled G1 is the first gate electrode, and the pattern labeled G2 is the gate electrode of the second transistor;

[0256] In FIG7A and FIG9A , the first control voltage line is labeled VDDO, the first electrode of the second transistor is labeled S2, and the second electrode of the second transistor is labeled D2;

[0257] In FIG8 , the first connecting portion is labeled B1 and the first connecting structure is labeled L1;

[0258] In FIG6 , the first active pattern is labeled A1, and the second active pattern is labeled A2;

[0259] As shown in FIG3A and FIG4A , the first gate pattern G1 is electrically connected to the first connection portion B1 through a via hole, and the first connection portion B1 is electrically connected to the first control voltage line VDDO through a via hole. The optional first connection portion B1 may be provided in the same layer as the pixel electrode or the common electrode included in the display area. The optional first connection portion B1 may be formed in an ITO (indium tin oxide) electrode layer.

[0260] The gate G2 of the second transistor is electrically connected to the first connection structure L1 through a via hole, and the first connection structure L1 is electrically connected to the first control voltage line VDDO through a via hole. Optionally, the first connection structure L1 may be provided on the same layer as the pixel electrode or the common electrode included in the display area. Optionally, the first connection structure may be formed on an ITO electrode layer.

[0261] A first electrode S2 of the second transistor is electrically connected to a first control voltage line VDDO, and a second electrode D2 of the second transistor is electrically connected to a first pull-down node PD1.

[0262] As shown in FIG. 7A and FIG. 9A , the first pull-down node PD1 may be electrically connected to the second electrode D2 of the second transistor and the first electrode of the fourth transistor, respectively.

[0263] In at least one embodiment of the present disclosure, the first pull-down node control circuit is further configured to write a first voltage signal provided by a first voltage line into the first pull-down node;

[0264] The array substrate further includes a second conductive portion provided on the base substrate;

[0265] The second conductive portion is electrically connected to the pull-up node.

[0266] Optionally, the second conductive portion is composed of a third gate pattern; or, the second conductive portion is composed of a third gate pattern and a third active pattern;

[0267] The third gate pattern is electrically connected to the pull-up node.

[0268] In at least one embodiment of the present disclosure, the third gate pattern may be directly electrically connected to the pull-up node, or the third gate pattern may be indirectly electrically connected to the pull-up node.

[0269] In a specific implementation, when the third gate pattern is indirectly electrically connected to the pull-up node, other components may be provided between the third gate pattern and the pull-up node, or the connection line between the third gate pattern and the pull-up node may be switched between different conductive layers; but the present invention is not limited thereto.

[0270] In FIG. 5 , the third gate pattern labeled G3 is included in the second conductive portion.

[0271] As shown in FIG. 3A and FIG. 4A , the third gate pattern G3 is electrically connected to the pull-up node PU, and the pull-up node PU may be electrically connected to the gate G4 of the fourth transistor.

[0272] In FIG5 , the node labeled PU is a pull-up node.

[0273] Optionally, the shortest distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first control voltage line on the substrate is greater than or equal to 4 μm to facilitate maintenance;

[0274] The shortest distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first voltage line on the substrate is greater than or equal to 4um and less than or equal to 12um, which facilitates wiring, electrical connection between the second conductive portion and the first voltage line, and maintenance.

[0275] The shortest distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first voltage line on the substrate is greater than or equal to 4 μm to facilitate maintenance;

[0276] The shortest distance between the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the first voltage line on the base substrate is less than or equal to 12 μm, so as to facilitate electrical connection between the second conductive portion and the first voltage line.

[0277] In at least one embodiment of the present disclosure, the first pull-down node control circuit includes a fourth transistor;

[0278] A gate of the fourth transistor is electrically connected to the pull-up node, a first electrode of the fourth transistor is electrically connected to the first pull-down node, and a second electrode of the fourth transistor is electrically connected to the first voltage line.

[0279] In FIG6 , the third active pattern is labeled A3, and the fourth active pattern is labeled A4;

[0280] In FIG5 , the gate of the fourth transistor is labeled G4 , and the gate G4 of the fourth transistor is electrically connected to the pull-up node PU.

[0281] In FIG. 7A and FIG. 9A , S4 is the first electrode of the fourth transistor, D4 is the second electrode of the fourth transistor, LVGL is the first voltage line, and PD1 is the first pull-down node.

[0282] As shown in FIG3A and FIG4A , a gate G4 of the fourth transistor is electrically connected to the pull-up node PU, a first electrode S4 of the fourth transistor is electrically connected to the first pull-down node PD1 , and a second electrode D4 of the fourth transistor is electrically connected to the first voltage line LVGL.

[0283] In at least one embodiment of the present disclosure, the driving circuit further includes a second pull-down node control circuit;

[0284] The second pull-down node control circuit is electrically connected to the second control voltage line and the second pull-down node respectively, and is used to control the writing of the second control voltage provided by the second control voltage line into the second pull-down node;

[0285] The array substrate further includes a third conductive portion provided on the base substrate;

[0286] The third conductive portion is electrically connected to the second control voltage line.

[0287] Optionally, the third conductive portion is composed of a fifth gate pattern; or, the third conductive portion is composed of a fifth gate pattern and a fifth active pattern.

[0288] In FIG. 5 , G5 is a fifth gate pattern included in the third conductive portion.

[0289] In FIG6 , the fifth active pattern is labeled A5.

[0290] In FIG. 7A and FIG. 9A , the second control voltage line is labeled VDDE.

[0291] In FIG8 , the second connection portion is labeled B2 .

[0292] As shown in FIG3A and FIG4A , the fifth gate pattern G5 is electrically connected to the second connection portion B2 through a via hole;

[0293] The second connection portion B2 is electrically connected to the second control voltage line VDDE through a via hole.

[0294] In at least one embodiment of the present disclosure, the shortest distance between the orthographic projection of the third conductive portion on the substrate and the orthographic projection of the second control voltage line on the substrate is greater than or equal to 4um and less than or equal to 12um, so as to facilitate wiring, facilitate electrical connection between the third conductive portion and the second control voltage line, and facilitate maintenance.

[0295] In a specific implementation, the shortest distance between the orthographic projection of the third conductive part on the substrate and the orthographic projection of the second control voltage line on the substrate is greater than or equal to 4um to facilitate maintenance; the shortest distance between the orthographic projection of the third conductive part on the substrate and the orthographic projection of the second control voltage line on the substrate is less than or equal to 12um to facilitate wiring, which is conducive to electrical connection between the third conductive part and the second control voltage line.

[0296] Optionally, the second pull-down node control circuit includes a sixth transistor;

[0297] A gate of the sixth transistor is electrically connected to the second connection structure, a first electrode of the sixth transistor is electrically connected to the second control voltage line, and a second electrode of the sixth transistor is electrically connected to the second pull-down node.

[0298] In at least one embodiment of the present disclosure, the second connection structure is electrically connected to a second control voltage line.

[0299] As shown in FIG5 , the gate of the sixth transistor is labeled G6 .

[0300] As shown in FIG6 , the sixth active pattern is labeled A6 .

[0301] In FIG7A and FIG9A , the first electrode of the sixth transistor is labeled S6 , and the second electrode of the sixth transistor is labeled D6 ;

[0302] In FIG8 , the second connection structure is labeled L2.

[0303] As shown in FIG3A and FIG4A , the gate G6 of the sixth transistor is electrically connected to the second connection structure L2 through a via, and the second connection structure L2 is electrically connected to the second control voltage line VDDE through a via;

[0304] The first electrode S6 of the sixth transistor is electrically connected to the second control voltage line VDDE;

[0305] The second electrode D6 of the sixth transistor is electrically connected to the second pull-down node PD2 , and the second pull-down node PD2 may be electrically connected to the first electrode of the eighth transistor.

[0306] In FIG. 7A and FIG. 9A , the node labeled PD2 is the second pull-down node.

[0307] In at least one embodiment of the present disclosure, the second pull-down node control circuit is further configured to write the first voltage signal provided by the first voltage line into the second pull-down node;

[0308] The array substrate further includes a fourth conductive portion provided on the base substrate;

[0309] The fourth conductive portion is electrically connected to the pull-up node.

[0310] Optionally, the fourth conductive portion is composed of the seventh gate pattern; or, the fourth conductive portion is composed of the seventh gate pattern and the seventh active pattern;

[0311] The seventh gate pattern is electrically connected to the pull-up node.

[0312] As shown in FIG5 , the seventh gate pattern labeled G7 is included in the fourth conductive portion;

[0313] As shown in FIG. 5 , the seventh gate pattern G7 is electrically connected to the pull-up node PU.

[0314] In FIG6 , the seventh active pattern is labeled A7.

[0315] Optionally, the shortest distance between the orthographic projection of the fourth conductive portion on the base substrate and the orthographic projection of the second control voltage line on the base substrate is greater than or equal to 4 μm to facilitate maintenance;

[0316] The shortest distance between the orthographic projection of the fourth conductive part on the base substrate and the orthographic projection of the first voltage line on the base substrate is greater than or equal to 4um and less than or equal to 12um, which facilitates wiring, facilitates electrical connection between the fourth conductive part and the first voltage line, and facilitates maintenance.

[0317] In a specific implementation, the shortest distance between the orthographic projection of the fourth conductive part on the substrate and the orthographic projection of the first voltage line on the substrate is greater than or equal to 4um to facilitate maintenance; the shortest distance between the orthographic projection of the fourth conductive part on the substrate and the orthographic projection of the first voltage line on the substrate is less than or equal to 12um to facilitate wiring, which is conducive to electrical connection between the fourth conductive part and the first voltage line.

[0318] In at least one embodiment of the present disclosure, the second pull-down node control circuit includes an eighth transistor;

[0319] A gate of the eighth transistor is electrically connected to the pull-up node, a first electrode of the eighth transistor is electrically connected to the second pull-down node, and a second electrode of the eighth transistor is electrically connected to the first voltage line.

[0320] 10 is a layout diagram of the second circuit portion of the 17T1C drive circuit shown in FIG1 , FIG10 is a layout diagram of the second circuit portion of the 21T1C drive circuit shown in FIG2 ;

[0321] 11 is a layout diagram of the gate metal layer in FIG. 10 , FIG. 12 is a layout diagram of the semiconductor layer in FIG. 10 , FIG. 13A and FIG. 13B are layout diagrams of the source / drain metal layer in FIG. 10 , and FIG. 14 is a layout diagram of the conductive layer in FIG. 10 ;

[0322] As shown in FIG11 , the gate of the eighth transistor is labeled G8;

[0323] In FIG12 , the eighth active pattern is labeled A8;

[0324] In FIG13A , S8 is a first electrode of the eighth transistor, and D8 is a second electrode of the eighth transistor.

[0325] As shown in FIG. 10 , the second electrode D8 of the eighth transistor is electrically connected to the first voltage line LVGL.

[0326] In at least one embodiment corresponding to FIG. 3A , FIG. 4A and FIG. 10 , the gate G8 of the eighth transistor is electrically connected to the gate G4 of the fourth transistor, that is, the gate G8 of the eighth transistor is electrically connected to the pull-up node;

[0327] The first electrode S8 of the eighth transistor is electrically connected to the second electrode D6 of the sixth transistor, that is, the first electrode S8 of the eighth transistor is electrically connected to the second pull-down node.

[0328] The array substrate according to at least one embodiment of the present disclosure further includes a first source-drain metal pattern and a third source-drain metal pattern provided on the base substrate;

[0329] The first source-drain metal pattern includes a first electrode of the first transistor and a second electrode of the first transistor;

[0330] A first electrode of the first transistor is electrically connected to the first control voltage line, and a second electrode of the first transistor is electrically connected to the first connection structure;

[0331] An orthographic projection of at least a portion of the first electrode of the first transistor on the substrate overlaps with an orthographic projection of the first conductive portion on the substrate, and an orthographic projection of at least a portion of the second electrode of the first transistor on the substrate overlaps with an orthographic projection of the first conductive portion on the substrate;

[0332] The third source-drain metal pattern includes a first electrode of a third transistor and a second electrode of the third transistor;

[0333] A first electrode of the third transistor is electrically connected to the first connection structure, and a second electrode of the third transistor is electrically connected to the first voltage line;

[0334] The orthographic projection of at least part of the first electrode of the third transistor on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the third transistor on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate.

[0335] In a specific implementation, an orthographic projection of at least a portion of the first electrode of the first transistor on the base substrate overlaps with an orthographic projection of the first gate pattern included in the first conductive portion on the base substrate, and an orthographic projection of at least a portion of the second electrode of the first transistor on the base substrate overlaps with an orthographic projection of the first gate pattern included in the first conductive portion on the base substrate;

[0336] The orthographic projection of at least part of the first electrode of the third transistor on the base substrate overlaps with the orthographic projection of the third gate pattern included in the second conductive portion on the base substrate, and the orthographic projection of at least part of the second electrode of the third transistor on the base substrate overlaps with the orthographic projection of the third gate pattern included in the second conductive portion on the base substrate.

[0337] The array substrate according to at least one embodiment of the present disclosure further includes a first source-drain metal pattern and a third source-drain metal pattern provided on the base substrate;

[0338] As shown in FIG9A , the first source-drain metal pattern includes a first electrode S1 of the first transistor and a second electrode D1 of the first transistor;

[0339] As shown in FIG4A , the first electrode S1 of the first transistor is electrically connected to the first control voltage line VDDO, and the second electrode D1 of the first transistor is electrically connected to the first connection structure L1;

[0340] An orthographic projection of at least a portion of the first electrode S1 of the first transistor on the base substrate overlaps with an orthographic projection of the first gate pattern G1 on the base substrate, and an orthographic projection of at least a portion of the second electrode D1 of the first transistor on the base substrate overlaps with an orthographic projection of the first gate pattern G1 on the base substrate;

[0341] As shown in FIG9A , the third source-drain metal pattern includes a first electrode S3 of the third transistor and a second electrode D3 of the third transistor;

[0342] As shown in FIG4A , the first electrode S3 of the third transistor is electrically connected to the first connection structure L1 , and the second electrode D3 of the third transistor is electrically connected to the first voltage line LVGL;

[0343] The orthographic projection of at least part of the first electrode S3 of the third transistor on the substrate overlaps with the orthographic projection of the third gate pattern G3 on the substrate, and the orthographic projection of at least part of the second electrode D3 of the third transistor on the substrate overlaps with the orthographic projection of the third gate pattern G3 on the substrate.

[0344] In at least one embodiment of the present disclosure, the array substrate further includes a fifth source-drain metal pattern disposed on the base substrate; the array substrate further includes a seventh source-drain metal pattern disposed on the base substrate;

[0345] The fifth source-drain metal pattern includes a first electrode of a fifth transistor and a second electrode of the fifth transistor;

[0346] A first electrode of the fifth transistor is electrically connected to the second control voltage line, and a second electrode of the fifth transistor is electrically connected to the second connection structure;

[0347] An orthographic projection of at least a portion of the first electrode of the fifth transistor on the substrate overlaps with an orthographic projection of the third conductive portion on the substrate, and an orthographic projection of at least a portion of the second electrode of the fifth transistor on the substrate overlaps with an orthographic projection of the third conductive portion on the substrate;

[0348] The seventh source-drain metal pattern includes a first electrode of a seventh transistor and a second electrode of the seventh transistor;

[0349] A first electrode of the seventh transistor is electrically connected to the second connection structure, and a second electrode of the seventh transistor is electrically connected to the first voltage line;

[0350] The orthographic projection of at least part of the first electrode of the seventh transistor on the substrate overlaps with the orthographic projection of the fourth conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the seventh transistor on the substrate overlaps with the orthographic projection of the fourth conductive portion on the substrate.

[0351] In a specific implementation, an orthographic projection of at least part of the first electrode of the fifth transistor on the substrate overlaps with an orthographic projection of the fifth gate pattern included in the third conductive portion on the substrate, and an orthographic projection of at least part of the second electrode of the fifth transistor on the substrate overlaps with an orthographic projection of the fifth gate pattern included in the third conductive portion on the substrate; an orthographic projection of at least part of the first electrode of the seventh transistor on the substrate overlaps with an orthographic projection of the seventh gate pattern included in the fourth conductive portion on the substrate, and an orthographic projection of at least part of the second electrode of the seventh transistor on the substrate overlaps with an orthographic projection of the seventh gate pattern included in the fourth conductive portion on the substrate.

[0352] In at least one embodiment of the present disclosure, the array substrate further includes a fifth source-drain metal pattern disposed on the base substrate; the array substrate further includes a seventh source-drain metal pattern disposed on the base substrate;

[0353] As shown in FIG9A , the fifth source-drain metal pattern includes a first electrode S5 of the fifth transistor and a second electrode D5 of the fifth transistor;

[0354] As shown in FIG4A , the first electrode S5 of the fifth transistor is electrically connected to the second control voltage line VDDE, and the second electrode D5 of the fifth transistor is electrically connected to the second connection structure L2;

[0355] An orthographic projection of at least a portion of the first electrode S5 of the fifth transistor on the base substrate overlaps with an orthographic projection of the fifth gate pattern G5 on the base substrate, and an orthographic projection of at least a portion of the second electrode D5 of the fifth transistor on the base substrate overlaps with an orthographic projection of the fifth gate pattern G5 on the base substrate;

[0356] As shown in FIG9A , the seventh source-drain metal pattern includes a first electrode S7 of the seventh transistor and a second electrode D7 of the seventh transistor;

[0357] As shown in FIG4A , the first electrode S7 of the seventh transistor is electrically connected to the second connection structure L2 , and the second electrode D7 of the seventh transistor is electrically connected to the first voltage line LVGL;

[0358] The orthographic projection of at least part of the first electrode S7 of the seventh transistor on the base substrate overlaps with the orthographic projection of the seventh gate pattern G7 on the base substrate, and the orthographic projection of at least part of the second electrode D7 of the seventh transistor on the base substrate overlaps with the orthographic projection of the seventh gate pattern G7 on the base substrate.

[0359] Optionally, the pull-up node control circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0360] The gate of the ninth transistor is electrically connected to the first input terminal, the first electrode of the ninth transistor is electrically connected to the second input terminal, and the second electrode of the ninth transistor is electrically connected to the pull-up node;

[0361] The gate of the tenth transistor is electrically connected to the reset terminal, the first electrode of the tenth transistor is electrically connected to the pull-up node, and the second electrode of the tenth transistor is electrically connected to the first voltage line;

[0362] The gate of the eleventh transistor is electrically connected to the starting voltage line, the first electrode of the eleventh transistor is electrically connected to the pull-up node, and the second electrode of the eleventh transistor is electrically connected to the first voltage line;

[0363] The gate of the twelfth transistor is electrically connected to the first pull-down node, the first electrode of the twelfth transistor is electrically connected to the pull-up node, and the second electrode of the twelfth transistor is electrically connected to the first voltage line;

[0364] A gate of the thirteenth transistor is electrically connected to the second pull-down node, a first electrode of the twelfth transistor is electrically connected to the pull-up node, and a second electrode of the twelfth transistor is electrically connected to the first voltage line.

[0365] In at least one embodiment of the present disclosure, the driving circuit further includes a first pull-down reset circuit and a second pull-down reset circuit; the first pull-down reset circuit includes a fourteenth transistor; the second pull-down reset circuit includes a fifteenth transistor;

[0366] The gate of the fourteenth transistor is electrically connected to the first input terminal, the first electrode of the fourteenth transistor is electrically connected to the first pull-down node, and the second electrode of the fourteenth transistor is electrically connected to the first voltage line;

[0367] A gate of the fifteenth transistor is electrically connected to the first input terminal, a first electrode of the fifteenth transistor is electrically connected to the second pull-down node, and a second electrode of the fourteenth transistor is electrically connected to the first voltage line.

[0368] The output circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a first capacitor;

[0369] The gate of the sixteenth transistor is electrically connected to the pull-up node, the first electrode of the sixteenth transistor is electrically connected to the clock signal line, and the second electrode of the sixteenth transistor is electrically connected to the driving signal output terminal;

[0370] The gate of the seventeenth transistor is electrically connected to the first pull-down node, the first electrode of the seventeenth transistor is electrically connected to the driving signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the second voltage terminal;

[0371] The gate of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the driving signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the second voltage terminal;

[0372] The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the driving signal output terminal.

[0373] In at least one embodiment of the present disclosure, the pull-up node control circuit may also include only a ninth transistor and a tenth transistor; the ninth transistor controls the connection or disconnection between the pull-up node and the second input terminal under the control of the first input signal provided by the first input terminal, and the tenth transistor controls the connection or disconnection between the pull-up node and the first voltage line under the control of the reset signal provided by the reset terminal.

[0374] In at least one embodiment of the present disclosure, the first input terminal and the second input terminal may be the same input terminal; or, the first input terminal may be different from the second input terminal.

[0375] In at least one embodiment of the present disclosure, the driving circuit further includes a carry output circuit;

[0376] The carry output circuit is electrically connected to the carry signal output terminal, the pull-up node, the first pull-down node, and the second pull-down node, respectively, and is used to control the carry signal output terminal to output a carry signal under the control of the potential of the pull-up node, the potential of the first pull-down node, and the potential of the second pull-down node;

[0377] The carry output circuit includes a nineteenth transistor, a twentieth transistor and a twenty-first transistor;

[0378] The gate of the nineteenth transistor is electrically connected to the pull-up node, the first electrode of the nineteenth transistor is electrically connected to the clock signal line, and the second electrode of the nineteenth transistor is electrically connected to the carry signal output terminal;

[0379] The gate of the twentieth transistor is electrically connected to the first pull-down node, the first electrode of the twentieth transistor is electrically connected to the carry signal output terminal, and the second electrode of the twentieth transistor is electrically connected to the first voltage terminal;

[0380] A gate of the twenty-first transistor is electrically connected to the second pull-down node, a first electrode of the twenty-first transistor is electrically connected to the carry signal output terminal, and a second electrode of the twenty-first transistor is electrically connected to the first voltage terminal.

[0381] Optionally, the first pull-down node control circuit and the second pull-down node control circuit are arranged in the first area;

[0382] The eleventh transistor is arranged on a side of the first region away from the display region;

[0383] The ninth transistor, the tenth transistor, the twelfth transistor, and the thirteenth transistor are disposed on a side of the first region close to the display region.

[0384] In at least one embodiment of the present disclosure, the first pull-down node control circuit and the second pull-down node control circuit are disposed in the first region;

[0385] The fourteenth transistor and the fifteenth transistor are arranged on a side of the first region close to the display region.

[0386] Optionally, the first electrode of the seventeenth transistor is connected to the first electrode of the eighteenth transistor, and the second electrode of the seventeenth transistor is connected to the second electrode of the eighteenth transistor;

[0387] The first pull-down node control circuit and the second pull-down node control circuit are arranged in the first area; the sixteenth transistor, the seventeenth transistor, the eighteenth transistor and the first capacitor are arranged on a side of the first area close to the display area.

[0388] Optionally, the first electrode of the 20th transistor is connected to the first electrode of the 21st transistor, and the second electrode of the 20th transistor is connected to the second electrode of the 21st transistor;

[0389] The nineteenth transistor, the twentieth transistor, and the twenty-first transistor are arranged on a side of the first region close to the display region.

[0390] FIG15 is a layout diagram of the third circuit section in the 17T1C driving circuit shown in FIG1 , and FIG15 is a layout diagram of the second circuit section in the 21T1C driving circuit shown in FIG2 .

[0391] Figure 16 is a layout diagram of the gate metal layer in Figure 15, Figure 17 is a layout diagram of the semiconductor layer in Figure 15, Figures 18A and 18B are layout diagrams of the source and drain metal layers in Figure 15, and Figure 19 is a layout diagram of the conductive layer in Figure 15.

[0392] FIG20 is a layout diagram of the fourth circuit portion in the 17T1C driving circuit shown in FIG1 , and FIG20 is a layout diagram of the fourth circuit portion in the 21T1C driving circuit shown in FIG2 .

[0393] Figure 21 is a layout diagram of the gate metal layer in Figure 20, Figure 22 is a layout diagram of the semiconductor layer in Figure 20, Figures 23A and 23B are layout diagrams of the source and drain metal layers in Figure 20, and Figure 24 is a layout diagram of the conductive layer in Figure 20.

[0394] FIG25 is a layout diagram of the fifth circuit section in the 17T1C driving circuit shown in FIG1 , and FIG25 is a layout diagram of the fifth circuit section in the 21T1C driving circuit shown in FIG2 .

[0395] Figure 26 is a layout diagram of the gate metal layer in Figure 25, Figure 27 is a layout diagram of the semiconductor layer in Figure 25, Figures 28A and 28B are layout diagrams of the source and drain metal layers in Figure 25, and Figure 29 is a layout diagram of the conductive layer in Figure 25.

[0396] FIG30 is a layout diagram of the sixth circuit section in the 17T1C driving circuit shown in FIG1 , and FIG30 is a layout diagram of the sixth circuit section in the 21T1C driving circuit shown in FIG2 .

[0397] 31 is a layout diagram of the gate metal layer in FIG 30 , FIG 32 is a layout diagram of the semiconductor layer in FIG 30 , and FIG 33A , FIG 33B and FIG 33C are layout diagrams of the source / drain metal layer in FIG 30 .

[0398] FIG34 is a layout diagram of the seventh circuit section in the 17T1C driving circuit shown in FIG1 , and FIG34 is a layout diagram of the seventh circuit section in the 21T1C driving circuit shown in FIG2 .

[0399] FIG35 is a layout diagram of the gate metal layer in FIG34 , FIG36 is a layout diagram of the source / drain metal layer in FIG34 , and FIG37 is a layout diagram of the conductive layer in FIG34 .

[0400] FIG38 is a layout diagram of the eighth circuit section in the 17T1C driving circuit shown in FIG1 , and FIG38 is a layout diagram of the eighth circuit section in the 21T1C driving circuit shown in FIG2 .

[0401] 39 is a layout diagram of the gate metal layer in FIG. 38 , FIG. 40 is a layout diagram of the semiconductor layer in FIG. 38 , and FIG. 41A and FIG. 41B are layout diagrams of the source / drain metal layer in FIG. 38 .

[0402] 42A and 42B are layout diagrams of the ninth circuit section in the 17T1C driving circuit shown in FIG. 1 , and FIG. 42A and 42B are layout diagrams of the ninth circuit section in the 21T1C driving circuit shown in FIG. 2 .

[0403] FIG43 is a layout diagram of the first circuit unit U1 in FIG42A;

[0404] FIG44 is a layout diagram of the gate metal layer in FIG43 , FIG45 is a layout diagram of the semiconductor layer in FIG43 , and FIG46 is a layout diagram of the source / drain metal layer in FIG43 .

[0405] FIG47 is a layout diagram of the second circuit unit U2 in FIG42A;

[0406] Figure 48 is a layout diagram of the gate metal layer in Figure 47, Figure 49 is a layout diagram of the semiconductor layer in Figure 47, Figure 50 is a layout diagram of the source and drain metal layer in Figure 47, and Figure 51 is a layout diagram of the conductive layer in Figure 47.

[0407] FIG52 is a layout diagram of a first portion of the 21T1C driving circuit shown in FIG2 when the transistors in the 21T1C driving circuit shown in FIG2 are a-Si (amorphous silicon) transistors. FIG53 is a layout diagram of the semiconductor layer in FIG52.

[0408] The layout diagram of the gate metal layer in Figure 52 is shown in Figure 5, the layout diagram of the source and drain metal layers in Figure 52 is shown in Figures 9A and 9B, and the conductive layer in Figure 52 is shown in Figure 8.

[0409] In FIG3A , VDDO is a first control voltage line, VDDE is a second control voltage line, CLK is a clock signal line, LVGL is a first voltage line, G1 is a first gate pattern, G3 is a third gate pattern, G5 is a fifth gate pattern, G7 is a seventh gate pattern, G2 is a gate of the second transistor, G4 is a gate of the fourth transistor, G6 is a gate of the sixth transistor, G11 is a gate of the eleventh transistor, L1 is a first connection structure, L2 is a second connection structure, B1 is a first connection portion, B2 is a second connection portion, A1 is a first active pattern, A3 is a third active pattern, A5 is a fifth active pattern, and A7 is a seventh active pattern.

[0410] In Figure 3B, the eleventh transistor is labeled M11, the second transistor is labeled M2, the fourth transistor is labeled M4, the sixth transistor is labeled M6, the first gate pattern is labeled G1, the third gate pattern is labeled G3, the fifth gate pattern is labeled G5, and the seventh gate pattern is labeled G7.

[0411] In FIG4A , VDDO is a first control voltage line, VDDE is a second control voltage line, CLK is a clock signal line, LVGL is a first voltage line, G11 is a gate of an eleventh transistor, G1 is a first gate pattern, G3 is a third gate pattern, G5 is a fifth gate pattern, G7 is a seventh gate pattern, G2 is a gate of a second transistor, G4 is a gate of a fourth transistor, G6 is a gate of a sixth transistor, and G7 is a seventh gate pattern. L1 is the first connection structure, L2 is the second connection structure, B1 is the first connection part, and B2 is the second connection part; S1 is the first electrode of the first transistor, D1 is the second electrode of the first transistor, S3 is the first electrode of the third transistor, D3 is the second electrode of the third transistor, S5 is the first electrode of the fifth transistor, D5 is the second electrode of the fifth transistor, S7 is the first electrode of the seventh transistor, and D7 is the second electrode of the seventh transistor.

[0412] In Figure 4B, the transistor labeled M11 is the eleventh transistor, the transistor labeled M1 is the first transistor, the transistor labeled M3 is the third transistor, the transistor labeled M5 is the fifth transistor, the transistor labeled M7 is the seventh transistor, the transistor labeled M2 is the second transistor, the transistor labeled M4 is the fourth transistor, and the transistor labeled M6 is the sixth transistor.

[0413] In Figure 5, labeled G11 is the gate of the eleventh transistor, labeled G1 is the first gate pattern, labeled G3 is the third gate pattern, labeled G5 is the fifth gate pattern, labeled G7 is the seventh gate pattern, labeled G2 is the gate of the second transistor, labeled G4 is the gate of the fourth transistor, labeled G6 is the gate of the sixth transistor, and labeled PU is the pull-up node.

[0414] In FIG6 , A11 is the eleventh active pattern, A1 is the first active pattern, A3 is the third active pattern, A5 is the fifth active pattern, A7 is the seventh active pattern, A2 is the second active pattern, A4 is the fourth active pattern, and A6 is the sixth active pattern.

[0415] In at least one embodiment of the present disclosure, the eleventh active pattern may be the active pattern of the eleventh transistor, the second active pattern may be the active pattern of the second transistor, the fourth active pattern may be the active pattern of the fourth transistor, and the sixth active pattern may be the active pattern of the sixth transistor.

[0416] In Figure 7A, the first control voltage line is labeled VDDO, the second control voltage line is labeled VDDE, the clock signal line is labeled CLK, the first voltage line is labeled LVGL, the first pull-down node is labeled PD1, the second pull-down node is labeled PD2, the first electrode of the second transistor is labeled S2, the second electrode of the second transistor is labeled D2, the first electrode of the fourth transistor is labeled S4, the second electrode of the fourth transistor is labeled D4, the first electrode of the sixth transistor is labeled S6, the second electrode of the sixth transistor is labeled D6, the first electrode of the sixth transistor is labeled S11, and the second electrode of the eleventh transistor is labeled D11.

[0417] In FIG. 7B , the eleventh source / drain pattern is labeled Y11 , the second source / drain pattern is labeled Y2 , the fourth source / drain pattern is labeled Y4 , and the sixth source / drain pattern is labeled Y6 .

[0418] In at least one embodiment of the present disclosure, the eleventh source-drain pattern includes the first electrode of the eleventh transistor and the second electrode of the eleventh transistor; the second source-drain pattern includes the first electrode of the second transistor and the second electrode of the second transistor; the fourth source-drain pattern includes the first electrode of the fourth transistor and the second electrode of the fourth transistor; and the sixth source-drain pattern includes the first electrode of the sixth transistor and the second electrode of the sixth transistor.

[0419] In FIG8 , L1 is a first connection structure, L2 is a second connection structure, B1 is a first connection portion, and B2 is a second connection portion.

[0420] In FIG9A , VDDO is a first control voltage line, VDDE is a second control voltage line, CLK is a clock signal line, LVGL is a first voltage line, PD1 is a first pull-down node, PD2 is a second pull-down node, S2 is a first electrode of a second transistor, D2 is a second electrode of a second transistor, S4 is a first electrode of a fourth transistor, D4 is a second electrode of a fourth transistor, and S6 is a first electrode of a fourth transistor. is the first electrode of the sixth transistor, D6 is the second electrode of the sixth transistor, S1 is the first electrode of the first transistor, D1 is the second electrode of the first transistor, S3 is the first electrode of the third transistor, D3 is the second electrode of the third transistor, S5 is the first electrode of the fifth transistor, D5 is the second electrode of the fifth transistor, S11 is the first electrode of the eleventh transistor, and D11 is the second electrode of the eleventh transistor.

[0421] In Figure 9B, the eleventh source-drain pattern is labeled Y11, the second source-drain pattern is labeled Y2, the fourth source-drain pattern is labeled Y4, the sixth source-drain pattern is labeled Y6, the first source-drain pattern is labeled Y1, the third source-drain pattern is labeled Y3, the fifth source-drain pattern is labeled Y5, and the seventh source-drain pattern is labeled Y7.

[0422] In at least one embodiment of the present disclosure, the first source-drain pattern includes the first electrode of the first transistor and the second electrode of the first transistor; the third source-drain pattern includes the first electrode of the third transistor and the second electrode of the third transistor; the fifth source-drain pattern includes the first electrode of the fifth transistor and the second electrode of the fifth transistor; and the seventh source-drain pattern includes the first electrode of the seventh transistor and the second electrode of the seventh transistor.

[0423] In FIG10 , LVGL is the first voltage line, CLK is the clock signal line, M8 is the eighth transistor, M12 is the twelfth transistor, M13 is the thirteenth transistor, and M20 is the twentieth transistor.

[0424] In FIG11 , G8 is the gate of the eighth transistor, G12 is the gate of the twelfth transistor, G13 is the gate of the thirteenth transistor, and G20 is the gate of the twentieth transistor.

[0425] In FIG. 12 , the eighth active pattern is labeled A8 , the twelfth active pattern is labeled A12 , the thirteenth active pattern is labeled A13 , and the twentieth active pattern is labeled A20 .

[0426] In at least one embodiment of the present disclosure, the eighth active pattern A8 is the active pattern of the eighth transistor, the twelfth active pattern A12 is the active pattern of the twelfth transistor, the thirteenth active pattern A13 is the active pattern of the thirteenth transistor, and the twentieth active pattern A20 is the active pattern of the twentieth transistor.

[0427] In Figure 13A, the first voltage line is labeled LVGL, the clock signal line is labeled CLK, the first electrode of the eighth transistor is labeled S8, the second electrode of the eighth transistor is labeled D8, the first electrode of the twelfth transistor is labeled S12, the second electrode of the twelfth transistor is labeled D12, the first electrode of the thirteenth transistor is labeled S13, the second electrode of the thirteenth transistor is labeled D13, the first electrode of the twentieth transistor is labeled S20, and the second electrode of the twentieth transistor is labeled D20.

[0428] In FIG13B , the eighth source-drain pattern is labeled Y8 , the twelfth source-drain pattern is labeled Y12 , the thirteenth source-drain pattern is labeled Y13 , and the twentieth source-drain pattern is labeled Y20 .

[0429] In at least one embodiment of the present disclosure, the eighth source-drain pattern includes the first electrode of the eighth transistor and the second electrode of the eighth transistor; the twelfth source-drain pattern includes the first electrode of the twelfth transistor and the second electrode of the twelfth transistor; the thirteenth source-drain pattern includes the first electrode of the thirteenth transistor and the second electrode of the thirteenth transistor; and the twentieth source-drain pattern includes the first electrode of the twentieth transistor and the second electrode of the twentieth transistor.

[0430] In FIG14 , L3 is the third connection structure, L4 is the fourth connection structure, L5 is the fifth connection structure, and L6 is the sixth connection structure.

[0431] In Figure 15, labeled LVGL is the first voltage line, labeled CR is the carry signal output terminal, labeled L7 is the seventh connection structure, labeled S21 is the first electrode of the twenty-first transistor, labeled M21 is the twenty-first transistor, and labeled M10 is the tenth transistor.

[0432] In FIG16 , G21 is the gate of the twenty-first transistor, G10 is the gate of the tenth transistor, and CR is the carry signal output terminal.

[0433] In FIG17 , the pattern labeled A21 is the twenty-first active pattern, and the pattern labeled A10 is the eleventh active pattern.

[0434] In at least one embodiment of the present disclosure, the twenty-first active pattern A21 may be an active pattern of a twenty-first transistor, and the tenth active pattern A10 may be an active pattern of a tenth transistor.

[0435] In Figure 18A, S21 is the first electrode of the twenty-first transistor, D21 is the second electrode of the twenty-first transistor, LVGL is the first voltage line, S10 is the first electrode of the tenth transistor, and D10 is the second electrode of the tenth transistor.

[0436] In FIG. 18B , the twenty-first source / drain pattern is labeled Y21 , and the tenth source / drain pattern is labeled Y10 .

[0437] In at least one embodiment of the present disclosure, the twenty-first source-drain pattern includes the first electrode and the second electrode of the twenty-first transistor, and the tenth source-drain pattern includes the first electrode and the second electrode of the tenth transistor.

[0438] In FIG19 , the seventh connection structure is labeled L7.

[0439] In FIG20 , the transistor labeled M18 is the eighteenth transistor, and the transistor labeled M17 is the seventeenth transistor.

[0440] In FIG21 , RST is a reset terminal, CR is a carry signal output terminal, G18 is a gate of the eighteenth transistor, and G17 is a gate of the seventeenth transistor.

[0441] In FIG22 , the pattern labeled A18 is the eighteenth active pattern, and the pattern labeled A17 is the seventeenth active pattern.

[0442] In at least one embodiment of the present disclosure, the eighteenth active pattern may be an active pattern of an eighteenth transistor, and the seventeenth active pattern may be an active pattern of a seventeenth transistor.

[0443] In Figure 23A, the first voltage line is labeled LVGL, the clock signal line is labeled CLK, the second voltage line is labeled VGL, the first electrode of the eighteenth transistor is labeled S18, the second electrode of the eighteenth transistor is labeled D18, the first electrode of the seventeenth transistor is labeled S17, and the second electrode of the seventeenth transistor is labeled D17.

[0444] In FIG. 23B , the eighteenth source / drain pattern is labeled Y18 , and the seventeenth source / drain pattern is labeled Y17 .

[0445] In at least one embodiment of the present disclosure, the eighteenth source-drain pattern may include the first electrode and the second electrode of the eighteenth transistor, and the seventeenth source-drain pattern may include the first electrode and the second electrode of the seventeenth transistor.

[0446] In FIG24 , the eighth connection structure is labeled L8.

[0447] In FIG25 , LVGL is the first voltage line, VGL is the second voltage line, O1 is the driving signal output terminal, M15 is the fifteenth transistor, and M14 is the fourteenth transistor.

[0448] In FIG26 , RST is a reset terminal, CR is a carry signal output terminal, G15 is a gate of the fifteenth transistor, and G14 is a gate of the fourteenth transistor.

[0449] As shown in FIG. 26 , a first via hole H1 is provided between G14 and G15 to facilitate heat dissipation.

[0450] In FIG27 , the pattern labeled A15 is the fifteenth active pattern, and the pattern labeled A14 is the fourteenth active pattern.

[0451] In at least one embodiment of the present disclosure, the fifteenth active pattern may be an active pattern of a fifteenth transistor, and the fourteenth active pattern may be an active pattern of a fourteenth transistor.

[0452] In Figure 28A, LVGL is the first voltage line, VGL is the second voltage line, CLK is the clock signal line, O1 is the drive signal output terminal, S15 is the first electrode of the fifteenth transistor, D15 is the second electrode of the fifteenth transistor, S14 is the first electrode of the fourteenth transistor, and D14 is the second electrode of the fourteenth transistor.

[0453] In FIG. 28B , the fifteenth source / drain pattern is labeled Y15 , and the fourteenth source / drain pattern is labeled Y14 .

[0454] In at least one embodiment of the present disclosure, the fifteenth source-drain pattern may include the first electrode and the second electrode of the fifteenth transistor, and the fourteenth source-drain pattern may include the first electrode and the second electrode of the fourteenth transistor.

[0455] In FIG29 , the ninth connection structure is labeled L9.

[0456] In FIG30 , M9 is a ninth transistor, VGL is a second voltage line, and O1 is a driving signal output terminal.

[0457] In FIG31 , G9 is the gate of the ninth transistor, RST is the reset terminal, and CR is the carry signal output terminal.

[0458] In FIG32, the ninth active pattern is labeled A9.

[0459] In at least one embodiment of the present disclosure, the ninth active pattern may be an active pattern of a ninth transistor.

[0460] In FIG33A , VGL is the second voltage line, CLK is the clock signal line, O1 is the drive signal output terminal, S9 is the first electrode of the ninth transistor, and D9 is the second electrode of the ninth transistor.

[0461] In FIG33B , VGL is the second voltage line, CLK is the clock signal line, O1 is the driving signal output terminal, and Y9 is the ninth source-drain pattern.

[0462] In at least one embodiment of the present disclosure, the ninth source-drain pattern includes a first electrode of the ninth transistor and a second electrode of the ninth transistor.

[0463] In Figure 34, the first input terminal is labeled I1, the reset terminal is labeled RST, the drive signal output terminal is labeled O1, the carry signal output terminal is labeled CR, the tenth connection structure is labeled L10, the eleventh connection structure is labeled L11, the twelfth connection structure is labeled L12, the thirteenth connection structure is labeled L13, the fourteenth connection structure is labeled L14, and the fifteenth connection structure is labeled L15.

[0464] In FIG35 , the terminal labeled I1 is the first input terminal, the terminal labeled RST is the reset terminal, and the terminal labeled CR is the carry signal output terminal.

[0465] In Figure 36, the second voltage line is labeled VGL, the clock signal line is labeled CLK, the drive signal output terminal is labeled O1, the third connection part is labeled B3, the fourth connection part is labeled B4, the fifth connection part is labeled B5, the sixth connection part is labeled B6, and the seventh connection part is labeled B7.

[0466] In Figure 37, the one labeled L10 is the tenth connection structure, the one labeled L11 is the eleventh connection structure, the one labeled L12 is the twelfth connection structure, the one labeled L13 is the thirteenth connection structure, the one labeled L14 is the fourteenth connection structure, and the one labeled L15 is the fifteenth connection structure.

[0467] In FIG38 , VGL is the second voltage line, O1 is the drive signal output terminal, CR is the carry signal output terminal, CLK is the clock signal line, and M19 is the nineteenth transistor.

[0468] In FIG39 , the gate electrode of the nineteenth transistor is labeled G19.

[0469] In FIG40, the pattern labeled A19 is the nineteenth active pattern.

[0470] In at least one embodiment of the present disclosure, the nineteenth active pattern may be an active pattern of a nineteenth transistor.

[0471] In Figure 41A, the first voltage line is labeled VGL, the drive signal output terminal is labeled O1, the carry signal output terminal is labeled CR, the clock signal line is labeled CLK, the first electrode of the nineteenth transistor is labeled S19, and the second electrode of the nineteenth transistor is labeled D19.

[0472] In FIG41B , the nineteenth source / drain pattern is labeled Y19.

[0473] In at least one embodiment of the present disclosure, the nineteenth source-drain pattern includes a first electrode of the nineteenth transistor and a second electrode of the nineteenth transistor.

[0474] In FIG42A , the first circuit unit is labeled U1 and the second circuit unit is labeled U2. Five repeating units may be provided between the first circuit unit U1 and the second circuit unit U2. The structure of the repeating units is the same as that of the first circuit unit U1.

[0475] In FIG43 , CLK is a clock signal line, M16-1 is a first portion of a sixteenth transistor, and C1-1 is a first portion of a first capacitor.

[0476] In FIG44 , the first portion of the gate of the sixteenth transistor is labeled G16 - 1 , and the first portion G16 - 1 of the gate of the sixteenth transistor is reused as the first portion of the first plate of the first capacitor.

[0477] In FIG. 45 , reference numeral A16 - 1 designates a first portion of an active pattern of a sixteenth transistor.

[0478] In FIG46 , O1 is a driving signal output terminal, S16-1 is a first portion of a first electrode of a sixteenth transistor, D16-1 is a first portion of a second electrode of a sixteenth transistor, and C1b-1 is a first portion of a second plate of a first capacitor. Referring to FIG43 , in this embodiment, in order to improve the driving capability of a sixteenth transistor M16 included in the output circuit, a plurality of repeating units having the same structure as M16-1 are provided, and M16-1 and the plurality of repeating units are connected together, and M16-1 and the adjacent repeating units are connected together. A first part C1-1 of the first capacitor is arranged between the repeated units, and a part of the first capacitor can be arranged between two adjacent repeated units; that is, multiple groups of repeated M16-1 and C1-1 are alternately arranged and arranged along one direction, for example, along the extension direction of the gate line included in the display panel. This arrangement can not only ensure the driving capability of the output transistor (the output transistor can be the sixteenth transistor included in the output circuit), but also reduce the position occupied by the transistor arrangement in the column direction, for high-resolution products, such as 8K or 16K products.

[0479] In FIG47 , CLK is a clock signal line, M16-2 is a second portion of the sixteenth transistor, VGL is a second voltage line, and L16 is a sixteenth connection structure.

[0480] In at least one embodiment of the present disclosure, as shown in Figure 51, the sixteenth connection structure L16 can be formed in a conductive layer to realize electrical connection between the driving signal output end of the driving circuit and the second electrode of the sixteenth transistor included in the output circuit. The driving signal output end can be formed in the gate metal layer, and the second electrode of the sixteenth transistor can be formed in the source and drain metal layer.

[0481] In FIG48 , G16-2 is the second portion of the gate of the sixteenth transistor, and B8 is the eighth connection portion.

[0482] In FIG49, reference numeral A16-2 denotes a second portion of the active pattern of the sixteenth transistor.

[0483] In Figure 50, labeled O1 is the driving signal output terminal, labeled S16-2 is the second part of the first electrode of the sixteenth transistor, labeled D16-2 is the second part of the second electrode of the sixteenth transistor, labeled VGL is the second voltage line, and labeled B9 is the ninth connection part.

[0484] In FIG51 , the sixteenth connection structure is labeled L16.

[0485] In Figure 52, the first control voltage line is labeled VDDO, the second control voltage line is labeled VDDE, the clock signal line is labeled CLK, the first connection structure is labeled L1, the second connection structure is labeled L2, the eleventh transistor is labeled M11, the first transistor is labeled M1, the second transistor is labeled M2, the third transistor is labeled M3, the fourth transistor is labeled M4, the fifth transistor is labeled M5, the sixth transistor is labeled M6, and the seventh transistor is labeled M7.

[0486] In FIG53 , A11 is the eleventh active pattern, A1 is the first active pattern, A2 is the second active pattern, A3 is the third active pattern, A4 is the fourth active pattern, A5 is the fifth active pattern, A6 is the sixth active pattern, and A7 is the seventh active pattern.

[0487] Figures 3A and 3B are layout diagrams of a first portion of the 17T1C drive circuit shown in Figure 1 , Figure 10 is a layout diagram of a second portion of the 17T1C drive circuit shown in Figure 1 , Figure 15 is a layout diagram of a third portion of the 17T1C drive circuit shown in Figure 1 , Figure 20 is a layout diagram of a fourth portion of the 17T1C drive circuit shown in Figure 1 , Figure 25 is a layout diagram of a fifth portion of the 17T1C drive circuit shown in Figure 1 , Figure 30 is a layout diagram of a sixth portion of the 17T1C drive circuit shown in Figure 1 , Figure 34 is a layout diagram of a seventh portion of the 17T1C drive circuit shown in Figure 1 , Figure 38 is a layout diagram of an eighth portion of the 17T1C drive circuit shown in Figure 1 , and Figure 42A is a layout diagram of a ninth portion of the 17T1C drive circuit shown in Figure 1 .

[0488] In FIG. 3A , FIG. 3B , FIG. 10 , FIG. 15 , FIG. 20 , FIG. 25 , FIG. 30 , FIG. 34 , FIG. 38 , and FIG. 42A , the transistors included in the 17T1C driving circuit are all oxide transistors.

[0489] In at least one embodiment of the present disclosure, the first part of the driving circuit of the 17T1C shown in Figure 3A, the second part of the driving circuit of the 17T1C shown in Figure 10, the third part of the driving circuit of the 17T1C shown in Figure 15, the fourth part of the driving circuit of the 17T1C shown in Figure 20, the fifth part of the driving circuit of the 17T1C shown in Figure 25, the sixth part of the driving circuit of the 17T1C shown in Figure 30, the seventh part of the driving circuit of the 17T1C shown in Figure 34, the eighth part of the driving circuit of the 17T1C shown in Figure 38 and the ninth part of the driving circuit of the 17T1C shown in Figure 42A are arranged in sequence along a direction close to the display area.

[0490] Figures 4A and 4B are layout diagrams of a first portion of the 21T1C drive circuit shown in Figure 2 , Figure 10 is a layout diagram of a second portion of the 21T1C drive circuit shown in Figure 2 , Figure 15 is a layout diagram of a third portion of the 21T1C drive circuit shown in Figure 2 , Figure 20 is a layout diagram of a fourth portion of the 21T1C drive circuit shown in Figure 2 , Figure 25 is a layout diagram of a fifth portion of the 21T1C drive circuit shown in Figure 2 , Figure 30 is a layout diagram of a sixth portion of the 21T1C drive circuit shown in Figure 2 , Figure 34 is a layout diagram of a seventh portion of the 21T1C drive circuit shown in Figure 2 , Figure 38 is a layout diagram of an eighth portion of the 21T1C drive circuit shown in Figure 2 , and Figure 42A is a layout diagram of a ninth portion of the 21T1C drive circuit shown in Figure 2 .

[0491] In FIG. 4A , FIG. 4B , FIG. 10 , FIG. 15 , FIG. 20 , FIG. 25 , FIG. 30 , FIG. 34 , FIG. 38 , and FIG. 42A , the transistors included in the 21T1C driving circuit are all oxide transistors.

[0492] In at least one embodiment of the present disclosure, the first part of the driving circuit of 21T1C shown in Figure 4A, the second part of the driving circuit of 21T1C shown in Figure 10, the third part of the driving circuit of 21T1C shown in Figure 15, the fourth part of the driving circuit of 21T1C shown in Figure 20, the fifth part of the driving circuit of 21T1C shown in Figure 25, the sixth part of the driving circuit of 21T1C shown in Figure 30, the seventh part of the driving circuit of 21T1C shown in Figure 34, the eighth part of the driving circuit of 21T1C shown in Figure 38, and the ninth part of the driving circuit of 21T1C shown in Figure 42A are arranged in sequence along a direction close to the display area.

[0493] As shown in FIG3A , although the 17T1C driving circuit does not include the first transistor, the third transistor, the fifth transistor, and the seventh transistor, the layout diagram of the 17T1C driving circuit shown in FIG3A is provided with a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion. The first conductive portion is composed of a first gate pattern G1 and a first active pattern A1, the second conductive portion is composed of a third gate pattern G3 and a third active pattern A3, the third conductive portion is composed of a fifth gate pattern G5 and a fifth active pattern A5, and the fourth conductive portion is composed of a seventh gate pattern G7 and a seventh active pattern A7. This allows conversion between a 17T1C driving circuit using oxide transistors and a 21T1C driving circuit using oxide transistors to be achieved by simply changing the mask of the source / drain metal layer.

[0494] In at least one embodiment of the present disclosure, a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion may be reserved in a 15T1C driving circuit architecture. By changing a source / drain metal layer mask, the 15T1C driving circuit may be converted into a 19T1C driving circuit.

[0495] FIG54 is a circuit diagram of at least one embodiment of a 15T1C driving circuit, and FIG55 is a circuit diagram of at least one embodiment of a 19T1C driving circuit.

[0496] The difference between at least one embodiment of the 15T1C driving circuit shown in FIG54 and at least one embodiment of the 17T1C driving circuit shown in FIG1 is that M14 and M15 are not provided.

[0497] The difference between at least one embodiment of the 15T1C driving circuit shown in FIG55 and at least one embodiment of the 17T1C driving circuit shown in FIG2 is that M14 and M15 are not provided.

[0498] Optionally, the output circuit includes a sixteenth transistor; a gate of the sixteenth transistor is electrically connected to the pull-up node, a first electrode of the sixteenth transistor is electrically connected to the clock signal line, and a second electrode of the sixteenth transistor is electrically connected to the drive signal output terminal;

[0499] The first electrode of the ninth transistor includes N first electrode portions, and the second electrode of the ninth transistor includes N second electrode portions;

[0500] The first electrode of the sixteenth transistor includes M first electrode portions, and the second electrode of the sixteenth transistor includes M second electrode portions;

[0501] The nth first electrode portion of the ninth transistor and the nth second electrode portion of the ninth transistor are provided in the nth first source-drain region;

[0502] The m-th first electrode portion of the sixteenth transistor and the m-th second electrode portion of the sixteenth transistor are provided in the m-th second source-drain region;

[0503] N and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M.

[0504] Optionally, the active pattern included in the transistor in the driving circuit includes at least one strip-shaped active pattern portion; or,

[0505] The transistor in the driving circuit includes an active pattern that is a block-shaped active pattern.

[0506] In at least one embodiment of the present disclosure, the oxide transistor may be an IGZO (Indium Gallium Zinc Oxide) transistor.

[0507] Since the on-current of IGZO transistors is larger than that of a-Si (amorphous silicon) transistors, they generate more heat, and the threshold voltage of transistors drifts and increases with increasing temperature. In order to extend the high-temperature life of the driving circuit, sufficient heat dissipation space must be reserved when manufacturing driving circuits using oxide transistors. The active pattern of the oxide transistors can be set as a single row or multiple rows of strips. At the same time, larger oxide transistors use a multi-branch structure.

[0508] As shown in FIG6 , the eleventh active pattern A11 includes two strip-shaped active pattern portions, the third active pattern A3 includes two strip-shaped active pattern portions, the seventh active pattern A7 includes two strip-shaped active pattern portions, the second active pattern A2 includes two strip-shaped active pattern portions, the sixth active pattern A6 includes two strip-shaped active pattern portions, and the fourth active pattern A4 includes two strip-shaped active pattern portions.

[0509] As shown in FIG. 12 , the eighth active pattern A8 includes three stripe-shaped active pattern portions, the twelfth active pattern A12 includes four stripe-shaped active pattern portions, the thirteenth active pattern A13 includes four stripe-shaped active pattern portions, and the twentieth active pattern A20 includes two stripe-shaped active pattern portions.

[0510] As shown in FIG. 17 , the twenty-first active pattern A21 includes two stripe-shaped active pattern portions, and the tenth active pattern A10 includes eight stripe-shaped active pattern portions.

[0511] As shown in FIG. 22 , the eighteenth active pattern A18 includes four stripe-shaped active pattern portions, and the seventeenth active pattern A17 includes four stripe-shaped active pattern portions.

[0512] As shown in FIG. 32 , the ninth active pattern A9 includes six stripe-shaped active pattern portions.

[0513] As shown in FIG. 40 , the nineteenth active pattern A19 includes twenty-five stripe-shaped active pattern portions.

[0514] As shown in FIG42A, the active pattern of the sixteenth transistor includes twenty-eight stripe-shaped active pattern portions.

[0515] As shown in FIG. 3A to FIG. 51 , in a driving circuit using oxide transistors, the active pattern of each transistor may include at least one strip-shaped active pattern portion to facilitate heat dissipation.

[0516] In at least one embodiment of the present disclosure, when the size of the oxide transistor is larger, the active pattern of the oxide transistor includes more strip-shaped active pattern portions, but the present invention is not limited thereto.

[0517] In at least one embodiment of the present disclosure, when the active pattern of the oxide transistor includes at least two strip-shaped active pattern portions, the shortest distance between adjacent strip-shaped active pattern portions is greater than or equal to 4.5 um to enable good heat dissipation.

[0518] As shown in FIG33A , FIG33B and FIG33C , the first electrode of the ninth transistor includes three first electrode portions, and the second electrode of the ninth transistor includes three second electrode portions;

[0519] As shown in FIG33C , the first electrode portion included in the first electrode of the ninth transistor and the first second electrode portion included in the second electrode of the ninth transistor are disposed in the first first source-drain region Q11 ;

[0520] The second first electrode portion included in the first electrode of the ninth transistor and the second second electrode portion included in the second electrode of the ninth transistor are disposed in the second first source-drain region Q21;

[0521] The third first electrode portion included in the first electrode of the ninth transistor and the third second electrode portion included in the second electrode of the ninth transistor are disposed in the third first source-drain region Q31 .

[0522] In at least one embodiment of the present disclosure, by dividing the source-drain pattern of the ninth transistor into three parts and arranging them in three different first source-drain regions, heat dissipation can be facilitated, and the layout of transistors in the driving circuit can be facilitated in high-resolution display products.

[0523] As shown in FIG42B , the first electrode of the ninth transistor includes three first electrode portions, and the second electrode of the ninth transistor includes three second electrode portions;

[0524] As shown in FIG42B , the first electrode portion included in the first electrode of the sixteenth transistor and the first second electrode portion included in the second electrode of the sixteenth transistor are disposed in the first second source-drain region Q12 ;

[0525] The second first electrode portion included in the first electrode of the sixteenth transistor and the second second electrode portion included in the second electrode of the sixteenth transistor are disposed in the second second source-drain region Q22;

[0526] The third first electrode portion included in the first electrode of the sixteenth transistor and the third second electrode portion included in the second electrode of the sixteenth transistor are disposed in the third second source-drain region Q32;

[0527] The fourth first electrode portion included in the first electrode of the sixteenth transistor and the fourth second electrode portion included in the second electrode of the sixteenth transistor are disposed in the fourth second source-drain region Q42;

[0528] The fifth first electrode portion included in the first electrode of the sixteenth transistor and the fifth second electrode portion included in the second electrode of the sixteenth transistor are disposed in the fifth second source-drain region Q52;

[0529] The sixth first electrode portion included in the first electrode of the sixteenth transistor and the sixth second electrode portion included in the second electrode of the sixteenth transistor are disposed in the sixth second source-drain region Q62;

[0530] The seventh first electrode portion included in the first electrode of the sixteenth transistor and the seventh second electrode portion included in the second electrode of the sixteenth transistor are disposed in the seventh second source-drain region Q72 .

[0531] In at least one embodiment of the present disclosure, by dividing the source-drain pattern of the sixteenth transistor into seven parts and arranging them in seven different second source-drain regions, heat dissipation can be facilitated, and the layout of transistors in the driving circuit can be facilitated in high-resolution display products.

[0532] As shown in FIG18A and FIG18B , the source-drain pattern of the tenth transistor can be divided into four parts and respectively arranged in four different source-drain regions to dissipate heat and facilitate the layout of transistors in the driving circuit in high-resolution display products;

[0533] As shown in Figures 23A and 23B, the source-drain pattern of the seventeenth transistor can be divided into two parts and respectively arranged in two different source-drain regions; the source-drain pattern of the eighteenth transistor can be divided into two parts and respectively arranged in two different source-drain regions to facilitate heat dissipation and facilitate the layout of transistors in the driving circuit in high-resolution display products.

[0534] As shown in FIG41A and FIG41B, the source-drain pattern of the nineteenth transistor can be divided into five parts and respectively arranged in different source-drain regions to facilitate heat dissipation and facilitate the layout of transistors in the driving circuit in high-resolution display products.

[0535] Optionally, the driving circuit further includes a carry output circuit, and the carry output circuit includes a nineteenth transistor;

[0536] The gate of the nineteenth transistor is electrically connected to the pull-up node, the first electrode of the nineteenth transistor is electrically connected to the clock signal line, and the second electrode of the nineteenth transistor is electrically connected to the carry signal output terminal;

[0537] The ninth transistor is an oxide transistor, and a width-to-length ratio of the ninth transistor is greater than or equal to 300 / 9 and less than or equal to 900 / 5; or the ninth transistor is an amorphous silicon transistor, and a width-to-length ratio of the ninth transistor is greater than or equal to 1400 / 4.6 and less than or equal to 2200 / 3.9;

[0538] The tenth transistor is an oxide transistor, and a width-to-length ratio of the tenth transistor is greater than or equal to 150 / 9 and less than or equal to 200 / 5; or the tenth transistor is an amorphous silicon transistor, and a width-to-length ratio of the tenth transistor is greater than or equal to 800 / 4.6 and less than or equal to 1400 / 3.9;

[0539] The sixteenth transistor is an oxide transistor, and a width-to-length ratio of the sixteenth transistor is greater than or equal to 1000 / 9 and less than or equal to 3000 / 5; or the sixteenth transistor is an amorphous silicon transistor, and a width-to-length ratio of the sixteenth transistor is greater than or equal to 10000 / 4.6 and less than or equal to 22000 / 3.9;

[0540] The nineteenth transistor is an oxide transistor, and the width-to-length ratio of the nineteenth transistor is greater than or equal to 750 / 9 and less than or equal to 1000 / 5; or, the nineteenth transistor is an amorphous silicon transistor, and the width-to-length ratio of the nineteenth transistor is greater than or equal to 1500 / 4.6 and less than or equal to 2200 / 3.9.

[0541] In at least one embodiment of the present disclosure, when each transistor is an oxide transistor, the width of the channel of the ninth transistor may be greater than or equal to 300um and less than or equal to 900um, the width of the channel of the tenth transistor may be greater than or equal to 150um and less than or equal to 200um, the width of the channel of the sixteenth transistor may be greater than or equal to 1000um and less than or equal to 3000um, the width of the channel of the second transistor and the width of the channel of the sixth transistor may be greater than or equal to 15um and less than or equal to 30um, the width of the channel of the fourth transistor and the width of the channel of the eighth transistor may be greater than or equal to 110um and less than or equal to 250um, and the width of the channel of the eleventh transistor may be greater than or equal to 1000um. The channel width of the first transistor and the channel width of the fifth transistor may be greater than or equal to 10um and less than or equal to 30um, the channel width of the twelfth transistor and the channel width of the thirteenth transistor may be greater than or equal to 90um and less than or equal to 120um, the channel width of the seventeenth transistor and the channel width of the eighteenth transistor may be greater than or equal to 160um and less than or equal to 240um, the channel width of the twentieth transistor and the channel width of the twenty-first transistor may be greater than or equal to 40um and less than or equal to 80um, the channel width of the nineteenth transistor may be greater than or equal to 750um and less than or equal to 1000um, the channel width of the fourteenth transistor and the channel width of the fifteenth transistor may be greater than or equal to 80um and less than or equal to 120um, and the length of the channel of the above transistors may be greater than or equal to 5um and less than or equal to 9um.

[0542] In at least one embodiment of the present disclosure, when each transistor is an amorphous silicon transistor, the width of the channel of the ninth transistor may be greater than or equal to 1400um and less than or equal to 2200um, the width of the channel of the tenth transistor may be greater than or equal to 800um and less than or equal to 1000um, the width of the channel of the sixteenth transistor may be greater than or equal to 10000um and less than or equal to 22000um, the width of the channel of the second transistor and the width of the channel of the sixth transistor may be greater than or equal to 100um and less than or equal to 160um, the width of the channel of the fourth transistor and the width of the channel of the eighth transistor may be greater than or equal to 500um and less than or equal to 800um, the width of the channel of the eleventh transistor may be greater than or equal to 400um and less than or equal to 600um, the width of the channel of the third transistor and the width of the channel of the seventh transistor may be greater than or equal to 60um and less than or equal to 350um, and the width of the channel of the eleventh transistor may be greater than or equal to 500um and less than or equal to 600um. The width of the channel of the first transistor and the width of the channel of the fifth transistor may be greater than or equal to 30um and less than or equal to 60um, the width of the channel of the twelfth transistor and the width of the channel of the thirteenth transistor may be greater than or equal to 500um and less than or equal to 700um, the width of the channel of the seventeenth transistor and the width of the channel of the eighteenth transistor may be greater than or equal to 1000um and less than or equal to 1500um, the width of the channel of the twentieth transistor and the width of the channel of the twenty-first transistor may be greater than or equal to 300um and less than or equal to 600um, the width of the channel of the nineteenth transistor may be greater than or equal to 1500um and less than or equal to 2200um, the width of the channel of the fourteenth transistor and the width of the channel of the fifteenth transistor may be greater than or equal to 300um and less than or equal to 800um, and the length of the channel of the above transistors may be greater than or equal to 3.9um and less than or equal to 4.6um.

[0543] FIG52 is a layout diagram of a first portion of the 21T1C driving circuit shown in FIG2 when the transistors in the 21T1C driving circuit shown in FIG2 are a-Si (amorphous silicon) transistors. FIG53 is a layout diagram of the semiconductor layer in FIG52.

[0544] The layout diagram of the gate metal layer in Figure 52 is shown in Figure 5, the layout diagram of the source and drain metal layers in Figure 52 is shown in Figures 9A and 9B, and the conductive layer in Figure 52 is shown in Figure 8.

[0545] The difference between the layout diagram of the first part of the circuit of the 21T1C driving circuit using amorphous silicon transistors shown in FIG52 and the layout diagram of the first part of the circuit of the 21T1C driving circuit using oxide transistors shown in FIG4A is that the active pattern of each transistor in the semiconductor layer is a block active pattern.

[0546] In at least one embodiment of the present disclosure, the difference between the layout of a 21T1C driving circuit using amorphous silicon transistors and the layout of a 21T1C driving circuit using oxide transistors is that:

[0547] In the semiconductor layer, the active pattern of each transistor is a block-shaped active pattern;

[0548] In the layout diagram of a 21T1C driving circuit using oxide transistors, the source / drain patterns of some transistors in the 21T1C driving circuit are divided into at least two parts in the source / drain metal layer. In the layout diagram of a 21T1C driving circuit using amorphous silicon oxide transistors, the source / drain patterns of all transistors in the 21T1C driving circuit are formed into a single part in the source / drain metal layer. That is, by changing two masks (the two masks may be the mask used when manufacturing the semiconductor layer and the mask used when manufacturing the source / drain metal layer), the conversion between a driving circuit using oxide transistors and a driving circuit using amorphous silicon transistors can be achieved.

[0549] Figure 56 is a layout diagram of the tenth transistor when the tenth transistor is an oxide transistor, Figure 57 is a layout diagram of the gate metal layer in Figure 56, Figure 58 is a layout diagram of the semiconductor layer in Figure 56, and Figure 58 is a layout diagram of the source and drain metal layer in Figure 56.

[0550] FIG60 is a layout diagram of the tenth transistor when the tenth transistor is an amorphous silicon transistor, FIG61 is a layout diagram of the semiconductor layer in FIG60, and FIG62 is a layout diagram of the source / drain metal layer in FIG60;

[0551] The layout diagram of the gate metal layer in Figure 60 is shown in Figure 57.

[0552] In FIG56 , the transistor labeled M10 is the tenth transistor, and the transistor labeled LVGL is the first voltage line.

[0553] In FIG57 , the gate electrode of the tenth transistor is labeled G10.

[0554] In FIG58, the tenth active pattern is labeled A10.

[0555] In FIG59 , S10 is the first electrode of the tenth transistor, D10 is the second electrode of the tenth transistor, and LVGL is the first voltage line.

[0556] In FIG60 , the transistor labeled M10 is the tenth transistor, and the transistor labeled LVGL is the first voltage line.

[0557] In FIG61, the tenth active pattern is labeled A10.

[0558] In FIG62 , S10 is the first electrode of the tenth transistor, D10 is the second electrode of the tenth transistor, and LVGL is the first voltage line.

[0559] FIG63 is a combined diagram of the layout diagram of the first portion of the 17T1C driving circuit shown in FIG3A and the layout diagram of the second portion of the driving circuit shown in FIG10 . In FIG63 , the first region is labeled Q1 .

[0560] FIG64 is a combined diagram of the layout diagram of the first portion of the 21T1C driving circuit shown in FIG4A and the layout diagram of the second portion of the driving circuit shown in FIG10 . In FIG64 , the first region is labeled Q1 .

[0561] As shown in FIG. 63 and FIG. 64 , the first pull-down node control circuit included in the driving circuit and the second pull-down node control circuit included in the driving circuit are provided in the first region Q1 .

[0562] In at least one embodiment of the present disclosure, when the number of clock signal lines used by the driving module (the driving module includes a multi-stage driving circuit) is the same, the cascade relationship of the 17T1C driving circuit is the same as the cascade relationship of the 21T1C driving circuit, and the timing of the 17T1C driving circuit is the same as the timing of the 21T1C driving circuit. The design of reserving the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion proposed in at least one embodiment of the present disclosure does not affect the cascade relationship and timing. Taking the driving module including 16 clock signal lines as an example, the input signals connected to the first input terminals of the first eight rows of driving circuits are all provided by the start signal line S0, the input signals connected to the first input terminal of the a-th row driving circuit are all provided by the carry signal output terminal of the a+8-th row driving circuit, and the carry signal output terminal of the a-th row driving circuit provides a reset signal to the reset terminal of the a-10-th row driving circuit; a is a positive integer.

[0563] In FIG65 , the first row driving circuit included in the driving module is labeled ST1, the second row driving circuit included in the driving module is labeled ST2, the third row driving circuit included in the driving module is labeled ST3, the fourth row driving circuit included in the driving module is labeled ST4, the fifth row driving circuit included in the driving module is labeled ST5, the sixth row driving circuit included in the driving module is labeled ST6, the seventh row driving circuit included in the driving module is labeled ST7, the eighth row driving circuit included in the driving module is labeled ST8, and the eighth row driving circuit included in the driving module is labeled ST9. ST9 is the ninth row driving circuit included in the driving module, ST10 is the tenth row driving circuit included in the driving module, ST11 is the eleventh row driving circuit included in the driving module, ST12 is the twelfth row driving circuit included in the driving module, ST13 is the thirteenth row driving circuit included in the driving module, ST14 is the fourteenth row driving circuit included in the driving module, ST15 is the fifteenth row driving circuit included in the driving module, and ST16 is the sixteenth row driving circuit included in the driving module;

[0564] ST1 is electrically connected to the first clock signal line CLK1, ST2 is electrically connected to the second clock signal line CLK2, ST3 is electrically connected to the third clock signal line CLK3, ST4 is electrically connected to the fourth clock signal line CLK4, ST5 is electrically connected to the fifth clock signal line CLK5, ST6 is electrically connected to the sixth clock signal line CLK6, ST7 is electrically connected to the seventh clock signal line CLK7, ST8 is electrically connected to the eighth clock signal line CLK8, ST9 is electrically connected to the ninth clock signal line CLK9, ST10 is electrically connected to the tenth clock signal line CLK10, ST11 is electrically connected to the eleventh clock signal line CLK11, ST12 is electrically connected to the twelfth clock signal line CLK12, ST13 is electrically connected to the thirteenth clock signal line CLK13, ST14 is electrically connected to the fourteenth clock signal line CLK14, ST15 is electrically connected to the fifteenth clock signal line CLK15, and ST16 is electrically connected to the sixteenth clock signal line CLK16;

[0565] a first input terminal of ST1, a first input terminal of ST3, a first input terminal of ST5, and a first input terminal of ST7 are electrically connected to a first start signal line S01, a first input terminal of ST2, a first input terminal of ST4, a first input terminal of ST6, and a first input terminal of ST8 are electrically connected to a second start signal line S02, a first input terminal of ST9 is electrically connected to a carry signal output terminal of ST1, a first input terminal of ST10 is electrically connected to a carry signal output terminal of ST2, a first input terminal of ST11 is electrically connected to a carry signal output terminal of ST3, a first input terminal of ST12 is electrically connected to a carry signal output terminal of ST4, a first input terminal of ST13 is electrically connected to a carry signal output terminal of ST5, a first input terminal of ST14 is electrically connected to a carry signal output terminal of ST6, a first input terminal of ST15 is electrically connected to a carry signal output terminal of ST7, and a first input terminal of ST16 is electrically connected to a carry signal output terminal of ST8;

[0566] The reset terminal of ST1 is electrically connected to the carry signal output terminal of ST11, the reset terminal of ST2 is electrically connected to the carry signal output terminal of ST12, the reset terminal of ST3 is electrically connected to the carry signal output terminal of ST13, the reset terminal of ST4 is electrically connected to the carry signal output terminal of ST14, the reset terminal of ST5 is electrically connected to the carry signal output terminal of ST15, the reset terminal of ST6 is electrically connected to the carry signal output terminal of ST16, the reset terminal of ST7 is electrically connected to the carry signal output terminal CR17 of the seventeenth row drive circuit, the reset terminal of ST8 is electrically connected to the carry signal output terminal CR18 of the eighteenth row drive circuit, and the reset terminal of ST9 is electrically connected to the carry signal output terminal CR19 of the nineteenth row drive circuit. In addition, the reset terminal of ST10 is electrically connected to the carry signal output terminal CR20 of the 20th row drive circuit, the reset terminal of ST11 is electrically connected to the carry signal output terminal CR21 of the 21st row drive circuit, the reset terminal of ST12 is electrically connected to the carry signal output terminal CR22 of the 22nd row drive circuit, the reset terminal of ST13 is electrically connected to the carry signal output terminal CR23 of the 23rd row drive circuit, the reset terminal of ST14 is electrically connected to the carry signal output terminal CR24 of the 24th row drive circuit, the reset terminal of ST15 is electrically connected to the carry signal output terminal CR25 of the 25th row drive circuit, and the reset terminal of ST16 is electrically connected to the carry signal output terminal CR26 of the 26th row drive circuit.

[0567] FIG66 is a timing diagram illustrating the operation of at least one embodiment of the driving module shown in FIG65 .

[0568] In FIG66 , the output terminal of the driving signal in the b-th row is labeled O1(b), where b is a positive integer.

[0569] The method for manufacturing an array substrate according to an embodiment of the present disclosure is used to manufacture the above-mentioned array substrate, and the method for manufacturing the array substrate includes:

[0570] Fabricating a pull-up node control circuit, a first pull-down node control circuit, and an output circuit on a base substrate;

[0571] A first conductive portion and a first control voltage line are fabricated on a base substrate, and the first conductive portion is electrically connected to the first control voltage line. In at least one embodiment of the present disclosure, the steps of fabricating the first conductive portion and the first control voltage line on the base substrate, and electrically connecting the first conductive portion to the first control voltage line include:

[0572] Fabricating a first metal layer on a base substrate, and patterning the first metal layer to form a first gate pattern, wherein the first gate pattern includes the first conductive portion;

[0573] forming a second metal layer on a side of the first metal layer away from the base substrate, and performing a patterning process on the second metal layer using a first mask to form a first control voltage line;

[0574] The first gate pattern is set to be electrically connected to the first control voltage line, and the first conductive portion and the second metal layer do not overlap in a direction perpendicular to the base substrate.

[0575] In a specific implementation, the first conductive portion and the second metal layer do not overlap in a direction perpendicular to the base substrate, that is, the orthographic projection of the first conductive portion on the base substrate does not overlap with the orthographic projection of the second metal layer on the base substrate.

[0576] In at least one embodiment of the present disclosure, when preparing a 17T1C driving circuit, a first mask can be used to perform a patterning process on the second metal layer (the second metal layer can be a source / drain metal layer) to form a first control voltage line. The first control voltage line is configured to be electrically connected to a first gate pattern included in the first conductive portion. At this time, there is no second metal layer above the first conductive portion whose orthographic projection overlaps with it.

[0577] Optionally, the first metal layer may be a gate metal layer, and the second metal layer may be a source / drain metal layer.

[0578] The step of manufacturing a first conductive portion and a first control voltage line on the base substrate and setting the first conductive portion to be electrically connected to the first control voltage line includes:

[0579] Fabricating a first metal layer on a base substrate, and patterning the first metal layer to form a first gate pattern, wherein the first gate pattern includes the first conductive portion;

[0580] A second metal layer is formed on a side of the first metal layer away from the base substrate, and a second mask is used to perform a composition process on the second metal layer to form a first control voltage line, and to form a first electrode of the first transistor and a second electrode of the first transistor; the orthographic projection of the first electrode of the first transistor on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the second electrode of the first transistor on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate.

[0581] In at least one embodiment of the present disclosure, when preparing a 21T1C driving circuit, a second mask can be used to perform a patterning process on the second metal layer (the second metal layer can be a source-drain metal layer) to form a first control voltage line, a first electrode of the first transistor, and a second electrode of the first transistor. In a direction perpendicular to the substrate, a projection of the first electrode of the first transistor at least partially overlaps with a projection of the first conductive portion, and a projection of the second electrode of the first transistor at least partially overlaps with a projection of the first conductive portion.

[0582] In at least one embodiment of the present disclosure, when patterning the second metal layer, either the first or second mask can be used to form a pattern formed on the second metal layer for a 17T1C driver circuit or a pattern formed on the second metal layer for a 21T1C driver circuit. The other masks used in fabricating the 17T1C driver circuit and the 21T1C driver circuit can be the same. In at least one embodiment of the present disclosure, conversion between a 17T1C driver circuit and a 21T1C driver circuit can be achieved by simply adding a single mask (which can be the mask used in fabricating the source and drain metal layers), effectively improving product compatibility while saving mask costs.

[0583] In at least one embodiment of the present disclosure, the method for manufacturing the array substrate may further include:

[0584] forming a conductive layer on a side of the second metal layer away from the base substrate, and performing a patterning process on the conductive layer to form a first connection structure;

[0585] Setting a first electrode of the first transistor to be electrically connected to a first control voltage line, and setting a second electrode of the first transistor to be electrically connected to the first connection structure;

[0586] The orthographic projection of at least part of the first electrode of the first transistor on the substrate is set to overlap with the orthographic projection of the first conductive part on the substrate, and the orthographic projection of at least part of the second electrode of the first transistor on the substrate is set to overlap with the orthographic projection of the first conductive part on the substrate.

[0587] The method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0588] performing a patterning process on the first metal layer to form a third gate pattern included in the second conductive portion;

[0589] The third gate pattern is disposed to be electrically connected to the pull-up node.

[0590] The method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0591] performing a patterning process on the second metal layer to form a first voltage line, a first electrode of the third transistor, and a second electrode of the third transistor;

[0592] Disposing a first electrode of the third transistor to be electrically connected to the first connection structure, and disposing a second electrode of the third transistor to be electrically connected to the first voltage line;

[0593] The orthographic projection of at least part of the first electrode of the third transistor on the substrate is set to overlap with the orthographic projection of the second conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the third transistor on the substrate is set to overlap with the orthographic projection of the second conductive portion on the substrate.

[0594] In at least one embodiment of the present disclosure, the method for manufacturing the array substrate further includes:

[0595] performing a patterning process on the first metal layer to form a fifth gate pattern included in the third conductive portion;

[0596] performing a patterning process on the second metal layer to form a second control voltage line;

[0597] The fifth gate pattern is configured to be electrically connected to the second control voltage line.

[0598] The method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0599] performing a patterning process on the second metal layer to form a first electrode of a fifth transistor and a second electrode of the fifth transistor;

[0600] performing a patterning process on the first conductive portion to form a second connection structure;

[0601] Disposing a first electrode of the fifth transistor to be electrically connected to the second control voltage line, and disposing a second electrode of the fifth transistor to be electrically connected to the second connection structure;

[0602] The orthographic projection of at least part of the first electrode of the fifth transistor on the substrate is set to overlap with the orthographic projection of the third conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the fifth transistor on the substrate is set to overlap with the orthographic projection of the third conductive portion on the substrate.

[0603] In at least one embodiment of the present disclosure, the method for manufacturing the array substrate further includes:

[0604] performing a patterning process on the first metal layer to form a seventh gate pattern included in the fourth conductive portion;

[0605] The seventh gate pattern is configured to be electrically connected to the pull-up node.

[0606] The method for manufacturing the array substrate according to at least one embodiment of the present disclosure further includes:

[0607] performing a patterning process on the second metal layer to form a first voltage line, a first electrode of the seventh transistor, and a second electrode of the seventh transistor;

[0608] Disposing a first electrode of the seventh transistor to be electrically connected to the second connection structure, and disposing a second electrode of the seventh transistor to be electrically connected to the first voltage line;

[0609] The orthographic projection of at least part of the first electrode of the seventh transistor on the substrate is set to overlap with the orthographic projection of the fourth conductive part on the substrate, and the orthographic projection of at least part of the second electrode of the seventh transistor on the substrate is set to overlap with the orthographic projection of the fourth conductive part on the substrate.

[0610] The display device described in the embodiment of the present disclosure includes the above-mentioned array substrate.

[0611] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. An array substrate, comprising a driving circuit disposed on a base substrate, wherein the driving circuit comprises a pull-up node control circuit, a first pull-down node control circuit and an output circuit; The pull-up node control circuit is electrically connected to the pull-up node and is used to control the potential of the pull-up node; The first pull-down node control circuit is electrically connected to the first control voltage line and the first pull-down node respectively, and is used to control the first control voltage provided by the first control voltage line to be written into the first pull-down node; The output circuit is electrically connected to the pull-up node and the drive signal output terminal respectively, and is used to control the drive signal output terminal to output a drive signal under the control of the potential of the pull-up node; The array substrate further comprises a first conductive portion disposed on the base substrate; The first conductive portion is electrically connected to the first control voltage line.

2. The array substrate according to claim 1, in, The shortest distance between an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the first control voltage line on the base substrate is greater than or equal to 4 um and less than or equal to 12 um.

3. The array substrate according to claim 1, in, The first conductive portion is composed of a first gate pattern; or, the first conductive portion is composed of a first gate pattern and a first active pattern; The first gate pattern is electrically connected to a first control voltage line.

4. The array substrate according to claim 3, in, The first pull-down node control circuit includes a second transistor; A gate of the second transistor is electrically connected to the first connection structure, a first electrode of the second transistor is electrically connected to the first control voltage line, and a second electrode of the second transistor is electrically connected to the first pull-down node.

5. The array substrate according to claim 4, in, The first connection structure is electrically connected to the first control voltage line.

6. The array substrate according to claim 4, in, The first pull-down node control circuit is further used to write a first voltage signal provided by a first voltage line into the first pull-down node; The array substrate further comprises a second conductive portion disposed on the base substrate; The second conductive portion is electrically connected to the pull-up node.

7. The array substrate according to claim 6, in, The second conductive portion is composed of a third gate pattern; or, the second conductive portion is composed of a third gate pattern and a third active pattern; The third gate pattern is electrically connected to the pull-up node.

8. The array substrate according to claim 6, in, The shortest distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first control voltage line on the substrate is greater than or equal to 4 um; The shortest distance between an orthographic projection of the second conductive portion on the base substrate and an orthographic projection of the first voltage line on the base substrate is greater than or equal to 4 um and less than or equal to 12 um.

9. The array substrate according to claim 6, in, The first pull-down node control circuit includes a fourth transistor; A gate of the fourth transistor is electrically connected to the pull-up node, a first electrode of the fourth transistor is electrically connected to the first pull-down node, and a second electrode of the fourth transistor is electrically connected to the first voltage line.

10. The array substrate according to claim 1, in, The driving circuit also includes a second pull-down node control circuit; The second pull-down node control circuit is electrically connected to the second control voltage line and the second pull-down node respectively, and is used to control the writing of the second control voltage provided by the second control voltage line into the second pull-down node; The array substrate further comprises a third conductive portion disposed on the base substrate; The third conductive portion is electrically connected to the second control voltage line.

11. The array substrate according to claim 10, in, The third conductive portion is composed of a fifth gate pattern; or, the third conductive portion is composed of a fifth gate pattern and a fifth active pattern.

12. The array substrate according to claim 10, in, The shortest distance between an orthographic projection of the third conductive portion on the substrate and an orthographic projection of the second control voltage line on the substrate is greater than or equal to 4 um and less than or equal to 12 um.

13. The array substrate according to claim 11, in, The second pull-down node control circuit includes a sixth transistor; A gate of the sixth transistor is electrically connected to the second connection structure, a first electrode of the sixth transistor is electrically connected to a second control voltage line, and a second electrode of the sixth transistor is electrically connected to a second pull-down node.

14. The array substrate according to claim 13, in, The second connection structure is electrically connected to a second control voltage line.

15. The array substrate according to claim 13, in, The second pull-down node control circuit is further used to write the first voltage signal provided by the first voltage line into the second pull-down node; The array substrate further comprises a fourth conductive portion disposed on the base substrate; The fourth conductive portion is electrically connected to the pull-up node.

16. The array substrate according to claim 15, in, The fourth conductive portion is composed of the seventh gate pattern; or, the fourth conductive portion is composed of the seventh gate pattern and the seventh active pattern; The seventh gate pattern is electrically connected to the pull-up node.

17. The array substrate according to claim 16, in, The shortest distance between the orthographic projection of the fourth conductive portion on the substrate and the orthographic projection of the second control voltage line on the substrate is greater than or equal to 4um, and the shortest distance between the orthographic projection of the fourth conductive portion on the substrate and the orthographic projection of the first voltage line on the substrate is greater than or equal to 4um and less than or equal to 12um.

18. The array substrate according to claim 15, in, The second pull-down node control circuit includes an eighth transistor; A gate of the eighth transistor is electrically connected to the pull-up node, a first electrode of the eighth transistor is electrically connected to the second pull-down node, and a second electrode of the eighth transistor is electrically connected to the first voltage line.

19. The array substrate according to claim 6, in, The array substrate further comprises a first source-drain metal pattern and a third source-drain metal pattern disposed on the base substrate; The first source-drain metal pattern includes a first electrode of the first transistor and a second electrode of the first transistor; A first electrode of the first transistor is electrically connected to the first control voltage line, and a second electrode of the first transistor is electrically connected to the first connection structure; An orthographic projection of at least a portion of a first electrode of the first transistor on the substrate overlaps with an orthographic projection of the first conductive portion on the substrate, and an orthographic projection of at least a portion of a second electrode of the first transistor on the substrate overlaps with an orthographic projection of the first conductive portion on the substrate; The third source-drain metal pattern includes a first electrode of a third transistor and a second electrode of the third transistor; A first electrode of the third transistor is electrically connected to the first connection structure, and a second electrode of the third transistor is electrically connected to the first voltage line; The orthographic projection of at least part of the first electrode of the third transistor on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the third transistor on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate.

20. The array substrate according to claim 15, in, The array substrate further comprises a fifth source-drain metal pattern disposed on the base substrate; the array substrate further comprises a seventh source-drain metal pattern disposed on the base substrate; The fifth source-drain metal pattern includes a first electrode of a fifth transistor and a second electrode of the fifth transistor; A first electrode of the fifth transistor is electrically connected to the second control voltage line, and a second electrode of the fifth transistor is electrically connected to the second connection structure; An orthographic projection of at least a portion of the first electrode of the fifth transistor on the substrate overlaps with an orthographic projection of the third conductive portion on the substrate, and an orthographic projection of at least a portion of the second electrode of the fifth transistor on the substrate overlaps with an orthographic projection of the third conductive portion on the substrate; The seventh source-drain metal pattern includes a first electrode of a seventh transistor and a second electrode of the seventh transistor; A first electrode of the seventh transistor is electrically connected to the second connection structure, and a second electrode of the seventh transistor is electrically connected to the first voltage line; The orthographic projection of at least part of the first electrode of the seventh transistor on the substrate overlaps with the orthographic projection of the fourth conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the seventh transistor on the substrate overlaps with the orthographic projection of the fourth conductive portion on the substrate.

21. The array substrate according to any one of claims 1 to 20, in, The pull-up node control circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; The gate of the ninth transistor is electrically connected to the first input terminal, the first electrode of the ninth transistor is electrically connected to the second input terminal, and the second electrode of the ninth transistor is electrically connected to the pull-up node; The gate of the tenth transistor is electrically connected to the reset terminal, the first electrode of the tenth transistor is electrically connected to the pull-up node, and the second electrode of the tenth transistor is electrically connected to the first voltage line; The gate of the eleventh transistor is electrically connected to the starting voltage line, the first electrode of the eleventh transistor is electrically connected to the pull-up node, and the second electrode of the eleventh transistor is electrically connected to the first voltage line; The gate of the twelfth transistor is electrically connected to the first pull-down node, the first electrode of the twelfth transistor is electrically connected to the pull-up node, and the second electrode of the twelfth transistor is electrically connected to the first voltage line; A gate of the thirteenth transistor is electrically connected to the second pull-down node, a first electrode of the twelfth transistor is electrically connected to the pull-up node, and a second electrode of the twelfth transistor is electrically connected to the first voltage line.

22. The array substrate according to any one of claims 3 to 20, in, The driving circuit further includes a first pull-down reset circuit and a second pull-down reset circuit; the first pull-down reset circuit includes a fourteenth transistor; the second pull-down reset circuit includes a fifteenth transistor; The gate of the fourteenth transistor is electrically connected to the first input terminal, the first electrode of the fourteenth transistor is electrically connected to the first pull-down node, and the second electrode of the fourteenth transistor is electrically connected to the first voltage line; A gate of the fifteenth transistor is electrically connected to the first input terminal, a first electrode of the fifteenth transistor is electrically connected to the second pull-down node, and a second electrode of the fourteenth transistor is electrically connected to the first voltage line.

23. The array substrate according to claim 21, in, The output circuit includes a sixteenth transistor; a gate of the sixteenth transistor is electrically connected to the pull-up node, a first electrode of the sixteenth transistor is electrically connected to the clock signal line, and a second electrode of the sixteenth transistor is electrically connected to the drive signal output terminal; The first electrode of the ninth transistor includes N first electrode portions, and the second electrode of the ninth transistor includes N second electrode portions; The first electrode of the sixteenth transistor includes M first electrode portions, and the sixteenth transistor The second electrode includes M second electrode portions; The nth first electrode portion of the ninth transistor and the nth second electrode portion of the ninth transistor are disposed in the nth first source-drain region; The m-th first electrode portion of the sixteenth transistor and the m-th second electrode portion of the sixteenth transistor are disposed in the m-th second source-drain region; N and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M.

24. The array substrate according to any one of claims 1 to 20, in, The active pattern included in the transistor in the driving circuit includes at least one strip-shaped active pattern portion; or, The transistor in the driving circuit includes an active pattern which is a block-shaped active pattern.

25. A method for manufacturing an array substrate, used for manufacturing the array substrate according to any one of claims 1 to 24, wherein the method for manufacturing the array substrate include: Fabricating a pull-up node control circuit, a first pull-down node control circuit and an output circuit on a substrate; A first conductive portion and a first control voltage line are manufactured on a base substrate, and the first conductive portion is arranged to be electrically connected to the first control voltage line.

26. The method for manufacturing an array substrate according to claim 25, in, The step of manufacturing a first conductive portion and a first control voltage line on the base substrate, and setting the first conductive portion to be electrically connected to the first control voltage line comprises: Manufacturing a first metal layer on the base substrate, and performing a patterning process on the first metal layer to form a first gate pattern, wherein the first gate pattern includes the first conductive portion; Manufacturing a second metal layer on a side of the first metal layer away from the base substrate, and performing a patterning process on the second metal layer using a first mask to form a first control voltage line; The first gate pattern is arranged to be electrically connected to the first control voltage line, and the first conductive portion and the second metal layer do not overlap in a direction perpendicular to the base substrate.

27. The method for manufacturing an array substrate according to claim 25, in, The step of manufacturing a first conductive portion and a first control voltage line on the base substrate, and setting the first conductive portion to be electrically connected to the first control voltage line comprises: A first metal layer is formed on the substrate, and a patterning process is performed on the first metal layer to form a first gate pattern, the first gate pattern comprising the first conductive portion; A second metal layer is manufactured on a side of the first metal layer away from the base substrate, and a second mask is used to perform a composition process on the second metal layer to form a first control voltage line, and to form a first electrode of the first transistor and a second electrode of the first transistor, wherein the orthographic projection of the first electrode on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the second electrode on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate.

28. The method for manufacturing an array substrate according to claim 27, in, The invention also includes: manufacturing a conductive layer on a side of the second metal layer away from the base substrate, and performing a patterning process on the conductive layer to form a first connection structure; Setting a first electrode of the first transistor to be electrically connected to a first control voltage line, and setting a second electrode of the first transistor to be electrically connected to the first connection structure; The orthographic projection of at least part of the first electrode of the first transistor on the substrate is set to overlap with the orthographic projection of the first conductive part on the substrate, and the orthographic projection of at least part of the second electrode of the first transistor on the substrate is set to overlap with the orthographic projection of the first conductive part on the substrate.

29. The method for manufacturing an array substrate according to claim 28, in, Also includes: Performing a patterning process on the first metal layer to form a third gate pattern included in the second conductive portion; The third gate pattern is disposed to be electrically connected to the pull-up node.

30. The method for manufacturing an array substrate according to claim 29, in, Also includes: Performing a patterning process on the second metal layer to form a first voltage line, a first electrode of the third transistor, and a second electrode of the third transistor; Disposing a first electrode of the third transistor to be electrically connected to the first connection structure, and disposing a second electrode of the third transistor to be electrically connected to the first voltage line; The orthographic projection of at least part of the first electrode of the third transistor on the substrate is set to overlap with the orthographic projection of the second conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the third transistor on the substrate is set to overlap with the orthographic projection of the second conductive portion on the substrate.

31. The method for manufacturing an array substrate according to claim 28, in, Also includes: Performing a patterning process on the first metal layer to form a fifth gate pattern included in the third conductive portion; Performing a patterning process on the second metal layer to form a second control voltage line; The fifth gate pattern is arranged to be electrically connected to the second control voltage line.

32. The method for manufacturing the array substrate according to claim 31, in, Also includes: Performing a patterning process on the second metal layer to form a first electrode of a fifth transistor and a second electrode of the fifth transistor; Performing a patterning process on the first conductive portion to form a second connection structure; Setting the first electrode of the fifth transistor to be electrically connected to the second control voltage line, and setting the second electrode of the fifth transistor to be electrically connected to the second connection structure; The orthographic projection of at least part of the first electrode of the fifth transistor on the substrate is set to overlap with the orthographic projection of the third conductive portion on the substrate, and the orthographic projection of at least part of the second electrode of the fifth transistor on the substrate is set to overlap with the orthographic projection of the third conductive portion on the substrate.

33. The method for manufacturing an array substrate according to claim 32, in, Also includes: Performing a patterning process on the first metal layer to form a seventh gate pattern included in the fourth conductive portion; The seventh gate pattern is arranged to be electrically connected to the pull-up node.

34. The method for manufacturing an array substrate according to claim 33, in, Also includes: Performing a patterning process on the second metal layer to form a first voltage line, a first electrode of the seventh transistor, and a second electrode of the seventh transistor; The first electrode of the seventh transistor is set to be electrically connected to the second connection structure, and the second electrode of the seventh transistor is set to be electrically connected to the first voltage line; The orthographic projection of at least a portion of the first electrode of the seventh transistor on the substrate is set to overlap with the orthographic projection of the fourth conductive portion on the substrate, and the orthographic projection of at least a portion of the second electrode of the seventh transistor on the substrate is set to overlap with the orthographic projection of the fourth conductive portion on the substrate.

35. A display device, comprising the array substrate according to any one of claims 1 to 24.

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