A method and apparatus for automatically testing a chip

Abstract

Embodiments of the present application provide a method and device for automatically testing a chip, the method comprising: automatically generating a test routine for different pins, and compiling the test routine into an executable ELF file, wherein the executable ELF file comprises all codes and data to be tested; placing the executable ELF file in a specified location; receiving an input chip model and pin information to obtain test parameters, wherein the test parameters are used to establish a Joint Test Action Group (JTAG) connection; and automatically connecting to the chip through a JTAG interface and performing a test according to the test parameters. The technical solution of the embodiments of the present application significantly reduces the technical threshold, reduces the risk of human operation errors, improves the test efficiency, greatly reduces the labor cost, and brings significant acceleration effect to the chip production and screening process.

Description

[0001] This application claims priority to patent application CN202410033968.8, filed on January 9, 2024, entitled “A method and device for automatically testing a chip,” and the entire contents of that application are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of chip testing, and specifically, embodiments of the present application relate to a method and apparatus for automatically testing a chip. Background Art

[0003] Chip testing faces numerous technical challenges, primarily related to the complexity, time-consuming nature, and labor costs of the testing process. Traditional chip testing requires connecting to an emulator, downloading, compiling, and running each test routine individually, resulting in time-consuming and complex testing. This approach also incurs significant human resource and cost expenditures for large-scale testing and in environments with limited test equipment.

[0004] The existing technical problems mainly include:

[0005] 1. Complicated test process: The traditional chip test process requires each routine to be connected to the simulator, downloaded, compiled, and run separately, which increases the number of steps and time consumption, seriously affecting test efficiency.

[0006] 2. Extensive manual intervention: Manually testing each routine requires testers to intervene at every step, which can easily introduce operational errors and increase the risk of manual intervention.

[0007] 3. High technical threshold: Traditional testing methods require testers to be familiar with various testing principles and operating procedures, which is a challenge for those who lack professional skills or understanding of the operation of test equipment.

[0008] 4. Long test time: Because each routine needs to be operated separately, the complete test of a chip takes a lot of time, which is unacceptable in large-scale testing.

[0009] 5. High cost: Due to the need for a lot of manpower and time-consuming operation, traditional testing methods bring significant labor and operating costs.

[0010] The above problems hinder the efficiency and automation of the chip testing process, increase production costs and time investment. Therefore, how to improve chip testing efficiency has become a technical problem that needs to be solved urgently. Summary of the Invention

[0011] The purpose of the embodiments of the present application is to provide a method and device for automatically testing chips. The embodiments of the present application can automatically generate test routines for different pins (pins, also called pins, called Pin in English) and compile them into corresponding elf files. Users only need to put these elf files in the specified location, connect the development board with a seat or the core board, connect the emulator and the power cord. The system supports multiple chip models and pin numbers, automatically connects to the target chip through the JTAG interface and performs tests. The technical solution of the embodiments of the present application significantly lowers the technical threshold, reduces the risk of human operational errors, improves test efficiency, greatly reduces labor costs, and brings significant acceleration effects to the chip production and screening process.

[0012] In a first aspect, an embodiment of the present application provides a method for automatically testing a chip, the method comprising: automatically generating test routines for different pins, and compiling the test routines into an executable ELF file, wherein the executable ELF file includes all code and data to be tested; placing the executable ELF file in a specified location; receiving input chip model and pin information to obtain test parameters, wherein the test parameters are used to establish a joint test working group JTAG connection; automatically connecting to the chip through the JTAG interface according to the test parameters and performing the test.

[0013] In some embodiments, automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters includes: automatically loading and executing the test routine in the executable ELF file according to a preset test sequence.

[0014] In some embodiments, automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters also includes: if it is confirmed that the first test routine is set to output print information, then the corresponding print information is displayed on the command line interface when executing the first test routine.

[0015] In some embodiments, before automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters, the method also includes: receiving input connection information of the hardware connection for the second test routine; automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters includes: if it is confirmed that the test is to the second test routine, providing a connection prompt for the connection information and waiting for the input connection to complete the instruction to continue the test.

[0016] In some embodiments, the connection prompt is provided via a command line, and the instruction is triggered by the enter key.

[0017] In some embodiments, automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters also includes: providing the test results through the command line after each test routine is completed, wherein the test results include test pass or test fail.

[0018] In some embodiments, automatically connecting to the chip through the JTAG interface and performing testing according to the test parameters also includes: after all test routines are tested, providing summary test results through the command line, wherein the summary test results include the name of each test routine and the corresponding test results.

[0019] In some embodiments, before compiling the test routine into an executable ELF file, the method further includes: receiving pin configuration parameters required by different hardware through a compilation parameter configuration interface, so that each executable ELF file adapts to different hardware requirements.

[0020] In some embodiments, compiling the test routine into an executable ELF file includes: during the compilation process, providing real-time feedback on the compilation status through an interface.

[0021] In a second aspect, some embodiments of the present application provide a device for automatically testing chips, the device comprising: a compilation and generation executable file module, configured to automatically generate test routines for different pins, and compile the test routines into an executable ELF file, wherein the executable ELF file includes all codes and data to be tested; a storage module, configured to place the executable ELF file into a specified location; an automatic connection information input module, configured to receive input chip model and pin information, and obtain test parameters, wherein the test parameters are used to establish a joint test working group JTAG connection; a connection and test module, configured to automatically connect to the chip through the JTAG interface and perform testing according to the test parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 One of the flow charts of the method for automatically testing a chip provided in an embodiment of the present application;

[0024] Figure 2 This is one of the block diagrams of the device for automatically testing a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0026] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0027] Some embodiments of the present application provide a method for automatically testing a chip, which is an automated chip testing method based on a JTAG interface. The method exemplarily includes: automatically generating test routines for different pins and compiling them into corresponding elf files. The user only needs to put these elf files into a specified location and insert a development board with a seat into the chip or core board, connect the emulator and the power cord. The chip testing method of the present application supports a variety of chip models and pin numbers, automatically connects to the target chip through the JTAG interface and performs the test. For example, in some embodiments of the present application, if a specific connection setting is required, the method for automatically testing a chip in some embodiments of the present application also provides a clear guidance interface, so that the user can easily configure the test environment. The method for automatically testing a chip provided in some embodiments of the present application also includes that after the test is completed, the user will obtain a test report, wherein each test routine in the test report is marked with a "pass" or a "fail" mark, so that the problem is quickly visible.

[0028] The automated chip testing method employed in the embodiments of this application significantly lowers the technical barrier to entry, reduces the risk of human error, improves testing efficiency, significantly reduces labor costs, and significantly accelerates the chip production and screening process. This innovative automated testing system provides a more convenient and efficient solution for chip testing, bringing higher productivity to the entire industry.

[0029] It is not difficult to understand that compared with traditional technologies, the embodiments of the present application can automatically test chips, from compiling test routines to the end of testing, reducing manual intervention. The method of automatically testing chips in the embodiments of the present application provides automated hardware connection preparation, reducing operational risks. The method of automatically testing chips in some embodiments of the present application solves the problem of automatically connecting chips. The user only needs to enter the chip model and the number of pins, and the system will automatically perform the JTAG connection and start testing. Unlike traditional test results that usually require users to manually analyze, some embodiments of the present application also provide clear test result reports to help users quickly screen chips.

[0030] Please see Figure 1 , Figure 1 A method for automatically testing a chip is provided for an embodiment of the present application. The method includes: S101, automatically generating test routines for different pins, and compiling the test routines into an executable ELF file, wherein the executable ELF file includes all code and data to be tested; S102, placing the executable ELF file in a specified location; S103, receiving input chip model and pin information, and obtaining test parameters, wherein the test parameters are used to establish a joint test working group JTAG connection; S104, automatically connecting to the chip through the JTAG interface according to the test parameters and performing a test.

[0031] In some embodiments of the present application, S104 exemplarily includes: automatically loading and executing the test routine in the executable ELF file according to a preset test sequence.

[0032] In some embodiments of the present application, S104 further exemplarily includes: if it is confirmed that the first test routine is set to output print information, then corresponding print information is displayed on the command line interface when the first test routine is executed.

[0033] In some embodiments of the present application, before executing S104, the method further includes: receiving input connection information for hardware connections for a second test routine; and automatically connecting to the chip via the JTAG interface and executing the test based on the test parameters, including: if the test is confirmed to be in the second test routine, providing a connection prompt for the connection information and waiting for input of an instruction to continue the test after the connection is complete. For example, in some embodiments of the present application, the connection prompt is provided via a command line, and the instruction is triggered by the Enter key.

[0034] In some embodiments of the present application, S104 further exemplarily includes: providing a test result through a command line after each test routine is completed, wherein the test result includes a test pass or a test fail.

[0035] In some embodiments of the present application, S104 further exemplarily includes: after all test routines are tested, providing summary test results through a command line, wherein the summary test results include the name of each test routine and the corresponding test results.

[0036] In some embodiments of the present application, before compiling the test routine into an executable ELF file, the method further includes: receiving pin configuration parameters required by different hardware through a compilation parameter configuration interface, so that each executable ELF file adapts to different hardware requirements.

[0037] In some embodiments of the present application, compiling the test routine into an executable ELF file includes: during the compilation process, providing real-time feedback on the compilation status through an interface.

[0038] The following combination Figure 2 The method of automatically testing a chip according to some embodiments of the present application is exemplified.

[0039] 1. Source code preparation and upload

[0040] 1.1 Developers first need to write the corresponding test source code according to their own needs.

[0041] 1.2 Upload the compiled source code to the storage directory specified by the system through the upload function provided by the system.

[0042] 2. Compilation process

[0043] 2.1 Parameter configuration before compilation: The developer will first enter the parameter configuration interface of the compilation system to perform parameter configuration or the developer will directly configure the parameters through the command line (for example, in .bat). In this link, some embodiments of the present application need to specify the pin configuration parameters required for different hardware. For example, you can choose to configure the hardware parameters of specifications such as 64Pin (i.e. 64 pins) or 128Pin (i.e. 128 pins). Once the configuration is complete, the developer can start the compilation process. The intelligent setting of this stage greatly improves flexibility, ensuring that the executable ELF file generated can accurately adapt to different hardware requirements. The method of the automatic test chip of the present application will automatically store the ELF file generated by compilation in a folder named after the number of pins according to the pin parameters set by the developer, so that file management becomes clear and organized, which is convenient for subsequent testing and debugging. During the compilation process, the interface will display whether the compilation is successful or not. If not successful, the error of the code will be displayed for easy modification.

[0044] 2.2 Real-time feedback during the compilation process: During the compilation process, the method for automatically testing a chip in an embodiment of the present application includes providing real-time feedback on the compilation status via an interface. If the compilation is successful, the interface will provide a clear success prompt. If the compilation fails, the system will accurately display the line of code causing the compilation error and the specific error message. This real-time feedback mechanism not only saves developers time in error checking but also greatly simplifies the code debugging process. Developers can directly perform code corrections and optimizations based on error prompts in the compilation interface, thereby achieving rapid iteration and efficient error resolution strategies.

[0045] 3. Hardware device and interface connection

[0046] During the hardware configuration stage, the embodiment of the present application requires that the development board or core board containing the base be connected to the computer through the JTAG interface in order to burn and debug the program.

[0047] 4. Start automatic testing

[0048] 4.1 Preparing the test environment

[0049] First, developers need to place the executable ELF (Executable and Linkable Format) file in a predefined directory. The ELF file contains all the code and data to be tested and is the core of subsequent automated testing. Placing the test routine ELF file in the specified location is a prerequisite for ensuring that the test system can correctly identify and call the test script.

[0050] 4.2 Configure test parameters

[0051] In some embodiments of the present application, in a command line environment, test parameters are configured by receiving specific chip models and pin information input by relevant personnel. These parameters are crucial for establishing a JTAG connection because different chip models and different pin assignments will directly affect the communication method between the test script and the chip.

[0052] JTAG (Joint Test Action Group) technology provides a mechanism for testing and debugging a chip when it is not running a regular application. In some embodiments of the present application, the test system can access the test access port (TAP) inside the chip through the JTAG interface and perform tests without interfering with the normal operation of the chip.

[0053] 4.3 Automatic testing process

[0054] After entering the correct chip model and pin information, the method for automatically testing the chip in the embodiment of the present application begins to automatically connect to the chip through JTAG. Once the connection is successfully established, the test routine in the ELF file is automatically loaded and executed according to the preset test sequence.

[0055] During testing, if the test routines are written to output print information, then when executing these specific routines, the print information will be displayed directly on the command line interface. This provides developers with immediate feedback, helping to monitor test progress and identify problems.

[0056] For tests that require specific hardware connections, the automated chip testing method provided in this application allows developers to enter the necessary connection information before testing begins. Once a test phase requiring specific hardware setup is reached, the system prompts the developer in the command line, waiting for confirmation that the connection is complete. At this point, the developer must ensure that all necessary hardware connections are set up and press Enter in the command line to continue testing.

[0057] 4.4 Result Feedback and Recording

[0058] In some embodiments of the present application, after each test routine is completed, the system will output the test result of the routine in the command line, showing it as pass (Pass) or fail (Fail). For failed routines, the system will provide additional error information as much as possible to help developers diagnose the problem.

[0059] In some embodiments of the present application, when all test routines are executed, the system will provide a summary result in the command line, which generally includes the name of each test routine and its corresponding pass or fail status. Such summary results are very important for developers, as they provide a comprehensive overview of the tests and allow them to quickly identify problem areas that require further investigation.

[0060] The method for automatically testing chips provided in this application is based on scripting and monitoring, providing efficient assurance for software quality. It does not require a complex user interface, is simple to operate, and is not restricted by the operator's technical level.

[0061] like Figure 2 As shown, this figure shows an automatic chip testing device provided by some embodiments of the present application, which includes: a compilation and execution file generation module 101, a storage module 102, an automatic connection information input module 103 and a connection and testing module 104.

[0062] The compile and generate executable file module is configured to automatically generate test routines for different pins and compile the test routines into executable ELF files, wherein the executable ELF files include all codes and data to be tested.

[0063] The storage module is configured to store the executable ELF file in a specified location.

[0064] The automatic connection information input module is configured to receive the input chip model and pin information and obtain test parameters, wherein the test parameters are used to establish a joint test working group JTAG connection.

[0065] The connection and test module is configured to automatically connect to the chip through the JTAG interface and perform testing according to the test parameters.

[0066] For the implementation details of the corresponding modules in the device, please refer to the description of the method in the previous article. To avoid repetition, we will not go into details here.

[0067] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0068] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0069] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0070] The foregoing is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0071] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0072] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

Claims

1. A method for automatically testing a chip, characterized in that: The method comprises: Receive the pin configuration parameters required by different hardware through the compilation parameter configuration interface, so that each executable ELF file can adapt to different hardware requirements; Automatically generate test routines for different pins, and compile the test routines into executable ELF files, wherein the executable ELF files include all codes and data to be tested; Placing the executable ELF file in a designated location, including automatically storing the compiled ELF files in folders named after the number of pins according to the set pin parameters; Receive input chip model and pin information, and obtain test parameters, wherein the test parameters are used to establish a joint test working group JTAG connection; Automatically connect to the chip through the JTAG interface and perform testing according to the test parameters.

2. The method according to claim 1, wherein The method of automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters includes: The test routines in the executable ELF file are automatically loaded and executed according to a preset test sequence.

3. The method according to claim 2, wherein The method of automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters further includes: If it is confirmed that the first test routine is set to output print information, then corresponding print information is displayed on the command line interface when the first test routine is executed.

4. The method according to claim 3, wherein Before automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters, the method further includes: receiving input connection information of hardware connections for a second test routine; The method of automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters includes: If it is confirmed that the test reaches the second test routine, a connection prompt for the connection information is provided and an instruction for inputting connection completion to continue the test is waited for.

5. The method according to claim 4, wherein The connection prompt is provided through a command line, and the instruction is triggered by the enter key.

6. The method according to claim 1, wherein The method of automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters further includes: After each test routine is completed, a test result is provided through a command line, wherein the test result includes a test pass or a test fail.

7. The method according to claim 6, wherein The method of automatically connecting to the chip through the JTAG interface and performing the test according to the test parameters further includes: After all test routines are tested, a summary test result is provided through a command line, wherein the summary test result includes the name of each test routine and the corresponding test result.

8. The method according to claim 1, wherein Compiling the test routine into an executable ELF file includes: During the compilation process, the compilation status is fed back in real time through the interface.

9. A device for automatically testing a chip, characterized in that: The device comprises: The compile and generate executable file module is configured to receive pin configuration parameters required by different hardware through a compilation parameter configuration interface, so that each executable ELF file adapts to different hardware requirements, automatically generates test routines for different pins, and compiles the test routines into executable ELF files, wherein the executable ELF files include all the code and data to be tested; A storage module is configured to place the executable ELF file in a specified location, including automatically storing the compiled ELF files in folders named after the number of pins according to the set pin parameters; An automatic connection information input module is configured to receive input chip model and pin information and obtain test parameters, wherein the test parameters are used to establish a joint test working group JTAG connection; The connection and test module is configured to automatically connect to the chip through the JTAG interface and perform testing according to the test parameters.

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