Interactive chip performance test method and system

Abstract

The invention provides an interactive chip performance testing method and system, and relates to the technical field of testing, and the method comprises the steps: dividing a port of a to-be-tested chip into an input port and an output port; inputting a first operation parameter and a first test program, inputting first test data into the input port, detecting temperature data of a plurality of detection positions, and further determining a heat dissipation influence performance score; and inputting a second operation parameter and a second test program, inputting second test data, receiving output level data, detecting output voltage data, and further determining an operation performance score. According to the invention, the temperature data of a plurality of positions around the chip to be detected can be detected, so that the influence of heat dissipation of the chip to be detected in the operation process on surrounding electronic devices is determined, and the voltage sensor can detect that the output level data of the chip to be detected may have errors. Therefore, the output accuracy and the voltage accuracy of the to-be-tested chip are determined, and the operation and output performance of the chip can be comprehensively tested.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to an interactive chip performance testing method and system. Background Art

[0002] In the related art, CN119199487A discloses a chip testing method, device, electronic device and storage medium, which relates to the field of semiconductor testing technology, wherein the method includes: establishing a foolproof detection mechanism, using a camera device to move horizontally and a foolproof detection mechanism to horizontally scan a wafer to obtain a horizontal wafer, obtaining the center position and diameter of the wafer according to the characteristic point position of the wafer, the distance calculation formula and the visual recognition function of the camera, obtaining a map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips and the center position and characteristic point position of the wafer, obtaining a needle tip offset angle through a camera, rotating the wafer according to the needle tip offset angle and updating the map according to the needle tip offset angle, and performing chip testing according to the map. This solution solves the problems of poor compatibility, low automation, low production efficiency and accuracy of the prior art.

[0003] CN119178988A discloses a device and method for mass production testing of high-speed interface chip performance, which belongs to the field of chip mass production testing technology. It includes a tester and a test board, the test board is designed with an attenuation loopback link, the attenuation loopback link has a predetermined attenuation value, the tester provides test functions and test resources, the chip is fixed to the test board through a socket, the uplink and downlink outputs of the chip are respectively connected to the attenuation loopback link by a multi-channel transmitting end and a receiving end, and the tester is connected to the test board through a JTAG interface. At the same time, through a series of operation processes including power-on, configuration, correct code stream test, injection error test and result judgment, the SERDES performance of the chip is comprehensively tested to ensure that the quality and performance of the chip meet the requirements.

[0004] CN119199486A discloses a LED driver chip test system and method, which relates to the field of chip testing technology. The method includes: collecting the first electrical data in the steady-state load test process and the second electrical data in the transient load test process; extracting the steady-state index parameters and transient index parameters of multiple load points and determining multiple target load points; constructing the electrical characteristic correlation matrix and the electrical fluctuation correlation matrix corresponding to the multiple target load points; performing feature fusion on the electrical fluctuation correlation matrix and the electrical characteristic correlation matrix to generate a target correlation matrix, determining multiple electrical parameter linkage combinations based on the target key matrix, generating the first linkage test scheme for each electrical parameter linkage combination, and performing linkage test on the LED driver chip based on multiple first linkage test schemes. This scheme improves the effectiveness and comprehensiveness of LED driver chip testing.

[0005] Therefore, in the related technology, the performance, quality and other parameters of the chip can be tested, but the chip may generate heat during operation and affect surrounding electronic devices, and the related technology makes it difficult to detect the impact of the chip on surrounding electronic devices.

[0006] The information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to those skilled in the art. Summary of the invention

[0007] The present invention provides an interactive chip performance testing method and system, which can solve the technical problem that related technologies are difficult to detect the impact of chips on surrounding electronic devices.

[0008] According to a first aspect of the present invention, there is provided an interactive chip performance testing method, comprising:

[0009] Connecting multiple ports of the chip to be tested to the test ports of the interactive test device, and dividing the multiple ports of the chip to be tested into input ports and output ports;

[0010] Entering a first operation parameter and a first test program into the chip under test through the interactive test device via multiple ports of the chip under test, wherein the first test program is a program that calls all computing power of the chip under test;

[0011] Inputting first test data into the input port according to a preset first input frequency;

[0012] At a plurality of first test moments when the chip under test is running according to the first test program, the first test data and the first operation parameter, detecting temperature data of a plurality of detection positions around the chip under test by a temperature sensor;

[0013] Obtaining a heat dissipation impact performance score of the chip to be tested according to the temperature data and the detection position;

[0014] Clearing the first operation parameter and the first test program through the interactive test device via multiple ports of the chip under test, and entering second operation parameters and a second test program into the chip under test, wherein the second test program is a data operation program;

[0015] At multiple second test moments, input second test data to the chip under test, receive output level data of the output port, and obtain output voltage data through multiple voltage sensors arranged at the output port, wherein the output level data is multi-dimensional data, and the data of each dimension is 0 or 1;

[0016] Determining a computing performance score of the chip to be tested according to the output level data and the output voltage data;

[0017] A performance test report of the chip to be tested is obtained according to the computing performance score and the heat dissipation impact performance score.

[0018] According to a second aspect of the present invention, there is provided an interactive chip performance testing system, comprising:

[0019] A division module, used for connecting multiple ports of the chip to be tested with the test ports of the interactive test device, and dividing the multiple ports of the chip to be tested into input ports and output ports;

[0020] A first input module, used to input a first operation parameter and a first test program into the chip under test through the interactive test device via multiple ports of the chip under test, wherein the first test program is a program that calls all computing power of the chip under test;

[0021] A first input module, used for inputting first test data to the input port according to a preset first input frequency;

[0022] A temperature data module is used to detect temperature data of multiple detection positions around the chip under test through a temperature sensor at multiple first test moments when the chip under test is running according to the first test program, the first test data and the first operation parameter;

[0023] A heat dissipation impact performance scoring module, used to obtain a heat dissipation impact performance score of the chip to be tested according to the temperature data and the detection position;

[0024] A second input module is used to clear the first operation parameter and the first test program through the interactive test device and multiple ports of the chip under test, and input second operation parameters and a second test program into the chip under test, wherein the second test program is a data operation program;

[0025] an acquisition module, used for inputting second test data to the chip under test at multiple second test moments, receiving output level data of the output port, and acquiring output voltage data through multiple voltage sensors arranged at the output port, wherein the output level data is multi-dimensional data, and the data of each dimension is 0 or 1;

[0026] An operation performance scoring module, used to determine the operation performance score of the chip to be tested according to the output level data and the output voltage data;

[0027] The test report module is used to obtain a performance test report of the chip to be tested according to the computing performance score and the heat dissipation impact performance score.

[0028] By adopting the above technical solution, the present invention can achieve the following technical effects:

[0029] According to the present invention, the test equipment can be provided with a temperature measurement function, so as to measure the temperature data at multiple positions around the chip to be tested, so as to determine the influence of the heat dissipation of the chip to be tested on the surrounding electronic devices during operation. In addition, the output level data of the chip to be tested may be detected by a voltage sensor, so as to determine the output accuracy and voltage accuracy of the chip to be tested, so as to facilitate comprehensive testing of the chip's operation and output performance, and improve the accuracy of the test. When determining the heat dissipation influence function, based on the inverse correlation between temperature and distance, and the relationship between heat and distance during the diffusion process, a coefficient equation in the form of a quadratic polynomial can be set to accurately describe the relationship between the temperature of each position and the distance between each position and the origin, and then solve the coefficient to be determined to obtain the heat dissipation influence function, thereby improving the accuracy and objectivity of the heat dissipation influence function. When determining the heat dissipation influence performance score, the total influence of the chip to be tested on the surrounding electronic devices at a specific moment can be determined by integrating the heat dissipation influence function, and the maximum change rate of the total influence can be determined as the influence of the heat accumulated around the chip heat dissipation on the surrounding electronic devices, and then the heat dissipation influence performance score can be obtained, which can objectively and accurately reflect the temperature control ability of the chip to be tested and the influence on the surrounding electronic devices. When determining the program operation performance score, the conditional function can be used to screen the results of the chip under test operating each second test data, and compared with the predicted output data to determine the operation accuracy of the chip under test. The average execution time of the program can also be determined to determine the program operation performance score, thereby reflecting the program execution capability of the chip under test from the two aspects of operation accuracy and operation efficiency. When determining the level accuracy score, the cosine similarity can be used to determine the accuracy of each level value in the output data, and the minimum value function can be used to identify the level corresponding to the output voltage data, without the need for special identification and comparison, which improves the convenience of operation, and can determine the operation accuracy of the output voltage value, thereby describing the output accuracy of the chip under test from the two aspects of the output level value and the accuracy of the output voltage value, and obtaining the level accuracy score, thereby improving the accuracy and comprehensiveness of the level accuracy score.

[0030] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and not limiting of the present invention. Other features and aspects of the present invention will become more apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic diagram showing an interactive chip performance testing method according to an embodiment of the present invention is exemplarily shown;

[0033] Figure 2 A block diagram of an interactive chip performance testing system according to an embodiment of the present invention is exemplarily shown. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0036] Figure 1 A flow chart of an interactive chip performance testing method according to an embodiment of the present invention is exemplarily shown, wherein the method comprises:

[0037] Step S101, connecting multiple ports of the chip to be tested to test ports of an interactive test device, and dividing the multiple ports of the chip to be tested into input ports and output ports;

[0038] Step S102, inputting a first operation parameter and a first test program into the chip under test through the interactive test device via multiple ports of the chip under test, wherein the first test program is a program that calls all computing power of the chip under test;

[0039] Step S103, inputting first test data to the input port according to a preset first input frequency;

[0040] Step S104, detecting temperature data of multiple detection positions around the chip under test by a temperature sensor at multiple first test moments when the chip under test is running according to the first test program, the first test data and the first operation parameter;

[0041] Step S105, obtaining a heat dissipation impact performance score of the chip to be tested according to the temperature data and the detection position;

[0042] Step S106, clearing the first operation parameter and the first test program through the interactive test device via multiple ports of the chip under test, and entering second operation parameters and a second test program into the chip under test, wherein the second test program is a data operation program;

[0043] Step S107, at multiple second test moments, input second test data to the chip under test, receive output level data of the output port, and obtain output voltage data through multiple voltage sensors arranged at the output port, wherein the output level data is multi-dimensional data, and the data of each dimension is 0 or 1;

[0044] Step S108, determining the computing performance score of the chip to be tested according to the output level data and the output voltage data;

[0045] Step S109, obtaining a performance test report of the chip to be tested according to the computing performance score and the heat dissipation impact performance score.

[0046] According to the interactive chip performance test method of the embodiment of the present invention, the test equipment can have a temperature measurement function, so as to measure the temperature data at multiple positions around the chip to be tested, so as to determine the influence of the heat dissipation of the chip to be tested on the surrounding electronic devices during operation. In addition, the output level data of the chip to be tested may be detected by a voltage sensor, so as to determine the output accuracy and voltage accuracy of the chip to be tested, which is convenient for comprehensive testing of the chip's operation and output performance, and improves the accuracy of the test.

[0047] According to an embodiment of the present invention, in step S101, a test port of the interactive test device may be connected to a port of the chip under test, and multiple ports of the chip under test may be divided into input ports and output ports according to the functions of the ports of the chip under test.

[0048] According to an embodiment of the present invention, in step S102, the interactive test device may store the first test program and the first operation parameter in the chip under test, for example, burn them into the chip under test, so that the chip under test can execute the first test program. The first test program may call all computing resources of the chip under test, for example, call all threads of the processor and call all memory, that is, make the chip under test use all computing power for calculation.

[0049] According to one embodiment of the present invention, in step S103, the first input frequency is a preset frequency for inputting first test data, that is, the first test data is input to the input port of the chip under test once every preset time period, and the first test data input each time may be the same or different.

[0050] According to one embodiment of the present invention, in step S104, the chip to be tested is operated according to the first test program, the first test data and the first operation parameter. For example, the first test data can be operated with the first operation parameter according to the steps of the first test program, such as multiplication, addition, convolution and other operations. And at multiple first test moments during the operation, the temperature data of multiple detection positions around the chip to be tested are detected by a temperature sensor. As described above, the first test program can call all the computing power of the chip to be tested, and the chip to be tested can generate heat during the execution process. Therefore, the temperature data of multiple detection positions around the chip to be tested can be detected by the temperature sensor when the heat generation is the maximum. The temperature sensor can be an infrared temperature sensor, etc., and the present invention does not limit the specific type of the temperature sensor.

[0051] According to an embodiment of the present invention, in step S105, the heat dissipation impact performance score is used to evaluate the control capability of the chip under test for heat dissipation, and the impact of the chip under test on surrounding electronic devices when dissipating heat.

[0052] According to one embodiment of the present invention, the heat dissipation impact performance score of the chip to be tested is obtained based on the temperature data and the detection position, including: establishing a test coordinate system with the bottom surface centroid of the chip to be tested as the origin, the bottom surface of the chip to be tested as the XOY plane, and the direction perpendicular to the bottom surface of the chip to be tested as the Z-axis direction; determining the position coordinates of the detection position in the test coordinate system; determining the heat dissipation impact function at each first test moment based on the temperature data detected by multiple temperature sensors at each first test moment, and the position coordinates; and determining the heat dissipation impact performance score of the chip to be tested based on the heat dissipation impact function at each first test moment.

[0053] According to an embodiment of the present invention, after the test coordinate system is established, each detection position and the position of the chip to be tested can have a unified measurement standard, that is, they are in the same coordinate system, which facilitates the calculation of the distance and position relationship between each position.

[0054] According to an embodiment of the present invention, the heat dissipation impact function is used to describe the relationship between the temperature and position around the chip under test, and can describe the distribution and change rules of the temperature, so as to determine the impact of the heat dissipation of the chip under test on the surrounding electronic devices.

[0055] According to an embodiment of the present invention, the heat dissipation influence function at each first test moment is determined according to the temperature data detected by the plurality of temperature sensors at each first test moment and the position coordinates, including: determining the undetermined coefficient equation of the heat dissipation influence function at the i-th first test moment according to formula (1),

[0056] T 1,i,j =α1(x j ) 2 +α2(y j ) 2 +α3(z j ) 2 +α4x j y j +α5y j z j +α6x j z j +α7x j +

[0057] α8y j +α9z j +α 10 (1)

[0058] Among them, T 1,i,j is the temperature data of the jth detection position at the i-th first test moment, (x j ,y j ,z j ) is the position coordinate of the jth detection position, α1, α2, α3, α4, α5, α6, α7, α8, α9 and α 10 is the undetermined coefficient; the undetermined coefficient is solved by the temperature data at multiple detection positions at the i-th first test moment, and the position coordinates of the multiple detection positions, to obtain the solution value of the undetermined coefficient; according to the solution value of the undetermined coefficient and the undetermined coefficient equation of the heat dissipation influence function at the i-th first test moment, the heat dissipation influence function at the i-th first test moment is obtained.

[0059] According to one embodiment of the present invention, since the heat source is the chip to be tested, and the bottom centroid of the chip to be tested is located at the origin of the coordinates, the temperature rise of the chip to be tested and the influence of heat dissipation on the surroundings are correlated with the distance between the surrounding positions and the chip to be tested, and as the distance increases, its influence does not decrease linearly, but is inversely correlated with the square of the distance. This is because as the distance increases, the heat diffuses to the surroundings, and the surface area of ​​the heat diffusion area is positively correlated with the square of the distance. Therefore, the temperature of each position in the area is inversely correlated with the distance. Based on the inverse correlation between the temperature and the distance of each position, a coefficient equation in the form of a quadratic polynomial can be set, that is, formula (1), and the solution value of the coefficient to be determined is calculated through the temperature data at multiple (at least 10) detection positions and the position coordinates at multiple detection positions, and the solution value of the coefficient to be determined is substituted into formula (1) to obtain the heat dissipation influence function at the i-th first test moment. Further, the temperature data at multiple detection positions at each first test moment can be processed as above to obtain the heat dissipation influence function at each first test moment.

[0060] In this way, based on the inverse correlation between temperature and distance, and the relationship between heat and distance during the diffusion process, an equation with undetermined coefficients in the form of a quadratic polynomial can be set to accurately describe the relationship between the temperature at each location and the distance between each location and the origin, and then the undetermined coefficients can be solved to obtain the heat dissipation influence function, thereby improving the accuracy and objectivity of the heat dissipation influence function.

[0061] According to an embodiment of the present invention, the heat dissipation impact performance score of the chip to be tested is determined according to the heat dissipation impact function at each first test moment, including: determining the heat dissipation impact performance score S of the chip to be tested according to formula (2): D ,

[0062]

[0063] Among them, T 1,i+1 (x, y, z) is the heat dissipation influence function at the first test time of the i+1th time, T 1,i (x, y, z) is the heat dissipation influence function at the i-th first test moment, Ω is the preset area around the chip to be tested, Δt1 is the time interval between adjacent first test moments, k p is the preset change rate, max is the maximum value function, n is the number of the first test moment, i≤n-1, and i and n are both positive integers.

[0064] According to one embodiment of the present invention, in formula (2), ∫∫∫ Ω T 1,i+1(x, y, z)dxdydz is the integral of the heat dissipation influence function at the i+1th first test moment in the preset area, which can represent the total influence of the heat dissipation of the chip under test at the i+1th moment on the surrounding electronic devices. Similarly, ∫∫∫ Ω T 1,i (x,y,z)dxdydz represents the total impact of the heat dissipation of the chip under test on the surrounding electronic devices at the i-th moment. It can represent the rate of change of the total effect of heat dissipation at the adjacent first test moment, That is, it is the maximum value of the rate of change of the total impact of heat dissipation corresponding to multiple adjacent moments, indicating the maximum increase rate of the impact of chip heat dissipation on surrounding electronic devices. This maximum increase rate can be used to indicate the maximum increase rate of heat accumulation, which can objectively indicate the impact of the heat accumulated around the chip heat dissipation on the surrounding electronic devices. The greater the maximum increase rate of heat accumulation, the worse the temperature control ability of the chip, the slower the heat dissipation, and the greater the impact on the surrounding electronic devices. The relative difference between the maximum increase rate and the preset change rate can be used as a heat dissipation impact performance score. The larger the score, the better the temperature control ability of the chip to be tested, the slower the temperature accumulation, and the smaller the impact on the surrounding electronic devices.

[0065] In this way, the total impact of the chip under test on the surrounding electronic devices at a specific moment can be determined by integrating the heat dissipation impact function, and the maximum change rate of the total impact can be determined as the impact of the heat accumulated around the chip as heat dissipates on the surrounding electronic devices, thereby obtaining a heat dissipation impact performance score, which can objectively and accurately reflect the temperature control capability of the chip under test and its impact on the surrounding electronic devices.

[0066] According to one embodiment of the present invention, in step S106, the first operation parameters and the first test program can be cleared, and the second operation parameters and the second test program can be burned into the chip to be tested. The second test program is a common data operation program and does not need to call the full computing power of the chip to be tested.

[0067] According to one embodiment of the present invention, in step S107, at multiple second test moments, second test data can be input into the chip to be tested, the chip to be tested executes a second test program, uses second operation parameters and the second test data to perform operations, obtains operation results, and outputs them through the output port. When outputting, a group of level data can be output through multiple output ports, and the level output by each output port is a high level or a low level, representing 1 or 0, respectively.

[0068] According to one embodiment of the present invention, in step S108, the computing performance score of the chip to be tested is determined according to the output level data and the output voltage data, including: obtaining predicted output data corresponding to the second test data according to the second test data, the second operating parameters and the second test program; determining the program computing performance score according to the predicted output data, the output level data and the second test moment corresponding to the output level data and the second test moment corresponding to the second test data; determining the level accuracy score according to the predicted output data, the output level data and the output voltage data; and determining the computing performance score of the chip to be tested according to the program computing performance score and the level accuracy score.

[0069] According to one embodiment of the present invention, the second test program is a common data operation program, and therefore, the output data can be predicted artificially. For example, the second test program is a multiplication operation program, and the second test data and the second operation parameter can be multiplied. Therefore, the predicted output data, that is, the theoretical output data, can be determined artificially.

[0070] According to an embodiment of the present invention, the program operation performance score can be used to describe the program execution capability of the chip under test, for example, it can be used to reflect the correctness and operation speed of the operation. Determining the program operation performance score according to the predicted output data, the output level data, the second test time corresponding to the output level data, and the second test time corresponding to the second test data includes: determining the program operation performance score S according to formula (3) p ,

[0071]

[0072] Among them, O p,s is a vector composed of the predicted output data corresponding to the second test data at the s-th second test moment, ( p,s ) T O p,s The transposed vector of 2,s+h is a vector composed of the output level data at the s+hth second test moment, k sim is the preset similarity threshold, if is the conditional function, min is the minimum value function, Δt2 is the time interval between adjacent second test moments, Δt p is the preset duration, m is the number of second test moments for inputting the second test data, w1 and w2 are preset weights, s≤m, and s, h and m are all positive integers.

[0073] According to one embodiment of the present invention, in formula (3), Indicated in If , the value of the conditional function is h, otherwise represents the cosine similarity between the vector composed of the predicted output data corresponding to the second test data at the s-th second test moment and the vector composed of the output level data after h second test moments. If the cosine similarity is greater than or equal to the preset similarity threshold, the output level data at the s+h-th second test moment is the data output after the second test data at the s-th second test moment is calculated. Therefore, h is the number of moments required to calculate the second test data at the s-th second test moment. That is, the total time required to operate on each second test data. Indicated in In the case of , the value of the conditional function is 1, otherwise it is 0, that is, if there is data output after the second test data at the sth second test moment is calculated, the conditional function value is 1, otherwise it is 0. When the conditional function value is 1, it means that the chip under test calculates correctly, otherwise, the chip under test calculates incorrectly. Therefore, Indicates the number of second test data that the chip under test operates correctly. Indicates the average operation time of the second test data that all chips under test operate correctly, That is, it is the average operation time of the second test data that all the chips to be tested operate correctly. That is, the relative difference between the preset duration of executing the second test program and the above average operation duration. It can be used as the computing speed score of the chip under test. The higher the computing speed score, the shorter the average computing time, the faster the computing speed, and the higher the execution efficiency.

[0074] According to one embodiment of the present invention, The calculation accuracy of the chip under test for calculating the second test data can be used as the calculation accuracy and the calculation rate score to obtain the program calculation performance score, thereby reflecting the program execution capability of the chip under test from the two aspects of calculation accuracy and calculation efficiency.

[0075] In this way, the conditional function can be used to screen the results of the chip under test's operation on each second test data, and compared with the predicted output data to determine the operation accuracy of the chip under test. The average execution time of the program can also be determined to determine the program operation performance score, thereby reflecting the program execution capability of the chip under test from the two aspects of operation accuracy and operation efficiency.

[0076] According to an embodiment of the present invention, the level accuracy score can be used to describe the accuracy of the output level of the chip to be tested. According to the predicted output data, the output level data and the output voltage data, the level accuracy score is determined, including: determining a first preset output voltage corresponding to a high level and a second preset output voltage corresponding to a low level; determining the level accuracy score S according to formula (4)a ,

[0077]

[0078] Among them, O 2,s,c is a vector composed of output level data corresponding to the second test data at the second test time, U 2,s,g O 2,s,c The output voltage data corresponding to the output level data of the gth component, U 1,p is the first preset output voltage, U 2,p is the second preset output voltage, N s O 2,s,c The number of output level data in g≤N s , and g and N s All are positive integers, and min is the minimum value function.

[0079] According to one embodiment of the present invention, 2,s,c Equal to O p,s The cosine similarity is greater than or equal to k sim of That is O 2,s,c With O p,s The cosine similarity of can also represent the calculation accuracy of the second test data at the s-th second test moment, in other words, the accuracy of all level values ​​therein.

[0080] According to one embodiment of the present invention, |U 2,s,g -U 1,p | is the difference between the g-th output voltage data and the first preset output voltage, |U 2,s,g -U 2,p | is the difference between the g-th output voltage data and the g-th preset output voltage, min(|U 2,s,g -U 1,p |,|U 2,s,g -U 2,p |) is the minimum value between the two, that is, if the minimum value is equal to |U 2,s,g -U 1,p |, the g-th output voltage data corresponds to a high level, otherwise, the g-th output voltage data corresponds to a low level. The minimum function can automatically identify the level corresponding to the output voltage data without special identification and comparison. It represents the error of the voltage value. The smaller the error is, the closer the output voltage data is to the first preset output voltage or the second preset output voltage, and the more accurate the recognition of the level is. This indicates the correctness of the voltage value. It can show the accuracy of each output voltage data.

[0081] According to one embodiment of the present invention, by multiplying the accuracy of all the above level values ​​and the accuracy of all output voltage data, the calculation accuracy of the output data of the second test data of the chip under test at the sth second test moment can be obtained. By averaging the calculation accuracy of the output data of each correctly calculated second test data, the calculation accuracy of each output data can be obtained, which can be used as the level accuracy score.

[0082] In this way, the accuracy of each level value in the output data can be determined by cosine similarity, and the level corresponding to the output voltage data can be identified by taking the minimum function without special identification and comparison, which improves the convenience of calculation and determines the accuracy of the output voltage value. The output accuracy of the chip under test can be described from two aspects: the output level value and the accuracy of the output voltage value, and the level accuracy score is obtained, thereby improving the accuracy and comprehensiveness of the level accuracy score.

[0083] According to an embodiment of the present invention, the program operation performance score and the level accuracy score may be weighted and summed to obtain the operation performance score of the chip to be tested.

[0084] According to one embodiment of the present invention, in step S109, based on the computing performance score and the heat dissipation impact performance score, the performance of the chip under test can be reflected from two aspects: the computing power and the heat control capability of the chip under test, and a performance test report of the chip under test can be generated. The report can include a description of the computing power and the heat control capability of the chip under test.

[0085] According to the interactive chip performance test method of the embodiment of the present invention, the test equipment can have a temperature measurement function, so as to measure the temperature data at multiple positions around the chip to be tested, so as to determine the influence of the heat dissipation of the chip to be tested on the surrounding electronic devices during operation. In addition, the output level data of the chip to be tested may be detected by a voltage sensor, so as to determine the output accuracy and voltage accuracy of the chip to be tested, so as to facilitate comprehensive testing of the chip's operation and output performance and improve the accuracy of the test. When determining the heat dissipation influence function, based on the inverse correlation between temperature and distance, and the relationship between heat and distance during the diffusion process, the coefficient equation in the form of a quadratic polynomial can be set to accurately describe the relationship between the temperature of each position and the distance between each position and the origin, and then solve the coefficient to be determined to obtain the heat dissipation influence function, thereby improving the accuracy and objectivity of the heat dissipation influence function. When determining the heat dissipation impact performance score, the total impact of the chip under test on the surrounding electronic devices at a specific moment can be determined by integrating the heat dissipation impact function, and the maximum change rate of the total impact can be determined as the impact of the heat accumulated around the chip heat dissipation on the surrounding electronic devices, thereby obtaining the heat dissipation impact performance score, which can objectively and accurately reflect the temperature control ability of the chip under test and the impact on the surrounding electronic devices. When determining the program operation performance score, the conditional function can be used to screen the results of the chip under test operating each second test data, and compared with the predicted output data to determine the operation accuracy of the chip under test, and the average execution time of the program can also be determined to determine the program operation performance score, thereby reflecting the program execution ability of the chip under test from the two aspects of operation accuracy and operation efficiency. When determining the level accuracy score, the cosine similarity can be used to determine the accuracy of each level value in the output data, and the minimum value function can be used to identify the level corresponding to the output voltage data, without special identification and comparison, to improve the convenience of operation, and the operation accuracy of the output voltage value can be determined, thereby describing the output accuracy of the chip under test from the two aspects of the output level value and the accuracy of the output voltage value, and obtaining the level accuracy score, thereby improving the accuracy and comprehensiveness of the level accuracy score.

[0086] Figure 2 A block diagram of an interactive chip performance test system according to an embodiment of the present invention is exemplarily shown, the system comprising:

[0087] A division module, used for connecting multiple ports of the chip to be tested with the test ports of the interactive test device, and dividing the multiple ports of the chip to be tested into input ports and output ports;

[0088] A first input module, used to input a first operation parameter and a first test program into the chip under test through the interactive test device via multiple ports of the chip under test, wherein the first test program is a program that calls all computing power of the chip under test;

[0089] A first input module, used for inputting first test data to the input port according to a preset first input frequency;

[0090] A temperature data module is used to detect temperature data of multiple detection positions around the chip under test through a temperature sensor at multiple first test moments when the chip under test is running according to the first test program, the first test data and the first operation parameter;

[0091] A heat dissipation impact performance scoring module, used to obtain a heat dissipation impact performance score of the chip to be tested according to the temperature data and the detection position;

[0092] A second input module is used to clear the first operation parameter and the first test program through the interactive test device and multiple ports of the chip under test, and input second operation parameters and a second test program into the chip under test, wherein the second test program is a data operation program;

[0093] an acquisition module, used for inputting second test data to the chip under test at multiple second test moments, receiving output level data of the output port, and acquiring output voltage data through multiple voltage sensors arranged at the output port, wherein the output level data is multi-dimensional data, and the data of each dimension is 0 or 1;

[0094] An operation performance scoring module, used to determine the operation performance score of the chip to be tested according to the output level data and the output voltage data;

[0095] The test report module is used to obtain a performance test report of the chip to be tested according to the computing performance score and the heat dissipation impact performance score.

[0096] It should be understood by those skilled in the art that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The purpose of the present invention has been fully and effectively achieved. The functional and structural principles of the present invention have been demonstrated and explained in the embodiments, and the embodiments of the present invention may be deformed or modified in any way without departing from the principles.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An interactive chip performance testing method, characterized in that: include: Connecting multiple ports of the chip to be tested to the test ports of the interactive test device, and dividing the multiple ports of the chip to be tested into input ports and output ports; Entering a first operation parameter and a first test program into the chip under test through the interactive test device via multiple ports of the chip under test, wherein the first test program is a program that calls all computing power of the chip under test; Inputting first test data into the input port according to a preset first input frequency; At a plurality of first test moments when the chip under test is running according to the first test program, the first test data and the first operation parameter, detecting temperature data of a plurality of detection positions around the chip under test by a temperature sensor; Obtaining a heat dissipation impact performance score of the chip to be tested according to the temperature data and the detection position; Clearing the first operation parameter and the first test program through the interactive test device via multiple ports of the chip under test, and entering second operation parameters and a second test program into the chip under test, wherein the second test program is a data operation program; At multiple second test moments, input second test data to the chip under test, receive output level data of the output port, and obtain output voltage data through multiple voltage sensors arranged at the output port, wherein the output level data is multi-dimensional data, and the data of each dimension is 0 or 1; Determining a computing performance score of the chip to be tested according to the output level data and the output voltage data; A performance test report of the chip to be tested is obtained according to the computing performance score and the heat dissipation impact performance score.

2. The interactive chip performance testing method according to claim 1, characterized in that: Obtaining a heat dissipation impact performance score of the chip to be tested according to the temperature data and the detection position, including: A test coordinate system is established with the bottom centroid of the chip to be tested as the origin, the bottom surface of the chip to be tested as the XOY plane, and the direction perpendicular to the bottom surface of the chip to be tested as the Z-axis direction; Determine the position coordinates of the detection position in the test coordinate system; Determine the heat dissipation influence function at each first test moment according to the temperature data detected by the plurality of temperature sensors at each first test moment and the position coordinates; The heat dissipation impact performance score of the chip to be tested is determined according to the heat dissipation impact function at each first test moment.

3. The interactive chip performance testing method according to claim 2, characterized in that: Determining the heat dissipation influence function at each first test moment according to the temperature data detected by the plurality of temperature sensors at each first test moment and the position coordinates includes: According to the formula T 1,i,j =α1(x j ) 2 +α2(y j ) 2 +α3(z j ) 2 +α4x j y j +α5y j z j +α6x j z j +α7x j +α8y j +α9z j +a 10 Determine the undetermined coefficient equation of the heat dissipation influence function at the i-th first test moment, where T 1,i,j is the temperature data of the jth detection position at the i-th first test moment, (x j ,y j ,z j ) is the position coordinate of the jth detection position, α1, α2, α3, α4, α5, α6, α7, α8, α9 and α 10 is the coefficient to be determined; Solving the undetermined coefficients by using the temperature data at the multiple detection positions at the i-th first test moment and the position coordinates of the multiple detection positions to obtain the solution values ​​of the undetermined coefficients; The heat dissipation influence function at the i-th first test moment is obtained according to the solved value of the undetermined coefficient and the undetermined coefficient equation of the heat dissipation influence function at the i-th first test moment.

4. The interactive chip performance testing method according to claim 2, characterized in that: According to the heat dissipation impact function at each first test moment, the heat dissipation impact performance score of the chip under test is determined, including: According to the formula Determine the heat dissipation impact performance score S of the chip under test D , where T 1,i+1 (x, y, z) is the heat dissipation influence function at the first test time of the i+1th time, T 1,i (x, y, z) is the heat dissipation influence function at the i-th first test moment, Ω is the preset area around the chip to be tested, Δt1 is the time interval between adjacent first test moments, k p is the preset change rate, max is the maximum value function, n is the number of the first test moment, i≤n-1, and i and n are both positive integers.

5. The interactive chip performance testing method according to claim 1, characterized in that: Determining the computing performance score of the chip to be tested according to the output level data and the output voltage data includes: Obtaining predicted output data corresponding to the second test data according to the second test data, the second operation parameter and the second test program; Determining a program operation performance score according to the predicted output data, the output level data, the second test time corresponding to the output level data, and the second test time corresponding to the second test data; determining a level accuracy score based on the predicted output data, the output level data, and the output voltage data; The computing performance score of the chip to be tested is determined according to the program computing performance score and the level accuracy score.

6. The interactive chip performance testing method according to claim 5, characterized in that: Determining a program operation performance score according to the predicted output data, the output level data, the second test time corresponding to the output level data, and the second test time corresponding to the second test data includes: According to the formula Determine the program computing performance score S p , where O p,s is a vector composed of the predicted output data corresponding to the second test data at the s-th second test moment, ( p,s ) T O p,s The transposed vector of 2,s+h is a vector composed of the output level data at the s+hth second test moment, k sim is the preset similarity threshold, if is the conditional function, Δt2 is the time interval between adjacent second test moments, Δt p is the preset duration, m is the number of second test moments for inputting the second test data, w1 and w2 are preset weights, s≤m, and s, h and m are all positive integers.

7. The interactive chip performance testing method according to claim 6, characterized in that: Determining a level accuracy score according to the predicted output data, the output level data, and the output voltage data, comprising: Determine a first preset output voltage corresponding to a high level and a second preset output voltage corresponding to a low level; According to the formula Determine the level accuracy score S a , where O 2,s,c is a vector composed of output level data corresponding to the second test data at the second test time, U 2,s,g O 2,s,c The output voltage data corresponding to the output level data of the gth component, U 1,p is the first preset output voltage, U 2,p is the second preset output voltage, N s O 2,s,c The number of output level data in g≤N s , and g and N s They are all positive integers, and min is the minimum value function.

8. An interactive chip performance testing system, characterized in that: include: A division module, used for connecting multiple ports of the chip to be tested with the test ports of the interactive test device, and dividing the multiple ports of the chip to be tested into input ports and output ports; A first input module, used to input a first operation parameter and a first test program into the chip under test through the interactive test device via multiple ports of the chip under test, wherein the first test program is a program that calls all computing power of the chip under test; A first input module, used for inputting first test data to the input port according to a preset first input frequency; A temperature data module is used to detect temperature data of multiple detection positions around the chip under test through a temperature sensor at multiple first test moments when the chip under test is running according to the first test program, the first test data and the first operation parameter; A heat dissipation impact performance scoring module, used to obtain a heat dissipation impact performance score of the chip to be tested according to the temperature data and the detection position; A second input module is used to clear the first operation parameter and the first test program through the interactive test device and multiple ports of the chip under test, and input second operation parameters and a second test program into the chip under test, wherein the second test program is a data operation program; an acquisition module, used for inputting second test data to the chip under test at multiple second test moments, receiving output level data of the output port, and acquiring output voltage data through multiple voltage sensors arranged at the output port, wherein the output level data is multi-dimensional data, and the data of each dimension is 0 or 1; An operation performance scoring module, used to determine the operation performance score of the chip to be tested according to the output level data and the output voltage data; The test report module is used to obtain a performance test report of the chip to be tested according to the computing performance score and the heat dissipation impact performance score.

Images