Array substrate and manufacturing method thereof, liquid crystal display panel and terminal equipment

Abstract

The invention provides an array substrate and a manufacturing method thereof, a liquid crystal display panel and terminal equipment. The array substrate comprises a substrate and a first transistor arranged on the substrate. The first flat layer is arranged on the first transistor, comprises a plurality of first contact holes and extends downwards to the upper surface of the second electrode. The first common electrode is arranged on the first flat layer and comprises a plurality of electrode parts and conductive connecting parts connected with the electrode parts. The electrode part is located in the display area and comprises a first sub-part and a second sub-part which are connected, only the second sub-part extends along the hole wall of the first contact hole and has a first preset distance with the upper surface of the second electrode, and the conductive connecting part is located in the non-display area. The first insulating layer covers the first common electrode, and a second preset distance is formed between the first insulating layer and the upper surface of the second electrode. The pixel electrode is arranged on the first insulating layer and extends to the upper surface of the second electrode along the hole wall, and the first sub-part and the second sub-part are both arranged opposite to the pixel electrode. The second common electrode is insulated from the pixel electrode and is electrically connected with the first common electrode in the non-display area.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a liquid crystal display panel and a terminal device. Background Art

[0002] As the proportion of VR (virtual reality) products in the market gradually increases, consumers have higher and higher requirements for the resolution of VR products. In order to bring users a more realistic experience, high PPI (pixel resolution) display is an inevitable trend of development. High PPI means that the pixel pitch (pitch) is gradually reduced, which leads to a limited overlap area between the pixel electrode and the common electrode, and the storage capacitor formed is difficult to meet the charging requirements. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide an array substrate and a manufacturing method thereof, a liquid crystal display panel and a terminal device, so as to solve the problem that the storage capacitor formed by the high PPI liquid crystal display panel is difficult to meet the charging requirements due to the reduced pixel pitch and the limited overlap area between the pixel electrode and the common electrode. The specific technical solution is as follows:

[0004] According to a first aspect of the present application, there is provided an array substrate, comprising a display area and a non-display area arranged outside the display area, wherein the display area includes a plurality of sub-pixels, and the array substrate includes: a substrate substrate; a plurality of first transistors located in the display area, arranged on one side of the substrate substrate, including an active layer, a first gate insulating layer, a first gate, and a first electrode and a second electrode electrically connected to the active layer; a first planar layer, arranged on a side of the first transistor away from the substrate substrate, including a plurality of first contact holes arranged at intervals, wherein the first contact holes extend downwardly along the thickness direction of the array substrate to the upper surface of the second electrode; a first common electrode, arranged on a side of the first planar layer away from the substrate substrate, including a plurality of electrode portions arranged at intervals and a conductive connection portion connecting the electrode portions, wherein the electrode portions are located in the display area and correspond to a row or a column of sub-pixels, and the electrode portions include The present invention comprises a first sub-portion and a second sub-portion connected to each other, the first sub-portion is located outside the first contact hole, the second sub-portion extends along the hole wall of the first contact hole, the second sub-portion has a first preset distance from the upper surface of the second electrode, and the conductive connection portion is located in the non-display area; a first insulating layer, covering the first common electrode from the side away from the base substrate, and having a second preset distance from the upper surface of the second electrode; a pixel electrode, arranged on the side of the first insulating layer away from the base substrate, and extending along the hole wall of the first contact hole to the upper surface of the second electrode, the first sub-portion and the second sub-portion are both arranged opposite to the pixel electrode; a second insulating layer, covering the pixel electrode from the side away from the base substrate; a second common electrode, arranged on the side of the second insulating layer away from the base substrate, and electrically connected to the first common electrode in the non-display area.

[0005] In some embodiments, the array substrate also includes a second flat layer for filling the first contact hole, and the pixel electrode includes a first sub-electrode and a second sub-electrode; the first sub-electrode is arranged on a side of the first insulating layer away from the base substrate, and extends along the hole wall of the first contact hole to the upper surface of the second electrode, and the orthographic projection along the thickness direction of the array substrate that does not overlap with the first contact hole is recorded as the first part; the second sub-electrode includes a third part and a fourth part, the third part is located above the first part and contacts each other, the fourth part is located on the second flat layer on at least one side of the third part along the first direction, and the orthographic projection of the fourth part on the base substrate only overlaps with the orthographic projection of a pixel electrode of a sub-pixel on the base substrate, and the third part and the fourth part are both arranged opposite to the second common electrode.

[0006] In some embodiments, the orthographic projection of the extending portion of the second sub-portion along the hole wall of one of the first contact holes on the substrate is 0.12 times to 0.15 times the orthographic projection of the total extending length of a single electrode portion on the substrate.

[0007] In some embodiments, the first preset distance is equal to the second preset distance.

[0008] In some embodiments, the first preset distance is greater than or equal to 1 / 10 and less than or equal to 1 / 3 of the depth of the first contact hole.

[0009] In some embodiments, the first pole and the second pole are arranged in different layers, a first interlayer insulating layer is provided between the first pole and the second pole, and the first pole is located on a side of the first interlayer insulating layer close to the base substrate.

[0010] In some embodiments, the array substrate includes a first routing line and a second routing line, the first routing line is arranged on the same layer as the first electrode, and the second routing line is arranged on the same layer as the first gate; the second common electrode is electrically connected to the first routing line through a first via hole, the first common electrode is electrically connected to the second routing line through a second via hole, and the first routing line is electrically connected to the second routing line through a third via hole.

[0011] In some embodiments, the first transistor further includes a second gate, the second gate is located on a side of the active layer close to the substrate, and the first gate is located on a side of the active layer away from the substrate; the orthographic projection of the first gate on the substrate is located within the orthographic projection of the second gate on the substrate.

[0012] In some embodiments, the array substrate includes a color resist layer, the color resist layer includes at least a first color resist, a second color resist and a third color resist arranged in an array in sequence, and the color resist layer is disposed on a side of the planar layer close to the base substrate.

[0013] In some embodiments, the second common electrode has a plurality of first openings in the display area, the orthographic projection of the first openings on the base substrate partially overlaps with the orthographic projection of a single pixel electrode on the base substrate, and the orthographic projection of the first opening along its long side direction on the base substrate surrounds the orthographic projection of the corresponding color resist along the long side direction on the base substrate.

[0014] A second aspect of the present application provides a method for manufacturing an array substrate, which is used to manufacture the array substrate described above, wherein the array substrate has a display area and a non-display area provided on at least one side of the display area, the display area includes a plurality of sub-pixels, and the array substrate comprises the following steps:

[0015] providing a substrate base plate;

[0016] On one side of the base substrate, a first transistor located in the display area is manufactured, wherein the first transistor comprises an active layer, a first gate insulating layer, a first gate, and a first electrode and a second electrode electrically connected to the active layer;

[0017] Prepare a first planar layer on a side of the first transistor away from the substrate;

[0018] Etching the first planar layer until the upper surface of the second electrode is exposed;

[0019] A first common electrode is formed on a side of the first flat layer away from the base substrate, comprising a plurality of electrode portions arranged at intervals and a conductive connection portion connecting the electrode portions, wherein the electrode portion is located in the display area and corresponds to a row or a column of sub-pixels, wherein the electrode portion comprises a first sub-portion and a second sub-portion connected to each other, wherein the first sub-portion is located outside the first contact hole, the second sub-portion extends along the hole wall of the first contact hole, the second sub-portion has a first preset distance from the upper surface of the second electrode, and the conductive connection portion is located in the non-display area;

[0020] forming a first insulating layer on the first common electrode, wherein the first insulating layer covers the first common electrode;

[0021] Etching the first insulating layer at a position corresponding to the first contact hole until the upper surface of the second electrode is exposed and a second contact hole is formed;

[0022] A first pixel electrode is formed on a side of the first insulating layer away from the base substrate, the first pixel electrode is electrically connected to the second electrode through the second contact hole, and the first sub-portion and the second sub-portion are both arranged opposite to the pixel electrode;

[0023] Forming a second insulating layer on a side of the first pixel electrode away from the base substrate;

[0024] A second common electrode is formed on a side of the second insulating layer away from the base substrate, and the first common electrode is electrically connected to the second common electrode in a non-display area.

[0025] In some embodiments, the non-display area of ​​the array substrate includes a first routing line and a second routing line, the first routing line is synchronously produced with the first pole, the second routing line is synchronously produced with the first gate, the first via hole is synchronously produced with the first contact hole and the second contact hole, the second via hole is synchronously produced with the via hole of the second pole, and the third via hole is synchronously produced with the via hole of the first pole; the first common electrode is electrically connected to the second routing line through the second via hole, the second common electrode is electrically connected to the first routing line through the first via hole, and the first routing line is electrically connected to the second routing line through the third via hole.

[0026] A third aspect of the present application provides a liquid crystal display panel, comprising the array substrate described above, a matching substrate arranged in a box with the array substrate, and a liquid crystal layer located between the array substrate and the matching substrate.

[0027] A fourth aspect of the present application provides a terminal device, characterized in that it includes the liquid crystal display panel mentioned above.

[0028] Beneficial effects of the embodiments of the present application:

[0029] The array substrate and its manufacturing method, liquid crystal display panel and terminal device provided by the embodiment of the present application are that the array substrate increases a layer of first common electrode, and the first common electrode and the second common electrode are electrically connected in the non-display area, so the overlapping area between the first common electrode and the pixel electrode increases, which is equivalent to the increase of the overlapping area between the overall common electrode and the pixel electrode. The first common electrode and the pixel electrode have overlapping parts not only outside the first contact hole, but also inside the first contact hole. Although the pixel pitch is reduced due to the requirement of high PPI, resulting in a reduction in the overlapping area between the pixel electrode and the common electrode, by adding a layer of first common electrode, which is arranged opposite to the pixel electrode in the first contact hole, the overlapping area between the two is increased, so that the overlapping area between the pixel electrode and the common electrode does not decrease due to the reduction in the pixel pitch. That is to say, the first common electrode can make up for the problem of insufficient storage capacitance caused by the reduction in pixel pitch because it is arranged opposite to the pixel electrode in the first contact hole.

[0030] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0032] Figure 1 A schematic cross-sectional view of an array substrate provided in an embodiment of the present application along a column of sub-pixels;

[0033] Figure 2 for Figure 1 A magnified schematic diagram of the S part;

[0034] Figure 3 A schematic cross-sectional view of an array substrate provided in an embodiment of the present application along a row of sub-pixels;

[0035] Figure 4 is a simplified structural schematic diagram of a first common electrode;

[0036] Figure 5 is a schematic diagram of the extension structure of a single electrode portion in the first contact hole;

[0037] Figure 6 is a top view of a non-display area of ​​an array substrate;

[0038] Figure 7 for Figure 6 Section view along section line BB;

[0039] Figure 8 A top view of the first planar layer, the first common electrode, the first insulating layer, the first sub-electrode, and the second sub-electrode;

[0040] Fig. 9 It is a top view of the first planar layer, the first common electrode, the first insulating layer, the first sub-electrode, the second sub-electrode and the second common electrode.

[0041] The reference numerals are as follows:

[0042] Array substrate 100; display area AA; non-display area NA; substrate 101; first transistor T; active layer 102; first gate insulating layer 103; first gate 104; first electrode 105; interlayer insulating layer 106; first interlayer insulating layer 107; second electrode 108; second gate insulating layer 109; second gate 110; first flat layer 111; first contact hole 1111; first common electrode 112; electrode portion 1121; first sub-portion 11211; second sub-portion 11212; conductive connecting portion 1122; first insulating layer 113; second contact hole 1131; pixel electrode 114; first sub-electrode 1141; first part 11411; second part 11412; second sub-electrode 1142; third part 11421; fourth part 11422; second flat layer 115; second insulating layer 116; second common electrode 117; first opening 1171; first wiring 118; second wiring 119; first via 120; second via 121; third via 122; common auxiliary electrode 123; buffer layer 130; second interlayer insulating layer 131; shielding metal 132; color resist layer 140; first color resist 141; second color resist 142; first preset distance L1; second preset distance L2; thickness direction H. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0044] In order to solve the problem that the pixel pitch of a liquid crystal display panel is gradually reduced due to the demand for high PPI, which leads to a reduction in the overlap area between the pixel electrode 114 and the common electrode, so that the storage capacitance formed between the pixel electrode 114 and the common electrode is reduced, and it is difficult to meet the charging requirement. To this end, the first aspect of the embodiment of the present application provides an array substrate 100, such as Figure 1 , Figure 2 , Figure 3 As shown, Figure 1 is a cross-sectional view of the array substrate 100 along a column of sub-pixels, Figure 2 for Figure 1 The enlarged schematic diagram of the S part, Figure 3 : is a schematic cross-sectional view of an array substrate along a row of sub-pixels. In order to clearly illustrate the solution of the present application, the direction of a row of sub-pixels is defined as X, the direction of a column of sub-pixels is defined as Y, and the thickness direction H of the display module is perpendicular to the X direction and the Y direction. The array substrate 100 has a display area AA and a non-display area NA disposed outside the display area AA, such as Figure 1As shown in the figure, the left side of the dotted line is the display area AA, and the right side of the dotted line is the non-display area NA. The display area AA includes a plurality of sub-pixels, and the array substrate 100 includes: a base substrate 101, a plurality of first transistors T located in the display area AA, a first flat layer 111, a first common electrode 112, a first insulating layer 113, a first pixel electrode 114, a second insulating layer 116, and a second common electrode 117.

[0045] The first transistor T is disposed on one side of the base substrate 101, and includes an active layer 102, a first gate insulating layer 103, a first gate 104, and a first electrode 105 and a second electrode 108 electrically connected to the active layer 102. The first planar layer 111 is disposed on a side of the first transistor T away from the base substrate 101, and includes a plurality of first contact holes 1111 disposed at intervals, and the first contact holes 1111 extend downward along the thickness direction H of the array substrate 100 to the upper surface of the second electrode 108. The first common electrode 112 is disposed on a side of the first flat layer 111 away from the base substrate 101, and includes a plurality of electrode portions 1121 disposed at intervals and a conductive connection portion 1122 connected to the electrode portions 1121. The electrode portion 1121 is located in the display area AA and corresponds to a row or a column of sub-pixels. The electrode portion 1121 includes a first sub-portion 11211 and a second sub-portion 11212 connected to each other. The first sub-portion 11211 is located outside the first contact hole 1111, and the second sub-portion 11212 extends along the hole wall of the first contact hole 1111. The second sub-portion 11212 has a first preset distance L1 from the upper surface of the second electrode 108, and the conductive connection portion 1122 is located in the non-display area NA. The first insulating layer 113 covers the first common electrode 112 from the side away from the base substrate 101, and has a second preset distance L2 from the upper surface of the second electrode 108. The pixel electrode 114 is disposed on a side of the first insulating layer 113 away from the base substrate 101, and extends along the hole wall of the first contact hole 1111 to the upper surface of the second electrode 108, and the first sub-portion 11211 and the second sub-portion 11212 are both disposed opposite to the pixel electrode 114. The second insulating layer 116 covers the pixel electrode 114 from a side away from the base substrate 101. The second common electrode 117 is disposed on a side of the second insulating layer 116 away from the base substrate 101, and is electrically connected to the first common electrode 112 in the non-display area NA.

[0046] The first transistor T is disposed in the display area AA and is a transistor in the pixel circuit. The non-display area NA of the array substrate 100 also includes a peripheral circuit, which includes a second transistor (not shown in the figure). The peripheral circuit is a circuit for driving the pixel circuit.

[0047] The first transistor T includes an active layer 102, a first gate electrode 104 opposite to the active layer 102, a gate insulating layer between the active layer 102 and the first gate electrode 104, and a first electrode 105 and a stacked second electrode 108 electrically connected to the active layer 102. The gate insulating layer is used to insulate the first gate electrode 104 from the active layer 102, and the gate insulating layer can be made of inorganic materials, such as silicon oxide, silicon nitride and other inorganic materials. The active layer 102 can be a single crystal silicon semiconductor layer, a polycrystalline silicon semiconductor layer or an oxide semiconductor layer, preferably an oxide semiconductor layer. One of the first electrode 105 and the second electrode 108 is a source electrode, and the other is a drain electrode.

[0048] The first transistor T may be a thin film transistor, and the thin film transistor may be a top gate type, a bottom gate type, or a top-bottom gate type. The first electrode 105 and the second electrode 108 may be arranged in the same layer as the first gate 104, or in different layers. This embodiment shows the situation where the first electrode 105 and the second electrode 108 are arranged on the side of the first gate 104 away from the substrate 101, that is, the first electrode 105 and the second electrode 108 are arranged in different layers from the first gate 104. The first electrode 105, the second electrode 108 and the first gate 104 are separated by at least one interlayer insulating layer 106. The first electrode 105 and the second electrode 108 may be arranged in the same layer or in different layers. When the two are arranged in different layers, the first electrode 105 and the second electrode 108 are separated by an interlayer insulating layer 106. When the two are arranged in different layers, it is preferred that the second electrode 108 is further away from the substrate 101 than the first electrode 105, so that when the pixel electrode 114 is electrically connected to the second electrode 108, fewer film layers need to be etched, which can reduce the difficulty of etching.

[0049] The base substrate 101 may be a flexible base substrate 101, such as a polyimide (PI) substrate, or a rigid base substrate 101, such as a glass substrate. A buffer layer 130 is generally provided on the base substrate 101, and then the film layers related to the first transistor T are prepared on the buffer layer 130.

[0050] When the first electrode 105 and the second electrode 108 are arranged in the same layer, the first flat layer 111 is arranged on the side of the first electrode 105 and the second electrode 108 away from the base substrate 101. When the first electrode 105 and the second electrode 108 are arranged in different layers, the first flat layer 111 is arranged on the side of the second electrode 108 away from the base substrate 101. The first flat layer 111 may be an organic resin layer.

[0051] Combination Figure 1 , Figure 3 , Figure 4 and Figure 5As shown, the first common electrode 112 has a plurality of electrode portions 1121 spaced apart in the display area AA, and a conductive connection portion 1122 in the non-display area NA, that is, the plurality of electrode portions 1121 are disconnected from each other in the display area AA, and are connected as a whole through the conductive connection portion 1122 in the non-display area NA. Each electrode portion 1121 may correspond to a row or a column of sub-pixels, and the present embodiment shows a situation where the electrode portion 1121 corresponds to a row of sub-pixels. The electrode portion 1121 includes a first sub-portion 11211 and a second sub-portion 11212, the first sub-portion 11211 being located outside the first contact hole 1111, the second sub-portion 11212 extending along the hole wall of the first contact hole 1111, and having a first preset distance L1 from the upper surface of the second electrode 108, that is, the first common electrode 112 is not in contact with the second electrode 108. By Figure 5 It can be seen that the second sub-portions 11212 are respectively located in two adjacent first contact holes 1111 .

[0052] A first insulating layer 113 is disposed on a side of the first common electrode 112 away from the base substrate 101, and the first insulating layer 113 is used to insulate and isolate the first common electrode 112 from the pixel electrode 114. The first insulating layer 113 can be made of an inorganic material or an organic material, such as SPVX (a polyvinyl chloride insulating layer modified by a certain material or a specific process). Figure 2 The first insulating layer 113 covers the surface of the first common electrode 112, and has a second preset distance L2 from the upper surface of the second electrode 108. In a specific implementation process, it can be: depositing a whole layer of the first insulating layer 113, and providing a second contact hole 1131 at a position of the first insulating layer 113 corresponding to the first contact hole 1111, that is, the second contact hole 1131 is nested in the first contact hole 1111, and the upper surface of the second electrode 108 is exposed through the second contact hole 1131, so when the pixel electrode 114 is formed on the first insulating layer 113, it can be electrically connected to the upper surface of the second electrode 108 through the second contact hole 1131.

[0053] The first common electrode 112 and the pixel electrode 114 are arranged opposite to each other outside the first contact hole 1111 and are also arranged opposite to each other inside the first contact hole 1111, wherein the opposite arrangement can be understood as the two being arranged roughly in parallel. A second insulating layer 116 is provided on the side of the pixel electrode 114 away from the base substrate 101, and the second insulating layer 116 is used to insulate and isolate the first pixel electrode 114 from the second common electrode 117. The second insulating layer 116 can be made of an inorganic material or an organic material, such as PVX (an insulating layer made of a polyvinyl chloride-based material). The second common electrode 117 is electrically connected to the first common electrode 112 in the non-display area NA.

[0054] In this embodiment, by adding a layer of the first common electrode 112, the first common electrode 112 and the second common electrode 117 are electrically connected in the non-display area NA, so the overlapping area between the first common electrode 112 and the pixel electrode 114 increases, which is equivalent to the increase in the overlapping area between the overall common electrode and the pixel electrode 114. The first common electrode 112 and the pixel electrode 114 have overlapping portions not only outside the first contact hole 1111, but also inside the first contact hole 1111. Although the pixel pitch is reduced due to the requirement of high PPI, resulting in a reduction in the overlapping area between the pixel electrode 114 and the common electrode, by adding a layer of the first common electrode 112, the first common electrode 112 is arranged opposite to the pixel electrode 114 in the first contact hole 1111, and the overlapping area between the two is increased, so that the overlapping area between the pixel electrode 114 and the common electrode does not decrease due to the reduction in the pixel pitch. That is to say, the first common electrode 112 can make up for the problem of insufficient storage capacitance caused by the reduction in the pixel pitch because it is arranged opposite to the pixel electrode 114 in the first contact hole 1111.

[0055] This is because the storage capacitance is proportional to the area facing the electrode plates. As the overlapping area between the common electrode and the pixel electrode 114 increases, that is, the facing area increases, the storage capacitance is increased, which is used to maintain sufficient voltage applied to the pixel electrode 114, improve the stability of the voltage of the pixel electrode 114, and ensure the stability of the image display, so that the liquid crystal display panel can further improve the PPI.

[0056] In some embodiments, Figure 1 As shown, a common auxiliary electrode 123 that is in contact and electrically connected with the second common electrode 117 is also provided on the side of the second common electrode 117 close to the base substrate 101. The common auxiliary electrode 123 (CMTL) is a metal layer, and the first common electrode 112 and the second common electrode 117 are transparent metal layers. Compared with the resistance of the second common electrode, the resistance of the common auxiliary electrode 123 is lower. In addition, the common auxiliary electrode 123 also acts as a light shielding layer. For example, by shielding light from adjacent pixels, the occurrence of color mixing can be suppressed. The common auxiliary electrode 123 may be consistent with the pattern of the second common electrode 117, or it may be inconsistent. This application does not limit this.

[0057] In some embodiments, Figure 1 , Figure 2As shown, the array substrate 100 further includes a second flat layer 115 for filling the first contact hole 1111. The pixel electrode 114 includes a first sub-electrode 1141 and a second sub-electrode 1142. The first sub-electrode 1141 is disposed on a side of the first insulating layer 113 away from the base substrate 101, and extends along the hole wall of the first contact hole 1111 to the upper surface of the second electrode 108, and the orthographic projection along the thickness direction H of the array substrate 100 that does not overlap with the first contact hole 1111 is recorded as the first portion 11411. The second sub-electrode 1142 includes a third part 11421 and a fourth part 11422, the third part 11421 is located on the first part 11411 and contacts each other, the fourth part 11422 is located on the second flat layer 115 on at least one side of the third part 11421 along the first direction, and the orthographic projection of the fourth part 11422 on the base substrate 101 only overlaps with the orthographic projection of the pixel electrode 114 of one sub-pixel on the base substrate 101, and the third part 11421 and the fourth part 11422 are both arranged opposite to the second common electrode 117.

[0058] In this embodiment, the portion where the orthographic projection of the second sub-electrode 1142 along the thickness direction H of the array substrate 100 overlaps with the first contact hole 1111 is recorded as the second portion 11412. Figure 2 The first portion 11411 is the portion of the first sub-electrode 1141 located outside the first contact hole 1111, and the second portion 11412 is the portion of the first sub-electrode 1141 extending along the hole wall. The third portion 11421 is the portion of the second sub-electrode 1142 located above the first portion 11411, that is, Figure 2 The fourth portion 11422 is the portion between the two dotted lines in the figure. The fourth portion 11422 is the portion of the second sub-electrode 1142 located on the second planar layer 115, that is, the portion to the left of the left dotted line and to the right of the right dotted line. The fourth portion 11422 has two sections. The first contact hole 1111 is filled with the second flat layer 115, that is, the second flat layer 115 can make up for the step difference between the first part 11411 and the second part 11412 of the first sub-electrode 1141, and then the second sub-electrode 1142 is arranged above the first part 11411 and the second flat layer 115, so that the fourth part 11422 of the second sub-electrode 1142 is also arranged opposite to the second common electrode 117. Therefore, not only the opposite area between the pixel electrode 114 and the second common electrode 117 is increased, but also the distance between the two electrode plates is reduced. According to the relationship that the capacitance is proportional to the opposite area between the electrode plates and inversely proportional to the distance between the electrode plates, the storage capacitance between the pixel electrode 114 and the second common electrode 117 can be increased to maintain sufficient voltage applied to the pixel electrode 114, improve the stability of the voltage of the pixel electrode 114, and ensure the stability of image display, so that the liquid crystal display panel can further improve the PPI.

[0059] The orthographic projection of the fourth portion 11422 on the substrate 101 only overlaps with the orthographic projection of the pixel electrode 114 of one sub-pixel on the substrate 101, that is, the orthographic projection of the fourth portion 11422 on the substrate 101 does not overlap with the orthographic projection of the pixel electrode 114 of another adjacent sub-pixel on the substrate 101. In this way, no storage capacitor is formed between the fourth portion 11422 and the first sub-electrode 1141 of the adjacent pixel, and no short circuit is formed with the second sub-electrode 1142 of the adjacent pixel, so that no crosstalk or short circuit problems occur between adjacent sub-pixels.

[0060] Exemplarily, when the fourth portion 11422 is provided on both sides of the third portion 11421, the fourth portion 11422 corresponds to two adjacent first contact holes 1111, and the pixel electrode 114 in each first contact hole 1111 corresponds to a sub-pixel, and the pixel electrode 114 corresponding to the fourth portion 11422 depends on the first sub-electrode 1141 below, and the first sub-electrode 1141 is only electrically connected to the second electrode 108 exposed by one of the first contact holes 1111, and the pixel electrode 114 is only used to drive the conduction and cutoff of the first transistor T corresponding to the second electrode 108. The orthographic projection of the fourth portion 11422 on the base substrate 101 does not overlap with the orthographic projection of the pixel electrode 114 of the adjacent sub-pixel on the base substrate 101, which can prevent crosstalk between adjacent sub-pixels, thereby avoiding signal crosstalk and other defects.

[0061] In some embodiments, the second sub-electrode 1142 includes a third portion 11421 and fourth portions 11422 located at both sides of the third portion 11421 along the horizontal direction.

[0062] In this embodiment, the fourth portion 11422 is provided on both sides of the third portion 11421, which can increase the area of ​​the fourth portion 11422 facing the second common electrode 117, further increase the storage capacitance between the pixel electrode 114 and the common electrode, and is used to maintain sufficient voltage applied to the pixel electrode 114, thereby improving the voltage stability of the pixel electrode 114. The projection of the fourth portion 11422 on the base substrate 101 does not overlap with the positive projection of the pixel electrode 114 of the adjacent sub-pixel on the base substrate 101, that is, the first sub-electrode 1141 only covers a portion of the first contact hole 1111, and two adjacent sub-pixels can share one first contact hole 1111, thereby reducing the pixel pitch and improving the pixel density, which is beneficial to improving the high resolution of the liquid crystal display panel.

[0063] Figure 5 Optionally, the first sub-electrode 1141 may cover a half of the first contact hole 1111 , so that there is enough design space for the second sub-electrode 1142 of another sub-pixel.

[0064] In some embodiments of the present application, Figure 3 , Figure 4 and Figure 5 As shown, the length of the orthographic projection of the second sub-portion 11212 along the hole wall extension portion of one of the first contact holes 1111 on the substrate 101 is 0.12 times to 0.15 times the total length of the orthographic projection of the single electrode portion 1121 on the substrate 101 .

[0065] It should be noted that, combined with Figure 5 , a single electrode portion 1121 is composed of a second sub-portion 11212 located in two adjacent first contact holes 1111 and a first sub-portion 11211 located between the two first contact holes 1111. The length of the orthographic projection of the second sub-portion 11212 along the hole wall extension of one of the first contact holes 1111 on the base substrate 101 accounts for 0.12 times to 0.15 times the total length of the orthographic projection of the single electrode portion 1121 on the base substrate 101, that is, the area directly facing the single electrode portion 1121 and the first sub-electrode 1141 mainly depends on the overlapping area of ​​the first sub-portion 11211 and the first portion 11411, and the overlapping area of ​​the second sub-portion 11212 and the second portion 11412 plays an additional supplementary role. By increasing the overlapping area of ​​the second sub-portion 11212 and the second portion 11412, the storage capacitance between the pixel electrode 114 and the common electrode can be increased from 8fF (femtofarad) to 24fF (femtofarad).

[0066] Optionally, in one embodiment, the length of the orthographic projection of the extending portion of the second sub-portion 11212 along the first contact hole 1111 on the substrate 101 is 0.8μm-1.2μm, for example, it can be 0.8μm, 0.9μm, 1.0μm, 1.1μm, etc., and the total length of the orthographic projection of one electrode portion on the substrate 101 is 6.5μm-7.5μm, for example, it can be 6.5μm, 7.0μm, 7.5μm, etc.

[0067] In some embodiments of the present application, the first preset distance L1 is equal to the second preset distance L2. The "equal" here can be understood as being approximately equal, because the first insulating layer 113 needs to cover the first common electrode 112, so there is at least one thickness difference of the first insulating layer 113 between the two, but since the thickness of the first insulating layer 113 is very small, it can be ignored. The first preset distance L1 is approximately equal to the second preset distance L2, that is, the first insulating layer 113 only needs to cover the first common electrode 112 and no longer extends downward along the hole wall of the first contact hole 1111. In this way, the pixel electrode 114 can directly contact the first flat layer 111 below the first common electrode 112 in the first contact hole 1111, and the pixel electrode 114 has better contact and adhesion with the first flat layer 111, which is conducive to improving the continuity of the pixel electrode 114 and reducing the probability of poor climbing.

[0068] In some embodiments of the present application, the first preset distance L1 is greater than or equal to 1 / 10 and less than or equal to 1 / 3 of the depth of the first contact hole 1111 , for example, it may be 1 / 10, 1 / 9, 1 / 8, 1 / 7, 1 / 6, 1 / 5, 1 / 4, 1 / 3, etc. of the depth of the first contact hole 1111 .

[0069] In this embodiment, the first preset distance L1 is greater than or equal to 1 / 10 of the depth of the first contact hole 1111, so that there is a sufficient distance between the first common electrode 112 and the second electrode 108 to avoid a short circuit connection between the two. The first preset distance L1 is less than or equal to 1 / 3 of the depth of the first contact hole 1111, so that the pixel electrode 114 and the first common electrode 112 have a larger overlapping area in the hole, thereby increasing the storage capacitance between the pixel electrode 114 and the common electrode.

[0070] In some embodiments of the present application, Figure 1 , Figure 2 As shown, the first electrode 105 and the second electrode 108 are arranged in different layers, a first interlayer insulating layer 107 is arranged between the first electrode 105 and the second electrode 108, and the first electrode 105 is located on the side of the first interlayer insulating layer 107 close to the base substrate 101. The first electrode 105 and the second electrode 108 are arranged in different layers, which can reasonably utilize the layout space of each layer, reasonably distribute one layer of wiring to two layers, solve the problem of wiring difficulty, and help improve the pixel density of the array substrate 100. Compared with the first electrode 105, the second electrode 108 is farther away from the base substrate 101, which can shorten the depth of the via hole between the pixel electrode 114 and the second electrode 108 and reduce the difficulty of etching.

[0071] In some embodiments of the present application, Figure 1 , Figure 6 and Figure 7As shown, the array substrate 100 includes a first wiring 118 and a second wiring 119, the first wiring 118 is arranged in the same layer as the first electrode 105, and the second wiring 119 is arranged in the same layer as the first gate 104. The second common electrode 117 is electrically connected to the first wiring 118 through a first via 120, the first common electrode 112 is electrically connected to the second wiring 119 through a second via 121, and the first wiring 118 is electrically connected to the second wiring 119 through a third via 122.

[0072] In this embodiment, the first wiring 118 is used to input a signal to the common electrode, the second common electrode 117 is directly electrically connected to the first wiring 118, and the first common electrode 112 is switched through the second wiring 119 to be electrically connected to the first wiring 118, thereby realizing the electrical connection between the first common electrode 112 and the second common electrode 117 in the non-display area NA. The second via hole 121 and the via hole connecting the second pole 108 and the active layer 102 are only one layer of the first gate insulating layer 103 apart, and the etching depth difference is small, and a mask can be shared. The third via hole 122 and the via hole connecting the first pole 105 and the active layer 102 are also only one layer of the first gate insulating layer 103 apart, and the etching depth difference is small, and a mask can be shared.

[0073] In some embodiments of the present application, Figure 1 , Figure 2 As shown, the first transistor T further includes a second gate 110, which is located on a side of the active layer 102 close to the substrate 101, and the first gate 104 is located on a side of the active layer 102 away from the substrate 101. The orthographic projection of the first gate 104 on the substrate 101 is located within the orthographic projection of the second gate 110 on the substrate 101.

[0074] The active layer 102 and the first gate 104 and the second gate 110 all form a channel. The second gate insulating layer 109 between the active layer 102 and the second gate 110 is relatively thick, so the first gate 104 plays a major role. This can increase the on-state current (I on ), the two channels work together for a better effect. And the orthographic projection of the first gate 104 on the base substrate 101 is located within the orthographic projection of the second gate 110 on the base substrate 101, and the second gate 110 can also play the role of shielding the channel.

[0075] like Figure 1As shown, the array substrate 100 also includes a shielding metal 132, which is arranged on the side of the second gate 110 close to the base substrate 101, and a second interlayer insulating layer 131 is provided between the shielding metal 132 and the second gate 110 for insulating the two. The orthographic projection of the via hole electrically connecting the first pole 105 and the first active layer 102 on the base substrate 101 is located within the orthographic projection of the shielding metal 132 on the base substrate 101, so that the shielding metal 132 can shield the light leakage of the via hole electrically connecting the first pole 105 and the active layer 102.

[0076] In some embodiments of the present application, Figure 1 , Figure 2 As shown, the array substrate 100 includes a color resist layer 140 , which includes at least a first color resist 141 , a second color resist 142 and a third color resist (not shown) arranged in an array in sequence. The color resist layer 140 is disposed on a side of the flat layer close to the base substrate 101 .

[0077] The technology of preparing the color resist layer 140 on the array substrate 100 is also called COA (Color filter on array). The COA structure reduces the coupling between the pixel electrode 114 and the metal wiring, and the delay of the signal on the metal line is improved. The COA structure can significantly reduce the size of the parasitic capacitance, increase the aperture ratio of the liquid crystal display panel, and improve the display quality of the liquid crystal display panel.

[0078] Combination Figure 1 , Figure 3 , Figure 8 , Fig. 9 The second common electrode 117 has a plurality of first openings 1171 in the display area AA, and the orthographic projection of the first opening 1171 on the base substrate 101 partially overlaps with the orthographic projection of a single pixel electrode 114 on the base substrate 101, and the orthographic projection of the first opening 1171 along its long side direction on the base substrate 101 surrounds the orthographic projection of the corresponding color resist along the long side direction on the base substrate 101.

[0079] The second common electrode 117 is provided with a first opening 1171 at a position corresponding to a single pixel electrode and a color resistor, which can optimize the distribution of the electric field in the pixel electrode 114, thereby improving the alignment of the liquid crystal molecules and enhancing the display effect. The position and size of the first opening 1171 can be precisely designed according to actual needs, thereby achieving more precise control of the liquid crystal molecules and improving the display precision and contrast.

[0080] The first opening 1171 of the second common electrode 117 surrounds the corresponding color resistance along its long side direction, that is, the coverage area of ​​the second common electrode 117 along the long side direction is larger than the area of ​​the corresponding color resistance, which can ensure that the liquid crystal molecules in the color resistance area are within the effective electric field range, so that the color resistance can be controlled by a relatively uniform electric field, thereby making the color display more uniform and accurate, which helps to improve the display quality of the entire screen. However, the first opening 1171 should not be too large, which will increase the risk of mutual interference between the electric fields of adjacent pixels.

[0081] In a second aspect of the present application, a method for manufacturing an array substrate 100 is provided, which is used to manufacture the array substrate described above. The array substrate 100 has a display area AA and a non-display area NA provided on at least one side of the display area AA. The display area AA includes a plurality of sub-pixels. The array substrate 100 includes the following steps:

[0082] S1: providing a base substrate 101 .

[0083] S2: On one side of the base substrate 101 , a first transistor T is manufactured in the display area AA. The first transistor T includes an active layer 102 , a first gate insulating layer 103 , a first gate 104 , and a first electrode 105 and a second electrode 108 electrically connected to the active layer 102 .

[0084] S3 : preparing a first planar layer 111 on a side of the first transistor T away from the substrate 101 .

[0085] S4: Etching the first planar layer 111 until the upper surface of the second electrode 108 is exposed.

[0086] S5: A first common electrode 112 is formed on a side of the first flat layer 111 away from the base substrate 101, including a plurality of electrode portions 1121 spaced apart and a conductive connection portion 1122 connecting the electrode portions 1121, the electrode portion 1121 is located in the display area AA and corresponds to a row or a column of sub-pixels, the electrode portion 1121 includes a first sub-portion 11211 and a second sub-portion 11212 connected to each other, the first sub-portion 11211 is located outside the first contact hole 1111, the second sub-portion 11212 extends along the hole wall of the first contact hole 1111, the second sub-portion 11212 has a first preset distance L1 from the upper surface of the second electrode 108, and the conductive connection portion 1122 is located in the non-display area NA.

[0087] S6 : forming a first insulating layer 113 on the first common electrode 112 , wherein the first insulating layer 113 covers the first common electrode 112 .

[0088] S7: etching the first insulating layer 113 at a position corresponding to the first contact hole 1111 until the upper surface of the second electrode 108 is exposed, and forming a second contact hole 1131 .

[0089] S8: A first pixel electrode 114 is formed on a side of the first insulating layer 113 away from the base substrate 101 . The first pixel electrode 114 is electrically connected to the second electrode 108 through the second contact hole 1131 . The first sub-portion 11211 and the second sub-portion 11212 are both arranged opposite to the pixel electrode 114 .

[0090] S9 : forming a second insulating layer 116 on a side of the first pixel electrode 114 away from the base substrate 101 .

[0091] S10 : forming a second common electrode 117 on a side of the second insulating layer 116 away from the base substrate 101 , and the first common electrode 112 is electrically connected to the second common electrode 117 in the non-display area NA.

[0092] The array substrate 100 provided in the present embodiment has a first common electrode 112 layer arranged between the first flat layer 111 and the pixel electrode 114 layer. The first common electrode 112 and the pixel electrode 114 have overlapping portions not only outside the first contact hole 1111 but also inside the first contact hole 1111. Although the pixel pitch is reduced due to the requirement of high PPI, resulting in a reduction in the overlapping area between the pixel electrode 114 and the common electrode, an additional first common electrode 112 is arranged opposite to the pixel electrode 114 inside the first contact hole 1111, thereby increasing the overlapping area between the two, so that the overlapping area between the pixel electrode 114 and the common electrode does not decrease due to the reduction in the pixel pitch. That is to say, the first common electrode 112 can make up for the problem of insufficient storage capacitance caused by the reduction in the pixel pitch because it is arranged opposite to the pixel electrode 114 inside the first contact hole 1111.

[0093] In some embodiments of the present application, the non-display area NA of the array substrate 100 includes a first routing line 118 and a second routing line 119, the first routing line 118 is synchronously manufactured with the first pole 105, the second routing line 119 is synchronously manufactured with the first gate 104, the first via hole 120 is synchronously manufactured with the first contact hole 1111 and the second contact hole 1131, the second via hole 121 is synchronously manufactured with the via hole of the second pole 108 shown, and the third via hole 122 is synchronously manufactured with the via hole of the first pole 105; the first common electrode 112 is electrically connected to the second routing line 119 through the second via hole 121, the second common electrode 117 is electrically connected to the first routing line 118 through the first via hole 120, and the first routing line 118 is electrically connected to the second routing line 119 through the third via hole 122.

[0094] In this embodiment, the first wiring 118 is manufactured synchronously with the first electrode 105, the second wiring 119 is manufactured synchronously with the first gate 104, and no additional mask is added, and the second common electrode 117 is electrically connected to the first wiring 118 through the first via 120, and the first common electrode 112 is electrically connected to the first wiring 118 through the third via 122. The first via 120 can be manufactured synchronously with the first contact hole 1111 and the second contact hole 1131, the second via 121 can be manufactured synchronously with the via of the second electrode 108 and the active layer 102, and the third via 122 can be manufactured synchronously with the via of the first electrode 105 and the active layer 102, and no additional mask is added, which can simplify the manufacturing process and reduce the manufacturing cost.

[0095] The third aspect of the present application provides a liquid crystal display panel, comprising the array substrate 100 described above, a counter-box substrate arranged in a box with the array substrate 100, and a liquid crystal layer located between the array substrate 100 and the counter-box substrate. The array substrate 100 of the liquid crystal display panel is provided with an additional first common electrode 112, wherein the first common electrode 112 and the pixel electrode 114 are arranged opposite to each other not only outside the first contact hole 1111 but also inside the first contact hole 1111, and the first common electrode 112 and the second common electrode 117 are electrically connected in the peripheral area, so that the overlapping area between the common electrode and the pixel electrode 114 formed by the first common electrode 112 and the second common electrode 117, that is, the facing area is increased, and according to the relationship that the capacitance is proportional to the facing area of ​​the electrode plate, the storage capacitance between the common electrode and the pixel electrode 114 is increased, which is used to keep the voltage applied to the pixel electrode 114 sufficient, improve the stability of the voltage of the pixel electrode 114, and ensure the stability of the image display, so that the liquid crystal display panel can further improve the PPI.

[0096] A fourth aspect of the present application provides a terminal device, which may be, but is not limited to, a laptop computer, a car computer, a mobile phone, a television, or other electronic product, and the terminal device includes the liquid crystal display panel described above.

[0097] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0098] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0099] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: The array substrate has a display area and a non-display area arranged outside the display area, wherein the display area includes a plurality of sub-pixels, and the array substrate includes: substrate substrate; A plurality of first transistors located in the display area are arranged on one side of the base substrate, and include an active layer, a first gate insulating layer, a first gate, and a first electrode and a second electrode electrically connected to the active layer; A first planar layer is provided on a side of the first transistor away from the base substrate, and includes a plurality of first contact holes arranged at intervals, wherein the first contact holes extend downward along the thickness direction of the array substrate to the upper surface of the second electrode; a first common electrode, arranged on a side of the first flat layer away from the base substrate, comprising a plurality of electrode portions arranged at intervals and a conductive connection portion connecting the electrode portions, wherein the electrode portion is located in the display area and corresponds to a row or a column of sub-pixels, wherein the electrode portion comprises a first sub-portion and a second sub-portion connected to each other, wherein the first sub-portion is located outside the first contact hole, the second sub-portion extends along the hole wall of the first contact hole, the second sub-portion has a first preset distance from an upper surface of the second electrode, and the conductive connection portion is located in the non-display area; A first insulating layer, covering the first common electrode from a side away from the base substrate and having a second preset distance from an upper surface of the second electrode; A pixel electrode is disposed on a side of the first insulating layer away from the base substrate and extends along the hole wall of the first contact hole to the upper surface of the second electrode, and the first sub-portion and the second sub-portion are both disposed opposite to the pixel electrode; A second insulating layer covers the pixel electrode from a side away from the base substrate; The second common electrode is disposed on a side of the second insulating layer away from the base substrate and is electrically connected to the first common electrode in the non-display area.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises a second planar layer for filling the first contact hole, and the pixel electrode comprises a first sub-electrode and a second sub-electrode; The first sub-electrode is arranged on a side of the first insulating layer away from the base substrate, and extends along the hole wall of the first contact hole to the upper surface of the second electrode, and the part of the orthographic projection along the thickness direction of the array substrate that does not overlap with the first contact hole is recorded as the first part; The second sub-electrode includes a third part and a fourth part, the third part is located on the first part and contacts each other, the fourth part is located on the second flat layer on at least one side of the third part along the first direction, and the orthographic projection of the fourth part on the base substrate only overlaps with the orthographic projection of a pixel electrode of one sub-pixel on the base substrate, and the third part and the fourth part are both arranged opposite to the second common electrode.

3. The array substrate according to claim 1, characterized in that: The length of the orthographic projection of the second sub-portion along the hole wall extension portion of one of the first contact holes on the substrate is 0.12 times to 0.15 times the total length of the orthographic projection of a single electrode portion on the substrate.

4. The array substrate according to claim 1, characterized in that: The first preset distance is equal to the second preset distance.

5. The array substrate according to claim 4, characterized in that: The first preset distance is greater than or equal to 1 / 10 and less than or equal to 1 / 3 of the depth of the first contact hole.

6. The array substrate according to claim 1, characterized in that: The first pole and the second pole are arranged in different layers, a first interlayer insulating layer is arranged between the first pole and the second pole, and the first pole is located on a side of the first interlayer insulating layer close to the base substrate.

7. The array substrate according to claim 6, characterized in that: The array substrate comprises a first wiring and a second wiring, wherein the first wiring is arranged on the same layer as the first gate, and the second wiring is arranged on the same layer as the first gate; The second common electrode is electrically connected to the first wiring through a first via hole, the first common electrode is electrically connected to the second wiring through a second via hole, and the first wiring is electrically connected to the second wiring through a third via hole.

8. The array substrate according to any one of claims 1 to 7, characterized in that: The first transistor further includes a second gate, the second gate is located on a side of the active layer close to the substrate, and the first gate is located on a side of the active layer away from the substrate; The orthographic projection of the first gate on the substrate is located within the orthographic projection of the second gate on the substrate.

9. The array substrate according to any one of claims 1 to 7, characterized in that: The array substrate comprises a color resist layer, the color resist layer comprises at least a first color resist, a second color resist and a third color resist arranged in sequence in an array, and the color resist layer is arranged on a side of the planar layer close to the base substrate.

10. The array substrate according to claim 9, characterized in that: The second common electrode has multiple first openings in the display area, and the orthographic projection of the first opening on the base substrate partially overlaps with the orthographic projection of a single pixel electrode on the base substrate, and the orthographic projection of the first opening along its long side direction on the base substrate surrounds the orthographic projection of the corresponding color resistance along the long side direction on the base substrate.

11. A method for manufacturing an array substrate, characterized in that: Used to manufacture an array substrate according to any one of claims 1 to 10, the array substrate having a display area and a non-display area provided on at least one side of the display area, the display area including a plurality of sub-pixels, the array substrate comprising the following steps: providing a substrate base plate; On one side of the base substrate, a first transistor located in the display area is manufactured, wherein the first transistor comprises an active layer, a first gate insulating layer, a first gate, and a first electrode and a second electrode electrically connected to the active layer; Prepare a first planar layer on a side of the first transistor away from the substrate; Etching the first planar layer until the upper surface of the second electrode is exposed; A first common electrode is formed on a side of the first flat layer away from the base substrate, comprising a plurality of electrode portions arranged at intervals and a conductive connection portion connecting the electrode portions, wherein the electrode portion is located in the display area and corresponds to a row or a column of sub-pixels, wherein the electrode portion comprises a first sub-portion and a second sub-portion connected to each other, wherein the first sub-portion is located outside the first contact hole, the second sub-portion extends along the hole wall of the first contact hole, the second sub-portion has a first preset distance from the upper surface of the second electrode, and the conductive connection portion is located in the non-display area; forming a first insulating layer on the first common electrode, wherein the first insulating layer covers the first common electrode; Etching the first insulating layer at a position corresponding to the first contact hole until the upper surface of the second electrode is exposed and a second contact hole is formed; A first pixel electrode is formed on a side of the first insulating layer away from the base substrate, the first pixel electrode is electrically connected to the second electrode through the second contact hole, and the first sub-portion and the second sub-portion are both arranged opposite to the pixel electrode; Forming a second insulating layer on a side of the first pixel electrode away from the base substrate; A second common electrode is formed on a side of the second insulating layer away from the base substrate, and the first common electrode is electrically connected to the second common electrode in a non-display area.

12. The method for manufacturing an array substrate according to claim 11, characterized in that: The non-display area of ​​the array substrate comprises a first wiring and a second wiring, the first wiring is synchronously manufactured with the first electrode, the second wiring is synchronously manufactured with the first gate, the first via hole is synchronously manufactured with the first contact hole and the second contact hole, the second via hole is synchronously manufactured with the via hole of the second electrode, and the third via hole is synchronously manufactured with the via hole of the first electrode; The first common electrode is electrically connected to the second routing line through the second via hole, the second common electrode is electrically connected to the first routing line through the first via hole, and the first routing line is electrically connected to the second routing line through the third via hole.

13. A liquid crystal display panel, comprising the array substrate according to any one of claims 1 to 10, a cell-matching substrate arranged cell-matching therewith, and a liquid crystal layer located between the array substrate and the cell-matching substrate.

14. A terminal device, characterized in that: Includes the liquid crystal display panel as described in claim 13.

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