Low-power-consumption vibration signal acquisition and processing system and method based on heterogeneous multi-core system

Abstract

The invention relates to a low-power-consumption vibration signal collecting and processing system and method based on a heterogeneous multi-core system. The system comprises an MCU, an MPU, an SOC in-chip interconnection module, a trigger signal module and a data collecting controller module. The SOC in-chip interconnection module comprises a signal routing module, an interruption interconnection module, a shared data address bus and a shared RAM (Random Access Memory); the MCU comprises a first sleep wake-up module, a first data acquisition module, a first data storage module and an MPU wake-up synchronization module; the MPU comprises a second dormancy awakening module, a second data acquisition module, a second data storage module and an MCU acquisition data carrying module; the invention further provides an acquisition method based on the system, the vibration signal acquisition system can be quickly awakened, and loss of signal data in the whole awakening process can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of low-power vibration signal acquisition, and in particular to a low-power vibration signal acquisition and processing method based on a heterogeneous multi-core system. Background Art

[0002] Some devices in MPU-based data vibration signal collection scenarios are battery-powered and require low power consumption. To maintain low power consumption, some devices are generally in sleep mode and only need to start collecting and perform complex data processing after being triggered by a specific signal. However, the MPU's sleep wake-up time is relatively long. In addition, the vibration signal will be lost during the time when the MPU receives the signal to wake up and enter the collection state. Summary of the invention

[0003] The purpose of the present invention is to provide a low-power vibration signal acquisition and processing system and method based on a heterogeneous multi-core system to solve the problems raised in the above background technology.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions: a low-power vibration signal acquisition and processing system based on a heterogeneous multi-core system, the system includes an MCU, an MPU, a SOC on-chip interconnection module module, a trigger signal module, and a data acquisition controller module;

[0005] The SOC on-chip interconnection module includes: a signal routing module, an interrupt interconnection module, a shared data address bus, and a shared RAM;

[0006] The MCU includes: a first sleep wake-up module, a first data acquisition module, a first data storage module, and an MPU wake-up synchronization module;

[0007] The MPU includes: a second sleep and wake-up module, a second data acquisition module, a second data storage module, and an MCU data acquisition and handling module;

[0008] The trigger signal module is used for triggering a signal;

[0009] The data acquisition controller module is used to control data acquisition;

[0010] The signal routing module is used for routing of trigger signals;

[0011] The interrupt interconnection module is used to generate interrupt information and transmit interrupt signals;

[0012] The shared RAM module is used for data sharing between MCU and MPU;

[0013] The first sleep awakening module and the second sleep awakening module are used to awaken the sleep state;

[0014] The MPU wake-up synchronization module is used for the MCU to send a wake-up signal to the MPU through an inter-core interrupt signal.

[0015] And receive the wake-up notification signal sent by MPU;

[0016] The second data acquisition module is used for the MPU to collect data from the data acquisition controller;

[0017] The first data storage module and the second data storage module are used for storing data;

[0018] The MCU data collection and transfer module is used to transfer the shared RAM module to the MPU.

[0019] Preferably, the data acquisition controller is a SPI AD acquisition controller.

[0020] Preferably, it also includes a complete data splicing module, and the SPI AD acquisition controller also includes a data cache FIFO module;

[0021] The data cache FIFO module is used to cache the data collected by the data acquisition controller;

[0022] The complete data splicing module is used to splice the data from the data cache FIFO module and the MCU data collection and handling module in the second data storage module;

[0023] The present invention also provides a low-power vibration signal acquisition and processing method based on a heterogeneous multi-core system. The method is based on the low-power vibration signal acquisition and processing system based on a heterogeneous multi-core system described above, and the method comprises the following steps:

[0024] Step 1: an external trigger signal sends a trigger signal to the SOC on-chip interconnection module, and the trigger signal is transmitted to the first sleep and wake-up module through the SOC on-chip interconnection module to wake up the MCU;

[0025] Step 2: The data acquisition controller transmits data to the SOC on-chip interconnection module, the interrupt interconnection sends an interrupt signal to the MCU, the first data acquisition module in the MCU receives the interrupt signal and collects data, and the first data acquisition module stores the collected data in the first data storage module;

[0026] Step 3: The first data storage module temporarily stores data in the shared RAM in the SOC on-chip interconnection module;

[0027] Step 4: While the first data acquisition module is collecting data, the MPU wake-up synchronization module sends a wake-up signal to the second sleep wake-up module of the MPU, and the MPU is awakened;

[0028] Step 5: After being awakened, the MPU enters the ready state and notifies the MCU through its second sleep wake-up module and the inter-core interrupt signal that it is ready;

[0029] Step 6: After receiving the signal, the MCU stops operating the data acquisition controller and sends an inter-core interrupt signal to the MPU;

[0030] Step 7: The MPU collects data through the MCU and the data transfer module transfers the temporarily stored data in the shared RAM module to the second data storage module;

[0031] Step 8: The MPU second data acquisition module starts and continuously acquires data from the data acquisition controller, stores the acquired data in the second data storage module, and processes the data;

[0032] Step 9: After collecting and processing data, the MPU enters sleep mode.

[0033] Preferably, in step 1, the external trigger signal is routed to the first sleep-wake-up module in the MCU through the signal routing module in the SOC on-chip interconnection module, and the first sleep-wake-up module wakes up the MCU.

[0034] Preferably, after step 6, the method further includes a step in which the data acquisition controller temporarily stores the collected data in its internal data cache FIFO, and after step 7, the method further includes a step in which the data acquisition controller reads the data stored in the data cache FIFO through the second data acquisition module, and splices the data collected from the data cache FIFO with the data moved from the shared RAM through the complete data splicing module in the second data storage module. After the splicing is completed, the second data acquisition module of the MPU starts and continues to collect data in the data acquisition controller.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] The present invention adopts the MPU+MCU combination (heterogeneous multi-core) mode, and combines with shared RAM, which can realize low power consumption and fast wake-up of the vibration signal acquisition system, and can avoid the loss of signal data in the whole wake-up process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A system structure block diagram of Embodiment 1 provided by the present invention;

[0038] Figure 2 A system structure block diagram of Embodiment 2 provided by the present invention; DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0040] Example 1

[0041] See also Figure 1 :

[0042] A low-power vibration signal acquisition and processing system based on a heterogeneous multi-core system, the system includes an MCU, an MPU, a SOC on-chip interconnection module, a trigger signal module, and a data acquisition controller module;

[0043] The SOC on-chip interconnection module includes: a signal routing module, an interrupt interconnection module, a shared data address bus, and a shared RAM;

[0044] The MCU includes: a first sleep wake-up module, a first data acquisition module, a first data storage module, and an MPU wake-up synchronization module;

[0045] The MPU includes: a second sleep and wake-up module, a second data acquisition module, a second data storage module, and an MCU data acquisition and handling module;

[0046] The trigger signal module is used for triggering a signal;

[0047] The data acquisition controller module is used to control data acquisition;

[0048] The signal routing module is used for routing of trigger signals;

[0049] The interrupt interconnection module is used to generate interrupt information and transmit interrupt signals;

[0050] The shared RAM module is used for data sharing between MCU and MPU;

[0051] The first sleep awakening module and the second sleep awakening module are used to awaken the sleep state;

[0052] The MPU wake-up synchronization module is used for the MCU to send a wake-up signal to the MPU through an inter-core interrupt signal.

[0053] And receive the wake-up notification signal sent by MPU;

[0054] The second data acquisition module is used for the MPU to collect data from the data acquisition controller;

[0055] The first data storage module and the second data storage module are used for storing data;

[0056] The MCU data collection and transfer module is used to transfer the shared RAM module to the MPU.

[0057] The present invention also provides a low-power vibration signal acquisition and processing method based on a heterogeneous multi-core system, the method comprising the following steps:

[0058] Step 1: an external trigger signal sends a trigger signal to the SOC on-chip interconnection module, a signal routing module in the SOC on-chip interconnection module routes the trigger signal to the first sleep and wake-up module in the MCU, and the first sleep and wake-up module wakes up the MCU;

[0059] Step 2: The data acquisition controller transmits data to the SOC on-chip interconnection module, the interrupt interconnection sends an interrupt signal to the MCU, the first data acquisition module in the MCU receives the interrupt signal and collects data, and the first data acquisition module stores the collected data in the first data storage module;

[0060] Step 3: The first data storage module temporarily stores data in the shared RAM in the SOC on-chip interconnection module;

[0061] Step 4: While the first data acquisition module is collecting data, the MPU wake-up synchronization module sends a wake-up signal to the second sleep wake-up module of the MPU, and the MPU is awakened;

[0062] Step 5: After being awakened, the MPU enters the ready state and notifies the MCU through its second sleep wake-up module and the inter-core interrupt signal that it is ready;

[0063] Step 6: After receiving the signal, the MCU stops operating the data acquisition controller and sends an inter-core interrupt signal to the MPU;

[0064] Step 7: The MPU collects data through the MCU and the data transfer module transfers the temporarily stored data in the shared RAM module to the second data storage module;

[0065] Step 8: The MPU second data acquisition module starts and continuously acquires data from the data acquisition controller, stores the acquired data in the second data storage module, and processes the data;

[0066] Step 9: After collecting and processing data, the MPU enters sleep mode.

[0067] This solution adopts the MPU+MCU combination (heterogeneous multi-core) and shared RAM to realize MPU. MCU is in sleep state under normal circumstances to keep the device low power consumption. When there is a trigger signal, MCU is woken up first. The wake-up time of MCU is much faster than that of MPU. After MCU wakes up, it wakes up MPU and immediately starts to collect data and cache it in shared RAM until MPULinux wakes up. After MPU Linux wakes up, it takes over the data collection work and starts the subsequent complex processing flow.

[0068] After the MPU takes over the data collection and processing work, the MCU enters the sleep state again, and the MPU enters the sleep state again after completing the subsequent data collection and processing work. Therefore, low power consumption and fast wake-up can be achieved, and at the same time, signal data loss during the wake-up process is minimized.

[0069] Example 2

[0070] See also Figure 2 :

[0071] The low-power vibration signal acquisition and processing system based on a heterogeneous multi-core system of the present embodiment 2 is a low-power vibration signal acquisition and processing system based on a heterogeneous multi-core system based on the embodiment 1, and adopts an SPI AD acquisition controller as a data acquisition controller on the basis of the embodiment 1. At the same time, the present embodiment 2 also includes a complete data splicing module, and the SPIAD acquisition controller also includes a data cache FIFO module; the data cache FIFO module is used to cache the data collected by the data acquisition controller; the complete data splicing module is arranged in the second data storage module and is used to splice the data from the data cache FIFO module and the MCU acquisition data handling module;

[0072] The low-power vibration signal acquisition and processing method based on a heterogeneous multi-core system provided in this embodiment 2 is a low-power vibration signal acquisition and processing method based on a heterogeneous multi-core system based on embodiment 1, and on the basis of embodiment 1, in order to avoid data loss between the time when the MCU stops controlling the acquisition data controller and the time when the MPU starts controlling the acquisition data controller, after step 6, it also includes a step in which the data acquisition controller temporarily stores the collected data in its internal data cache FIFO, and after step 7, it also includes a step in which the data stored in the data cache FIFO is read through the second data acquisition module, and the data collected from the data cache FIFO is spliced ​​with the data moved from the shared RAM through the complete data splicing module in the second data storage module. After the splicing is completed, the second data acquisition module of the MPU starts and continues to collect data in the data acquisition controller.

[0073] Based on Example 1, this solution adopts an SPI AD acquisition controller and utilizes its data cache FIFO. During the data transfer of the shared RAM module, the data acquisition controller temporarily stores the collected data in the internal data cache FIFO. After the transfer is completed, the data stored in the data cache FIFO is first read to the second data storage module through the second data acquisition module, and the data is spliced ​​with the transferred data through the complete data splicing module. After that, the data of the SPI AD acquisition controller is started and continuously collected through the second data acquisition module, thereby avoiding the loss of signal data during the entire wake-up process.

[0074] The above are only embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A low-power vibration signal acquisition and processing system based on a heterogeneous multi-core system, characterized by: The system includes MCU, MPU, SOC on-chip interconnection module, trigger signal module, and data acquisition controller module; The SOC on-chip interconnection module includes: a signal routing module, an interrupt interconnection module, a shared data address bus, and a shared RAM; The MCU includes: a first sleep wake-up module, a first data acquisition module, a first data storage module, and an MPU wake-up synchronization module; The MPU includes: a second sleep and wake-up module, a second data acquisition module, a second data storage module, and an MCU data acquisition and handling module; The trigger signal module is used for triggering a signal; The data acquisition controller module is used to control data acquisition; The signal routing module is used for routing of trigger signals; The interrupt interconnection module is used to generate interrupt information and transmit interrupt signals; The shared RAM module is used for data sharing between MCU and MPU; The first sleep awakening module and the second sleep awakening module are used to awaken the sleep state; The MPU wake-up synchronization module is used for the MCU to send a wake-up signal to the MPU through an inter-core interrupt signal. And receive the wake-up notification signal sent by MPU; The second data acquisition module is used for the MPU to collect data from the data acquisition controller; The first data storage module and the second data storage module are used for storing data; The MCU data collection and transfer module is used to transfer the shared RAM module to the MPU.

2. A low-power vibration signal acquisition and processing system based on a heterogeneous multi-core system, characterized in that: The data acquisition controller is a SPI AD acquisition controller.

3. According to the low-power vibration signal acquisition and processing system based on heterogeneous multi-core system, it is characterized by: It also includes a complete data splicing module, and the SPI AD acquisition controller also includes a data cache FIFO module; The data cache FIFO module is used to cache the data collected by the data acquisition controller; The complete data splicing module is used to splice the data from the data cache FIFO module and the MCU data collection and handling module in the second data storage module.

4. A low-power vibration signal acquisition and processing method based on a heterogeneous multi-core system, characterized in that: The method is based on the low-power vibration signal acquisition and processing system based on a heterogeneous multi-core system according to any one of claims 1 to 3, and the method comprises the following steps: Step 1: an external trigger signal sends a trigger signal to the SOC on-chip interconnection module, and the trigger signal is transmitted to the first sleep and wake-up module through the SOC on-chip interconnection module to wake up the MCU; Step 2: The data acquisition controller transmits data to the SOC on-chip interconnection module, the interrupt interconnection sends an interrupt signal to the MCU, the first data acquisition module in the MCU receives the interrupt signal and collects data, and the first data acquisition module stores the collected data in the first data storage module; Step 3: The first data storage module temporarily stores data in the shared RAM in the SOC on-chip interconnection module; Step 4: While the first data acquisition module is collecting data, the MPU wake-up synchronization module sends a wake-up signal to the second sleep wake-up module of the MPU, and the MPU is awakened; Step 5: After being awakened, the MPU enters the ready state and notifies the MCU through its second sleep wake-up module and the inter-core interrupt signal that it is ready; Step 6: After receiving the signal, the MCU stops operating the data acquisition controller and sends an inter-core interrupt signal to the MPU; Step 7: The MPU collects data through the MCU and the data transfer module transfers the temporarily stored data in the shared RAM module to the second data storage module; Step 8: The MPU second data acquisition module starts and continuously acquires data from the data acquisition controller, stores the acquired data in the second data storage module, and processes the data; Step 9: After collecting and processing data, the MPU enters sleep mode.

5. The low-power vibration signal acquisition and processing method based on a heterogeneous multi-core system according to claim 4 is characterized in that: In step 1, the external trigger signal is routed to the first sleep-wake-up module in the MCU through the signal routing module in the SOC on-chip interconnection module, and the first sleep-wake-up module wakes up the MCU.

6. The low-power vibration signal acquisition and processing method based on a heterogeneous multi-core system according to claim 4 is characterized in that: After step 6, the method also includes a step in which the data acquisition controller temporarily stores the collected data in its internal data cache FIFO, and after step 7, the method also includes a step in which the data stored in the data cache FIFO is read through the second data acquisition module, and the data collected from the data cache FIFO is spliced ​​with the data moved from the shared RAM through the complete data splicing module in the second data storage module. After the splicing is completed, the second data acquisition module of the MPU starts and continues to collect data in the data acquisition controller.

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