Subarray signal synchronization and control architecture for ultrasonic chip

Abstract

The invention discloses a subarray signal synchronization and control architecture for an ultrasonic chip, relates to the technical field of semiconductors, and solves the technical problems of signal synchronization deviation and multi-clock domain coordination of the existing ultrasonic chip. Through combination of distributed signal management and cross-clock domain processing of a local clock and a reset module, signal distribution and time sequence control are optimized, and global signal integrity of a large-scale ultrasonic array chip is ensured. Meanwhile, the architecture supports multiple ultrasonic imaging modes, and the beam forming precision and the signal-to-noise ratio can be remarkably improved. In addition, the modular design is adopted, ultrasonic array frameworks of different sizes can be flexibly expanded, and the diversified requirements of one-dimensional, two-dimensional and three-dimensional ultrasonic chips are met. According to the technical scheme, the performance and reliability of the ultrasonic chip in multi-mode imaging are remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a subarray signal synchronization and control architecture for an ultrasound chip. Background Art

[0002] With the rapid development of ultrasound imaging technology, especially in the field of three-dimensional ultrasound imaging, the scale and complexity of ultrasound chips have increased significantly. However, the existing technology has many shortcomings in signal synchronization and multi-clock domain coordinated control, which restricts the performance and expansion capabilities of ultrasound imaging systems.

[0003] In large-scale ultrasound array chips, signal delay and deviation between subarrays are the main bottlenecks affecting system performance. Due to the imbalance of signal path length and clock tree structure inside the chip, there are significant differences in the time when different subarrays receive or transmit signals, resulting in a decrease in the synchronization of the beamforming algorithm, thereby affecting the imaging resolution and signal-to-noise ratio. Existing technologies usually adopt a globally synchronized centralized architecture, but it is difficult to adapt to the dynamically changing subarray signal requirements.

[0004] Ultrasound chips usually involve multiple clock domains (such as system clock, transmit clock, receive clock), and the synchronization between these clock domains is critical to chip performance. However, in complex multi-beam imaging modes, the phase deviation and delay matching problems between clock domains greatly increase the complexity of system design. The traditional architecture lacks a flexible distributed clock management mechanism, resulting in poor system scalability and operational stability. Existing technologies have limited capabilities in cross-clock domain signal transmission, especially in high-frequency environments, where timing issues are more prominent.

[0005] As the scale of ultrasound arrays expands from one dimension to two and three dimensions, the demand for modular design of its subarray structure becomes increasingly prominent. However, the centralized signal distribution and control methods in the existing technology limit the expansion capability of the chip. Especially when the subarray signal path load is uneven, the existing methods are difficult to achieve effective distributed management, resulting in a significant decrease in system performance as the array size increases.

[0006] Ultrasound chips are usually designed based on high-frequency clocks to meet real-time imaging requirements. In such a high-frequency environment, the delay management and timing convergence of the signal path become significantly more difficult, especially when complex process nodes are used, where the accuracy of timing control and signal integrity are difficult to guarantee. In addition, the complex wiring structure inside large-scale array chips further exacerbates the inconsistency of signal transmission.

[0007] In summary, existing ultrasound chips face the following problems in large-scale arrays:

[0008] (1) Subarray signal synchronization deviation leads to reduced beamforming accuracy.

[0009] (2) Phase deviation and delay mismatch between multiple clock domains increase design complexity.

[0010] (3) The centralized architecture lacks distributed signal management capabilities, which limits the scalability and adaptability of the system.

[0011] (4) Timing convergence and signal integrity are difficult to guarantee under high-frequency operation and complex process nodes. Summary of the invention

[0012] The present application provides a sub-array signal synchronization and control architecture for an ultrasound chip, the technical purpose of which is to solve the technical difficulties of existing ultrasound chips in signal synchronization and multi-clock domain collaborative control, and to improve system performance and expansion capabilities.

[0013] The above technical objectives of this application are achieved through the following technical solutions: A subarray signal synchronization and control architecture for an ultrasound chip comprises a subarray island module and a local clock and reset module arranged in each subarray, wherein a global clock signal and a reset signal enter the subarray island module through a peripheral circuit, the subarray island module balances the signal path load and distributes the clock signal and the reset signal, and the local clock and reset module synchronizes the clock signal and the reset signal input by the subarray island module and provides them to a local logic module; wherein adjacent subarray island modules are cascaded; and the upper-level subarray island module distributes the clock signal and the reset signal to its corresponding local clock and reset module and the lower-level subarray island module.

[0014] Furthermore, the subarray module includes: Buffer groups, used to drive global signals and optimize clock and reset paths; Decoupling capacitor bank, used to balance global power distribution and reduce signal interference; A placeholder cell group is used to fill unused areas.

[0015] Furthermore, the sub-array island module is provided in the analog circuit or digital circuit of the sub-array.

[0016] Furthermore, adjacent sub-array island modules are cascaded via a buffer group.

[0017] Furthermore, adjacent sub-array island modules are cascaded through digital circuits or analog circuits.

[0018] Furthermore, the sub-array island module is designed as a modular hardware unit.

[0019] Furthermore, the sub-array island module is arranged at a central position or an edge position of the analog circuit and the digital circuit.

[0020] Furthermore, the sub-array island module is arranged at any position of the analog circuit and the digital circuit.

[0021] Furthermore, the number of buffers from each sub-array to the peripheral circuit is the same as the sum of the number of buffers in the corresponding sub-array island modules.

[0022] Furthermore, the global clock signal is input from a clock source of the peripheral circuit and enters the sub-array island module of each sub-array through a buffer.

[0023] The subarray signal synchronization and control architecture for an ultrasound chip described in the present application includes a subarray island module and a local clock and reset module provided in each subarray, and its beneficial effects are:

[0024] (1) Improved beamforming accuracy: Through distributed signal management and cross-clock domain processing, the signal synchronization between sub-arrays is improved, supporting multiple ultrasound imaging modes (such as B mode, PW mode, harmonic mode), and significantly improving imaging resolution and signal-to-noise ratio.

[0025] (2) Enhanced system stability: The local clock and reset modules are used to achieve precise coordination and reset synchronization of multiple clock domains, ensuring the timing stability of the chip under high-frequency operation.

[0026] (3) Scalability and applicability: The modular design supports ultrasound array architectures of different sizes, adapts to the diverse needs of one-dimensional, two-dimensional, and three-dimensional ultrasound chips, and meets the future needs for higher performance and higher resolution ultrasound chips.

[0027] (4) Flexible adaptability: The subarray island module flexibly adjusts signal distribution and path load balancing according to the physical layout and signal requirements of different subarrays to adapt to complex scenarios under various working modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the clock tree structure in the embodiment of the present application.

[0029] Figure 2a and Figure 2b It is a schematic diagram of the signal passing method in the digital circuit in the embodiment of the present application.

[0030] Figure 2c and Figure 2d It is a schematic diagram of the signal passing method in the analog circuit in the embodiment of the present application.

[0031] Figure 3 Schematic diagram of a sub-array island module in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solution of the present application will be described in detail below with reference to the accompanying drawings.

[0033] The subarray signal synchronization and control architecture for ultrasound chips described in the present application includes a subarray island module and a local clock and reset module provided in each subarray. The subarray island module is the core module of the architecture, and its main function is to realize distributed management and synchronization of signals, and ensure the global timing consistency and signal integrity of the entire ultrasound array chip.

[0034] like Figure 1 As shown, the subarray island module transmits the global clock signal from the peripheral circuit to each subarray through the distributed clock tree design, and accurately distributes it within the subarray, reducing signal delay and path deviation, and realizing clock tree optimization.

[0035] At the same time, the sub-array island module uniformly dispatches reset signals, global digital control signals and analog signals to ensure the coordinated work and synchronization between sub-arrays.

[0036] Preferably, the sub-array island module includes a buffer group (Buffer Group), a decoupling capacitor group (Decap Group) and an idle unit (Dummy Group), such as Figure 3 By flexibly configuring these modules, the load balance of the signal path is optimized and different sub-array requirements can be met.

[0037] Preferably, in terms of modular design, the subarray island module is designed as a modular hardware unit and can be flexibly deployed at the central position of the subarray (such as Figure 2b and Figure 2d ) or edge positions (such as Figure 2a and Figure 2c ), or the sub-array island module can be deployed at any location except the center and edge. Through modular design, the back-end implementation only needs to adjust the analog circuit area in the sub-array island module to adapt to the physical layout of different sub-arrays.

[0038] Preferably, the local clock and reset module is independently configured for each sub-array, connected to the sub-array island module in the sub-array, and is mainly responsible for multi-clock domain management and reset signal synchronization.

[0039] The local clock and reset module receives the global clock signal from the sub-array island module, and generates a local clock signal suitable for the sub-array through the frequency division module to achieve clock frequency division.

[0040] For multiple clock domains (such as system clock, transmit clock, receive clock), the local clock and reset module can adjust the signal phase and complete synchronization to ensure the consistency and reliability of signal transmission and achieve cross-clock domain synchronization.

[0041] In addition, the local clock and reset module supports the synchronous release design of asynchronous reset signals to ensure the system reset reliability under complex process conditions. In different reset paths, the local clock and reset module can dynamically control the reset delay to ensure the reset consistency of each sub-array.

[0042] Preferably, the number of buffers from each sub-array to the peripheral circuit is the same as the sum of the number of buffers in the corresponding sub-array island modules.

[0043] Figure 1 In , there are M subarray groups, each subarray group has N subarrays, and there are a total of M×N subarrays.

[0044] For subarray 1 of subarray group 1: the number of buffers from the peripheral circuit to its subarray island module is k, the number of buffers in the subarray island module is xN, and the number of buffers from the subarray island module to the peripheral circuit is (k+xN).

[0045] For subarray 2 of subarray group 1: the number of buffers from the peripheral circuit to its subarray island module is k+1, and the number of buffers in the subarray island module is (xN-1), then the number of buffers from the subarray island module to the peripheral circuit is (k+1+xN-1), that is, (k+xN).

[0046] For subarray 3 of subarray group 1: the number of buffers from the peripheral circuit to its subarray island module is k+2, and the number of buffers in the subarray island module is (xN-2), then the number of buffers from the subarray island module to the peripheral circuit is (k+2+xN-2), that is, (k+xN).

[0047] By analogy, the number of buffers from each sub-array in sub-array group 1 to the peripheral circuit is the same as the sum of the number of buffers in each corresponding sub-array island module.

[0048] Preferably, adjacent sub-array island modules are cascaded via a buffer group. Figure 1 In the embodiment, each sub-array island module in the sub-array group 1 is cascaded through a buffer. Obviously, there is at least one buffer between adjacent sub-array island modules.

[0049] Preferably, the local clock and reset module includes: Clock frequency division module: realizes local frequency division of global clock signal; Cross-clock domain processing module: ensures that signals remain consistent when transmitted between different clock domains; Asynchronous reset synchronous release module: synchronizes the asynchronous reset signal and provides it to the local logic module in the sub-array.

[0050] In the present application, the signal path includes a clock signal path, a reset signal path, and other global signals, such as a transmit sequence signal and a receive sequence signal.

[0051] The clock signal path is as follows Figure 1 As shown, the global clock signal enters the sub-array island module through the peripheral circuit, and is transmitted to the local clock and reset module of the sub-array after buffer optimization. The local clock and reset module divides the clock signal and adjusts the phase, and distributes the synchronized signal to the internal logic module of the sub-array.

[0052] The reset signal path is as follows Figure 2a to Figure 2d As shown, the reset signal is transmitted from the peripheral circuit to the sub-array island module, and the reset signal is load balanced by the sub-array island module and then distributed to each sub-array.

[0053] For the signal path traversal method, this application provides two options, such as Figure 2a to Figure 2d shown.

[0054] Figure 2a and Figure 2b Indicates that the signal passes through the digital macro. Its advantages are shorter paths, lower signal delays, and reduced wiring resources. However, it requires additional physical layout design inside the macro of the digital circuit, which increases the complexity of implementation.

[0055] When the signal passes through the digital macro, the data signal path, clock signal path and reset signal path are connected in the form of internal logic channels, that is, when the signal passes through the digital macro, in physical implementation, since the digital circuits of multiple sub-arrays are a whole, the global signal is wired and connected in the internal channels of the digital circuit without crossing the analog circuit. The reset signal transmitted from the sub-array island module to the local clock and reset module is synchronously released and provided to the local logic module.

[0056] Figure 2c and Figure 2d It means that the signal passes through the outside of the digital macro, which can reduce signal interference and electromagnetic coupling, and can provide higher signal integrity, which is suitable for high-frequency signal transmission. Its wiring method is more intuitive and convenient for back-end implementation, but the longer path may increase signal delay and have higher requirements for load balancing. According to specific needs, you can weigh the signal delay, design complexity and implementation cost to choose a suitable solution.

[0057] When the signal passes through the outside of the digital macro, the clock signal and the reset signal are transmitted from the upper-level sub-array island module to the lower-level sub-array sub-array island module through the analog circuit.

[0058] The above are exemplary embodiments of the present application, and the protection scope of the present application is defined by the claims and their equivalents.

Claims

1. A subarray signal synchronization and control architecture for an ultrasound chip, characterized in that: The invention comprises a subarray island module and a local clock and reset module arranged in each subarray, wherein a global clock signal and a reset signal enter the subarray island module through a peripheral circuit, the subarray island module balances the signal path load and distributes the clock signal and the reset signal, and the local clock and reset module synchronizes the clock signal and the reset signal input by the subarray island module and provides them to a local logic module; wherein adjacent subarray island modules are cascaded; and the upper-level subarray island module distributes the clock signal and the reset signal to its corresponding local clock and reset module and the lower-level subarray island module.

2. The subarray signal synchronization and control architecture for an ultrasound chip according to claim 1, characterized in that: The subarray module comprises: Buffer groups, used to drive global signals and optimize clock and reset paths; Decoupling capacitor bank, used to balance global power distribution and reduce signal interference; A placeholder group is used to fill unused areas.

3. The subarray signal synchronization and control architecture for an ultrasound chip according to claim 1, characterized in that: The sub-array island module is arranged in the analog circuit or digital circuit of the sub-array.

4. The subarray signal synchronization and control architecture for an ultrasound chip according to claim 3, characterized in that: Adjacent sub-array island modules are cascaded via a buffer group.

5. The subarray signal synchronization and control architecture for an ultrasound chip according to claim 4, characterized in that: The adjacent sub-array island modules are cascaded through digital circuits or analog circuits.

6. The subarray signal synchronization and control architecture for an ultrasound chip according to claim 1, characterized in that: The sub-array island module is designed as a modular hardware unit.

7. The subarray signal synchronization and control architecture for an ultrasound chip according to any one of claims 3 to 6, characterized in that: The sub-array island module is arranged at the center or edge of the analog circuit and the digital circuit.

8. The subarray signal synchronization and control architecture for an ultrasound chip according to claim 7, characterized in that: The sub-array island module is arranged at any position of the analog circuit and the digital circuit.

9. The subarray signal synchronization and control architecture for an ultrasound chip according to claim 2, characterized in that: The number of buffers from each sub-array to the peripheral circuit is the same as the sum of the number of buffers in the corresponding sub-array island modules.

10. The subarray signal synchronization and control architecture for an ultrasound chip according to claim 8, characterized in that: The global clock signal is input from the clock source of the peripheral circuit and enters the sub-array island module of each sub-array through the buffer.

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