Adjustable filtering LDO (Low Dropout Regulator) chip circuit

Abstract

The invention provides an adjustable filtering LDO (Low Dropout Regulator) chip circuit. The adjustable filtering LDO chip circuit comprises a power supply, a biasing circuit, a voltage stabilizing diode, a voltage follower, a band-gap reference circuit, an amplifying circuit, an under-voltage protection circuit, a filtering unit and a signal output end, the input end of the biasing circuit is connected with a power supply, and the output end of the biasing circuit is electrically connected with the voltage stabilizing diode, the voltage follower, the band-gap reference circuit, the amplifying circuit, the under-voltage protection circuit, the filtering unit and the signal output end in sequence; the anode of the voltage stabilizing diode is grounded, and the cathode of the voltage stabilizing diode is connected with the input end of the voltage follower; the amplifying circuit comprises an operational amplifier, a first MOS tube, a first resistor and a second resistor. According to the adjustable filtering LDO chip circuit, filtering can be adjusted to ensure the safety of the circuit, and the LDO chip is high in reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage stabilizing chip circuits, and in particular to an adjustable filtering LDO chip circuit. Background Art

[0002] With the booming development of downstream markets such as artificial intelligence, automotive electronics, medical electronics, and the Internet of Things, the demand for high-performance LDO regulators will surely increase further. The commonly used low dropout linear regulator (LDO) has been widely used in portable electronic products due to its simple structure, low power consumption, low output noise, small chip area, and low price. Compared with DC-DC converters, LDO has the advantages of low ripple and low output noise, which makes LDO have incomparable advantages in some occasions with strict requirements on output voltage accuracy and stability, and the market development prospects are very broad.

[0003] However, each switching power supply has its own power supply voltage operating range. Only when it works within this range can the chip work properly. When the power supply is over-discharged or a fault occurs in the power supply part, the power supply voltage will drop below its minimum operating voltage, which is called an undervoltage state. When the power supply voltage is in an undervoltage state, some modules inside the chip will be in an abnormal working state, which will cause the entire system to work disorderly and even cause a certain degree of damage to the chip, and the circuit undervoltage protection effect is poor. Summary of the invention

[0004] The invention provides an adjustable filtering LDO chip circuit, aiming to solve the problems of poor undervoltage protection and low reliability of the existing LDO chip circuit.

[0005] An embodiment of the present invention provides an adjustable filtering LDO chip circuit, comprising: a power supply, a bias circuit, a voltage zener diode, a voltage follower, a bandgap reference circuit, an amplifier circuit, an undervoltage protection circuit, a filtering unit and a signal output end; the input end of the bias circuit is connected to the power supply, and the output end of the bias circuit is electrically connected to the voltage zener diode, the voltage follower, the bandgap reference circuit, the amplifier circuit, the undervoltage protection circuit, the filtering unit and the signal output end in sequence; the positive electrode of the voltage zener diode is grounded, and the negative electrode of the voltage zener diode is connected to the input end of the voltage follower;

[0006] The amplifier circuit includes an operational amplifier, a first MOS tube, a first resistor and a second resistor. The negative input terminal of the operational amplifier serves as the input terminal of the amplifier circuit, the output terminal of the operational amplifier is connected to the gate of the first MOS tube, the source of the first MOS tube is connected to the first end of the first resistor, the second end of the first resistor is respectively connected to the first end of the second resistor and the positive input terminal of the operational amplifier, and the second end of the second resistor is grounded; the drain of the first MOS tube is connected to the power supply, and the source of the first MOS tube also serves as the output terminal of the amplifier circuit.

[0007] Preferably, the undervoltage protection circuit includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a comparator, an inverter, a second MOS tube and a third MOS tube;

[0008] The first end of the third resistor is connected to the power supply, the second end of the third resistor is respectively connected to the first end of the fourth resistor and the positive input end of the comparator, the second end of the fourth resistor is respectively connected to the first end of the fifth resistor and the drain of the second MOS tube, the second end of the fifth resistor is connected to the source of the second MOS tube and grounded, the negative input end of the comparator serves as the input end of the undervoltage protection circuit, the output end of the comparator is connected to the input end of the inverter, the output end of the inverter is respectively connected to the gate of the second MOS tube and the first end of the sixth resistor, the second end of the sixth resistor is connected to the gate of the third MOS tube, the source of the third MOS tube is connected to the power supply, and the drain of the third MOS tube serves as the output end of the undervoltage protection circuit.

[0009] Preferably, the inverter includes a fourth MOS tube and a fifth MOS tube, the gate of the fourth MOS tube is connected to the gate of the fifth MOS tube and serves as the input end of the inverter, the source of the fourth MOS tube is connected to the power supply, the drain of the fourth MOS tube is connected to the drain of the fifth MOS tube and serves as the output end of the inverter, and the source of the fifth MOS tube is grounded.

[0010] Preferably, the third resistor is defined as R3, the fourth resistor is defined as R4, the fifth resistor is defined as R5, and the sixth resistor is defined as R6; Vref is the internal reference voltage of the negative input terminal of the comparator; in the process of the power supply increasing, when the power supply voltage reaches a certain value, the chip is converted from the undervoltage state to the normal working state, and the instantaneous flip voltage is the rising threshold voltage VDDthH of the circuit;

[0011] The rising threshold voltage VDDthH is as shown in Expression (1);

[0012]

[0013] During the power supply voltage reduction process, when the power supply voltage reaches a certain value, the chip switches from a normal working state to an abnormal working state, and the falling threshold is represented by VDDthL;

[0014]

[0015] The difference between the rising threshold voltage and the falling threshold voltage is the hysteresis voltage, and the hysteresis voltage is as shown in formula (3);

[0016] VDDthhold=VDDthH-VDDthL(3).

[0017] Preferably, the first MOS tube is an N-type MOS tube.

[0018] Preferably, the second MOS tube is a P-type MOS tube.

[0019] Preferably, the voltage regulator diode is a Zener voltage regulator diode.

[0020] Compared with the prior art, the beneficial effect of the present invention is that, by connecting the input end of the bias circuit to the power supply, the output end of the bias circuit is electrically connected to the voltage stabilizing diode, the voltage follower, the bandgap reference circuit, the amplifier circuit, the undervoltage protection circuit, the filter unit and the signal output end in sequence; the positive electrode of the voltage stabilizing diode is grounded, and the negative electrode of the voltage stabilizing diode is connected to the input end of the voltage follower; the negative input end of the operational amplifier is used as the input end of the amplifier circuit, the output end of the operational amplifier is connected to the gate of the first MOS tube, the source of the first MOS tube is connected to the first end of the first resistor, the second end of the first resistor is respectively connected to the first end of the second resistor and the positive input end of the operational amplifier, and the second end of the second resistor is grounded; the drain of the first MOS tube is connected to the power supply, and the source of the first MOS tube is also used as the output end of the amplifier circuit. In this way, the protection requirements of the undervoltage circuit of the traditional LDO chip circuit can be overcome, and at the same time, the filter can be adjusted to ensure the safety of the circuit. The LDO chip has high reliability and great practical significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0022] Figure 1 is a circuit diagram of an adjustable filter LDO chip circuit provided by an embodiment of the present invention;

[0023] Figure 2is a circuit diagram of an undervoltage protection circuit provided by an embodiment of the present invention;

[0024] Figure 3 is an output diagram of a comparator provided by an embodiment of the present invention;

[0025] Figure 4 is a circuit diagram of an inverter provided by an embodiment of the present invention.

[0026] Among them, 1. bias circuit, 2. voltage follower, 3. bandgap reference circuit, 4. amplifier circuit, 5. undervoltage protection circuit, 6. filter unit, 7. inverter. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] Combined with Figure 1-Figure 4 As shown, an embodiment of the present invention provides an adjustable filtering LDO chip circuit, including: a power supply VDD, a bias circuit 1, a voltage follower D1, a voltage follower 2, a bandgap reference circuit 3, an amplifier circuit 4, an undervoltage protection circuit 5, a filter unit 6 and a signal output terminal Vout; the input end of the bias circuit 1 is connected to the power supply VDD, and the output end of the bias circuit 1 is electrically connected to the voltage follower D1, the voltage follower 2, the bandgap reference circuit 3, the amplifier circuit 4, the undervoltage protection circuit 5, the filter unit 6 and the signal output terminal Vout in sequence; the positive electrode of the voltage follower D1 is grounded, and the negative electrode of the voltage follower D1 is connected to the input end of the voltage follower 2.

[0029] The amplifier circuit 4 includes an operational amplifier OPA, a first MOS tube M1, a first resistor R1 and a second resistor R2. The negative input end of the operational amplifier OPA serves as the input end of the amplifier circuit 4. The output end of the operational amplifier OPA is connected to the gate of the first MOS tube M1. The source of the first MOS tube M1 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is respectively connected to the first end of the second resistor R2 and the positive input end of the operational amplifier OPA. The second end of the second resistor R2 is grounded. The drain of the first MOS tube M1 is connected to the power supply VDD. The source of the first MOS tube M1 also serves as the output end of the amplifier circuit 4.

[0030] In this embodiment, the undervoltage protection circuit 5 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a comparator COMP, an inverter 7, a second MOS transistor M2 and a third MOS transistor M3.

[0031] The first end of the third resistor R3 is connected to the power supply VDD, the second end of the third resistor R3 is respectively connected to the first end of the fourth resistor R4 and the positive input end of the comparator COMP, the second end of the fourth resistor R4 is respectively connected to the first end of the fifth resistor R5 and the drain of the second MOS tube M2, the second end of the fifth resistor R5 is connected to the source of the second MOS tube M2 and grounded, the negative input end of the comparator COMP serves as the input end of the undervoltage protection circuit 5, the output end of the comparator COMP is connected to the input end of the inverter 7, the output end of the inverter 7 is respectively connected to the gate of the second MOS tube M2 and the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected to the gate of the third MOS tube M3, the source of the third MOS tube M3 is connected to the power supply VDD, and the drain of the third MOS tube M3 serves as the output end of the undervoltage protection circuit 5.

[0032] Specifically, its main structure is a sampling part, a comparison part, and an output shaping part. The sampling part is implemented by the third resistor R3, the fourth resistor R4, and the fifth resistor R5 for voltage division, VDD is the power supply voltage, and Vref is the internal reference voltage of the chip. The circuit uses resistor voltage division to compare with the reference voltage to determine whether the threshold voltage has been reached, thereby determining whether the system is working normally. V1 is the voltage drop on the third resistor R3 and the fourth resistor R4 after the third resistor R3, the fourth resistor R4, and the fifth resistor R5 divide the power supply voltage VDD, and the voltage drop is compared with the reference voltage Vref.

[0033] Specifically, one output end of the operational amplifier OPA is positively fed back to the non-inverting input of the operational amplifier OPA through the linear proportional relationship between the first resistor R1 and the second resistor R2, and the other output end of the operational amplifier OPA is connected to the load resistor RLoad through the drain of the second MOS tube M2 to obtain a stable low-voltage output voltage Vout; a bandgap reference circuit 3 (BGR); wherein the primary power supply voltage high voltage VDD is connected to the voltage follower 2, the voltage follower 2, the bandgap reference circuit 3, and the operational amplifier OPA are connected in series in sequence, the secondary power supply voltage VDD at the output end of the voltage follower 2 is connected to the input end of the bandgap reference circuit 3, and the reference voltage Vref at the output end of the bandgap reference circuit 3 is connected to the inverting input end of the operational amplifier OPA.

[0034] Preferably, the voltage follower 2 includes a primary power supply voltage high voltage VDD, a bias circuit 1, a voltage regulator diode D1, a first MOS tube M1, a first resistor R1, and a ground terminal GND, the input terminal of the bias circuit 1 is connected to the primary power supply voltage high voltage VDD, the output terminal of the bias circuit 1 is connected in series with the voltage regulator diode D1 and grounded, one end of the tap between the output terminal of the bias circuit 1 and the voltage regulator diode D1 is connected to the gate of the first MOS tube M1, the drain of the first MOS tube M1 is pressurized with the primary power supply voltage high voltage VDD, and the source of the first MOS tube M1 is connected to the second resistor R2 and grounded.

[0035] The bandgap reference circuit 3 uses two series base-emitter voltage reference voltage generating circuits to obtain a stable high-precision reference voltage Vref operational amplifier OPA, which is composed of an operational amplifier OPA and a first MOS tube M1 connected in series. One input end of the operational amplifier OPA is pressurized with a secondary power supply voltage VDD, and the other input end is grounded. The first MOS tube pressurizes the secondary power supply voltage VDD through the source. The drain of the first MOS tube M1 is connected in series with a first resistor R1 and a second resistor R2 and grounded. The tapped end of the first resistor R1 and the second resistor R2 is positively fed back to the non-inverting input of the operational amplifier OPA. The first MOS tube M1 is connected to the load resistor RLoad through the drain output to obtain a stable low-voltage output voltage Vout, and the output end is simultaneously tapped to a filter capacitor C. The voltages of the non-inverting input and the inverting input of the operational amplifier OPA are the same, and the voltage regulator diode D1 adopts a Zener voltage regulator diode D1. The first MOS tube M1 adopts an N-type MOS tube, the second MOS tube M2 adopts a P-type MOS tube, the second MOS tube M2 works in the linear region, the P-type MOS tube and the N-type MOS tube both adopt a high-voltage LDMOS primary power supply voltage, the high-voltage VDD value range is: 8V ~ 30V, and the output voltage Vout voltage value range is: 5V.

[0036] In this embodiment, the inverter 7 includes a fourth MOS tube M4 and a fifth MOS tube M5, the gate of the fourth MOS tube M4 is connected to the gate of the fifth MOS tube M5 and serves as the input end of the inverter 7, the source of the fourth MOS tube M4 is connected to the power supply VDD, the drain of the fourth MOS tube M4 is connected to the drain of the fifth MOS tube M5 and serves as the output end of the inverter 7, and the source of the fifth MOS tube M5 is grounded. The fourth MOS tube M4 and the fifth MOS tube M5 constitute the inverter 7 to reverse the signal polarity: the input high level can be converted to a low level, and vice versa, to achieve the inversion of signal logic. In addition, the signal driving capability is enhanced: sometimes the strength and driving capability of the output signal can be improved to better drive the subsequent circuit.

[0037] In this embodiment, the third resistor is defined as R3, the fourth resistor is defined as R4, the fifth resistor is defined as R5, and the sixth resistor is defined as R6; Vref is the internal reference voltage of the negative input terminal of the comparator COMP; during the increase of the power supply VDD, when the power supply voltage reaches a certain value, the chip is converted from the undervoltage state to the normal working state, and the instantaneous flip voltage is the rising threshold voltage VDDthH of the circuit;

[0038] The rising threshold voltage VDDthH is as shown in Expression (1);

[0039]

[0040] During the power supply voltage reduction process, when the power supply voltage reaches a certain value, the chip switches from a normal working state to an abnormal working state, and the falling threshold value is represented by VDDthL;

[0041]

[0042] The difference between the rising threshold voltage and the falling threshold voltage is the hysteresis voltage, and the hysteresis voltage is as shown in formula (3);

[0043] VDDthhold=VDDthH-VDDthL(3).

[0044] Specifically, Figure 4 This is the output diagram of the comparator COMP. When V1-Vref<0, the output signal is low level, and after passing through the inverter 7, it becomes high level, M2 is turned on, R5 is short-circuited, and the voltage of V1 is further steadily reduced, and after passing through R3 (current limiting to protect the gate of M3), M3 is turned off at a high level, and the circuit is turned off. When V1-Vref>0, the output signal is high level, after passing through the inverter 7, it becomes high level, M2 is turned off, the voltage of V1 is increased, and after passing through R3 (current limiting to protect the gate of M3), M3 is turned on at a low level, and the circuit is operated normally. There will be a certain difference between the falling threshold and the rising threshold, that is, there will be a certain hysteresis effect. In the process of power supply voltage rising, when the power supply voltage reaches a certain value, the chip is converted from the undervoltage state to the normal working state, and the instantaneous flip voltage is the rising threshold voltage VDDthH of the circuit. From the analysis of the figure, it can be known that when undervoltage, the control signal UVLO OUT is the power supply voltage, Mo is turned on, R5 is short-circuited, and the voltage division cannot be continued. Therefore, ignoring the conduction voltage drop of the MOS tube Mo, the rising threshold voltage VDDthH can be expressed as:

[0045] The rising threshold voltage VDDthH is as shown in Expression (1);

[0046]

[0047] During the power supply voltage reduction process, when the power supply voltage reaches a certain value, the chip switches from the normal working state to the abnormal working state. When the power supply voltage is in the normal working range, the output control signal UVLOOUT of the undervoltage protection circuit 5 is low level, so that Mo is cut off, and the fifth resistor R5 plays the role of voltage division again. The falling threshold is represented by VDDthL;

[0048]

[0049] Among them, it can be seen from the formulas of the two thresholds VDDthH and VDDthL that the rising threshold voltage is lower than the falling threshold voltage, and the difference is the hysteresis voltage. The difference between the rising threshold voltage and the falling threshold voltage is the hysteresis voltage, and the hysteresis voltage is shown in formula (3);

[0050] VDDthhold=VDDthH-VDDthL(3).

[0051] From the formula derived above, it can be seen that the threshold of the undervoltage protection circuit 5 is closely related to the voltage divider resistor and the reference voltage, and the hysteresis voltage is mainly affected by the fifth resistor R5. By reasonably setting the relevant factors, the required design can be obtained.

[0052] In this embodiment, the first MOS transistor M1 is an N-type MOS transistor.

[0053] In this embodiment, the second MOS transistor M2 is a P-type MOS transistor.

[0054] In this embodiment, the voltage regulator diode D1 is a Zener voltage regulator diode D1.

[0055] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0056] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. An adjustable filter LDO chip circuit, characterized in that: include: Power supply, bias circuit, voltage stabilizing diode, voltage follower, bandgap reference circuit, amplifier circuit, undervoltage protection circuit, filter unit and signal output terminal; The input end of the bias circuit is connected to a power supply, and the output end of the bias circuit is electrically connected to the voltage-stabilizing diode, the voltage follower, the bandgap reference circuit, the amplifier circuit, the undervoltage protection circuit, the filter unit, and the signal output end in sequence; the positive electrode of the voltage-stabilizing diode is grounded, and the negative electrode of the voltage-stabilizing diode is connected to the input end of the voltage follower; The amplifier circuit includes an operational amplifier, a first MOS tube, a first resistor and a second resistor. The negative input terminal of the operational amplifier serves as the input terminal of the amplifier circuit, the output terminal of the operational amplifier is connected to the gate of the first MOS tube, the source of the first MOS tube is connected to the first end of the first resistor, the second end of the first resistor is respectively connected to the first end of the second resistor and the positive input terminal of the operational amplifier, and the second end of the second resistor is grounded; the drain of the first MOS tube is connected to the power supply, and the source of the first MOS tube also serves as the output terminal of the amplifier circuit.

2. The adjustable filter LDO chip circuit according to claim 1, characterized in that: The undervoltage protection circuit includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a comparator, an inverter, a second MOS tube and a third MOS tube; The first end of the third resistor is connected to the power supply, the second end of the third resistor is respectively connected to the first end of the fourth resistor and the positive input end of the comparator, the second end of the fourth resistor is respectively connected to the first end of the fifth resistor and the drain of the second MOS tube, the second end of the fifth resistor is connected to the source of the second MOS tube and grounded, the negative input end of the comparator serves as the input end of the undervoltage protection circuit, the output end of the comparator is connected to the input end of the inverter, the output end of the inverter is respectively connected to the gate of the second MOS tube and the first end of the sixth resistor, the second end of the sixth resistor is connected to the gate of the third MOS tube, the source of the third MOS tube is connected to the power supply, and the drain of the third MOS tube serves as the output end of the undervoltage protection circuit.

3. The adjustable filter LDO chip circuit according to claim 2, characterized in that: The inverter comprises a fourth MOS tube and a fifth MOS tube, the gate of the fourth MOS tube is connected to the gate of the fifth MOS tube and serves as the input end of the inverter, the source of the fourth MOS tube is connected to the power supply, the drain of the fourth MOS tube is connected to the drain of the fifth MOS tube and serves as the output end of the inverter, and the source of the fifth MOS tube is grounded.

4. The adjustable filter LDO chip circuit according to claim 3, characterized in that: The third resistor is defined as R3, the fourth resistor is defined as R4, the fifth resistor is defined as R5, and the sixth resistor is defined as R6; Vref is the internal reference voltage of the negative input terminal of the comparator; in the process of the power supply increasing, when the power supply voltage reaches a certain value, the chip is converted from the undervoltage state to the normal working state, and the instantaneous flip voltage is the rising threshold voltage VDDthH of the circuit; The rising threshold voltage VDDthH is as shown in Expression (1); During the power supply voltage reduction process, when the power supply voltage reaches a certain value, the chip switches from a normal working state to an abnormal working state, and the falling threshold value is represented by VDDthL; The difference between the rising threshold voltage and the falling threshold voltage is the hysteresis voltage, and the hysteresis voltage is as shown in formula (3); VDDthhold=VDDthH-VDDthL(3).

5. The adjustable filter LDO chip circuit according to claim 1, characterized in that: The first MOS tube is an N-type MOS tube.

6. The adjustable filter LDO chip circuit according to claim 2, characterized in that: The second MOS tube is a P-type MOS tube.

7. The adjustable filter LDO chip circuit according to claim 1, characterized in that: The voltage regulator diode is a Zener voltage regulator diode.

Images